gdb/mips-tdep.h

   1 /* Target-dependent header for the MIPS architecture, for GDB, the GNU Debugger.
   2
   3    Copyright (C) 2002-2023 Free Software Foundation, Inc.
   4
   5    This file is part of GDB.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 #ifndef MIPS_TDEP_H
  21 #define MIPS_TDEP_H
  22
  23 #include "objfiles.h"
  24 #include "gdbarch.h"
  25
  26 struct gdbarch;
  27
  28 /* All the possible MIPS ABIs.  */
  29 enum mips_abi
  30   {
  31     MIPS_ABI_UNKNOWN = 0,
  32     MIPS_ABI_N32,
  33     MIPS_ABI_O32,
  34     MIPS_ABI_N64,
  35     MIPS_ABI_O64,
  36     MIPS_ABI_EABI32,
  37     MIPS_ABI_EABI64,
  38     MIPS_ABI_LAST
  39   };
  40
  41 /* Return the MIPS ABI associated with GDBARCH.  */
  42 enum mips_abi mips_abi (struct gdbarch *gdbarch);
  43
  44 /* Base and compressed MIPS ISA variations.  */
  45 enum mips_isa
  46   {
  47     ISA_MIPS = -1,              /* mips_compression_string depends on it.  */
  48     ISA_MIPS16,
  49     ISA_MICROMIPS
  50   };
  51
  52 /* Corresponding MSYMBOL_TARGET_FLAG aliases.  */
  53 #define MSYMBOL_TARGET_FLAG_MIPS16(sym) \
  54         (sym)->target_flag_1 ()
  55
  56 #define SET_MSYMBOL_TARGET_FLAG_MIPS16(sym) \
  57         (sym)->set_target_flag_1 (true)
  58
  59 #define MSYMBOL_TARGET_FLAG_MICROMIPS(sym) \
  60         (sym)->target_flag_2 ()
  61
  62 #define SET_MSYMBOL_TARGET_FLAG_MICROMIPS(sym) \
  63         (sym)->set_target_flag_2 (true)
  64
  65 /* Return the MIPS ISA's register size.  Just a short cut to the BFD
  66    architecture's word size.  */
  67 extern int mips_isa_regsize (struct gdbarch *gdbarch);
  68
  69 /* Return the current index for various MIPS registers.  */
  70 struct mips_regnum
  71 {
  72   int pc;
  73   int fp0;
  74   int fp_implementation_revision;
  75   int fp_control_status;
  76   int badvaddr;         /* Bad vaddr for addressing exception.  */
  77   int cause;            /* Describes last exception.  */
  78   int hi;               /* Multiply/divide temp.  */
  79   int lo;               /* ...  */
  80   int dspacc;           /* SmartMIPS/DSP accumulators.  */
  81   int dspctl;           /* DSP control.  */
  82 };
  83 extern const struct mips_regnum *mips_regnum (struct gdbarch *gdbarch);
  84
  85 /* Some MIPS boards don't support floating point while others only
  86    support single-precision floating-point operations.  */
  87
  88 enum mips_fpu_type
  89 {
  90   MIPS_FPU_DOUBLE,              /* Full double precision floating point.  */
  91   MIPS_FPU_SINGLE,              /* Single precision floating point (R4650).  */
  92   MIPS_FPU_NONE                 /* No floating point.  */
  93 };
  94
  95 /* MIPS specific per-architecture information.  */
  96 struct mips_gdbarch_tdep : gdbarch_tdep_base
  97 {
  98   /* from the elf header */
  99   int elf_flags = 0;
 100
 101   /* mips options */
 102   enum mips_abi mips_abi {};
 103   enum mips_abi found_abi {};
 104   enum mips_isa mips_isa {};
 105   enum mips_fpu_type mips_fpu_type {};
 106   int mips_last_arg_regnum = 0;
 107   int mips_last_fp_arg_regnum = 0;
 108   int default_mask_address_p = 0;
 109   /* Is the target using 64-bit raw integer registers but only
 110      storing a left-aligned 32-bit value in each?  */
 111   int mips64_transfers_32bit_regs_p = 0;
 112   /* Indexes for various registers.  IRIX and embedded have
 113      different values.  This contains the "public" fields.  Don't
 114      add any that do not need to be public.  */
 115   const struct mips_regnum *regnum = nullptr;
 116   /* Register names table for the current register set.  */
 117   const char * const *mips_processor_reg_names = nullptr;
 118
 119   /* The size of register data available from the target, if known.
 120      This doesn't quite obsolete the manual
 121      mips64_transfers_32bit_regs_p, since that is documented to force
 122      left alignment even for big endian (very strange).  */
 123   int register_size_valid_p = 0;
 124   int register_size = 0;
 125
 126   /* Return the expected next PC if FRAME is stopped at a syscall
 127      instruction.  */
 128   CORE_ADDR (*syscall_next_pc) (frame_info_ptr frame) = nullptr;
 129 };
 130
 131 /* Register numbers of various important registers.  */
 132
 133 enum
 134 {
 135   MIPS_ZERO_REGNUM = 0,         /* Read-only register, always 0.  */
 136   MIPS_AT_REGNUM = 1,
 137   MIPS_V0_REGNUM = 2,           /* Function integer return value.  */
 138   MIPS_A0_REGNUM = 4,           /* Loc of first arg during a subr call.  */
 139   MIPS_S2_REGNUM = 18,          /* Contains return address in MIPS16 thunks. */
 140   MIPS_T9_REGNUM = 25,          /* Contains address of callee in PIC.  */
 141   MIPS_GP_REGNUM = 28,
 142   MIPS_SP_REGNUM = 29,
 143   MIPS_RA_REGNUM = 31,
 144   MIPS_PS_REGNUM = 32,          /* Contains processor status.  */
 145   MIPS_EMBED_LO_REGNUM = 33,
 146   MIPS_EMBED_HI_REGNUM = 34,
 147   MIPS_EMBED_BADVADDR_REGNUM = 35,
 148   MIPS_EMBED_CAUSE_REGNUM = 36,
 149   MIPS_EMBED_PC_REGNUM = 37,
 150   MIPS_EMBED_FP0_REGNUM = 38,
 151   MIPS_UNUSED_REGNUM = 73,      /* Never used, FIXME.  */
 152   MIPS_FIRST_EMBED_REGNUM = 74, /* First CP0 register for embedded use.  */
 153   MIPS_PRID_REGNUM = 89,        /* Processor ID.  */
 154   MIPS_LAST_EMBED_REGNUM = 89   /* Last one.  */
 155 };
 156
 157 /* Instruction sizes and other useful constants.  */
 158 enum
 159 {
 160   MIPS_INSN16_SIZE = 2,
 161   MIPS_INSN32_SIZE = 4,
 162   /* The number of floating-point or integer registers.  */
 163   MIPS_NUMREGS = 32
 164 };
 165
 166 /* Single step based on where the current instruction will take us.  */
 167 extern std::vector<CORE_ADDR> mips_software_single_step
 168   (struct regcache *regcache);
 169
 170 /* Strip the ISA (compression) bit off from ADDR.  */
 171 extern CORE_ADDR mips_unmake_compact_addr (CORE_ADDR addr);
 172
 173 /* Tell if the program counter value in MEMADDR is in a standard
 174    MIPS function.  */
 175 extern int mips_pc_is_mips (CORE_ADDR memaddr);
 176
 177 /* Tell if the program counter value in MEMADDR is in a MIPS16
 178    function.  */
 179 extern int mips_pc_is_mips16 (struct gdbarch *gdbarch, CORE_ADDR memaddr);
 180
 181 /* Tell if the program counter value in MEMADDR is in a microMIPS
 182    function.  */
 183 extern int mips_pc_is_micromips (struct gdbarch *gdbarch, CORE_ADDR memaddr);
 184
 185 /* Return the currently configured (or set) saved register size.  */
 186 extern unsigned int mips_abi_regsize (struct gdbarch *gdbarch);
 187
 188 /* Make PC the address of the next instruction to execute.  */
 189 extern void mips_write_pc (struct regcache *regcache, CORE_ADDR pc);
 190
 191 /* Target descriptions which only indicate the size of general
 192    registers.  */
 193 extern struct target_desc *mips_tdesc_gp32;
 194 extern struct target_desc *mips_tdesc_gp64;
 195
 196 /* Return non-zero if PC is in a MIPS SVR4 lazy binding stub section.  */
 197
 198 static inline int
 199 in_mips_stubs_section (CORE_ADDR pc)
 200 {
 201   return pc_in_section (pc, ".MIPS.stubs");
 202 }
 203
 204 #endif /* MIPS_TDEP_H */