opcodes/fr30-desc.c

   1 /* CPU data for fr30.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #include "sysdep.h"
  26 #include <stdio.h>
  27 #include <stdarg.h>
  28 #include "ansidecl.h"
  29 #include "bfd.h"
  30 #include "symcat.h"
  31 #include "fr30-desc.h"
  32 #include "fr30-opc.h"
  33 #include "opintl.h"
  34 #include "libiberty.h"
  35
  36 /* Attributes.  */
  37
  38 static const CGEN_ATTR_ENTRY bool_attr[] =
  39 {
  40   { "#f", 0 },
  41   { "#t", 1 },
  42   { 0, 0 }
  43 };
  44
  45 static const CGEN_ATTR_ENTRY MACH_attr[] =
  46 {
  47   { "base", MACH_BASE },
  48   { "fr30", MACH_FR30 },
  49   { "max", MACH_MAX },
  50   { 0, 0 }
  51 };
  52
  53 static const CGEN_ATTR_ENTRY ISA_attr[] =
  54 {
  55   { "fr30", ISA_FR30 },
  56   { "max", ISA_MAX },
  57   { 0, 0 }
  58 };
  59
  60 const CGEN_ATTR_TABLE fr30_cgen_ifield_attr_table[] =
  61 {
  62   { "MACH", & MACH_attr[0], & MACH_attr[0] },
  63   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  64   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
  65   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
  66   { "RESERVED", &bool_attr[0], &bool_attr[0] },
  67   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
  68   { "SIGNED", &bool_attr[0], &bool_attr[0] },
  69   { 0, 0, 0 }
  70 };
  71
  72 const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[] =
  73 {
  74   { "MACH", & MACH_attr[0], & MACH_attr[0] },
  75   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  76   { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
  77   { "PC", &bool_attr[0], &bool_attr[0] },
  78   { "PROFILE", &bool_attr[0], &bool_attr[0] },
  79   { 0, 0, 0 }
  80 };
  81
  82 const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[] =
  83 {
  84   { "MACH", & MACH_attr[0], & MACH_attr[0] },
  85   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  86   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
  87   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
  88   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
  89   { "SIGNED", &bool_attr[0], &bool_attr[0] },
  90   { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
  91   { "RELAX", &bool_attr[0], &bool_attr[0] },
  92   { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
  93   { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] },
  94   { 0, 0, 0 }
  95 };
  96
  97 const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[] =
  98 {
  99   { "MACH", & MACH_attr[0], & MACH_attr[0] },
 100   { "ALIAS", &bool_attr[0], &bool_attr[0] },
 101   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 102   { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
 103   { "COND-CTI", &bool_attr[0], &bool_attr[0] },
 104   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
 105   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
 106   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
 107   { "RELAX", &bool_attr[0], &bool_attr[0] },
 108   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
 109   { "PBB", &bool_attr[0], &bool_attr[0] },
 110   { "NOT-IN-DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
 111   { 0, 0, 0 }
 112 };
 113
 114 /* Instruction set variants.  */
 115
 116 static const CGEN_ISA fr30_cgen_isa_table[] = {
 117   { "fr30", 16, 16, 16, 48 },
 118   { 0, 0, 0, 0, 0 }
 119 };
 120
 121 /* Machine variants.  */
 122
 123 static const CGEN_MACH fr30_cgen_mach_table[] = {
 124   { "fr30", "fr30", MACH_FR30, 0 },
 125   { 0, 0, 0, 0 }
 126 };
 127
 128 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_gr_names_entries[] =
 129 {
 130   { "r0", 0, {0, {0}}, 0, 0 },
 131   { "r1", 1, {0, {0}}, 0, 0 },
 132   { "r2", 2, {0, {0}}, 0, 0 },
 133   { "r3", 3, {0, {0}}, 0, 0 },
 134   { "r4", 4, {0, {0}}, 0, 0 },
 135   { "r5", 5, {0, {0}}, 0, 0 },
 136   { "r6", 6, {0, {0}}, 0, 0 },
 137   { "r7", 7, {0, {0}}, 0, 0 },
 138   { "r8", 8, {0, {0}}, 0, 0 },
 139   { "r9", 9, {0, {0}}, 0, 0 },
 140   { "r10", 10, {0, {0}}, 0, 0 },
 141   { "r11", 11, {0, {0}}, 0, 0 },
 142   { "r12", 12, {0, {0}}, 0, 0 },
 143   { "r13", 13, {0, {0}}, 0, 0 },
 144   { "r14", 14, {0, {0}}, 0, 0 },
 145   { "r15", 15, {0, {0}}, 0, 0 },
 146   { "ac", 13, {0, {0}}, 0, 0 },
 147   { "fp", 14, {0, {0}}, 0, 0 },
 148   { "sp", 15, {0, {0}}, 0, 0 }
 149 };
 150
 151 CGEN_KEYWORD fr30_cgen_opval_gr_names =
 152 {
 153   & fr30_cgen_opval_gr_names_entries[0],
 154   19,
 155   0, 0, 0, 0, ""
 156 };
 157
 158 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_cr_names_entries[] =
 159 {
 160   { "cr0", 0, {0, {0}}, 0, 0 },
 161   { "cr1", 1, {0, {0}}, 0, 0 },
 162   { "cr2", 2, {0, {0}}, 0, 0 },
 163   { "cr3", 3, {0, {0}}, 0, 0 },
 164   { "cr4", 4, {0, {0}}, 0, 0 },
 165   { "cr5", 5, {0, {0}}, 0, 0 },
 166   { "cr6", 6, {0, {0}}, 0, 0 },
 167   { "cr7", 7, {0, {0}}, 0, 0 },
 168   { "cr8", 8, {0, {0}}, 0, 0 },
 169   { "cr9", 9, {0, {0}}, 0, 0 },
 170   { "cr10", 10, {0, {0}}, 0, 0 },
 171   { "cr11", 11, {0, {0}}, 0, 0 },
 172   { "cr12", 12, {0, {0}}, 0, 0 },
 173   { "cr13", 13, {0, {0}}, 0, 0 },
 174   { "cr14", 14, {0, {0}}, 0, 0 },
 175   { "cr15", 15, {0, {0}}, 0, 0 }
 176 };
 177
 178 CGEN_KEYWORD fr30_cgen_opval_cr_names =
 179 {
 180   & fr30_cgen_opval_cr_names_entries[0],
 181   16,
 182   0, 0, 0, 0, ""
 183 };
 184
 185 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_dr_names_entries[] =
 186 {
 187   { "tbr", 0, {0, {0}}, 0, 0 },
 188   { "rp", 1, {0, {0}}, 0, 0 },
 189   { "ssp", 2, {0, {0}}, 0, 0 },
 190   { "usp", 3, {0, {0}}, 0, 0 },
 191   { "mdh", 4, {0, {0}}, 0, 0 },
 192   { "mdl", 5, {0, {0}}, 0, 0 }
 193 };
 194
 195 CGEN_KEYWORD fr30_cgen_opval_dr_names =
 196 {
 197   & fr30_cgen_opval_dr_names_entries[0],
 198   6,
 199   0, 0, 0, 0, ""
 200 };
 201
 202 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_ps_entries[] =
 203 {
 204   { "ps", 0, {0, {0}}, 0, 0 }
 205 };
 206
 207 CGEN_KEYWORD fr30_cgen_opval_h_ps =
 208 {
 209   & fr30_cgen_opval_h_ps_entries[0],
 210   1,
 211   0, 0, 0, 0, ""
 212 };
 213
 214 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r13_entries[] =
 215 {
 216   { "r13", 0, {0, {0}}, 0, 0 }
 217 };
 218
 219 CGEN_KEYWORD fr30_cgen_opval_h_r13 =
 220 {
 221   & fr30_cgen_opval_h_r13_entries[0],
 222   1,
 223   0, 0, 0, 0, ""
 224 };
 225
 226 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r14_entries[] =
 227 {
 228   { "r14", 0, {0, {0}}, 0, 0 }
 229 };
 230
 231 CGEN_KEYWORD fr30_cgen_opval_h_r14 =
 232 {
 233   & fr30_cgen_opval_h_r14_entries[0],
 234   1,
 235   0, 0, 0, 0, ""
 236 };
 237
 238 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r15_entries[] =
 239 {
 240   { "r15", 0, {0, {0}}, 0, 0 }
 241 };
 242
 243 CGEN_KEYWORD fr30_cgen_opval_h_r15 =
 244 {
 245   & fr30_cgen_opval_h_r15_entries[0],
 246   1,
 247   0, 0, 0, 0, ""
 248 };
 249
 250
 251 /* The hardware table.  */
 252
 253 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 254 #define A(a) (1 << CGEN_HW_##a)
 255 #else
 256 #define A(a) (1 << CGEN_HW_/**/a)
 257 #endif
 258
 259 const CGEN_HW_ENTRY fr30_cgen_hw_table[] =
 260 {
 261   { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 262   { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 263   { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 264   { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 265   { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 266   { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } },
 267   { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { (1<<MACH_BASE) } } },
 268   { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_cr_names, { 0, { (1<<MACH_BASE) } } },
 269   { "h-dr", HW_H_DR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_dr_names, { 0, { (1<<MACH_BASE) } } },
 270   { "h-ps", HW_H_PS, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_ps, { 0, { (1<<MACH_BASE) } } },
 271   { "h-r13", HW_H_R13, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r13, { 0, { (1<<MACH_BASE) } } },
 272   { "h-r14", HW_H_R14, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r14, { 0, { (1<<MACH_BASE) } } },
 273   { "h-r15", HW_H_R15, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r15, { 0, { (1<<MACH_BASE) } } },
 274   { "h-nbit", HW_H_NBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 275   { "h-zbit", HW_H_ZBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 276   { "h-vbit", HW_H_VBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 277   { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 278   { "h-ibit", HW_H_IBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 279   { "h-sbit", HW_H_SBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 280   { "h-tbit", HW_H_TBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 281   { "h-d0bit", HW_H_D0BIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 282   { "h-d1bit", HW_H_D1BIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 283   { "h-ccr", HW_H_CCR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 284   { "h-scr", HW_H_SCR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 285   { "h-ilm", HW_H_ILM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 286   { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
 287 };
 288
 289 #undef A
 290
 291
 292 /* The instruction field table.  */
 293
 294 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 295 #define A(a) (1 << CGEN_IFLD_##a)
 296 #else
 297 #define A(a) (1 << CGEN_IFLD_/**/a)
 298 #endif
 299
 300 const CGEN_IFLD fr30_cgen_ifld_table[] =
 301 {
 302   { FR30_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
 303   { FR30_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
 304   { FR30_F_OP1, "f-op1", 0, 16, 0, 4, { 0, { (1<<MACH_BASE) } }  },
 305   { FR30_F_OP2, "f-op2", 0, 16, 4, 4, { 0, { (1<<MACH_BASE) } }  },
 306   { FR30_F_OP3, "f-op3", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
 307   { FR30_F_OP4, "f-op4", 0, 16, 12, 4, { 0, { (1<<MACH_BASE) } }  },
 308   { FR30_F_OP5, "f-op5", 0, 16, 4, 1, { 0, { (1<<MACH_BASE) } }  },
 309   { FR30_F_CC, "f-cc", 0, 16, 4, 4, { 0, { (1<<MACH_BASE) } }  },
 310   { FR30_F_CCC, "f-ccc", 16, 16, 0, 8, { 0, { (1<<MACH_BASE) } }  },
 311   { FR30_F_RJ, "f-Rj", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
 312   { FR30_F_RI, "f-Ri", 0, 16, 12, 4, { 0, { (1<<MACH_BASE) } }  },
 313   { FR30_F_RS1, "f-Rs1", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
 314   { FR30_F_RS2, "f-Rs2", 0, 16, 12, 4, { 0, { (1<<MACH_BASE) } }  },
 315   { FR30_F_RJC, "f-Rjc", 16, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
 316   { FR30_F_RIC, "f-Ric", 16, 16, 12, 4, { 0, { (1<<MACH_BASE) } }  },
 317   { FR30_F_CRJ, "f-CRj", 16, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
 318   { FR30_F_CRI, "f-CRi", 16, 16, 12, 4, { 0, { (1<<MACH_BASE) } }  },
 319   { FR30_F_U4, "f-u4", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
 320   { FR30_F_U4C, "f-u4c", 0, 16, 12, 4, { 0, { (1<<MACH_BASE) } }  },
 321   { FR30_F_I4, "f-i4", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
 322   { FR30_F_M4, "f-m4", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
 323   { FR30_F_U8, "f-u8", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
 324   { FR30_F_I8, "f-i8", 0, 16, 4, 8, { 0, { (1<<MACH_BASE) } }  },
 325   { FR30_F_I20_4, "f-i20-4", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
 326   { FR30_F_I20_16, "f-i20-16", 16, 16, 0, 16, { 0, { (1<<MACH_BASE) } }  },
 327   { FR30_F_I32, "f-i32", 16, 32, 0, 32, { 0|A(SIGN_OPT), { (1<<MACH_BASE) } }  },
 328   { FR30_F_UDISP6, "f-udisp6", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
 329   { FR30_F_DISP8, "f-disp8", 0, 16, 4, 8, { 0, { (1<<MACH_BASE) } }  },
 330   { FR30_F_DISP9, "f-disp9", 0, 16, 4, 8, { 0, { (1<<MACH_BASE) } }  },
 331   { FR30_F_DISP10, "f-disp10", 0, 16, 4, 8, { 0, { (1<<MACH_BASE) } }  },
 332   { FR30_F_S10, "f-s10", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
 333   { FR30_F_U10, "f-u10", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
 334   { FR30_F_REL9, "f-rel9", 0, 16, 8, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
 335   { FR30_F_DIR8, "f-dir8", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
 336   { FR30_F_DIR9, "f-dir9", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
 337   { FR30_F_DIR10, "f-dir10", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
 338   { FR30_F_REL12, "f-rel12", 0, 16, 5, 11, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
 339   { FR30_F_REGLIST_HI_ST, "f-reglist_hi_st", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
 340   { FR30_F_REGLIST_LOW_ST, "f-reglist_low_st", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
 341   { FR30_F_REGLIST_HI_LD, "f-reglist_hi_ld", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
 342   { FR30_F_REGLIST_LOW_LD, "f-reglist_low_ld", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
 343   { 0, 0, 0, 0, 0, 0, {0, {0}} }
 344 };
 345
 346 #undef A
 347
 348
 349
 350 /* multi ifield declarations */
 351
 352 const CGEN_MAYBE_MULTI_IFLD FR30_F_I20_MULTI_IFIELD [];
 353
 354
 355 /* multi ifield definitions */
 356
 357 const CGEN_MAYBE_MULTI_IFLD FR30_F_I20_MULTI_IFIELD [] =
 358 {
 359     { 0, &(fr30_cgen_ifld_table[23]) },
 360     { 0, &(fr30_cgen_ifld_table[24]) },
 361     {0,0}
 362 };
 363
 364 /* The operand table.  */
 365
 366 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 367 #define A(a) (1 << CGEN_OPERAND_##a)
 368 #else
 369 #define A(a) (1 << CGEN_OPERAND_/**/a)
 370 #endif
 371 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 372 #define OPERAND(op) FR30_OPERAND_##op
 373 #else
 374 #define OPERAND(op) FR30_OPERAND_/**/op
 375 #endif
 376
 377 const CGEN_OPERAND fr30_cgen_operand_table[] =
 378 {
 379 /* pc: program counter */
 380   { "pc", FR30_OPERAND_PC, HW_H_PC, 0, 0,
 381     { 0, &(fr30_cgen_ifld_table[0]) },
 382     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 383 /* Ri: destination register */
 384   { "Ri", FR30_OPERAND_RI, HW_H_GR, 12, 4,
 385     { 0, &(fr30_cgen_ifld_table[10]) },
 386     { 0, { (1<<MACH_BASE) } }  },
 387 /* Rj: source register */
 388   { "Rj", FR30_OPERAND_RJ, HW_H_GR, 8, 4,
 389     { 0, &(fr30_cgen_ifld_table[9]) },
 390     { 0, { (1<<MACH_BASE) } }  },
 391 /* Ric: target register coproc insn */
 392   { "Ric", FR30_OPERAND_RIC, HW_H_GR, 12, 4,
 393     { 0, &(fr30_cgen_ifld_table[14]) },
 394     { 0, { (1<<MACH_BASE) } }  },
 395 /* Rjc: source register coproc insn */
 396   { "Rjc", FR30_OPERAND_RJC, HW_H_GR, 8, 4,
 397     { 0, &(fr30_cgen_ifld_table[13]) },
 398     { 0, { (1<<MACH_BASE) } }  },
 399 /* CRi: coprocessor register */
 400   { "CRi", FR30_OPERAND_CRI, HW_H_CR, 12, 4,
 401     { 0, &(fr30_cgen_ifld_table[16]) },
 402     { 0, { (1<<MACH_BASE) } }  },
 403 /* CRj: coprocessor register */
 404   { "CRj", FR30_OPERAND_CRJ, HW_H_CR, 8, 4,
 405     { 0, &(fr30_cgen_ifld_table[15]) },
 406     { 0, { (1<<MACH_BASE) } }  },
 407 /* Rs1: dedicated register */
 408   { "Rs1", FR30_OPERAND_RS1, HW_H_DR, 8, 4,
 409     { 0, &(fr30_cgen_ifld_table[11]) },
 410     { 0, { (1<<MACH_BASE) } }  },
 411 /* Rs2: dedicated register */
 412   { "Rs2", FR30_OPERAND_RS2, HW_H_DR, 12, 4,
 413     { 0, &(fr30_cgen_ifld_table[12]) },
 414     { 0, { (1<<MACH_BASE) } }  },
 415 /* R13: General Register 13 */
 416   { "R13", FR30_OPERAND_R13, HW_H_R13, 0, 0,
 417     { 0, 0 },
 418     { 0, { (1<<MACH_BASE) } }  },
 419 /* R14: General Register 14 */
 420   { "R14", FR30_OPERAND_R14, HW_H_R14, 0, 0,
 421     { 0, 0 },
 422     { 0, { (1<<MACH_BASE) } }  },
 423 /* R15: General Register 15 */
 424   { "R15", FR30_OPERAND_R15, HW_H_R15, 0, 0,
 425     { 0, 0 },
 426     { 0, { (1<<MACH_BASE) } }  },
 427 /* ps: Program Status register */
 428   { "ps", FR30_OPERAND_PS, HW_H_PS, 0, 0,
 429     { 0, 0 },
 430     { 0, { (1<<MACH_BASE) } }  },
 431 /* u4: 4  bit unsigned immediate */
 432   { "u4", FR30_OPERAND_U4, HW_H_UINT, 8, 4,
 433     { 0, &(fr30_cgen_ifld_table[17]) },
 434     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 435 /* u4c: 4  bit unsigned immediate */
 436   { "u4c", FR30_OPERAND_U4C, HW_H_UINT, 12, 4,
 437     { 0, &(fr30_cgen_ifld_table[18]) },
 438     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 439 /* u8: 8  bit unsigned immediate */
 440   { "u8", FR30_OPERAND_U8, HW_H_UINT, 8, 8,
 441     { 0, &(fr30_cgen_ifld_table[21]) },
 442     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 443 /* i8: 8  bit unsigned immediate */
 444   { "i8", FR30_OPERAND_I8, HW_H_UINT, 4, 8,
 445     { 0, &(fr30_cgen_ifld_table[22]) },
 446     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 447 /* udisp6: 6  bit unsigned immediate */
 448   { "udisp6", FR30_OPERAND_UDISP6, HW_H_UINT, 8, 4,
 449     { 0, &(fr30_cgen_ifld_table[26]) },
 450     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 451 /* disp8: 8  bit signed   immediate */
 452   { "disp8", FR30_OPERAND_DISP8, HW_H_SINT, 4, 8,
 453     { 0, &(fr30_cgen_ifld_table[27]) },
 454     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 455 /* disp9: 9  bit signed   immediate */
 456   { "disp9", FR30_OPERAND_DISP9, HW_H_SINT, 4, 8,
 457     { 0, &(fr30_cgen_ifld_table[28]) },
 458     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 459 /* disp10: 10 bit signed   immediate */
 460   { "disp10", FR30_OPERAND_DISP10, HW_H_SINT, 4, 8,
 461     { 0, &(fr30_cgen_ifld_table[29]) },
 462     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 463 /* s10: 10 bit signed   immediate */
 464   { "s10", FR30_OPERAND_S10, HW_H_SINT, 8, 8,
 465     { 0, &(fr30_cgen_ifld_table[30]) },
 466     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 467 /* u10: 10 bit unsigned immediate */
 468   { "u10", FR30_OPERAND_U10, HW_H_UINT, 8, 8,
 469     { 0, &(fr30_cgen_ifld_table[31]) },
 470     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 471 /* i32: 32 bit immediate */
 472   { "i32", FR30_OPERAND_I32, HW_H_UINT, 0, 32,
 473     { 0, &(fr30_cgen_ifld_table[25]) },
 474     { 0|A(HASH_PREFIX)|A(SIGN_OPT), { (1<<MACH_BASE) } }  },
 475 /* m4: 4  bit negative immediate */
 476   { "m4", FR30_OPERAND_M4, HW_H_SINT, 8, 4,
 477     { 0, &(fr30_cgen_ifld_table[20]) },
 478     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 479 /* i20: 20 bit immediate */
 480   { "i20", FR30_OPERAND_I20, HW_H_UINT, 0, 20,
 481     { 2, &(FR30_F_I20_MULTI_IFIELD[0]) },
 482     { 0|A(HASH_PREFIX)|A(VIRTUAL), { (1<<MACH_BASE) } }  },
 483 /* dir8: 8  bit direct address */
 484   { "dir8", FR30_OPERAND_DIR8, HW_H_UINT, 8, 8,
 485     { 0, &(fr30_cgen_ifld_table[33]) },
 486     { 0, { (1<<MACH_BASE) } }  },
 487 /* dir9: 9  bit direct address */
 488   { "dir9", FR30_OPERAND_DIR9, HW_H_UINT, 8, 8,
 489     { 0, &(fr30_cgen_ifld_table[34]) },
 490     { 0, { (1<<MACH_BASE) } }  },
 491 /* dir10: 10 bit direct address */
 492   { "dir10", FR30_OPERAND_DIR10, HW_H_UINT, 8, 8,
 493     { 0, &(fr30_cgen_ifld_table[35]) },
 494     { 0, { (1<<MACH_BASE) } }  },
 495 /* label9: 9  bit pc relative address */
 496   { "label9", FR30_OPERAND_LABEL9, HW_H_IADDR, 8, 8,
 497     { 0, &(fr30_cgen_ifld_table[32]) },
 498     { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
 499 /* label12: 12 bit pc relative address */
 500   { "label12", FR30_OPERAND_LABEL12, HW_H_IADDR, 5, 11,
 501     { 0, &(fr30_cgen_ifld_table[36]) },
 502     { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
 503 /* reglist_low_ld: 8 bit low register mask for ldm */
 504   { "reglist_low_ld", FR30_OPERAND_REGLIST_LOW_LD, HW_H_UINT, 8, 8,
 505     { 0, &(fr30_cgen_ifld_table[40]) },
 506     { 0, { (1<<MACH_BASE) } }  },
 507 /* reglist_hi_ld: 8 bit high register mask for ldm */
 508   { "reglist_hi_ld", FR30_OPERAND_REGLIST_HI_LD, HW_H_UINT, 8, 8,
 509     { 0, &(fr30_cgen_ifld_table[39]) },
 510     { 0, { (1<<MACH_BASE) } }  },
 511 /* reglist_low_st: 8 bit low register mask for stm */
 512   { "reglist_low_st", FR30_OPERAND_REGLIST_LOW_ST, HW_H_UINT, 8, 8,
 513     { 0, &(fr30_cgen_ifld_table[38]) },
 514     { 0, { (1<<MACH_BASE) } }  },
 515 /* reglist_hi_st: 8 bit high register mask for stm */
 516   { "reglist_hi_st", FR30_OPERAND_REGLIST_HI_ST, HW_H_UINT, 8, 8,
 517     { 0, &(fr30_cgen_ifld_table[37]) },
 518     { 0, { (1<<MACH_BASE) } }  },
 519 /* cc: condition codes */
 520   { "cc", FR30_OPERAND_CC, HW_H_UINT, 4, 4,
 521     { 0, &(fr30_cgen_ifld_table[7]) },
 522     { 0, { (1<<MACH_BASE) } }  },
 523 /* ccc: coprocessor calc */
 524   { "ccc", FR30_OPERAND_CCC, HW_H_UINT, 0, 8,
 525     { 0, &(fr30_cgen_ifld_table[8]) },
 526     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 527 /* nbit: negative   bit */
 528   { "nbit", FR30_OPERAND_NBIT, HW_H_NBIT, 0, 0,
 529     { 0, 0 },
 530     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 531 /* vbit: overflow   bit */
 532   { "vbit", FR30_OPERAND_VBIT, HW_H_VBIT, 0, 0,
 533     { 0, 0 },
 534     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 535 /* zbit: zero       bit */
 536   { "zbit", FR30_OPERAND_ZBIT, HW_H_ZBIT, 0, 0,
 537     { 0, 0 },
 538     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 539 /* cbit: carry      bit */
 540   { "cbit", FR30_OPERAND_CBIT, HW_H_CBIT, 0, 0,
 541     { 0, 0 },
 542     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 543 /* ibit: interrupt  bit */
 544   { "ibit", FR30_OPERAND_IBIT, HW_H_IBIT, 0, 0,
 545     { 0, 0 },
 546     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 547 /* sbit: stack      bit */
 548   { "sbit", FR30_OPERAND_SBIT, HW_H_SBIT, 0, 0,
 549     { 0, 0 },
 550     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 551 /* tbit: trace trap bit */
 552   { "tbit", FR30_OPERAND_TBIT, HW_H_TBIT, 0, 0,
 553     { 0, 0 },
 554     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 555 /* d0bit: division 0 bit */
 556   { "d0bit", FR30_OPERAND_D0BIT, HW_H_D0BIT, 0, 0,
 557     { 0, 0 },
 558     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 559 /* d1bit: division 1 bit */
 560   { "d1bit", FR30_OPERAND_D1BIT, HW_H_D1BIT, 0, 0,
 561     { 0, 0 },
 562     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 563 /* ccr: condition code bits */
 564   { "ccr", FR30_OPERAND_CCR, HW_H_CCR, 0, 0,
 565     { 0, 0 },
 566     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 567 /* scr: system condition bits */
 568   { "scr", FR30_OPERAND_SCR, HW_H_SCR, 0, 0,
 569     { 0, 0 },
 570     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 571 /* ilm: interrupt level mask */
 572   { "ilm", FR30_OPERAND_ILM, HW_H_ILM, 0, 0,
 573     { 0, 0 },
 574     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 575   { 0, 0, 0, 0, 0, {0, {0}} }
 576 };
 577
 578 #undef A
 579
 580
 581 /* The instruction table.  */
 582
 583 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
 584 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 585 #define A(a) (1 << CGEN_INSN_##a)
 586 #else
 587 #define A(a) (1 << CGEN_INSN_/**/a)
 588 #endif
 589
 590 static const CGEN_IBASE fr30_cgen_insn_table[MAX_INSNS] =
 591 {
 592   /* Special null first entry.
 593      A `num' value of zero is thus invalid.
 594      Also, the special `invalid' insn resides here.  */
 595   { 0, 0, 0, 0, {0, {0}} },
 596 /* add $Rj,$Ri */
 597   {
 598     FR30_INSN_ADD, "add", "add", 16,
 599     { 0, { (1<<MACH_BASE) } }
 600   },
 601 /* add $u4,$Ri */
 602   {
 603     FR30_INSN_ADDI, "addi", "add", 16,
 604     { 0, { (1<<MACH_BASE) } }
 605   },
 606 /* add2 $m4,$Ri */
 607   {
 608     FR30_INSN_ADD2, "add2", "add2", 16,
 609     { 0, { (1<<MACH_BASE) } }
 610   },
 611 /* addc $Rj,$Ri */
 612   {
 613     FR30_INSN_ADDC, "addc", "addc", 16,
 614     { 0, { (1<<MACH_BASE) } }
 615   },
 616 /* addn $Rj,$Ri */
 617   {
 618     FR30_INSN_ADDN, "addn", "addn", 16,
 619     { 0, { (1<<MACH_BASE) } }
 620   },
 621 /* addn $u4,$Ri */
 622   {
 623     FR30_INSN_ADDNI, "addni", "addn", 16,
 624     { 0, { (1<<MACH_BASE) } }
 625   },
 626 /* addn2 $m4,$Ri */
 627   {
 628     FR30_INSN_ADDN2, "addn2", "addn2", 16,
 629     { 0, { (1<<MACH_BASE) } }
 630   },
 631 /* sub $Rj,$Ri */
 632   {
 633     FR30_INSN_SUB, "sub", "sub", 16,
 634     { 0, { (1<<MACH_BASE) } }
 635   },
 636 /* subc $Rj,$Ri */
 637   {
 638     FR30_INSN_SUBC, "subc", "subc", 16,
 639     { 0, { (1<<MACH_BASE) } }
 640   },
 641 /* subn $Rj,$Ri */
 642   {
 643     FR30_INSN_SUBN, "subn", "subn", 16,
 644     { 0, { (1<<MACH_BASE) } }
 645   },
 646 /* cmp $Rj,$Ri */
 647   {
 648     FR30_INSN_CMP, "cmp", "cmp", 16,
 649     { 0, { (1<<MACH_BASE) } }
 650   },
 651 /* cmp $u4,$Ri */
 652   {
 653     FR30_INSN_CMPI, "cmpi", "cmp", 16,
 654     { 0, { (1<<MACH_BASE) } }
 655   },
 656 /* cmp2 $m4,$Ri */
 657   {
 658     FR30_INSN_CMP2, "cmp2", "cmp2", 16,
 659     { 0, { (1<<MACH_BASE) } }
 660   },
 661 /* and $Rj,$Ri */
 662   {
 663     FR30_INSN_AND, "and", "and", 16,
 664     { 0, { (1<<MACH_BASE) } }
 665   },
 666 /* or $Rj,$Ri */
 667   {
 668     FR30_INSN_OR, "or", "or", 16,
 669     { 0, { (1<<MACH_BASE) } }
 670   },
 671 /* eor $Rj,$Ri */
 672   {
 673     FR30_INSN_EOR, "eor", "eor", 16,
 674     { 0, { (1<<MACH_BASE) } }
 675   },
 676 /* and $Rj,@$Ri */
 677   {
 678     FR30_INSN_ANDM, "andm", "and", 16,
 679     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 680   },
 681 /* andh $Rj,@$Ri */
 682   {
 683     FR30_INSN_ANDH, "andh", "andh", 16,
 684     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 685   },
 686 /* andb $Rj,@$Ri */
 687   {
 688     FR30_INSN_ANDB, "andb", "andb", 16,
 689     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 690   },
 691 /* or $Rj,@$Ri */
 692   {
 693     FR30_INSN_ORM, "orm", "or", 16,
 694     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 695   },
 696 /* orh $Rj,@$Ri */
 697   {
 698     FR30_INSN_ORH, "orh", "orh", 16,
 699     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 700   },
 701 /* orb $Rj,@$Ri */
 702   {
 703     FR30_INSN_ORB, "orb", "orb", 16,
 704     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 705   },
 706 /* eor $Rj,@$Ri */
 707   {
 708     FR30_INSN_EORM, "eorm", "eor", 16,
 709     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 710   },
 711 /* eorh $Rj,@$Ri */
 712   {
 713     FR30_INSN_EORH, "eorh", "eorh", 16,
 714     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 715   },
 716 /* eorb $Rj,@$Ri */
 717   {
 718     FR30_INSN_EORB, "eorb", "eorb", 16,
 719     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 720   },
 721 /* bandl $u4,@$Ri */
 722   {
 723     FR30_INSN_BANDL, "bandl", "bandl", 16,
 724     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 725   },
 726 /* borl $u4,@$Ri */
 727   {
 728     FR30_INSN_BORL, "borl", "borl", 16,
 729     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 730   },
 731 /* beorl $u4,@$Ri */
 732   {
 733     FR30_INSN_BEORL, "beorl", "beorl", 16,
 734     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 735   },
 736 /* bandh $u4,@$Ri */
 737   {
 738     FR30_INSN_BANDH, "bandh", "bandh", 16,
 739     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 740   },
 741 /* borh $u4,@$Ri */
 742   {
 743     FR30_INSN_BORH, "borh", "borh", 16,
 744     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 745   },
 746 /* beorh $u4,@$Ri */
 747   {
 748     FR30_INSN_BEORH, "beorh", "beorh", 16,
 749     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 750   },
 751 /* btstl $u4,@$Ri */
 752   {
 753     FR30_INSN_BTSTL, "btstl", "btstl", 16,
 754     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 755   },
 756 /* btsth $u4,@$Ri */
 757   {
 758     FR30_INSN_BTSTH, "btsth", "btsth", 16,
 759     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 760   },
 761 /* mul $Rj,$Ri */
 762   {
 763     FR30_INSN_MUL, "mul", "mul", 16,
 764     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 765   },
 766 /* mulu $Rj,$Ri */
 767   {
 768     FR30_INSN_MULU, "mulu", "mulu", 16,
 769     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 770   },
 771 /* mulh $Rj,$Ri */
 772   {
 773     FR30_INSN_MULH, "mulh", "mulh", 16,
 774     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 775   },
 776 /* muluh $Rj,$Ri */
 777   {
 778     FR30_INSN_MULUH, "muluh", "muluh", 16,
 779     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 780   },
 781 /* div0s $Ri */
 782   {
 783     FR30_INSN_DIV0S, "div0s", "div0s", 16,
 784     { 0, { (1<<MACH_BASE) } }
 785   },
 786 /* div0u $Ri */
 787   {
 788     FR30_INSN_DIV0U, "div0u", "div0u", 16,
 789     { 0, { (1<<MACH_BASE) } }
 790   },
 791 /* div1 $Ri */
 792   {
 793     FR30_INSN_DIV1, "div1", "div1", 16,
 794     { 0, { (1<<MACH_BASE) } }
 795   },
 796 /* div2 $Ri */
 797   {
 798     FR30_INSN_DIV2, "div2", "div2", 16,
 799     { 0, { (1<<MACH_BASE) } }
 800   },
 801 /* div3 */
 802   {
 803     FR30_INSN_DIV3, "div3", "div3", 16,
 804     { 0, { (1<<MACH_BASE) } }
 805   },
 806 /* div4s */
 807   {
 808     FR30_INSN_DIV4S, "div4s", "div4s", 16,
 809     { 0, { (1<<MACH_BASE) } }
 810   },
 811 /* lsl $Rj,$Ri */
 812   {
 813     FR30_INSN_LSL, "lsl", "lsl", 16,
 814     { 0, { (1<<MACH_BASE) } }
 815   },
 816 /* lsl $u4,$Ri */
 817   {
 818     FR30_INSN_LSLI, "lsli", "lsl", 16,
 819     { 0, { (1<<MACH_BASE) } }
 820   },
 821 /* lsl2 $u4,$Ri */
 822   {
 823     FR30_INSN_LSL2, "lsl2", "lsl2", 16,
 824     { 0, { (1<<MACH_BASE) } }
 825   },
 826 /* lsr $Rj,$Ri */
 827   {
 828     FR30_INSN_LSR, "lsr", "lsr", 16,
 829     { 0, { (1<<MACH_BASE) } }
 830   },
 831 /* lsr $u4,$Ri */
 832   {
 833     FR30_INSN_LSRI, "lsri", "lsr", 16,
 834     { 0, { (1<<MACH_BASE) } }
 835   },
 836 /* lsr2 $u4,$Ri */
 837   {
 838     FR30_INSN_LSR2, "lsr2", "lsr2", 16,
 839     { 0, { (1<<MACH_BASE) } }
 840   },
 841 /* asr $Rj,$Ri */
 842   {
 843     FR30_INSN_ASR, "asr", "asr", 16,
 844     { 0, { (1<<MACH_BASE) } }
 845   },
 846 /* asr $u4,$Ri */
 847   {
 848     FR30_INSN_ASRI, "asri", "asr", 16,
 849     { 0, { (1<<MACH_BASE) } }
 850   },
 851 /* asr2 $u4,$Ri */
 852   {
 853     FR30_INSN_ASR2, "asr2", "asr2", 16,
 854     { 0, { (1<<MACH_BASE) } }
 855   },
 856 /* ldi:8 $i8,$Ri */
 857   {
 858     FR30_INSN_LDI8, "ldi8", "ldi:8", 16,
 859     { 0, { (1<<MACH_BASE) } }
 860   },
 861 /* ldi:20 $i20,$Ri */
 862   {
 863     FR30_INSN_LDI20, "ldi20", "ldi:20", 32,
 864     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 865   },
 866 /* ldi:32 $i32,$Ri */
 867   {
 868     FR30_INSN_LDI32, "ldi32", "ldi:32", 48,
 869     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 870   },
 871 /* ld @$Rj,$Ri */
 872   {
 873     FR30_INSN_LD, "ld", "ld", 16,
 874     { 0, { (1<<MACH_BASE) } }
 875   },
 876 /* lduh @$Rj,$Ri */
 877   {
 878     FR30_INSN_LDUH, "lduh", "lduh", 16,
 879     { 0, { (1<<MACH_BASE) } }
 880   },
 881 /* ldub @$Rj,$Ri */
 882   {
 883     FR30_INSN_LDUB, "ldub", "ldub", 16,
 884     { 0, { (1<<MACH_BASE) } }
 885   },
 886 /* ld @($R13,$Rj),$Ri */
 887   {
 888     FR30_INSN_LDR13, "ldr13", "ld", 16,
 889     { 0, { (1<<MACH_BASE) } }
 890   },
 891 /* lduh @($R13,$Rj),$Ri */
 892   {
 893     FR30_INSN_LDR13UH, "ldr13uh", "lduh", 16,
 894     { 0, { (1<<MACH_BASE) } }
 895   },
 896 /* ldub @($R13,$Rj),$Ri */
 897   {
 898     FR30_INSN_LDR13UB, "ldr13ub", "ldub", 16,
 899     { 0, { (1<<MACH_BASE) } }
 900   },
 901 /* ld @($R14,$disp10),$Ri */
 902   {
 903     FR30_INSN_LDR14, "ldr14", "ld", 16,
 904     { 0, { (1<<MACH_BASE) } }
 905   },
 906 /* lduh @($R14,$disp9),$Ri */
 907   {
 908     FR30_INSN_LDR14UH, "ldr14uh", "lduh", 16,
 909     { 0, { (1<<MACH_BASE) } }
 910   },
 911 /* ldub @($R14,$disp8),$Ri */
 912   {
 913     FR30_INSN_LDR14UB, "ldr14ub", "ldub", 16,
 914     { 0, { (1<<MACH_BASE) } }
 915   },
 916 /* ld @($R15,$udisp6),$Ri */
 917   {
 918     FR30_INSN_LDR15, "ldr15", "ld", 16,
 919     { 0, { (1<<MACH_BASE) } }
 920   },
 921 /* ld @$R15+,$Ri */
 922   {
 923     FR30_INSN_LDR15GR, "ldr15gr", "ld", 16,
 924     { 0, { (1<<MACH_BASE) } }
 925   },
 926 /* ld @$R15+,$Rs2 */
 927   {
 928     FR30_INSN_LDR15DR, "ldr15dr", "ld", 16,
 929     { 0, { (1<<MACH_BASE) } }
 930   },
 931 /* ld @$R15+,$ps */
 932   {
 933     FR30_INSN_LDR15PS, "ldr15ps", "ld", 16,
 934     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 935   },
 936 /* st $Ri,@$Rj */
 937   {
 938     FR30_INSN_ST, "st", "st", 16,
 939     { 0, { (1<<MACH_BASE) } }
 940   },
 941 /* sth $Ri,@$Rj */
 942   {
 943     FR30_INSN_STH, "sth", "sth", 16,
 944     { 0, { (1<<MACH_BASE) } }
 945   },
 946 /* stb $Ri,@$Rj */
 947   {
 948     FR30_INSN_STB, "stb", "stb", 16,
 949     { 0, { (1<<MACH_BASE) } }
 950   },
 951 /* st $Ri,@($R13,$Rj) */
 952   {
 953     FR30_INSN_STR13, "str13", "st", 16,
 954     { 0, { (1<<MACH_BASE) } }
 955   },
 956 /* sth $Ri,@($R13,$Rj) */
 957   {
 958     FR30_INSN_STR13H, "str13h", "sth", 16,
 959     { 0, { (1<<MACH_BASE) } }
 960   },
 961 /* stb $Ri,@($R13,$Rj) */
 962   {
 963     FR30_INSN_STR13B, "str13b", "stb", 16,
 964     { 0, { (1<<MACH_BASE) } }
 965   },
 966 /* st $Ri,@($R14,$disp10) */
 967   {
 968     FR30_INSN_STR14, "str14", "st", 16,
 969     { 0, { (1<<MACH_BASE) } }
 970   },
 971 /* sth $Ri,@($R14,$disp9) */
 972   {
 973     FR30_INSN_STR14H, "str14h", "sth", 16,
 974     { 0, { (1<<MACH_BASE) } }
 975   },
 976 /* stb $Ri,@($R14,$disp8) */
 977   {
 978     FR30_INSN_STR14B, "str14b", "stb", 16,
 979     { 0, { (1<<MACH_BASE) } }
 980   },
 981 /* st $Ri,@($R15,$udisp6) */
 982   {
 983     FR30_INSN_STR15, "str15", "st", 16,
 984     { 0, { (1<<MACH_BASE) } }
 985   },
 986 /* st $Ri,@-$R15 */
 987   {
 988     FR30_INSN_STR15GR, "str15gr", "st", 16,
 989     { 0, { (1<<MACH_BASE) } }
 990   },
 991 /* st $Rs2,@-$R15 */
 992   {
 993     FR30_INSN_STR15DR, "str15dr", "st", 16,
 994     { 0, { (1<<MACH_BASE) } }
 995   },
 996 /* st $ps,@-$R15 */
 997   {
 998     FR30_INSN_STR15PS, "str15ps", "st", 16,
 999     { 0, { (1<<MACH_BASE) } }
1000   },
1001 /* mov $Rj,$Ri */
1002   {
1003     FR30_INSN_MOV, "mov", "mov", 16,
1004     { 0, { (1<<MACH_BASE) } }
1005   },
1006 /* mov $Rs1,$Ri */
1007   {
1008     FR30_INSN_MOVDR, "movdr", "mov", 16,
1009     { 0, { (1<<MACH_BASE) } }
1010   },
1011 /* mov $ps,$Ri */
1012   {
1013     FR30_INSN_MOVPS, "movps", "mov", 16,
1014     { 0, { (1<<MACH_BASE) } }
1015   },
1016 /* mov $Ri,$Rs1 */
1017   {
1018     FR30_INSN_MOV2DR, "mov2dr", "mov", 16,
1019     { 0, { (1<<MACH_BASE) } }
1020   },
1021 /* mov $Ri,$ps */
1022   {
1023     FR30_INSN_MOV2PS, "mov2ps", "mov", 16,
1024     { 0, { (1<<MACH_BASE) } }
1025   },
1026 /* jmp @$Ri */
1027   {
1028     FR30_INSN_JMP, "jmp", "jmp", 16,
1029     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1030   },
1031 /* jmp:d @$Ri */
1032   {
1033     FR30_INSN_JMPD, "jmpd", "jmp:d", 16,
1034     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1035   },
1036 /* call @$Ri */
1037   {
1038     FR30_INSN_CALLR, "callr", "call", 16,
1039     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1040   },
1041 /* call:d @$Ri */
1042   {
1043     FR30_INSN_CALLRD, "callrd", "call:d", 16,
1044     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1045   },
1046 /* call $label12 */
1047   {
1048     FR30_INSN_CALL, "call", "call", 16,
1049     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1050   },
1051 /* call:d $label12 */
1052   {
1053     FR30_INSN_CALLD, "calld", "call:d", 16,
1054     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1055   },
1056 /* ret */
1057   {
1058     FR30_INSN_RET, "ret", "ret", 16,
1059     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1060   },
1061 /* ret:d */
1062   {
1063     FR30_INSN_RET_D, "ret:d", "ret:d", 16,
1064     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1065   },
1066 /* int $u8 */
1067   {
1068     FR30_INSN_INT, "int", "int", 16,
1069     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1070   },
1071 /* inte */
1072   {
1073     FR30_INSN_INTE, "inte", "inte", 16,
1074     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1075   },
1076 /* reti */
1077   {
1078     FR30_INSN_RETI, "reti", "reti", 16,
1079     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1080   },
1081 /* bra:d $label9 */
1082   {
1083     FR30_INSN_BRAD, "brad", "bra:d", 16,
1084     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1085   },
1086 /* bra $label9 */
1087   {
1088     FR30_INSN_BRA, "bra", "bra", 16,
1089     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1090   },
1091 /* bno:d $label9 */
1092   {
1093     FR30_INSN_BNOD, "bnod", "bno:d", 16,
1094     { 0|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1095   },
1096 /* bno $label9 */
1097   {
1098     FR30_INSN_BNO, "bno", "bno", 16,
1099     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1100   },
1101 /* beq:d $label9 */
1102   {
1103     FR30_INSN_BEQD, "beqd", "beq:d", 16,
1104     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1105   },
1106 /* beq $label9 */
1107   {
1108     FR30_INSN_BEQ, "beq", "beq", 16,
1109     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1110   },
1111 /* bne:d $label9 */
1112   {
1113     FR30_INSN_BNED, "bned", "bne:d", 16,
1114     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1115   },
1116 /* bne $label9 */
1117   {
1118     FR30_INSN_BNE, "bne", "bne", 16,
1119     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1120   },
1121 /* bc:d $label9 */
1122   {
1123     FR30_INSN_BCD, "bcd", "bc:d", 16,
1124     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1125   },
1126 /* bc $label9 */
1127   {
1128     FR30_INSN_BC, "bc", "bc", 16,
1129     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1130   },
1131 /* bnc:d $label9 */
1132   {
1133     FR30_INSN_BNCD, "bncd", "bnc:d", 16,
1134     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1135   },
1136 /* bnc $label9 */
1137   {
1138     FR30_INSN_BNC, "bnc", "bnc", 16,
1139     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1140   },
1141 /* bn:d $label9 */
1142   {
1143     FR30_INSN_BND, "bnd", "bn:d", 16,
1144     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1145   },
1146 /* bn $label9 */
1147   {
1148     FR30_INSN_BN, "bn", "bn", 16,
1149     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1150   },
1151 /* bp:d $label9 */
1152   {
1153     FR30_INSN_BPD, "bpd", "bp:d", 16,
1154     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1155   },
1156 /* bp $label9 */
1157   {
1158     FR30_INSN_BP, "bp", "bp", 16,
1159     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1160   },
1161 /* bv:d $label9 */
1162   {
1163     FR30_INSN_BVD, "bvd", "bv:d", 16,
1164     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1165   },
1166 /* bv $label9 */
1167   {
1168     FR30_INSN_BV, "bv", "bv", 16,
1169     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1170   },
1171 /* bnv:d $label9 */
1172   {
1173     FR30_INSN_BNVD, "bnvd", "bnv:d", 16,
1174     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1175   },
1176 /* bnv $label9 */
1177   {
1178     FR30_INSN_BNV, "bnv", "bnv", 16,
1179     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1180   },
1181 /* blt:d $label9 */
1182   {
1183     FR30_INSN_BLTD, "bltd", "blt:d", 16,
1184     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1185   },
1186 /* blt $label9 */
1187   {
1188     FR30_INSN_BLT, "blt", "blt", 16,
1189     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1190   },
1191 /* bge:d $label9 */
1192   {
1193     FR30_INSN_BGED, "bged", "bge:d", 16,
1194     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1195   },
1196 /* bge $label9 */
1197   {
1198     FR30_INSN_BGE, "bge", "bge", 16,
1199     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1200   },
1201 /* ble:d $label9 */
1202   {
1203     FR30_INSN_BLED, "bled", "ble:d", 16,
1204     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1205   },
1206 /* ble $label9 */
1207   {
1208     FR30_INSN_BLE, "ble", "ble", 16,
1209     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1210   },
1211 /* bgt:d $label9 */
1212   {
1213     FR30_INSN_BGTD, "bgtd", "bgt:d", 16,
1214     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1215   },
1216 /* bgt $label9 */
1217   {
1218     FR30_INSN_BGT, "bgt", "bgt", 16,
1219     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1220   },
1221 /* bls:d $label9 */
1222   {
1223     FR30_INSN_BLSD, "blsd", "bls:d", 16,
1224     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1225   },
1226 /* bls $label9 */
1227   {
1228     FR30_INSN_BLS, "bls", "bls", 16,
1229     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1230   },
1231 /* bhi:d $label9 */
1232   {
1233     FR30_INSN_BHID, "bhid", "bhi:d", 16,
1234     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1235   },
1236 /* bhi $label9 */
1237   {
1238     FR30_INSN_BHI, "bhi", "bhi", 16,
1239     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1240   },
1241 /* dmov $R13,@$dir10 */
1242   {
1243     FR30_INSN_DMOVR13, "dmovr13", "dmov", 16,
1244     { 0, { (1<<MACH_BASE) } }
1245   },
1246 /* dmovh $R13,@$dir9 */
1247   {
1248     FR30_INSN_DMOVR13H, "dmovr13h", "dmovh", 16,
1249     { 0, { (1<<MACH_BASE) } }
1250   },
1251 /* dmovb $R13,@$dir8 */
1252   {
1253     FR30_INSN_DMOVR13B, "dmovr13b", "dmovb", 16,
1254     { 0, { (1<<MACH_BASE) } }
1255   },
1256 /* dmov @$R13+,@$dir10 */
1257   {
1258     FR30_INSN_DMOVR13PI, "dmovr13pi", "dmov", 16,
1259     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1260   },
1261 /* dmovh @$R13+,@$dir9 */
1262   {
1263     FR30_INSN_DMOVR13PIH, "dmovr13pih", "dmovh", 16,
1264     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1265   },
1266 /* dmovb @$R13+,@$dir8 */
1267   {
1268     FR30_INSN_DMOVR13PIB, "dmovr13pib", "dmovb", 16,
1269     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1270   },
1271 /* dmov @$R15+,@$dir10 */
1272   {
1273     FR30_INSN_DMOVR15PI, "dmovr15pi", "dmov", 16,
1274     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1275   },
1276 /* dmov @$dir10,$R13 */
1277   {
1278     FR30_INSN_DMOV2R13, "dmov2r13", "dmov", 16,
1279     { 0, { (1<<MACH_BASE) } }
1280   },
1281 /* dmovh @$dir9,$R13 */
1282   {
1283     FR30_INSN_DMOV2R13H, "dmov2r13h", "dmovh", 16,
1284     { 0, { (1<<MACH_BASE) } }
1285   },
1286 /* dmovb @$dir8,$R13 */
1287   {
1288     FR30_INSN_DMOV2R13B, "dmov2r13b", "dmovb", 16,
1289     { 0, { (1<<MACH_BASE) } }
1290   },
1291 /* dmov @$dir10,@$R13+ */
1292   {
1293     FR30_INSN_DMOV2R13PI, "dmov2r13pi", "dmov", 16,
1294     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1295   },
1296 /* dmovh @$dir9,@$R13+ */
1297   {
1298     FR30_INSN_DMOV2R13PIH, "dmov2r13pih", "dmovh", 16,
1299     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1300   },
1301 /* dmovb @$dir8,@$R13+ */
1302   {
1303     FR30_INSN_DMOV2R13PIB, "dmov2r13pib", "dmovb", 16,
1304     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1305   },
1306 /* dmov @$dir10,@-$R15 */
1307   {
1308     FR30_INSN_DMOV2R15PD, "dmov2r15pd", "dmov", 16,
1309     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1310   },
1311 /* ldres @$Ri+,$u4 */
1312   {
1313     FR30_INSN_LDRES, "ldres", "ldres", 16,
1314     { 0, { (1<<MACH_BASE) } }
1315   },
1316 /* stres $u4,@$Ri+ */
1317   {
1318     FR30_INSN_STRES, "stres", "stres", 16,
1319     { 0, { (1<<MACH_BASE) } }
1320   },
1321 /* copop $u4c,$ccc,$CRj,$CRi */
1322   {
1323     FR30_INSN_COPOP, "copop", "copop", 32,
1324     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1325   },
1326 /* copld $u4c,$ccc,$Rjc,$CRi */
1327   {
1328     FR30_INSN_COPLD, "copld", "copld", 32,
1329     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1330   },
1331 /* copst $u4c,$ccc,$CRj,$Ric */
1332   {
1333     FR30_INSN_COPST, "copst", "copst", 32,
1334     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1335   },
1336 /* copsv $u4c,$ccc,$CRj,$Ric */
1337   {
1338     FR30_INSN_COPSV, "copsv", "copsv", 32,
1339     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1340   },
1341 /* nop */
1342   {
1343     FR30_INSN_NOP, "nop", "nop", 16,
1344     { 0, { (1<<MACH_BASE) } }
1345   },
1346 /* andccr $u8 */
1347   {
1348     FR30_INSN_ANDCCR, "andccr", "andccr", 16,
1349     { 0, { (1<<MACH_BASE) } }
1350   },
1351 /* orccr $u8 */
1352   {
1353     FR30_INSN_ORCCR, "orccr", "orccr", 16,
1354     { 0, { (1<<MACH_BASE) } }
1355   },
1356 /* stilm $u8 */
1357   {
1358     FR30_INSN_STILM, "stilm", "stilm", 16,
1359     { 0, { (1<<MACH_BASE) } }
1360   },
1361 /* addsp $s10 */
1362   {
1363     FR30_INSN_ADDSP, "addsp", "addsp", 16,
1364     { 0, { (1<<MACH_BASE) } }
1365   },
1366 /* extsb $Ri */
1367   {
1368     FR30_INSN_EXTSB, "extsb", "extsb", 16,
1369     { 0, { (1<<MACH_BASE) } }
1370   },
1371 /* extub $Ri */
1372   {
1373     FR30_INSN_EXTUB, "extub", "extub", 16,
1374     { 0, { (1<<MACH_BASE) } }
1375   },
1376 /* extsh $Ri */
1377   {
1378     FR30_INSN_EXTSH, "extsh", "extsh", 16,
1379     { 0, { (1<<MACH_BASE) } }
1380   },
1381 /* extuh $Ri */
1382   {
1383     FR30_INSN_EXTUH, "extuh", "extuh", 16,
1384     { 0, { (1<<MACH_BASE) } }
1385   },
1386 /* ldm0 ($reglist_low_ld) */
1387   {
1388     FR30_INSN_LDM0, "ldm0", "ldm0", 16,
1389     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1390   },
1391 /* ldm1 ($reglist_hi_ld) */
1392   {
1393     FR30_INSN_LDM1, "ldm1", "ldm1", 16,
1394     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1395   },
1396 /* stm0 ($reglist_low_st) */
1397   {
1398     FR30_INSN_STM0, "stm0", "stm0", 16,
1399     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1400   },
1401 /* stm1 ($reglist_hi_st) */
1402   {
1403     FR30_INSN_STM1, "stm1", "stm1", 16,
1404     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1405   },
1406 /* enter $u10 */
1407   {
1408     FR30_INSN_ENTER, "enter", "enter", 16,
1409     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1410   },
1411 /* leave */
1412   {
1413     FR30_INSN_LEAVE, "leave", "leave", 16,
1414     { 0, { (1<<MACH_BASE) } }
1415   },
1416 /* xchb @$Rj,$Ri */
1417   {
1418     FR30_INSN_XCHB, "xchb", "xchb", 16,
1419     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1420   },
1421 };
1422
1423 #undef OP
1424 #undef A
1425
1426 /* Initialize anything needed to be done once, before any cpu_open call.  */
1427 static void init_tables PARAMS ((void));
1428
1429 static void
1430 init_tables ()
1431 {
1432 }
1433
1434 static const CGEN_MACH * lookup_mach_via_bfd_name
1435   PARAMS ((const CGEN_MACH *, const char *));
1436 static void build_hw_table  PARAMS ((CGEN_CPU_TABLE *));
1437 static void build_ifield_table  PARAMS ((CGEN_CPU_TABLE *));
1438 static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
1439 static void build_insn_table    PARAMS ((CGEN_CPU_TABLE *));
1440 static void fr30_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
1441
1442 /* Subroutine of fr30_cgen_cpu_open to look up a mach via its bfd name.  */
1443
1444 static const CGEN_MACH *
1445 lookup_mach_via_bfd_name (table, name)
1446      const CGEN_MACH *table;
1447      const char *name;
1448 {
1449   while (table->name)
1450     {
1451       if (strcmp (name, table->bfd_name) == 0)
1452         return table;
1453       ++table;
1454     }
1455   abort ();
1456 }
1457
1458 /* Subroutine of fr30_cgen_cpu_open to build the hardware table.  */
1459
1460 static void
1461 build_hw_table (cd)
1462      CGEN_CPU_TABLE *cd;
1463 {
1464   int i;
1465   int machs = cd->machs;
1466   const CGEN_HW_ENTRY *init = & fr30_cgen_hw_table[0];
1467   /* MAX_HW is only an upper bound on the number of selected entries.
1468      However each entry is indexed by it's enum so there can be holes in
1469      the table.  */
1470   const CGEN_HW_ENTRY **selected =
1471     (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
1472
1473   cd->hw_table.init_entries = init;
1474   cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
1475   memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
1476   /* ??? For now we just use machs to determine which ones we want.  */
1477   for (i = 0; init[i].name != NULL; ++i)
1478     if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
1479         & machs)
1480       selected[init[i].type] = &init[i];
1481   cd->hw_table.entries = selected;
1482   cd->hw_table.num_entries = MAX_HW;
1483 }
1484
1485 /* Subroutine of fr30_cgen_cpu_open to build the hardware table.  */
1486
1487 static void
1488 build_ifield_table (cd)
1489      CGEN_CPU_TABLE *cd;
1490 {
1491   cd->ifld_table = & fr30_cgen_ifld_table[0];
1492 }
1493
1494 /* Subroutine of fr30_cgen_cpu_open to build the hardware table.  */
1495
1496 static void
1497 build_operand_table (cd)
1498      CGEN_CPU_TABLE *cd;
1499 {
1500   int i;
1501   int machs = cd->machs;
1502   const CGEN_OPERAND *init = & fr30_cgen_operand_table[0];
1503   /* MAX_OPERANDS is only an upper bound on the number of selected entries.
1504      However each entry is indexed by it's enum so there can be holes in
1505      the table.  */
1506   const CGEN_OPERAND **selected =
1507     (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1508
1509   cd->operand_table.init_entries = init;
1510   cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
1511   memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1512   /* ??? For now we just use mach to determine which ones we want.  */
1513   for (i = 0; init[i].name != NULL; ++i)
1514     if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
1515         & machs)
1516       selected[init[i].type] = &init[i];
1517   cd->operand_table.entries = selected;
1518   cd->operand_table.num_entries = MAX_OPERANDS;
1519 }
1520
1521 /* Subroutine of fr30_cgen_cpu_open to build the hardware table.
1522    ??? This could leave out insns not supported by the specified mach/isa,
1523    but that would cause errors like "foo only supported by bar" to become
1524    "unknown insn", so for now we include all insns and require the app to
1525    do the checking later.
1526    ??? On the other hand, parsing of such insns may require their hardware or
1527    operand elements to be in the table [which they mightn't be].  */
1528
1529 static void
1530 build_insn_table (cd)
1531      CGEN_CPU_TABLE *cd;
1532 {
1533   int i;
1534   const CGEN_IBASE *ib = & fr30_cgen_insn_table[0];
1535   CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
1536
1537   memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
1538   for (i = 0; i < MAX_INSNS; ++i)
1539     insns[i].base = &ib[i];
1540   cd->insn_table.init_entries = insns;
1541   cd->insn_table.entry_size = sizeof (CGEN_IBASE);
1542   cd->insn_table.num_init_entries = MAX_INSNS;
1543 }
1544
1545 /* Subroutine of fr30_cgen_cpu_open to rebuild the tables.  */
1546
1547 static void
1548 fr30_cgen_rebuild_tables (cd)
1549      CGEN_CPU_TABLE *cd;
1550 {
1551   int i;
1552   unsigned int isas = cd->isas;
1553   unsigned int machs = cd->machs;
1554
1555   cd->int_insn_p = CGEN_INT_INSN_P;
1556
1557   /* Data derived from the isa spec.  */
1558 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
1559   cd->default_insn_bitsize = UNSET;
1560   cd->base_insn_bitsize = UNSET;
1561   cd->min_insn_bitsize = 65535; /* some ridiculously big number */
1562   cd->max_insn_bitsize = 0;
1563   for (i = 0; i < MAX_ISAS; ++i)
1564     if (((1 << i) & isas) != 0)
1565       {
1566         const CGEN_ISA *isa = & fr30_cgen_isa_table[i];
1567
1568         /* Default insn sizes of all selected isas must be
1569            equal or we set the result to 0, meaning "unknown".  */
1570         if (cd->default_insn_bitsize == UNSET)
1571           cd->default_insn_bitsize = isa->default_insn_bitsize;
1572         else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
1573           ; /* this is ok */
1574         else
1575           cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
1576
1577         /* Base insn sizes of all selected isas must be equal
1578            or we set the result to 0, meaning "unknown".  */
1579         if (cd->base_insn_bitsize == UNSET)
1580           cd->base_insn_bitsize = isa->base_insn_bitsize;
1581         else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
1582           ; /* this is ok */
1583         else
1584           cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
1585
1586         /* Set min,max insn sizes.  */
1587         if (isa->min_insn_bitsize < cd->min_insn_bitsize)
1588           cd->min_insn_bitsize = isa->min_insn_bitsize;
1589         if (isa->max_insn_bitsize > cd->max_insn_bitsize)
1590           cd->max_insn_bitsize = isa->max_insn_bitsize;
1591       }
1592
1593   /* Data derived from the mach spec.  */
1594   for (i = 0; i < MAX_MACHS; ++i)
1595     if (((1 << i) & machs) != 0)
1596       {
1597         const CGEN_MACH *mach = & fr30_cgen_mach_table[i];
1598
1599         if (mach->insn_chunk_bitsize != 0)
1600         {
1601           if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
1602             {
1603               fprintf (stderr, "fr30_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
1604                        cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
1605               abort ();
1606             }
1607
1608           cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
1609         }
1610       }
1611
1612   /* Determine which hw elements are used by MACH.  */
1613   build_hw_table (cd);
1614
1615   /* Build the ifield table.  */
1616   build_ifield_table (cd);
1617
1618   /* Determine which operands are used by MACH/ISA.  */
1619   build_operand_table (cd);
1620
1621   /* Build the instruction table.  */
1622   build_insn_table (cd);
1623 }
1624
1625 /* Initialize a cpu table and return a descriptor.
1626    It's much like opening a file, and must be the first function called.
1627    The arguments are a set of (type/value) pairs, terminated with
1628    CGEN_CPU_OPEN_END.
1629
1630    Currently supported values:
1631    CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
1632    CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
1633    CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
1634    CGEN_CPU_OPEN_ENDIAN:  specify endian choice
1635    CGEN_CPU_OPEN_END:     terminates arguments
1636
1637    ??? Simultaneous multiple isas might not make sense, but it's not (yet)
1638    precluded.
1639
1640    ??? We only support ISO C stdargs here, not K&R.
1641    Laziness, plus experiment to see if anything requires K&R - eventually
1642    K&R will no longer be supported - e.g. GDB is currently trying this.  */
1643
1644 CGEN_CPU_DESC
1645 fr30_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
1646 {
1647   CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
1648   static int init_p;
1649   unsigned int isas = 0;  /* 0 = "unspecified" */
1650   unsigned int machs = 0; /* 0 = "unspecified" */
1651   enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
1652   va_list ap;
1653
1654   if (! init_p)
1655     {
1656       init_tables ();
1657       init_p = 1;
1658     }
1659
1660   memset (cd, 0, sizeof (*cd));
1661
1662   va_start (ap, arg_type);
1663   while (arg_type != CGEN_CPU_OPEN_END)
1664     {
1665       switch (arg_type)
1666         {
1667         case CGEN_CPU_OPEN_ISAS :
1668           isas = va_arg (ap, unsigned int);
1669           break;
1670         case CGEN_CPU_OPEN_MACHS :
1671           machs = va_arg (ap, unsigned int);
1672           break;
1673         case CGEN_CPU_OPEN_BFDMACH :
1674           {
1675             const char *name = va_arg (ap, const char *);
1676             const CGEN_MACH *mach =
1677               lookup_mach_via_bfd_name (fr30_cgen_mach_table, name);
1678
1679             machs |= 1 << mach->num;
1680             break;
1681           }
1682         case CGEN_CPU_OPEN_ENDIAN :
1683           endian = va_arg (ap, enum cgen_endian);
1684           break;
1685         default :
1686           fprintf (stderr, "fr30_cgen_cpu_open: unsupported argument `%d'\n",
1687                    arg_type);
1688           abort (); /* ??? return NULL? */
1689         }
1690       arg_type = va_arg (ap, enum cgen_cpu_open_arg);
1691     }
1692   va_end (ap);
1693
1694   /* mach unspecified means "all" */
1695   if (machs == 0)
1696     machs = (1 << MAX_MACHS) - 1;
1697   /* base mach is always selected */
1698   machs |= 1;
1699   /* isa unspecified means "all" */
1700   if (isas == 0)
1701     isas = (1 << MAX_ISAS) - 1;
1702   if (endian == CGEN_ENDIAN_UNKNOWN)
1703     {
1704       /* ??? If target has only one, could have a default.  */
1705       fprintf (stderr, "fr30_cgen_cpu_open: no endianness specified\n");
1706       abort ();
1707     }
1708
1709   cd->isas = isas;
1710   cd->machs = machs;
1711   cd->endian = endian;
1712   /* FIXME: for the sparc case we can determine insn-endianness statically.
1713      The worry here is where both data and insn endian can be independently
1714      chosen, in which case this function will need another argument.
1715      Actually, will want to allow for more arguments in the future anyway.  */
1716   cd->insn_endian = endian;
1717
1718   /* Table (re)builder.  */
1719   cd->rebuild_tables = fr30_cgen_rebuild_tables;
1720   fr30_cgen_rebuild_tables (cd);
1721
1722   /* Default to not allowing signed overflow.  */
1723   cd->signed_overflow_ok_p = 0;
1724
1725   return (CGEN_CPU_DESC) cd;
1726 }
1727
1728 /* Cover fn to fr30_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
1729    MACH_NAME is the bfd name of the mach.  */
1730
1731 CGEN_CPU_DESC
1732 fr30_cgen_cpu_open_1 (mach_name, endian)
1733      const char *mach_name;
1734      enum cgen_endian endian;
1735 {
1736   return fr30_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
1737                                CGEN_CPU_OPEN_ENDIAN, endian,
1738                                CGEN_CPU_OPEN_END);
1739 }
1740
1741 /* Close a cpu table.
1742    ??? This can live in a machine independent file, but there's currently
1743    no place to put this file (there's no libcgen).  libopcodes is the wrong
1744    place as some simulator ports use this but they don't use libopcodes.  */
1745
1746 void
1747 fr30_cgen_cpu_close (cd)
1748      CGEN_CPU_DESC cd;
1749 {
1750   unsigned int i;
1751   CGEN_INSN *insns;
1752
1753   if (cd->macro_insn_table.init_entries)
1754     {
1755       insns = cd->macro_insn_table.init_entries;
1756       for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
1757         {
1758           if (CGEN_INSN_RX ((insns)))
1759             regfree(CGEN_INSN_RX (insns));
1760         }
1761     }
1762
1763   if (cd->insn_table.init_entries)
1764     {
1765       insns = cd->insn_table.init_entries;
1766       for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
1767         {
1768           if (CGEN_INSN_RX (insns))
1769             regfree(CGEN_INSN_RX (insns));
1770         }
1771     }
1772
1773
1774
1775   if (cd->macro_insn_table.init_entries)
1776     free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
1777
1778   if (cd->insn_table.init_entries)
1779     free ((CGEN_INSN *) cd->insn_table.init_entries);
1780
1781   if (cd->hw_table.entries)
1782     free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
1783
1784   if (cd->operand_table.entries)
1785     free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
1786
1787   free (cd);
1788 }
1789