| blob | 10c93e229b6fbb2f7aa69711932a79b440913f69 |
1 /* 32-bit ELF support for ARM
2 Copyright (C) 1998-2025 Free Software Foundation, Inc.
4 This file is part of BFD, the Binary File Descriptor library.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 #include <limits.h>
34 /* Return the relocation section associated with NAME. HTAB is the
35 bfd's elf32_arm_link_hash_entry. */
36 #define RELOC_SECTION(HTAB, NAME) \
39 /* Return size of a relocation entry. HTAB is the bfd's
40 elf32_arm_link_hash_entry. */
41 #define RELOC_SIZE(HTAB) \
42 ((HTAB)->use_rel \
43 ? sizeof (Elf32_External_Rel) \
44 : sizeof (Elf32_External_Rela))
46 /* Return function to swap relocations in. HTAB is the bfd's
47 elf32_arm_link_hash_entry. */
48 #define SWAP_RELOC_IN(HTAB) \
49 ((HTAB)->use_rel \
50 ? bfd_elf32_swap_reloc_in \
51 : bfd_elf32_swap_reloca_in)
53 /* Return function to swap relocations out. HTAB is the bfd's
54 elf32_arm_link_hash_entry. */
55 #define SWAP_RELOC_OUT(HTAB) \
56 ((HTAB)->use_rel \
57 ? bfd_elf32_swap_reloc_out \
58 : bfd_elf32_swap_reloca_out)
60 #define elf_info_to_howto NULL
61 #define elf_info_to_howto_rel elf32_arm_info_to_howto
63 #define ARM_ELF_ABI_VERSION 0
64 #define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
66 /* The Adjusted Place, as defined by AAELF. */
67 #define Pa(X) ((X) & 0xfffffffc)
74 /* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
75 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
76 in that slot. */
79 {
80 /* No relocation. */
109 /* 32 bit absolute */
124 /* standard 32bit pc-relative reloc */
139 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
154 /* 16 bit absolute */
169 /* 12 bit absolute */
198 /* 8 bit absolute */
297 /* BLX instruction for the ARM. */
312 /* BLX instruction for the Thumb. */
327 /* Dynamic TLS relocations. */
371 /* Relocs used in ARM Linux */
835 /* These are declared as 13-bit signed relocations because we can
836 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
837 versa. */
894 /* Group relocations. */
1274 /* End of group relocations. */
1488 /* GNU extension to record C++ vtable member usage */
1503 /* GNU extension to record C++ vtable hierarchy */
1546 /* TLS relocations */
1659 /* 112-127 private relocations. */
1677 /* R_ARM_ME_TOO, obsolete. */
1747 /* Relocations for Armv8.1-M Mainline. */
1787 };
1789 /* 160 onwards: */
1791 {
1896 };
1898 /* 249-255 extended, currently unused, relocations: */
1900 {
1956 };
1960 {
1973 }
1975 static bool
1978 {
1983 {
1984 /* xgettext:c-format */
1989 }
1991 }
1993 struct elf32_arm_reloc_map
1994 {
1995 bfd_reloc_code_real_type bfd_reloc_val;
1997 };
1999 /* All entries in this list must also be present in elf32_arm_howto_table. */
2001 {
2102 };
2106 bfd_reloc_code_real_type code)
2107 {
2115 }
2120 {
2139 }
2141 /* Support for core dump NOTE sections. */
2143 static bool
2145 {
2150 {
2155 /* pr_cursig */
2158 /* pr_pid */
2161 /* pr_reg */
2166 }
2168 /* Make a ".reg/999" section. */
2171 }
2173 static bool
2175 {
2177 {
2188 }
2190 /* Note that for some reason, a spurious space is tacked
2191 onto the end of the args in some (at least one anyway)
2192 implementations, so strip it off if it exists. */
2193 {
2199 }
2202 }
2207 {
2209 {
2214 {
2221 #if GCC_VERSION == 8000 || GCC_VERSION == 8001
2222 DIAGNOSTIC_PUSH;
2223 /* GCC 8.0 and 8.1 warn about 80 equals destination size with
2224 -Wstringop-truncation:
2225 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85643
2226 */
2227 DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION;
2228 #endif
2230 #if GCC_VERSION == 8000 || GCC_VERSION == 8001
2231 DIAGNOSTIC_POP;
2232 #endif
2237 }
2240 {
2259 }
2260 }
2261 }
2263 #define TARGET_LITTLE_SYM arm_elf32_le_vec
2265 #define TARGET_BIG_SYM arm_elf32_be_vec
2268 #define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2269 #define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
2270 #define elf_backend_write_core_note elf32_arm_nabi_write_core_note
2275 /* In lieu of proper flags, assume all EABIv4 or later objects are
2276 interworkable. */
2277 #define INTERWORK_FLAG(abfd) \
2278 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
2279 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2280 || ((abfd)->flags & BFD_LINKER_CREATED))
2282 /* The linker script knows the section names for placement.
2283 The entry_names are used to do simple name mangling on the stubs.
2284 Given a function name, and its type, the stub can be found. The
2285 name can be changed. The only requirement is the %s be present. */
2307 /* The name of the dynamic interpreter. This is put in the .interp
2308 section. */
2311 /* FDPIC default stack size. */
2312 #define DEFAULT_STACK_SIZE 0x8000
2315 {
2319 };
2322 {
2330 + dl_tlsdesc_lazy_resolver(GOT) */
2332 };
2334 /* NOTE: [Thumb nop sequence]
2335 When adding code that transitions from Thumb to Arm the instruction that
2336 should be used for the alignment padding should be 0xe7fd (b .-2) instead of
2337 a nop for performance reasons. */
2339 /* ARM FDPIC PLT entry. */
2340 /* The last 5 words contain PLT lazy fragment code and data. */
2342 {
2353 };
2355 /* Thumb FDPIC PLT entry. */
2356 /* The last 5 words contain PLT lazy fragment code and data. */
2358 {
2369 };
2371 #ifdef FOUR_WORD_PLT
2373 /* The first entry in a procedure linkage table looks like
2374 this. It is set up so that any shared library function that is
2375 called before the relocation has been set up calls the dynamic
2376 linker first. */
2378 {
2383 };
2385 /* Subsequent entries in a procedure linkage table look like
2386 this. */
2388 {
2393 };
2397 /* The first entry in a procedure linkage table looks like
2398 this. It is set up so that any shared library function that is
2399 called before the relocation has been set up calls the dynamic
2400 linker first. */
2402 {
2408 };
2410 /* By default subsequent entries in a procedure linkage table look like
2411 this. Offsets that don't fit into 28 bits will cause link error. */
2413 {
2417 };
2419 /* When explicitly asked, we'll use this "long" entry format
2420 which can cope with arbitrary displacements. */
2422 {
2427 };
2433 /* The first entry in a procedure linkage table looks like this.
2434 It is set up so that any shared library function that is called before the
2435 relocation has been set up calls the dynamic linker first. */
2437 {
2438 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2439 an instruction maybe encoded to one or two array elements. */
2442 /* add lr, pc */
2445 };
2447 /* Subsequent entries in a procedure linkage table for thumb only target
2448 look like this. */
2450 {
2451 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2452 an instruction maybe encoded to one or two array elements. */
2457 /* b .-4 */
2458 };
2460 /* The format of the first entry in the procedure linkage table
2461 for a VxWorks executable. */
2463 {
2468 };
2470 /* The format of subsequent entries in a VxWorks executable. */
2472 {
2479 };
2481 /* The format of entries in a VxWorks shared library. */
2483 {
2490 };
2492 /* An initial stub used if the PLT entry is referenced from Thumb code. */
2493 #define PLT_THUMB_STUB_SIZE 4
2495 {
2498 };
2500 /* The first entry in a procedure linkage table looks like
2501 this. It is set up so that any shared library function that is
2502 called before the relocation has been set up calls the dynamic
2503 linker first. */
2505 {
2506 /* First bundle: */
2511 /* Second bundle: */
2516 /* Third bundle: */
2520 /* .Lplt_tail: */
2522 /* Fourth bundle: */
2527 };
2528 #define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2530 /* Subsequent entries in a procedure linkage table look like this. */
2532 {
2537 };
2539 /* PR 28924:
2540 There was a bug due to too high values of THM_MAX_FWD_BRANCH_OFFSET and
2541 THM2_MAX_FWD_BRANCH_OFFSET. The first macro concerns the case when Thumb-2
2542 is not available, and second macro when Thumb-2 is available. Among other
2543 things, they affect the range of branches represented as BLX instructions
2544 in Encoding T2 defined in Section A8.8.25 of the ARM Architecture
2545 Reference Manual ARMv7-A and ARMv7-R edition issue C.d. Such branches are
2546 specified there to have a maximum forward offset that is a multiple of 4.
2547 Previously, the respective values defined here were multiples of 2 but not
2548 4 and they are included in comments for reference. */
2549 #define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2550 #define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2551 #define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) - 4 + 4)
2552 /* #def THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) - 2 + 4) */
2553 #define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2554 #define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 4) + 4)
2555 /* #def THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4) */
2556 #define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
2557 #define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2558 #define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
2560 enum stub_insn_type
2561 {
2563 THUMB32_TYPE,
2564 ARM_TYPE,
2565 DATA_TYPE
2566 };
2568 #define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2569 /* A bit of a hack. A Thumb conditional branch, in which the proper condition
2570 is inserted in arm_build_one_stub(). */
2571 #define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2572 #define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
2573 #define THUMB32_MOVT(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVT_ABS, 0}
2574 #define THUMB32_MOVW(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVW_ABS_NC, 0}
2575 #define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2576 #define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2577 #define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2578 #define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
2581 {
2582 bfd_vma data;
2588 /* See note [Thumb nop sequence] when adding a veneer. */
2590 /* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2591 to reach the stub if necessary. */
2593 {
2596 };
2598 /* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2599 available. */
2601 {
2605 };
2607 /* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
2609 {
2617 };
2619 /* Thumb -> Thumb long branch stub in thumb2 encoding. Used on armv7. */
2621 {
2624 };
2626 /* Thumb -> Thumb long branch stub. Used for PureCode sections on Thumb2
2627 M-profile architectures. */
2629 {
2634 /* The nop is added to ensure alignment of following stubs in the section. */
2635 };
2637 /* V4T Thumb -> Thumb long branch stub. Using the stack is not
2638 allowed. */
2640 {
2646 };
2648 /* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2649 available. */
2651 {
2656 };
2658 /* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2659 one, when the destination is close enough. */
2661 {
2665 };
2667 /* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
2668 blx to reach the stub if necessary. */
2670 {
2674 };
2676 /* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2677 blx to reach the stub if necessary. We can not add into pc;
2678 it is not guaranteed to mode switch (different in ARMv6 and
2679 ARMv7). */
2681 {
2686 };
2688 /* V4T ARM -> ARM long branch stub, PIC. */
2690 {
2695 };
2697 /* V4T Thumb -> ARM long branch stub, PIC. */
2699 {
2705 };
2707 /* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2708 architectures. */
2710 {
2718 };
2720 /* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2721 allowed. */
2723 {
2730 };
2732 /* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2733 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2735 {
2739 };
2741 /* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2742 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2744 {
2750 };
2752 /* NaCl ARM -> ARM long branch stub. */
2754 {
2763 };
2765 /* NaCl ARM -> ARM long branch stub, PIC. */
2767 {
2776 };
2778 /* Stub used for transition to secure state (aka SG veneer). */
2780 {
2783 };
2786 /* Cortex-A8 erratum-workaround stubs. */
2788 /* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2789 can't use a conditional branch to reach this stub). */
2792 {
2796 };
2798 /* Stub used for b.w and bl.w instructions. */
2801 {
2803 };
2806 {
2808 };
2810 /* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2811 instruction (which switches to ARM mode) to point to this stub. Jump to the
2812 real destination using an ARM-mode branch. */
2815 {
2817 };
2819 /* For each section group there can be a specially created linker section
2820 to hold the stubs for that group. The name of the stub section is based
2821 upon the name of another section within that group with the suffix below
2822 applied.
2824 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2825 create what appeared to be a linker stub section when it actually
2826 contained user code/data. For example, consider this fragment:
2828 const char * stubborn_problems[] = { "np" };
2830 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2831 section called:
2833 .data.rel.local.stubborn_problems
2835 This then causes problems in arm32_arm_build_stubs() as it triggers:
2837 // Ignore non-stub sections.
2838 if (!strstr (stub_sec->name, STUB_SUFFIX))
2839 continue;
2841 And so the section would be ignored instead of being processed. Hence
2842 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2843 C identifier. */
2846 /* One entry per long/short branch stub defined above. */
2847 #define DEF_STUBS \
2848 DEF_STUB (long_branch_any_any) \
2849 DEF_STUB (long_branch_v4t_arm_thumb) \
2850 DEF_STUB (long_branch_thumb_only) \
2851 DEF_STUB (long_branch_v4t_thumb_thumb) \
2852 DEF_STUB (long_branch_v4t_thumb_arm) \
2853 DEF_STUB (short_branch_v4t_thumb_arm) \
2854 DEF_STUB (long_branch_any_arm_pic) \
2855 DEF_STUB (long_branch_any_thumb_pic) \
2856 DEF_STUB (long_branch_v4t_thumb_thumb_pic) \
2857 DEF_STUB (long_branch_v4t_arm_thumb_pic) \
2858 DEF_STUB (long_branch_v4t_thumb_arm_pic) \
2859 DEF_STUB (long_branch_thumb_only_pic) \
2860 DEF_STUB (long_branch_any_tls_pic) \
2861 DEF_STUB (long_branch_v4t_thumb_tls_pic) \
2862 DEF_STUB (long_branch_arm_nacl) \
2863 DEF_STUB (long_branch_arm_nacl_pic) \
2864 DEF_STUB (cmse_branch_thumb_only) \
2865 DEF_STUB (a8_veneer_b_cond) \
2866 DEF_STUB (a8_veneer_b) \
2867 DEF_STUB (a8_veneer_bl) \
2868 DEF_STUB (a8_veneer_blx) \
2869 DEF_STUB (long_branch_thumb2_only) \
2870 DEF_STUB (long_branch_thumb2_only_pure)
2872 #define DEF_STUB(x) arm_stub_##x,
2873 enum elf32_arm_stub_type
2874 {
2875 arm_stub_none,
2876 DEF_STUBS
2877 max_stub_type
2878 };
2879 #undef DEF_STUB
2881 /* Note the first a8_veneer type. */
2885 {
2890 #define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
2892 {
2894 DEF_STUBS
2895 };
2897 struct elf32_arm_stub_hash_entry
2898 {
2899 /* Base hash table entry structure. */
2902 /* The stub section. */
2905 /* Offset within stub_sec of the beginning of this stub. */
2906 bfd_vma stub_offset;
2908 /* Given the symbol's value and its section we can determine its final
2909 value when building the stubs (so the stub knows where to jump). */
2910 bfd_vma target_value;
2913 /* Same as above but for the source of the branch to the stub. Used for
2914 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2915 such, source section does not need to be recorded since Cortex-A8 erratum
2916 workaround stubs are only generated when both source and target are in the
2917 same section. */
2918 bfd_vma source_value;
2920 /* The instruction which caused this stub to be generated (only valid for
2921 Cortex-A8 erratum workaround stubs at present). */
2924 /* The stub type. */
2926 /* Its encoding size in bytes. */
2928 /* Its template. */
2930 /* The size of the template (number of entries). */
2933 /* The symbol table entry, if any, that this was derived from. */
2936 /* Type of branch. */
2939 /* Where this stub is being called from, or, in the case of combined
2940 stub sections, the first input section in the group. */
2943 /* The name for the local symbol at the start of this stub. The
2944 stub name in the hash table has to be unique; this does not, so
2945 it can be friendlier. */
2947 };
2949 /* Used to build a map of a section. This is required for mixed-endian
2950 code/data. */
2953 {
2954 bfd_vma vma;
2956 }
2957 elf32_arm_section_map;
2959 /* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2962 {
2963 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2964 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2965 VFP11_ERRATUM_ARM_VENEER,
2966 VFP11_ERRATUM_THUMB_VENEER
2967 }
2968 elf32_vfp11_erratum_type;
2971 {
2973 bfd_vma vma;
2974 union
2975 {
2976 struct
2977 {
2981 struct
2982 {
2987 elf32_vfp11_erratum_type type;
2988 }
2989 elf32_vfp11_erratum_list;
2991 /* Information about a STM32L4XX erratum veneer, or a branch to such a
2992 veneer. */
2994 {
2995 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2996 STM32L4XX_ERRATUM_VENEER
2997 }
2998 elf32_stm32l4xx_erratum_type;
3001 {
3003 bfd_vma vma;
3004 union
3005 {
3006 struct
3007 {
3011 struct
3012 {
3017 elf32_stm32l4xx_erratum_type type;
3018 }
3019 elf32_stm32l4xx_erratum_list;
3022 {
3023 DELETE_EXIDX_ENTRY,
3024 INSERT_EXIDX_CANTUNWIND_AT_END
3025 }
3026 arm_unwind_edit_type;
3028 /* A (sorted) list of edits to apply to an unwind table. */
3030 {
3031 arm_unwind_edit_type type;
3032 /* Note: we sometimes want to insert an unwind entry corresponding to a
3033 section different from the one we're currently writing out, so record the
3034 (text) section this edit relates to here. */
3038 }
3039 arm_unwind_table_edit;
3042 {
3043 /* Information about mapping symbols. */
3048 /* Information about CPU errata. */
3054 /* Information about unwind tables. */
3055 union
3056 {
3057 /* Unwind info attached to a text section. */
3058 struct
3059 {
3063 /* Unwind info attached to an .ARM.exidx section. */
3064 struct
3065 {
3070 }
3071 _arm_elf_section_data;
3073 #define elf32_arm_section_data(sec) \
3074 ((_arm_elf_section_data *) elf_section_data (sec))
3076 /* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
3077 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
3078 so may be created multiple times: we use an array of these entries whilst
3079 relaxing which we can refresh easily, then create stubs for each potentially
3080 erratum-triggering instruction once we've settled on a solution. */
3082 struct a8_erratum_fix
3083 {
3086 bfd_vma offset;
3087 bfd_vma target_offset;
3092 };
3094 /* A table of relocs applied to branches which might trigger Cortex-A8
3095 erratum. */
3097 struct a8_erratum_reloc
3098 {
3099 bfd_vma from;
3100 bfd_vma destination;
3106 };
3108 /* The size of the thread control block. */
3109 #define TCB_SIZE 8
3111 /* ARM-specific information about a PLT entry, over and above the usual
3112 gotplt_union. */
3113 struct arm_plt_info
3114 {
3115 /* We reference count Thumb references to a PLT entry separately,
3116 so that we can emit the Thumb trampoline only if needed. */
3117 bfd_signed_vma thumb_refcount;
3119 /* Some references from Thumb code may be eliminated by BL->BLX
3120 conversion, so record them separately. */
3121 bfd_signed_vma maybe_thumb_refcount;
3123 /* How many of the recorded PLT accesses were from non-call relocations.
3124 This information is useful when deciding whether anything takes the
3125 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
3126 non-call references to the function should resolve directly to the
3127 real runtime target. */
3130 /* Since PLT entries have variable size if the Thumb prologue is
3131 used, we need to record the index into .got.plt instead of
3132 recomputing it from the PLT offset. */
3133 bfd_signed_vma got_offset;
3134 };
3136 /* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
3137 struct arm_local_iplt_info
3138 {
3139 /* The information that is usually found in the generic ELF part of
3140 the hash table entry. */
3143 /* The information that is usually found in the ARM-specific part of
3144 the hash table entry. */
3147 /* A list of all potential dynamic relocations against this symbol. */
3149 };
3151 /* Structure to handle FDPIC support for local functions. */
3152 struct fdpic_local
3153 {
3157 };
3159 struct elf_arm_obj_tdata
3160 {
3163 /* Zero to warn when linking objects with incompatible enum sizes. */
3166 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
3169 /* The number of entries in each of the arrays in this strcuture.
3170 Used to avoid buffer overruns. */
3171 bfd_size_type num_entries;
3173 /* tls_type for each local got entry. */
3176 /* GOTPLT entries for TLS descriptors. */
3179 /* Information for local symbols that need entries in .iplt. */
3182 /* Maintains FDPIC counters and funcdesc info. */
3184 };
3186 #define elf_arm_tdata(bfd) \
3187 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
3189 #define elf32_arm_num_entries(bfd) \
3190 (elf_arm_tdata (bfd)->num_entries)
3192 #define elf32_arm_local_got_tls_type(bfd) \
3193 (elf_arm_tdata (bfd)->local_got_tls_type)
3195 #define elf32_arm_local_tlsdesc_gotent(bfd) \
3196 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
3198 #define elf32_arm_local_iplt(bfd) \
3199 (elf_arm_tdata (bfd)->local_iplt)
3201 #define elf32_arm_local_fdpic_cnts(bfd) \
3202 (elf_arm_tdata (bfd)->local_fdpic_cnts)
3204 #define is_arm_elf(bfd) \
3205 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
3206 && elf_tdata (bfd) != NULL \
3207 && elf_object_id (bfd) == ARM_ELF_DATA)
3209 static bool
3211 {
3213 }
3215 #define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
3217 /* Structure to handle FDPIC support for extern functions. */
3224 };
3226 /* Arm ELF linker hash entry. */
3227 struct elf32_arm_link_hash_entry
3228 {
3231 /* ARM-specific PLT information. */
3234 #define GOT_UNKNOWN 0
3235 #define GOT_NORMAL 1
3236 #define GOT_TLS_GD 2
3237 #define GOT_TLS_IE 4
3238 #define GOT_TLS_GDESC 8
3239 #define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
3242 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
3247 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
3248 starting at the end of the jump table. */
3249 bfd_vma tlsdesc_got;
3251 /* The symbol marking the real symbol location for exported thumb
3252 symbols with Arm stubs. */
3255 /* A pointer to the most recently used stub hash entry against this
3256 symbol. */
3259 /* Counter for FDPIC relocations against this symbol. */
3261 };
3263 /* Traverse an arm ELF linker hash table. */
3264 #define elf32_arm_link_hash_traverse(table, func, info) \
3265 (elf_link_hash_traverse \
3266 (&(table)->root, \
3267 (bool (*) (struct elf_link_hash_entry *, void *)) (func), \
3268 (info)))
3270 /* Get the ARM elf linker hash table from a link_info structure. */
3271 #define elf32_arm_hash_table(p) \
3272 ((is_elf_hash_table ((p)->hash) \
3273 && elf_hash_table_id (elf_hash_table (p)) == ARM_ELF_DATA) \
3274 ? (struct elf32_arm_link_hash_table *) (p)->hash : NULL)
3276 #define arm_stub_hash_lookup(table, string, create, copy) \
3277 ((struct elf32_arm_stub_hash_entry *) \
3278 bfd_hash_lookup ((table), (string), (create), (copy)))
3280 /* Array to keep track of which stub sections have been created, and
3281 information on stub grouping. */
3282 struct map_stub
3283 {
3284 /* This is the section to which stubs in the group will be
3285 attached. */
3287 /* The stub section. */
3289 };
3291 #define elf32_arm_compute_jump_table_size(htab) \
3292 ((htab)->next_tls_desc_index * 4)
3294 /* ARM ELF linker hash table. */
3295 struct elf32_arm_link_hash_table
3296 {
3297 /* The main hash table. */
3300 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3301 bfd_size_type thumb_glue_size;
3303 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3304 bfd_size_type arm_glue_size;
3306 /* The size in bytes of section containing the ARMv4 BX veneers. */
3307 bfd_size_type bx_glue_size;
3309 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3310 veneer has been populated. */
3313 /* The size in bytes of the section containing glue for VFP11 erratum
3314 veneers. */
3315 bfd_size_type vfp11_erratum_glue_size;
3317 /* The size in bytes of the section containing glue for STM32L4XX erratum
3318 veneers. */
3319 bfd_size_type stm32l4xx_erratum_glue_size;
3321 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3322 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3323 elf32_arm_write_section(). */
3327 /* An arbitrary input BFD chosen to hold the glue sections. */
3330 /* Nonzero to output a BE8 image. */
3333 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3334 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3337 /* The relocation to use for R_ARM_TARGET2 relocations. */
3340 /* 0 = Ignore R_ARM_V4BX.
3341 1 = Convert BX to MOV PC.
3342 2 = Generate v4 interworing stubs. */
3345 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3348 /* Whether we should fix the ARM1176 BLX immediate issue. */
3351 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3354 /* What sort of code sequences we should look for which may trigger the
3355 VFP11 denorm erratum. */
3356 bfd_arm_vfp11_fix vfp11_fix;
3358 /* Global counter for the number of fixes we have emitted. */
3361 /* What sort of code sequences we should look for which may trigger the
3362 STM32L4XX erratum. */
3363 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3365 /* Global counter for the number of fixes we have emitted. */
3368 /* Nonzero to force PIC branch veneers. */
3371 /* The number of bytes in the initial entry in the PLT. */
3372 bfd_size_type plt_header_size;
3374 /* The number of bytes in the subsequent PLT etries. */
3375 bfd_size_type plt_entry_size;
3377 /* True if the target uses REL relocations. */
3380 /* Nonzero if import library must be a secure gateway import library
3381 as per ARMv8-M Security Extensions. */
3384 /* The import library whose symbols' address must remain stable in
3385 the import library generated. */
3388 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3389 bfd_vma next_tls_desc_index;
3391 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3392 bfd_vma num_tls_desc;
3394 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3397 /* Offset in .plt section of tls_arm_trampoline. */
3398 bfd_vma tls_trampoline;
3400 /* Data for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
3401 union
3402 {
3403 bfd_signed_vma refcount;
3404 bfd_vma offset;
3407 /* For convenience in allocate_dynrelocs. */
3410 /* The amount of space used by the reserved portion of the sgotplt
3411 section, plus whatever space is used by the jump slots. */
3412 bfd_vma sgotplt_jump_table_size;
3414 /* The stub hash table. */
3417 /* Linker stub bfd. */
3420 /* Linker call-backs. */
3425 /* Array to keep track of which stub sections have been created, and
3426 information on stub grouping. */
3429 /* Input stub section holding secure gateway veneers. */
3432 /* Offset in cmse_stub_sec where new SG veneers (not in input import library)
3433 start to be allocated. */
3434 bfd_vma new_cmse_stub_offset;
3436 /* Number of elements in stub_group. */
3439 /* Assorted information used by elf32_arm_size_stubs. */
3444 /* True if the target system uses FDPIC. */
3447 /* Fixup section. Used for FDPIC. */
3449 };
3451 /* Add an FDPIC read-only fixup. */
3452 static void
3454 {
3455 bfd_vma fixup_offset;
3460 }
3464 {
3465 #if GCC_VERSION >= 3004
3467 #else
3471 {
3475 }
3477 #endif
3478 }
3482 {
3483 #if GCC_VERSION >= 3004
3485 #else
3490 {
3492 sum++;
3494 }
3496 #endif
3497 }
3502 static void
3508 bfd_vma addr,
3509 bfd_vma dynreloc_value,
3510 bfd_vma seg)
3511 {
3513 {
3518 {
3520 Elf_Internal_Rela outrel;
3529 }
3530 else
3531 {
3545 }
3547 }
3548 }
3550 /* Create an entry in an ARM ELF linker hash table. */
3556 {
3560 /* Allocate the structure if it has not already been allocated by a
3561 subclass. */
3568 /* Call the allocation method of the superclass. */
3573 {
3590 }
3593 }
3595 /* Ensure that we have allocated bookkeeping structures for ABFD's local
3596 symbols. */
3598 static bool
3600 {
3602 {
3603 bfd_size_type num_syms;
3607 /* Whilst it might be tempting to allocate a single block of memory and
3608 then divide it up amoungst the arrays in the elf_arm_obj_tdata
3609 structure, this interferes with the work of memory checkers looking
3610 for buffer overruns. So allocate each array individually. */
3646 #if GCC_VERSION >= 3000
3655 #endif
3656 }
3658 }
3660 /* Return the .iplt information for local symbol R_SYMNDX, which belongs
3661 to input bfd ABFD. Create the information if it doesn't already exist.
3662 Return null if an allocation fails. */
3666 {
3678 }
3680 /* Try to obtain PLT information for the symbol with index R_SYMNDX
3681 in ABFD's symbol table. If the symbol is global, H points to its
3682 hash table entry, otherwise H is null.
3684 Return true if the symbol does have PLT information. When returning
3685 true, point *ROOT_PLT at the target-independent reference count/offset
3686 union and *ARM_PLT at the ARM-specific information. */
3688 static bool
3693 {
3700 {
3704 }
3719 }
3723 /* Return true if the PLT described by ARM_PLT requires a Thumb stub
3724 before it. */
3726 static bool
3729 {
3736 }
3738 /* Return a pointer to the head of the dynamic reloc list that should
3739 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3740 ABFD's symbol table. Return null if an error occurs. */
3745 {
3747 {
3754 }
3755 else
3756 {
3757 /* Track dynamic relocs needed for local syms too.
3758 We really need local syms available to do this
3759 easily. Oh well. */
3769 }
3770 }
3772 /* Initialize an entry in the stub hash table. */
3778 {
3779 /* Allocate the structure if it has not already been allocated by a
3780 subclass. */
3782 {
3787 }
3789 /* Call the allocation method of the superclass. */
3792 {
3795 /* Initialize the local fields. */
3810 }
3813 }
3815 /* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
3816 shortcuts to them in our hash table. */
3818 static bool
3820 {
3830 /* Also create .rofixup. */
3832 {
3839 }
3842 }
3844 /* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3846 static bool
3848 {
3853 flagword flags;
3861 {
3868 }
3871 {
3879 }
3882 {
3888 }
3890 }
3892 /* Determine if we're dealing with a Thumb only architecture. */
3894 static bool
3896 {
3899 Tag_CPU_arch_profile);
3906 /* Force return logic to be reviewed for each new architecture. */
3918 }
3920 /* Determine if we're dealing with a Thumb-2 object. */
3922 static bool
3924 {
3927 Tag_THUMB_ISA_use);
3929 /* No use of thumb permitted, or a legacy thumb-1/2 definition. */
3933 /* Variant of thumb is described by the architecture tag. */
3936 /* Force return logic to be reviewed for each new architecture. */
3946 }
3948 /* Determine whether Thumb-2 BL instruction is available. */
3950 static bool
3952 {
3956 /* Force return logic to be reviewed for each new architecture. */
3959 /* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
3962 }
3964 /* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3965 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
3966 hash table. */
3968 static bool
3970 {
3984 {
3989 {
3991 htab->plt_entry_size
3993 }
3994 else
3995 {
3996 htab->plt_header_size
3998 htab->plt_entry_size
4000 }
4004 }
4005 else
4006 {
4007 /* PR ld/16017
4008 Test for thumb only architectures. Note - we cannot just call
4009 using_thumb_only() as the attributes in the output bfd have not been
4010 initialised at this point, so instead we use the input bfd. */
4015 {
4018 }
4020 }
4026 else
4028 }
4037 }
4039 /* Copy the extra info we tack onto an elf_link_hash_entry. */
4041 static void
4045 {
4052 {
4053 /* Copy over PLT info. */
4061 /* Copy FDPIC counters. */
4066 /* We should only allocate a function to .iplt once the final
4067 symbol information is known. */
4071 {
4074 }
4075 }
4078 }
4080 /* Destroy an ARM elf linker hash table. */
4082 static void
4084 {
4090 }
4092 /* Create an ARM elf linker hash table. */
4096 {
4105 elf32_arm_link_hash_newfunc,
4107 {
4110 }
4114 #ifdef FOUR_WORD_PLT
4117 #else
4120 #endif
4127 {
4130 }
4134 }
4136 /* Determine what kind of NOPs are available. */
4138 static bool
4140 {
4142 Tag_CPU_arch);
4144 /* Force return logic to be reviewed for each new architecture. */
4153 }
4155 static bool
4157 {
4159 {
4176 }
4177 }
4179 /* Determine the type of stub needed, if any, for a call. */
4181 static enum elf32_arm_stub_type
4188 bfd_vma destination,
4192 {
4193 bfd_vma location;
4194 bfd_signed_vma branch_offset;
4219 /* True for architectures that implement the thumb2 movw instruction. */
4222 /* Determine where the call point is. */
4229 /* Don't pretend we know what stub to use (if any) when we target a
4230 Thumb-only target and we don't know the actual destination
4231 type. */
4235 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
4236 are considering a function call relocation. */
4240 {
4242 /* As an exception, assume that absolute symbols are of the
4243 right kind (Thumb). They are presumably defined in the
4244 linker script, where it is not possible to declare them as
4245 Thumb (and thus are seen as Arm mode). We'll inform the
4246 user with a warning, though, in
4247 elf32_arm_final_link_relocate. */
4249 else
4250 /* Otherwise do not silently build a stub, and let the users
4251 know they have to fix their code. Indeed, we could decide
4252 to insert a stub involving Arm code and/or BLX, leading to
4253 a run-time crash. */
4255 }
4257 /* For TLS call relocs, it is the caller's responsibility to provide
4258 the address of the appropriate trampoline. */
4265 {
4270 else
4273 {
4276 /* Note when dealing with PLT entries: the main PLT stub is in
4277 ARM mode, so if the branch is in Thumb mode, another
4278 Thumb->ARM stub will be inserted later just before the ARM
4279 PLT stub. If a long branch stub is needed, we'll add a
4280 Thumb->Arm one and branch directly to the ARM PLT entry.
4281 Here, we have to check if a pre-PLT Thumb->ARM stub
4282 is needed and if it will be close enough. */
4289 /* Thumb branch/call to PLT: it can become a branch to ARM
4290 or to Thumb. We must perform the same checks and
4291 corrections as in elf32_arm_final_link_relocate. */
4294 {
4298 {
4299 /* If the Thumb BLX instruction is available, convert
4300 the BL to a BLX instruction to call the ARM-mode
4301 PLT entry. */
4303 }
4304 else
4305 {
4307 /* Target the Thumb stub before the ARM PLT entry. */
4310 }
4311 }
4312 else
4313 {
4315 }
4316 }
4317 }
4318 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
4325 {
4326 /* Handle cases where:
4327 - this call goes too far (different Thumb/Thumb2 max
4328 distance)
4329 - it's a Thumb->Arm call and blx is not available, or it's a
4330 Thumb->Arm branch (not bl). A stub is needed in this case,
4331 but only if this call is not through a PLT entry. Indeed,
4332 PLT stubs handle mode switching already. */
4336 || (thumb2_bl
4339 || (thumb2
4349 {
4350 /* If we need to insert a Thumb-Thumb long branch stub to a
4351 PLT, use one that branches directly to the ARM PLT
4352 stub. If we pretended we'd use the pre-PLT Thumb->ARM
4353 stub, undo this now. */
4355 {
4358 }
4361 {
4362 /* Thumb to thumb. */
4364 {
4366 _bfd_error_handler
4368 " section with SHF_ARM_PURECODE section"
4369 " attribute is only supported for M-profile"
4374 /* PIC stubs. */
4377 /* V5T and above. Stub starts with ARM code, so
4378 we must be able to switch mode before
4379 reaching it, which is only possible for 'bl'
4380 (ie R_ARM_THM_CALL relocation). */
4381 ? arm_stub_long_branch_any_thumb_pic
4382 /* On V4T, use Thumb code only. */
4385 /* non-PIC stubs. */
4388 /* V5T and above. */
4389 ? arm_stub_long_branch_any_any
4390 /* V4T. */
4392 }
4393 else
4394 {
4397 else
4398 {
4400 _bfd_error_handler
4402 " section with SHF_ARM_PURECODE section"
4403 " attribute is only supported for M-profile"
4408 /* PIC stub. */
4409 ? arm_stub_long_branch_thumb_only_pic
4410 /* non-PIC stub. */
4413 }
4414 }
4415 }
4416 else
4417 {
4419 _bfd_error_handler
4421 " section with SHF_ARM_PURECODE section"
4426 /* Thumb to arm. */
4430 {
4431 _bfd_error_handler
4435 }
4437 stub_type =
4439 /* PIC stubs. */
4441 /* TLS PIC stubs. */
4445 /* V5T PIC and above. */
4446 ? arm_stub_long_branch_any_arm_pic
4447 /* V4T PIC stub. */
4450 /* non-PIC stubs. */
4452 /* V5T and above. */
4453 ? arm_stub_long_branch_any_any
4454 /* V4T. */
4457 /* Handle v4t short branches. */
4462 }
4463 }
4464 }
4469 {
4471 _bfd_error_handler
4473 " section with SHF_ARM_PURECODE section"
4474 " attribute is only supported for M-profile"
4478 {
4479 /* Arm to thumb. */
4484 {
4485 _bfd_error_handler
4489 }
4491 /* We have an extra 2-bytes reach because of
4492 the mode change (bit 24 (H) of BLX encoding). */
4498 {
4500 /* PIC stubs. */
4502 /* V5T and above. */
4503 ? arm_stub_long_branch_any_thumb_pic
4504 /* V4T stub. */
4507 /* non-PIC stubs. */
4509 /* V5T and above. */
4510 ? arm_stub_long_branch_any_any
4511 /* V4T. */
4513 }
4514 }
4515 else
4516 {
4517 /* Arm to arm. */
4520 {
4521 stub_type =
4523 /* PIC stubs. */
4525 /* TLS PIC Stub. */
4526 ? arm_stub_long_branch_any_tls_pic
4528 ? arm_stub_long_branch_arm_nacl_pic
4530 /* non-PIC stubs. */
4532 ? arm_stub_long_branch_arm_nacl
4534 }
4535 }
4536 }
4538 /* If a stub is needed, record the actual destination type. */
4543 }
4545 /* Build a name for an entry in the stub hash table. */
4553 {
4555 bfd_size_type len;
4558 {
4567 }
4568 else
4569 {
4581 }
4584 }
4586 /* Look up an entry in the stub hash. Stub entries are cached because
4587 creating the stub name takes a bit of time. */
4596 {
4604 /* If the input section is the CMSE stubs one and it needs a long
4605 branch stub to reach it's final destination, give up with an
4606 error message: this is not supported. See PR ld/24709. */
4608 {
4614 CMSE_STUB_NAME,
4620 /* Exit, rather than leave incompletely processed
4621 relocations. */
4623 }
4625 /* If this input section is part of a group of sections sharing one
4626 stub section, then use the id of the first section in the group.
4627 Stub names need to include a section id, as there may well be
4628 more than one stub used to reach say, printf, and we need to
4629 distinguish between them. */
4637 {
4639 }
4640 else
4641 {
4654 }
4657 }
4659 /* Whether veneers of type STUB_TYPE require to be in a dedicated output
4660 section. */
4662 static bool
4664 {
4669 {
4675 }
4678 }
4680 /* Required alignment (as a power of 2) for the dedicated section holding
4681 veneers of type STUB_TYPE, or 0 if veneers of this type are interspersed
4682 with input sections. */
4684 static int
4685 arm_dedicated_stub_output_section_required_alignment
4687 {
4692 {
4693 /* Vectors of Secure Gateway veneers must be aligned on 32byte
4694 boundary. */
4701 }
4704 }
4706 /* Name of the dedicated output section to put veneers of type STUB_TYPE, or
4707 NULL if veneers of this type are interspersed with input sections. */
4711 {
4716 {
4723 }
4726 }
4728 /* If veneers of type STUB_TYPE should go in a dedicated output section,
4729 returns the address of the hash table field in HTAB holding a pointer to the
4730 corresponding input section. Otherwise, returns NULL. */
4735 {
4740 {
4747 }
4750 }
4752 /* Find or create a stub section to contain a stub of type STUB_TYPE. SECTION
4753 is the section that branch into veneer and can be NULL if stub should go in
4754 a dedicated output section. Returns a pointer to the stub section, and the
4755 section to which the stub section will be attached (in *LINK_SEC_P).
4756 LINK_SEC_P may be NULL. */
4762 {
4770 {
4780 {
4784 }
4785 }
4786 else
4787 {
4797 }
4800 {
4802 bfd_size_type len;
4814 align);
4821 }
4830 }
4832 /* Add a new stub entry to the stub hash. Not all fields of the new
4833 stub entry are initialised. */
4839 {
4845 stub_type);
4849 /* Enter this entry into the linker stub hash table. */
4853 {
4859 }
4866 }
4868 /* Store an Arm insn into an output section not processed by
4869 elf32_arm_write_section. */
4871 static void
4874 {
4877 else
4879 }
4881 /* Store a 16-bit Thumb insn into an output section not processed by
4882 elf32_arm_write_section. */
4884 static void
4887 {
4890 else
4892 }
4894 /* Store a Thumb2 insn into an output section not processed by
4895 elf32_arm_write_section. */
4897 static void
4900 {
4901 /* T2 instructions are 16-bit streamed. */
4903 {
4906 }
4907 else
4908 {
4911 }
4912 }
4914 /* If it's possible to change R_TYPE to a more efficient access
4915 model, return the new reloc type. */
4917 static unsigned
4920 {
4927 /* We do not support relaxations for Old TLS models. */
4929 {
4936 }
4939 }
4941 static bfd_reloc_status_type elf32_arm_final_link_relocate
4947 static unsigned int
4949 {
4951 {
4983 }
4984 }
4986 /* Returns whether stubs of type STUB_TYPE take over the symbol they are
4987 veneering (TRUE) or have their own symbol (FALSE). */
4989 static bool
4991 {
4996 {
5002 }
5005 }
5007 /* Returns the padding needed for the dedicated section used stubs of type
5008 STUB_TYPE. */
5010 static int
5012 {
5017 {
5023 }
5026 }
5028 /* If veneers of type STUB_TYPE should go in a dedicated output section,
5029 returns the address of the hash table field in HTAB holding the offset at
5030 which new veneers should be layed out in the stub section. */
5035 {
5037 {
5044 }
5045 }
5047 static bool
5050 {
5051 #define MAXRELOCS 3
5059 bfd_vma sym_value;
5069 /* Massage our args to the form they really have. */
5073 /* Fail if the target section could not be assigned to an output
5074 section. The user should fix his linker script. */
5089 /* We have to do less-strictly-aligned fixes last. */
5092 /* Assign a slot at the end of section if none assigned yet. */
5094 {
5097 }
5102 /* This is the address of the stub destination. */
5112 {
5114 {
5116 {
5119 {
5120 /* We've borrowed the reloc_addend field to mean we should
5121 insert a condition code into this (Thumb-1 branch)
5122 instruction. See THUMB16_BCOND_INSN. */
5125 }
5128 }
5138 {
5141 }
5148 /* Handle cases where the target is encoded within the
5149 instruction. */
5151 {
5154 }
5168 }
5169 }
5174 /* Stub size has already been computed in arm_size_one_stub. Check
5175 consistency. */
5178 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
5182 /* Assume non empty slots have at least one and at most MAXRELOCS entries
5183 to relocate in each stub. */
5184 removed_sg_veneer =
5189 {
5190 Elf_Internal_Rela rel;
5193 bfd_vma points_to =
5202 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
5203 template should refer back to the instruction after the original
5204 branch. We use target_section as Cortex-A8 erratum workaround stubs
5205 are only generated when both source and target are in the same
5206 section. */
5218 }
5221 #undef MAXRELOCS
5222 }
5224 /* Calculate the template, template size and instruction size for a stub.
5225 Return value is the instruction size. */
5227 static unsigned int
5231 {
5246 {
5248 {
5262 }
5263 }
5266 }
5268 /* As above, but don't actually build the stub. Just bump offset so
5269 we know stub section sizes. */
5271 static bool
5274 {
5279 /* Massage our args to the form they really have. */
5288 /* Initialized to -1. Null size indicates an empty slot full of zeros. */
5290 {
5294 }
5296 /* Already accounted for. */
5304 }
5306 /* External entry points for sizing and building linker stubs. */
5308 /* Set up various things so that we can make a list of input sections
5309 for each output section included in the link. Returns -1 on error,
5310 0 when no stubs will be needed, and 1 on success. */
5312 int
5315 {
5327 /* Count the number of input BFDs and find the top input section id. */
5331 {
5336 {
5339 }
5340 }
5349 /* We can't use output_bfd->section_count here to find the top output
5350 section index as some sections may have been removed, and
5351 _bfd_strip_section_from_output doesn't renumber the indices. */
5355 {
5358 }
5367 /* For sections we aren't interested in, mark their entries with a
5368 value we can check later. */
5370 do
5377 {
5380 }
5383 }
5385 /* The linker repeatedly calls this function for each input section,
5386 in the order that input sections are linked into output sections.
5387 Build lists of input sections to determine groupings between which
5388 we may insert linker stubs. */
5390 void
5393 {
5400 {
5404 {
5405 /* Steal the link_sec pointer for our list. */
5406 #define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
5407 /* This happens to make the list in reverse order,
5408 which we reverse later. */
5411 }
5412 }
5413 }
5415 /* See whether we can group stub sections together. Grouping stub
5416 sections may result in fewer stubs. More importantly, we need to
5417 put all .init* and .fini* stubs at the end of the .init or
5418 .fini output sections respectively, because glibc splits the
5419 _init and _fini functions into multiple parts. Putting a stub in
5420 the middle of a function is not a good idea. */
5422 static void
5424 bfd_size_type stub_group_size,
5426 {
5429 do
5430 {
5437 /* Reverse the list: we must avoid placing stubs at the
5438 beginning of the section because the beginning of the text
5439 section may be required for an interrupt vector in bare metal
5440 code. */
5441 #define NEXT_SEC PREV_SEC
5444 {
5445 /* Pop from tail. */
5449 /* Push on head. */
5452 }
5455 {
5459 bfd_vma end_of_next;
5463 {
5467 /* End of NEXT is too far from start, so stop. */
5469 /* Add NEXT to the group. */
5471 }
5473 /* OK, the size from the start to the start of CURR is less
5474 than stub_group_size and thus can be handled by one stub
5475 section. (Or the head section is itself larger than
5476 stub_group_size, in which case we may be toast.)
5477 We should really be keeping track of the total size of
5478 stubs added here, as stubs contribute to the final output
5479 section size. */
5480 do
5481 {
5483 /* Set up this stub group. */
5485 }
5488 /* But wait, there's more! Input sections up to stub_group_size
5489 bytes after the stub section can be handled by it too. */
5491 {
5495 {
5498 /* End of NEXT is too far from stubs, so stop. */
5500 /* Add NEXT to the stub group. */
5504 }
5505 }
5507 }
5508 }
5512 #undef PREV_SEC
5513 #undef NEXT_SEC
5514 }
5516 /* Comparison function for sorting/searching relocations relating to Cortex-A8
5517 erratum fix. */
5519 static int
5521 {
5529 else
5531 }
5536 /* Helper function to scan code for sequences which might trigger the Cortex-A8
5537 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
5538 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
5539 otherwise. */
5541 static bool
5551 {
5564 {
5568 bfd_vma base_vma;
5587 {
5598 /* Span is entirely within a single 4KB region: skip scanning. */
5603 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
5605 * The opcode is BLX.W, BL.W, B.W, Bcc.W
5606 * The branch target is in the same 4KB region as the
5607 first half of the branch.
5608 * The instruction before the branch is a 32-bit
5609 length non-branch instruction. */
5611 {
5620 {
5621 /* Load the rest of the insn (in manual-friendly order). */
5624 /* Encoding T4: B<c>.W. */
5626 /* Encoding T1: BL<c>.W. */
5628 /* Encoding T2: BLX<c>.W. */
5630 /* Encoding T3: B<c>.W (not permitted in IT block). */
5633 }
5638 && insn_32bit
5639 && is_32bit_branch
5640 && last_was_32bit
5642 {
5646 bfd_vma target;
5658 {
5662 /* We don't care about the error returned from this
5663 function, only if there is glue or not. */
5670 /* Keep a simpler condition, for the sake of clarity. */
5676 {
5680 else
5682 }
5683 }
5685 /* Check if we have an offending branch instruction. */
5688 /* We've already made a stub for this instruction, e.g.
5689 it's a long branch or a Thumb->ARM stub. Assume that
5690 stub will suffice to work around the A8 erratum (see
5691 setting of always_after_branch above). */
5692 ;
5694 {
5703 }
5705 {
5725 }
5728 {
5731 /* The original instruction is a BL, but the target is
5732 an ARM instruction. If we were not making a stub,
5733 the BL would have been converted to a BLX. Use the
5734 BLX stub instead in that case. */
5737 {
5741 }
5742 /* Conversely, if the original instruction was
5743 BLX but the target is Thumb mode, use the BL
5744 stub. */
5747 {
5751 }
5756 /* If we found a relocation, use the proper destination,
5757 not the offset in the (unrelocated) instruction.
5758 Note this is always done if we switched the stub type
5759 above. */
5761 offset =
5764 /* If the stub will use a Thumb-mode branch to a
5765 PLT target, redirect it to the preceding Thumb
5766 entry point. */
5772 /* The BLX stub is ARM-mode code. Adjust the offset to
5773 take the different PC value (+8 instead of +4) into
5774 account. */
5779 {
5783 {
5789 }
5792 {
5793 /* If we're doing a subsequent scan,
5794 check if we've found the same fix as
5795 before, and try and reuse the stub
5796 name. */
5800 {
5804 }
5805 }
5808 {
5812 }
5825 num_a8_fixes++;
5826 }
5827 }
5828 }
5833 }
5834 }
5838 }
5845 }
5847 /* Create or update a stub entry depending on whether the stub can already be
5848 found in HTAB. The stub is identified by:
5849 - its type STUB_TYPE
5850 - its source branch (note that several can share the same stub) whose
5851 section and relocation (if any) are given by SECTION and IRELA
5852 respectively
5853 - its target symbol whose input section, hash, name, value and branch type
5854 are given in SYM_SEC, HASH, SYM_NAME, SYM_VALUE and BRANCH_TYPE
5855 respectively
5857 If found, the value of the stub's target symbol is updated from SYM_VALUE
5858 and *NEW_STUB is set to FALSE. Otherwise, *NEW_STUB is set to
5859 TRUE and the stub entry is initialized.
5861 Returns the stub that was created or updated, or NULL if an error
5862 occurred. */
5871 {
5883 else
5884 {
5889 /* Support for grouping stub sections. */
5892 /* Get the name of this stub. */
5894 stub_type);
5897 }
5901 /* The proper stub has already been created, just update its value. */
5903 {
5908 }
5912 {
5916 }
5926 else
5927 {
5934 {
5937 }
5939 /* For historical reasons, use the existing names for ARM-to-Thumb and
5940 Thumb-to-ARM stubs. */
5951 else
5953 }
5957 }
5959 /* Scan symbols in INPUT_BFD to identify secure entry functions needing a
5960 gateway veneer to transition from non secure to secure state and create them
5961 accordingly.
5963 "ARMv8-M Security Extensions: Requirements on Development Tools" document
5964 defines the conditions that govern Secure Gateway veneer creation for a
5965 given symbol <SYM> as follows:
5966 - it has function type
5967 - it has non local binding
5968 - a symbol named __acle_se_<SYM> (called special symbol) exists with the
5969 same type, binding and value as <SYM> (called normal symbol).
5970 An entry function can handle secure state transition itself in which case
5971 its special symbol would have a different value from the normal symbol.
5973 OUT_ATTR gives the output attributes, SYM_HASHES the symbol index to hash
5974 entry mapping while HTAB gives the name to hash entry mapping.
5975 *CMSE_STUB_CREATED is increased by the number of secure gateway veneer
5976 created.
5978 The return value gives whether a stub failed to be allocated. */
5980 static bool
5984 {
5992 bfd_vma sym_value;
6008 NULL);
6012 /* Scan symbols. */
6014 {
6018 {
6026 /* Special symbol with local binding. */
6028 }
6029 else
6030 {
6039 /* Special symbol has incorrect binding or type. */
6044 }
6047 {
6053 }
6056 {
6063 }
6069 /* No associated normal symbol or it is neither global nor weak. */
6074 {
6075 /* Initialize here to avoid warning about use of possibly
6076 uninitialized variable. */
6080 {
6081 /* Searching for a normal symbol with local binding. */
6083 {
6084 lsym_name =
6090 }
6091 }
6094 {
6095 _bfd_error_handler
6099 }
6100 else
6101 _bfd_error_handler
6106 }
6112 {
6113 _bfd_error_handler
6117 }
6121 /* If this section is a link-once section that will be discarded, then
6122 don't create any stubs. */
6124 {
6125 _bfd_error_handler
6128 }
6131 {
6132 _bfd_error_handler
6135 }
6140 stub_entry
6147 else
6148 {
6151 }
6152 }
6157 }
6159 /* Return TRUE iff a symbol identified by its linker HASH entry is a secure
6160 code entry function, ie can be called from non secure code without using a
6161 veneer. */
6163 static bool
6165 {
6169 file_ptr offset;
6172 /* Defined symbol of function type. */
6179 /* Read first instruction. */
6189 /* Starts by SG instruction. */
6191 }
6193 /* Output the name (in symbol table) of the veneer GEN_ENTRY if it is a new
6194 secure gateway veneers (ie. the veneers was not in the input import library)
6195 and there is no output import library (GEN_INFO->out_implib_bfd is NULL. */
6197 static bool
6199 {
6203 /* Massage our args to the form they really have. */
6217 }
6219 /* Set offset of each secure gateway veneers so that its address remain
6220 identical to the one in the input import library referred by
6221 HTAB->in_implib_bfd. A warning is issued for veneers that disappeared
6222 (present in input import library but absent from the executable being
6223 linked) or if new veneers appeared and there is no output import library
6224 (INFO->out_implib_bfd is NULL and *CMSE_STUB_CREATED is bigger than the
6225 number of secure gateway veneers found in the input import library.
6227 The function returns whether an error occurred. If no error occurred,
6228 *CMSE_STUB_CREATED gives the number of SG veneers created by both cmse_scan
6229 and this function and HTAB->new_cmse_stub_offset is set to the biggest
6230 veneer observed set for new veneers to be layed out after. */
6232 static bool
6236 {
6239 flagword flags;
6246 bfd_size_type cmse_stub_size;
6255 /* No input secure gateway import library. */
6261 {
6265 }
6267 /* Get symbol table size. */
6272 /* Read in the input secure gateway import library's symbol table. */
6279 {
6282 }
6285 cmse_stub_size =
6289 out_sec_name =
6291 stub_out_sec =
6296 /* Set addresses of veneers mentionned in input secure gateway import
6297 library's symbol table. */
6299 {
6310 {
6312 "symbol should be absolute, global and "
6317 }
6326 /* Stub entry should have been created by cmse_scan or the symbol be of
6327 a secure function callable from non secure code. */
6329 {
6332 _bfd_error_handler
6336 stub_entry
6343 else
6344 {
6346 new_cmse_stubs_created++;
6348 }
6351 }
6352 /* Symbol found is not callable from non secure code. */
6354 {
6356 {
6358 sym_name);
6360 }
6362 }
6363 else
6364 {
6365 /* Only stubs for SG veneers should have been created. */
6368 /* Check visibility hasn't changed. */
6371 _bfd_error_handler
6373 sym_name);
6376 }
6378 /* Size should match that of a SG veneer. */
6380 {
6384 }
6386 /* Previous veneer address is before current SG veneer section. */
6388 {
6389 /* Avoid offset underflow. */
6394 }
6396 /* Complain if stub offset not a multiple of stub size. */
6398 {
6399 _bfd_error_handler
6403 }
6408 new_cmse_stubs_created--;
6414 }
6417 {
6419 _bfd_error_handler
6423 }
6426 {
6427 _bfd_error_handler
6429 out_sec_name);
6431 }
6433 free_sym_buf:
6436 }
6438 /* Determine and set the size of the stub section for a final link.
6440 The basic idea here is to examine all the relocations looking for
6441 PC-relative calls to a target that is unreachable with a "bl"
6442 instruction. */
6444 bool
6448 bfd_signed_vma group_size,
6450 asection *,
6453 {
6457 bfd_size_type stub_group_size;
6469 {
6474 }
6476 /* Propagate mach to stub bfd, because it may not have been
6477 finalized when we created stub_bfd. */
6481 /* Stash our params away. */
6490 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
6491 as the first half of a 32-bit branch straddling two 4K pages. This is a
6492 crude way of enforcing that. */
6498 else
6502 {
6503 /* Default values. */
6504 /* Thumb branch range is +-4MB has to be used as the default
6505 maximum size (a given section can contain both ARM and Thumb
6506 code, so the worst case has to be taken into account).
6508 This value is 24K less than that, which allows for 2025
6509 12-byte stubs. If we exceed that, then we will fail to link.
6510 The user will have to relink with an explicit group size
6511 option. */
6513 }
6517 /* If we're applying the cortex A8 fix, we need to determine the
6518 program header size now, because we cannot change it later --
6519 that could alter section placements. Notice the A8 erratum fix
6520 ends up requiring the section addresses to remain unchanged
6521 modulo the page size. That's something we cannot represent
6522 inside BFD, and we don't want to force the section alignment to
6523 be the page size. */
6528 {
6540 {
6554 /* We'll need the symbol table in a second. */
6559 /* Limit scan of symbols to object file whose profile is
6560 Microcontroller to not hinder performance in the general case. */
6562 {
6572 }
6574 /* Walk over each section attached to the input bfd. */
6578 {
6581 /* If there aren't any relocs, then there's nothing more
6582 to do. */
6588 /* If this section is a link-once section that will be
6589 discarded, then don't create any stubs. */
6594 /* Get the relocs. */
6595 internal_relocs
6601 /* Now examine each relocation. */
6605 {
6608 bfd_vma sym_value;
6609 bfd_vma destination;
6620 {
6622 error_ret_free_internal:
6625 /* Fall through. */
6626 error_ret_free_local:
6630 }
6634 hash = elf32_arm_hash_entry
6638 /* Only look for stubs on branch instructions, or
6639 non-relaxed TLSCALL */
6653 : (elf32_arm_local_got_tls_type
6658 /* Now determine the call target, its name, value,
6659 section. */
6667 {
6668 /* A non-relaxed TLS call. The target is the
6669 plt-resident trampoline and nothing to do
6670 with the symbol. */
6677 }
6679 {
6680 /* It's a local symbol. */
6684 {
6685 local_syms
6688 local_syms
6694 }
6703 else
6704 sym_sec =
6708 /* This is an undefined symbol. It can never
6709 be resolved. */
6718 branch_type =
6720 sym_name
6724 }
6725 else
6726 {
6727 /* It's an external symbol. */
6735 {
6742 /* For a destination in a shared library,
6743 use the PLT stub as target address to
6744 decide whether a branch stub is
6745 needed. */
6750 {
6754 destination = (sym_value
6757 }
6762 }
6765 {
6766 /* For a shared library, use the PLT stub as
6767 target address to decide whether a long
6768 branch stub is needed.
6769 For absolute code, they cannot be handled. */
6777 {
6781 destination = (sym_value
6784 }
6785 else
6787 }
6788 else
6789 {
6792 }
6794 branch_type =
6797 }
6799 do
6800 {
6804 /* Determine what (if any) linker stub is needed. */
6812 /* We've either created a stub for this reloc already,
6813 or we are about to. */
6814 stub_entry =
6825 else
6827 }
6830 /* Look for relocations which might trigger Cortex-A8
6831 erratum. */
6837 {
6843 {
6844 /* Found a candidate. Note we haven't checked the
6845 destination is within 4K here: if we do so (and
6846 don't create an entry in a8_relocs) we can't tell
6847 that a branch should have been relocated when
6848 scanning later. */
6850 {
6856 }
6866 num_a8_relocs++;
6867 }
6868 }
6869 }
6871 /* We're done with the internal relocs, free them. */
6874 }
6877 {
6878 /* Sort relocs which might apply to Cortex-A8 erratum. */
6883 /* Scan for branches which might trigger Cortex-A8 erratum. */
6890 }
6894 {
6897 else
6899 }
6900 }
6913 /* OK, we've added some stubs. Find out the new size of the
6914 stub sections. */
6918 {
6919 /* Ignore non-stub sections. */
6924 }
6926 /* Add new SG veneers after those already in the input import
6927 library. */
6929 stub_type++)
6930 {
6942 }
6944 /* Compute stub section size, considering padding. */
6947 stub_type++)
6948 {
6954 /* Skip if no stub input section or no stub section padding
6955 required. */
6958 /* Stub section padding required but no dedicated section. */
6964 }
6966 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
6969 {
6976 stub_sec->size
6978 NULL);
6979 }
6982 /* Ask the linker to do its stuff. */
6985 }
6987 /* Add stubs for Cortex-A8 erratum fixes now. */
6989 {
6991 {
7004 {
7008 }
7027 }
7029 /* Stash the Cortex-A8 erratum fix array for use later in
7030 elf32_arm_write_section(). */
7033 }
7034 else
7035 {
7038 }
7040 }
7042 /* Build all the stubs associated with the current output file. The
7043 stubs are kept in a hash table attached to the main linker hash
7044 table. We also set up the .plt entries for statically linked PIC
7045 functions here. This function is called via arm_elf_finish in the
7046 linker. */
7048 bool
7050 {
7063 {
7064 bfd_size_type size;
7066 /* Ignore non-stub sections. */
7070 /* Allocate memory to hold the linker stubs. Zeroing the stub sections
7071 must at least be done for stub section requiring padding and for SG
7072 veneers to ensure that a non secure code branching to a removed SG
7073 veneer causes an error. */
7081 }
7083 /* Add new SG veneers after those already in the input import library. */
7085 {
7097 }
7099 /* Build the stubs as directed by the stub hash table. */
7103 {
7104 /* Place the cortex a8 stubs last. */
7107 }
7110 }
7112 /* Locate the Thumb encoded calling stub for NAME. */
7118 {
7123 /* We need a pointer to the armelf specific hash table. */
7135 hash = elf_link_hash_lookup
7139 {
7144 }
7149 }
7151 /* Locate the ARM encoded calling stub for NAME. */
7157 {
7162 /* We need a pointer to the elfarm specific hash table. */
7173 myh = elf_link_hash_lookup
7177 {
7182 }
7186 }
7188 /* ARM->Thumb glue (static images):
7190 .arm
7191 __func_from_arm:
7192 ldr r12, __func_addr
7193 bx r12
7194 __func_addr:
7195 .word func @ behave as if you saw a ARM_32 reloc.
7197 (v5t static images)
7198 .arm
7199 __func_from_arm:
7200 ldr pc, __func_addr
7201 __func_addr:
7202 .word func @ behave as if you saw a ARM_32 reloc.
7204 (relocatable images)
7205 .arm
7206 __func_from_arm:
7207 ldr r12, __func_offset
7208 add r12, r12, pc
7209 bx r12
7210 __func_offset:
7211 .word func - . */
7213 #define ARM2THUMB_STATIC_GLUE_SIZE 12
7218 #define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
7222 #define ARM2THUMB_PIC_GLUE_SIZE 16
7227 /* Thumb->ARM: Thumb->(non-interworking aware) ARM
7229 .thumb .thumb
7230 .align 2 .align 2
7231 __func_from_thumb: __func_from_thumb:
7232 bx pc push {r6, lr}
7233 nop ldr r6, __func_addr
7234 .arm mov lr, pc
7235 b func bx r6
7236 .arm
7237 ;; back_to_thumb
7238 ldmia r13! {r6, lr}
7239 bx lr
7240 __func_addr:
7241 .word func */
7243 #define THUMB2ARM_GLUE_SIZE 8
7248 #define VFP11_ERRATUM_VENEER_SIZE 8
7249 #define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
7250 #define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
7252 #define ARM_BX_VENEER_SIZE 12
7257 #ifndef ELFARM_NABI_C_INCLUDED
7258 static void
7260 {
7265 {
7266 /* Do not include empty glue sections in the output. */
7268 {
7272 }
7274 }
7286 }
7288 bool
7290 {
7298 ARM2THUMB_GLUE_SECTION_NAME);
7302 THUMB2ARM_GLUE_SECTION_NAME);
7306 VFP11_ERRATUM_VENEER_SECTION_NAME);
7310 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7314 ARM_BX_GLUE_SECTION_NAME);
7317 }
7319 /* Allocate space and symbols for calling a Thumb function from Arm mode.
7320 returns the symbol identifying the stub. */
7325 {
7332 bfd_vma val;
7333 bfd_size_type size;
7339 s = bfd_get_linker_section
7350 myh = elf_link_hash_lookup
7354 {
7355 /* We've already seen this guy. */
7358 }
7360 /* The only trick here is using hash_table->arm_glue_size as the value.
7361 Even though the section isn't allocated yet, this is where we will be
7362 putting it. The +1 on the value marks that the stub has not been
7363 output yet - not that it is a Thumb function. */
7381 else
7388 }
7390 /* Allocate space for ARMv4 BX veneers. */
7392 static void
7394 {
7400 bfd_vma val;
7402 /* BX PC does not need a veneer. */
7410 /* Check if this veneer has already been allocated. */
7414 s = bfd_get_linker_section
7419 /* Add symbol for veneer. */
7426 myh = elf_link_hash_lookup
7444 }
7447 /* Add an entry to the code/data map for section SEC. */
7449 static void
7451 {
7456 {
7461 }
7466 {
7471 }
7474 {
7477 }
7478 }
7481 /* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
7482 veneers are handled for now. */
7484 static bfd_vma
7490 {
7496 bfd_vma val;
7504 s = bfd_get_linker_section
7518 myh = elf_link_hash_lookup
7533 /* Link veneer back to calling location. */
7547 /* A symbol for the return from the veneer. */
7551 myh = elf_link_hash_lookup
7568 /* Generate a mapping symbol for the veneer section, and explicitly add an
7569 entry for that symbol to the code/data map for the section. */
7571 {
7573 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
7574 ever requires this erratum fix. */
7584 /* The elf32_arm_init_maps function only cares about symbols from input
7585 BFDs. We must make a note of this generated mapping symbol
7586 ourselves so that code byteswapping works properly in
7587 elf32_arm_write_section. */
7589 }
7595 /* The offset of the veneer. */
7597 }
7599 /* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
7600 veneers need to be handled because used only in Cortex-M. */
7602 static bfd_vma
7608 bfd_size_type veneer_size)
7609 {
7615 bfd_vma val;
7623 s = bfd_get_linker_section
7637 myh = elf_link_hash_lookup
7652 /* Link veneer back to calling location. */
7666 /* A symbol for the return from the veneer. */
7670 myh = elf_link_hash_lookup
7687 /* Generate a mapping symbol for the veneer section, and explicitly add an
7688 entry for that symbol to the code/data map for the section. */
7690 {
7692 /* Creates a THUMB symbol since there is no other choice. */
7702 /* The elf32_arm_init_maps function only cares about symbols from input
7703 BFDs. We must make a note of this generated mapping symbol
7704 ourselves so that code byteswapping works properly in
7705 elf32_arm_write_section. */
7707 }
7713 /* The offset of the veneer. */
7715 }
7717 #define ARM_GLUE_SECTION_FLAGS \
7718 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
7719 | SEC_READONLY | SEC_LINKER_CREATED)
7721 /* Create a fake section for use by the ARM backend of the linker. */
7723 static bool
7725 {
7730 /* Already made. */
7739 /* Set the gc mark to prevent the section from being removed by garbage
7740 collection, despite the fact that no relocs refer to this section. */
7744 }
7746 /* Set size of .plt entries. This function is called from the
7747 linker scripts in ld/emultempl/{armelf}.em. */
7749 void
7751 {
7753 }
7755 /* Add the glue sections to ABFD. This function is called from the
7756 linker scripts in ld/emultempl/{armelf}.em. */
7758 bool
7761 {
7767 /* If we are only performing a partial
7768 link do not bother adding the glue. */
7780 return addglue
7782 }
7784 /* Mark output sections of veneers needing a dedicated one with SEC_KEEP. This
7785 ensures they are not marked for deletion by
7786 strip_excluded_output_sections () when veneers are going to be created
7787 later. Not doing so would trigger assert on empty section size in
7788 lang_size_sections_1 (). */
7790 void
7792 {
7795 /* If we are only performing a partial
7796 link do not bother adding the glue. */
7801 {
7812 }
7813 }
7815 /* Select a BFD to be used to hold the sections used by the glue code.
7816 This function is called from the linker scripts in ld/emultempl/
7817 {armelf/pe}.em. */
7819 bool
7821 {
7824 /* If we are only performing a partial link
7825 do not bother getting a bfd to hold the glue. */
7829 /* Make sure we don't attach the glue sections to a dynamic object. */
7838 /* Save the bfd for later use. */
7842 }
7844 static void
7846 {
7850 Tag_CPU_arch);
7853 {
7856 }
7857 else
7858 {
7861 }
7862 }
7864 bool
7867 {
7876 /* If we are only performing a partial link do not bother
7877 to construct any glue. */
7881 /* Here we have a bfd that is to be included on the link. We have a
7882 hook to do reloc rummaging, before section sizes are nailed down. */
7889 {
7891 abfd);
7893 }
7895 /* PR 5398: If we have not decided to include any loadable sections in
7896 the output then we will not have a glue owner bfd. This is OK, it
7897 just means that there is nothing else for us to do here. */
7901 /* Rummage around all the relocs and map the glue vectors. */
7908 {
7918 /* Load the relocs. */
7919 internal_relocs
7927 {
7936 /* These are the only relocation types we care about. */
7941 /* Get the section contents if we haven't done so already. */
7943 {
7944 /* Get cached copy if it exists. */
7947 else
7948 {
7949 /* Go get them off disk. */
7952 }
7953 }
7956 {
7962 }
7964 /* If the relocation is not against a symbol it cannot concern us. */
7967 /* We don't care about local symbols. */
7971 /* This is an external symbol. */
7976 /* If the relocation is against a static symbol it must be within
7977 the current section and so cannot be a cross ARM/Thumb relocation. */
7981 /* If the call will go through a PLT entry then we do not need
7982 glue. */
7987 {
7989 /* This one is a call from arm code. We need to look up
7990 the target of the call. If it is a thumb target, we
7991 insert glue. */
7999 }
8000 }
8009 }
8013 error_return:
8020 }
8021 #endif
8024 /* Initialise maps of ARM/Thumb/data for input BFDs. */
8026 void
8028 {
8033 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
8043 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
8044 should contain the number of local symbols, which should come before any
8045 global symbols. Mapping symbols are always local. */
8047 NULL);
8049 /* No internal symbols read? Skip this BFD. */
8054 {
8061 {
8066 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
8068 }
8069 }
8070 }
8073 /* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
8074 say what they wanted. */
8076 void
8078 {
8086 {
8087 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
8092 else
8094 }
8095 }
8098 void
8100 {
8106 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
8108 {
8110 {
8117 /* Give a warning, but do as the user requests anyway. */
8120 }
8121 }
8123 /* For earlier architectures, we might need the workaround, but do not
8124 enable it by default. If users is running with broken hardware, they
8125 must enable the erratum fix explicitly. */
8127 }
8129 void
8131 {
8138 /* We assume only Cortex-M4 may require the fix. */
8141 {
8143 /* Give a warning, but do as the user requests anyway. */
8144 _bfd_error_handler
8147 }
8148 }
8150 enum bfd_arm_vfp11_pipe
8151 {
8152 VFP11_FMAC,
8153 VFP11_LS,
8154 VFP11_DS,
8155 VFP11_BAD
8156 };
8158 /* Return a VFP register number. This is encoded as RX:X for single-precision
8159 registers, or X:RX for double-precision registers, where RX is the group of
8160 four bits in the instruction encoding and X is the single extension bit.
8161 RX and X fields are specified using their lowest (starting) bit. The return
8162 value is:
8164 0...31: single-precision registers s0...s31
8165 32...63: double-precision registers d0...d31.
8167 Although X should be zero for VFP11 (encoding d0...d15 only), we might
8168 encounter VFP3 instructions, so we allow the full range for DP registers. */
8170 static unsigned int
8173 {
8176 else
8178 }
8180 /* Set bits in *WMASK according to a register number REG as encoded by
8181 bfd_arm_vfp11_regno(). Ignore d16-d31. */
8183 static void
8185 {
8190 }
8192 /* Return TRUE if WMASK overwrites anything in REGS. */
8194 static bool
8196 {
8200 {
8213 }
8216 }
8218 /* In this function, we're interested in two things: finding input registers
8219 for VFP data-processing instructions, and finding the set of registers which
8220 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
8221 hold the written set, so FLDM etc. are easy to deal with (we're only
8222 interested in 32 SP registers or 16 dp registers, due to the VFP version
8223 implemented by the chip in question). DP registers are marked by setting
8224 both SP registers in the write mask). */
8226 static enum bfd_arm_vfp11_pipe
8229 {
8234 {
8244 {
8266 vfp_binop:
8274 {
8279 {
8293 /* These instructions will not bounce due to underflow. */
8299 /* fsqrt cannot underflow, but it can (perhaps) overwrite
8300 registers to cause the erratum in previous instructions. */
8306 {
8311 /* Only FCVTSD can underflow. */
8318 }
8323 }
8324 }
8329 }
8330 }
8331 /* Two-register transfer. */
8333 {
8337 {
8340 else
8341 {
8344 }
8345 }
8348 }
8350 {
8355 {
8362 {
8370 }
8380 }
8383 }
8384 /* Single-register transfer. Note L==0. */
8386 {
8391 {
8394 /* Mark fmdhr and fmdlr as writing to the whole of the DP
8395 destination register. I don't know if this is exactly right,
8396 but it is the conservative choice. */
8402 }
8405 }
8408 }
8414 /* Look for potentially-troublesome code sequences which might trigger the
8415 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
8416 (available from ARM) for details of the erratum. A short version is
8417 described in ld.texinfo. */
8419 bool
8421 {
8432 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
8433 The states transition as follows:
8435 0 -> 1 (vector) or 0 -> 2 (scalar)
8436 A VFP FMAC-pipeline instruction has been seen. Fill
8437 regs[0]..regs[numregs-1] with its input operands. Remember this
8438 instruction in 'first_fmac'.
8440 1 -> 2
8441 Any instruction, except for a VFP instruction which overwrites
8442 regs[*].
8444 1 -> 3 [ -> 0 ] or
8445 2 -> 3 [ -> 0 ]
8446 A VFP instruction has been seen which overwrites any of regs[*].
8447 We must make a veneer! Reset state to 0 before examining next
8448 instruction.
8450 2 -> 0
8451 If we fail to match anything in state 2, reset to state 0 and reset
8452 the instruction pointer to the instruction after 'first_fmac'.
8454 If the VFP11 vector mode is in use, there must be at least two unrelated
8455 instructions between anti-dependent VFP11 instructions to properly avoid
8456 triggering the erratum, hence the use of the extra state 1. */
8458 /* If we are only performing a partial link do not bother
8459 to construct any glue. */
8463 /* Skip if this bfd does not correspond to an ELF image. */
8467 /* We should have chosen a fix type by the time we get here. */
8473 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8478 {
8482 /* If we don't have executable progbits, we're not interested in this
8483 section. Also skip if section is to be excluded. */
8503 elf32_arm_compare_mapping);
8506 {
8512 /* FIXME: Only ARM mode is supported at present. We may need to
8513 support Thumb-2 mode also at some point. */
8518 {
8533 {
8537 /* I'm assuming the VFP11 erratum can trigger with denorm
8538 operands on either the FMAC or the DS pipeline. This might
8539 lead to slightly overenthusiastic veneer insertion. */
8541 {
8545 }
8549 {
8552 other_regs,
8556 numregs))
8558 else
8560 }
8564 {
8567 other_regs,
8571 numregs))
8573 else
8574 {
8577 }
8578 }
8583 }
8586 {
8595 {
8602 }
8605 first_fmac);
8613 }
8616 }
8617 }
8622 }
8626 error_return:
8631 }
8633 /* Find virtual-memory addresses for VFP11 erratum veneers and return locations
8634 after sections have been laid out, using specially-named symbols. */
8636 void
8639 {
8647 /* Skip if this bfd does not correspond to an ELF image. */
8660 {
8665 {
8667 bfd_vma vma;
8670 {
8673 /* Find veneer symbol. */
8677 myh = elf_link_hash_lookup
8693 /* Find return location. */
8697 myh = elf_link_hash_lookup
8713 }
8714 }
8715 }
8718 }
8720 /* Find virtual-memory addresses for STM32L4XX erratum veneers and
8721 return locations after sections have been laid out, using
8722 specially-named symbols. */
8724 void
8727 {
8735 /* Skip if this bfd does not correspond to an ELF image. */
8748 {
8753 {
8755 bfd_vma vma;
8758 {
8760 /* Find veneer symbol. */
8764 myh = elf_link_hash_lookup
8779 /* Find return location. */
8783 myh = elf_link_hash_lookup
8799 }
8800 }
8801 }
8804 }
8808 {
8809 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
8810 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
8812 }
8816 {
8817 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
8818 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
8820 }
8824 {
8825 /* A6.5 Extension register load or store instruction
8826 A7.7.229
8827 We look for SP 32-bit and DP 64-bit registers.
8828 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
8829 <list> is consecutive 64-bit registers
8830 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
8831 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
8832 <list> is consecutive 32-bit registers
8833 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
8834 if P==0 && U==1 && W==1 && Rn=1101 VPOP
8835 if PUW=010 || PUW=011 || PUW=101 VLDM. */
8836 return
8841 /* (IA with !), includes VPOP (when reg number is SP). */
8843 /* (DB with !). */
8845 }
8847 /* STM STM32L4XX erratum : This function assumes that it receives an LDM or
8848 VLDM opcode and:
8849 - computes the number and the mode of memory accesses
8850 - decides if the replacement should be done:
8851 . replaces only if > 8-word accesses
8852 . or (testing purposes only) replaces all accesses. */
8854 static bool
8856 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
8857 {
8860 /* The field encoding the register list is the same for both LDMIA
8861 and LDMDB encodings. */
8867 /* DEFAULT mode accounts for the real bug condition situation,
8868 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
8872 }
8874 /* Look for potentially-troublesome code sequences which might trigger
8875 the STM STM32L4XX erratum. */
8877 bool
8880 {
8888 /* If we are only performing a partial link do not bother
8889 to construct any glue. */
8893 /* Skip if this bfd does not correspond to an ELF image. */
8900 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8905 {
8909 /* If we don't have executable progbits, we're not interested in this
8910 section. Also skip if section is to be excluded. */
8930 elf32_arm_compare_mapping);
8933 {
8940 /* Only Thumb2 mode need be supported with this CM4 specific
8941 code, we should not encounter any arm mode eg span_type
8942 != 'a'. */
8947 {
8954 /* The first 16-bits of all 32-bit thumb2 instructions start
8955 with opcode[15..13]=0b111 and the encoded op1 can be anything
8956 except opcode[12..11]!=0b00.
8957 See 32-bit Thumb instruction encoding. */
8961 /* Compute the predicate that tells if the instruction
8962 is concerned by the IT block
8963 - Creates an error if there is a ldm that is not
8964 last in the IT block thus cannot be replaced
8965 - Otherwise we can create a branch at the end of the
8966 IT block, it will be controlled naturally by IT
8967 with the proper pseudo-predicate
8968 - So the only interesting predicate is the one that
8969 tells that we are not on the last item of an IT
8970 block. */
8975 {
8976 /* Load the rest of the insn (in manual-friendly order). */
8981 /* Veneers are created for (v)ldm depending on
8982 option flags and memory accesses conditions; but
8983 if the instruction is not the last instruction of
8984 an IT block, we cannot create a jump there, so we
8985 bail out. */
8987 && stm32l4xx_need_create_replacing_stub
8989 {
8991 {
8992 _bfd_error_handler
8993 /* xgettext:c-format */
8995 " in non-last IT block instruction:"
8996 " STM32L4XX veneer cannot be generated; "
8997 "use gcc option -mrestrict-it to generate"
9000 }
9001 else
9002 {
9005 bfd_zmalloc
9011 /* We create only thumb branches. */
9013 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
9014 record_stm32l4xx_erratum_veneer
9016 i,
9017 is_ldm ?
9018 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
9019 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
9023 }
9024 }
9025 }
9026 else
9027 {
9028 /* A7.7.37 IT p208
9029 IT blocks are only encoded in T1
9030 Encoding T1: IT{x{y{z}}} <firstcond>
9031 1 0 1 1 - 1 1 1 1 - firstcond - mask
9032 if mask = '0000' then see 'related encodings'
9033 We don't deal with UNPREDICTABLE, just ignore these.
9034 There can be no nested IT blocks so an IT block
9035 is naturally a new one for which it is worth
9036 computing its size. */
9039 /* If we have a new IT block we compute its size. */
9041 {
9042 /* Compute the number of instructions controlled
9043 by the IT block, it will be used to decide
9044 whether we are inside an IT block or not. */
9047 }
9048 }
9051 }
9052 }
9057 }
9061 error_return:
9066 }
9068 /* Set target relocation values needed during linking. */
9070 void
9074 {
9090 else
9091 {
9094 }
9101 else
9113 }
9115 /* Replace the target offset of a Thumb bl or b.w instruction. */
9117 static void
9119 {
9120 bfd_vma upper;
9121 bfd_vma lower;
9138 }
9140 /* Thumb code calling an ARM function. */
9142 static int
9150 bfd_vma offset,
9151 bfd_signed_vma addend,
9152 bfd_vma val,
9154 {
9156 bfd_vma my_offset;
9172 THUMB2ARM_GLUE_SECTION_NAME);
9179 {
9183 {
9184 _bfd_error_handler
9190 }
9201 ret_offset =
9202 /* Address of destination of the stub. */
9205 /* Offset from the start of the current section
9206 to the start of the stubs. */
9208 /* Offset of the start of this stub from the start of the stubs. */
9209 + my_offset
9210 /* Address of the start of the current section. */
9212 /* The branch instruction is 4 bytes into the stub. */
9214 /* ARM branches work from the pc of the instruction + 8. */
9220 }
9224 /* Now go back and fix up the original BL insn to point to here. */
9225 ret_offset =
9226 /* Address of where the stub is located. */
9228 /* Address of where the BL is located. */
9231 /* Addend in the relocation. */
9232 - addend
9233 /* Biassing for PC-relative addressing. */
9239 }
9241 /* Populate an Arm to Thumb stub. Returns the stub symbol. */
9249 bfd_vma val,
9252 {
9253 bfd_vma my_offset;
9269 {
9273 {
9274 _bfd_error_handler
9278 }
9285 {
9286 /* For relocatable objects we can't use absolute addresses,
9287 so construct the address from a relative offset. */
9288 /* TODO: If the offset is small it's probably worth
9289 constructing the address with adds. */
9296 /* Adjust the offset by 4 for the position of the add,
9297 and 8 for the pipeline offset. */
9304 }
9306 {
9310 /* It's a thumb address. Add the low order bit. */
9313 }
9314 else
9315 {
9322 /* It's a thumb address. Add the low order bit. */
9327 }
9328 }
9333 }
9335 /* Arm code calling a Thumb function. */
9337 static int
9345 bfd_vma offset,
9346 bfd_signed_vma addend,
9347 bfd_vma val,
9349 {
9351 bfd_vma my_offset;
9362 ARM2THUMB_GLUE_SECTION_NAME);
9376 /* Somehow these are both 4 too far, so subtract 8. */
9378 + my_offset
9390 }
9392 /* Populate Arm stub for an exported Thumb function. */
9394 static bool
9396 {
9403 bfd_vma val;
9407 /* Allocate stubs for exported Thumb functions on v4t. */
9416 ARM2THUMB_GLUE_SECTION_NAME);
9434 }
9436 /* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
9438 static bfd_vma
9440 {
9442 bfd_vma glue_addr;
9451 ARM_BX_GLUE_SECTION_NAME);
9461 {
9467 }
9470 }
9472 /* Generate Arm stubs for exported Thumb symbols. */
9473 static void
9476 {
9480 /* Ignore this if we are not called by the ELF backend linker. */
9487 /* If blx is available then exported Thumb symbols are OK and there is
9488 nothing to do. */
9493 link_info);
9494 }
9496 /* Reserve space for COUNT dynamic relocations in relocation selection
9497 SRELOC. */
9499 static void
9501 bfd_size_type count)
9502 {
9510 }
9512 /* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
9513 dynamic, the relocations should go in SRELOC, otherwise they should
9514 go in the special .rel.iplt section. */
9516 static void
9518 bfd_size_type count)
9519 {
9525 else
9526 {
9529 }
9530 }
9532 /* Add relocation REL to the end of relocation section SRELOC. */
9534 static void
9537 {
9552 }
9554 /* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
9555 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
9556 to .plt. */
9558 static void
9563 {
9571 {
9575 /* NaCl uses a special first entry in .iplt too. */
9579 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
9581 }
9582 else
9583 {
9588 {
9589 /* Allocate room for R_ARM_FUNCDESC_VALUE. */
9590 /* For lazy binding, relocations will be put into .rel.plt, in
9591 .rel.got otherwise. */
9592 /* FIXME: today we don't support lazy binding so put it in .rel.got */
9595 else
9597 }
9598 else
9599 {
9600 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
9602 }
9604 /* If this is the first .plt entry, make room for the special
9605 first entry. */
9610 }
9612 /* Allocate the PLT entry itself, including any leading Thumb stub. */
9618 /* We also need to make an entry in the .got.plt section, which
9619 will be placed in the .got section by the linker script. */
9622 else
9625 /* Function descriptor takes 64 bits in GOT. */
9627 else
9629 }
9631 static bfd_vma
9633 {
9635 }
9637 static bfd_vma
9639 {
9641 }
9643 /* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
9644 the entry lives in .iplt and resolves to (*SYM_VALUE)().
9645 Otherwise, DYNINDX is the index of the symbol in the dynamic
9646 symbol table and SYM_VALUE is undefined.
9648 ROOT_PLT points to the offset of the PLT entry from the start of its
9649 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
9650 bookkeeping information.
9652 Returns FALSE if there was a problem. */
9654 static bool
9659 {
9665 bfd_vma plt_index;
9666 Elf_Internal_Rela rel;
9667 bfd_vma got_header_size;
9671 /* Pick the appropriate sections and sizes. */
9673 {
9678 /* There are no reserved entries in .igot.plt, and no special
9679 first entry in .iplt. */
9681 }
9682 else
9683 {
9689 }
9698 /* Get the offset into the .(i)got.plt table of the entry that
9699 corresponds to this function. */
9702 /* Get the index in the procedure linkage table which
9703 corresponds to this symbol. This is the index of this symbol
9704 in all the symbols for which we are making plt entries.
9705 After the reserved .got.plt entries, all symbols appear in
9706 the same order as in .plt. */
9708 /* Function descriptor takes 8 bytes. */
9710 else
9713 /* Calculate the address of the GOT entry. */
9718 /* ...and the address of the PLT entry. */
9725 {
9727 bfd_vma val;
9730 {
9738 else
9740 }
9741 }
9743 {
9745 bfd_vma val;
9748 {
9758 else
9760 }
9765 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
9766 referencing the GOT for this PLT entry. */
9773 /* Create the R_ARM_ABS32 relocation referencing the
9774 beginning of the PLT for this GOT entry. */
9779 }
9781 {
9782 /* Calculate the displacement between the PLT slot and the
9783 common tail that's part of the special initial PLT slot. */
9784 int32_t tail_displacement
9794 /* Calculate the displacement between the PLT slot and the entry
9795 in the GOT. The offset accounts for the value produced by
9796 adding to pc in the penultimate instruction of the PLT stub. */
9797 got_displacement = (got_address
9800 /* NaCl does not support interworking at all. */
9818 }
9820 {
9822 ? elf32_arm_fdpic_thumb_plt_entry
9825 /* Fill-up Thumb stub if needed. */
9827 {
9832 }
9833 /* As we are using 32 bit instructions even for the Thumb
9834 version, we have to use 'put_arm_insn' instead of
9835 'put_thumb_insn'. */
9843 {
9844 /* funcdesc_value_reloc_offset. */
9852 }
9853 }
9855 {
9856 /* PR ld/16017: Generate thumb only PLT entries. */
9858 {
9859 /* FIXME: We ought to be able to generate thumb-1 PLT
9860 instructions... */
9862 output_bfd);
9864 }
9866 /* Calculate the displacement between the PLT slot and the entry in
9867 the GOT. The 12-byte offset accounts for the value produced by
9868 adding to pc in the 3rd instruction of the PLT stub. */
9871 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
9872 instead of 'put_thumb_insn'. */
9893 }
9894 else
9895 {
9896 /* Calculate the displacement between the PLT slot and the
9897 entry in the GOT. The eight-byte offset accounts for the
9898 value produced by adding to pc in the first instruction
9899 of the PLT stub. */
9903 {
9908 }
9911 {
9926 #ifdef FOUR_WORD_PLT
9928 #endif
9929 }
9930 else
9931 {
9948 }
9949 }
9951 /* Fill in the entry in the .rel(a).(i)plt section. */
9955 {
9956 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
9957 The dynamic linker or static executable then calls SYM_VALUE
9958 to determine the correct run-time value of the .igot.plt entry. */
9961 }
9962 else
9963 {
9964 /* For FDPIC we will have to resolve a R_ARM_FUNCDESC_VALUE
9965 used by PLT entry. */
9967 {
9970 }
9971 else
9972 {
9977 /* PR ld/16017
9978 When thumb only we need to set the LSB for any address that
9979 will be used with an interworking branch instruction. */
9982 }
9983 }
9985 /* Fill in the entry in the global offset table. */
9990 {
9991 /* Setup initial funcdesc value. */
9992 /* FIXME: we don't support lazy binding because there is a
9993 race condition between both words getting written and
9994 some other thread attempting to read them. The ARM
9995 architecture does not have an atomic 64 bit load/store
9996 instruction that could be used to prevent it; it is
9997 recommended that threaded FDPIC applications run with the
9998 LD_BIND_NOW environment variable set. */
10003 }
10007 else
10008 {
10010 {
10011 /* For FDPIC we put PLT relocationss into .rel.got when not
10012 lazy binding otherwise we put them in .rel.plt. For now,
10013 we don't support lazy binding so put it in .rel.got. */
10016 else
10018 }
10019 else
10020 {
10023 }
10024 }
10027 }
10029 /* Some relocations map to different relocations depending on the
10030 target. Return the real relocation. */
10032 static int
10035 {
10037 {
10041 else
10049 }
10050 }
10052 /* Return the base VMA address which should be subtracted from real addresses
10053 when resolving @dtpoff relocation.
10054 This is PT_TLS segment p_vaddr. */
10056 static bfd_vma
10058 {
10059 /* If tls_sec is NULL, we should have signalled an error already. */
10063 }
10065 /* Return the relocation value for @tpoff relocation
10066 if STT_TLS virtual address is ADDRESS. */
10068 static bfd_vma
10070 {
10072 bfd_vma base;
10074 /* If tls_sec is NULL, we should have signalled an error already. */
10079 }
10081 /* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
10082 VALUE is the relocation value. */
10084 static bfd_reloc_status_type
10086 {
10093 }
10095 /* Handle TLS relaxations. Relaxing is possible for symbols that use
10096 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
10097 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
10099 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
10100 is to then call final_link_relocate. Return other values in the
10101 case of error.
10103 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
10104 the pre-relaxed code. It would be nice if the relocs were updated
10105 to match the optimization. */
10107 static bfd_reloc_status_type
10111 {
10115 {
10122 else
10123 {
10127 else
10129 }
10134 /* Thumb insn. */
10137 {
10139 /* nop */
10141 }
10143 {
10145 /* nop */
10147 else
10148 /* ldr rx,[ry] */
10150 }
10152 {
10154 /* nop */
10156 else
10157 /* mov r0, rx */
10160 }
10161 else
10162 {
10164 /* It's a 32 bit instruction, fetch the rest of it for
10165 error generation. */
10168 _bfd_error_handler
10169 /* xgettext:c-format */
10175 }
10179 /* arm insn. */
10182 {
10184 /* mov rx, ry */
10187 }
10189 {
10191 /* nop */
10193 else
10194 /* ldr rx,[ry] */
10197 }
10199 {
10201 /* nop */
10203 else
10204 /* mov r0, rx */
10207 }
10208 else
10209 {
10210 _bfd_error_handler
10211 /* xgettext:c-format */
10217 }
10221 /* GD->IE relaxation, turn the instruction into 'nop' or
10222 'ldr r0, [pc,r0]' */
10228 /* GD->IE relaxation. */
10230 /* add r0,pc; ldr r0, [r0] */
10233 /* nop.w */
10235 else
10236 /* nop; nop */
10242 }
10244 }
10246 /* For a given value of n, calculate the value of G_n as required to
10247 deal with group relocations. We return it in the form of an
10248 encoded constant-and-rotation, together with the final residual. If n is
10249 specified as less than zero, then final_residual is filled with the
10250 input value and no further action is performed. */
10252 static bfd_vma
10254 {
10256 bfd_vma g_n;
10261 {
10264 /* Calculate which part of the value to mask. */
10267 else
10268 {
10271 /* Determine the most significant bit in the residual and
10272 align the resulting value to a 2-bit boundary. */
10277 /* The desired shift is now (msb - 6), or zero, whichever
10278 is the greater. */
10282 }
10284 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
10289 /* Calculate the residual for the next time around. */
10291 }
10296 }
10298 /* Given an ARM instruction, determine whether it is an ADD or a SUB.
10299 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
10301 static int
10303 {
10313 }
10315 /* Perform a relocation as part of a final link. */
10317 static bfd_reloc_status_type
10324 bfd_vma value,
10333 {
10343 bfd_vma addend;
10344 bfd_signed_vma signed_addend;
10346 bfd_vma dynreloc_value;
10351 bfd_vma plt_offset;
10352 bfd_vma gotplt_offset;
10363 /* Some relocation types map to different relocations depending on the
10364 target. We pick the right one here. */
10367 /* It is possible to have linker relaxations on some TLS access
10368 models. Update our information here. */
10381 else
10387 {
10388 bfd_vma sign;
10391 {
10396 }
10397 /* Note: the addend and signed_addend calculated here are
10398 incorrect for any split field. */
10404 }
10405 else
10408 /* Record the symbol information that should be used in dynamic
10409 relocations. */
10415 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
10416 VALUE appropriately for relocations that we resolve at link time. */
10421 {
10426 {
10430 /* Populate .iplt entries here, because not all of them will
10431 be seen by finish_dynamic_symbol. The lower bit is set if
10432 we have already populated the entry. */
10434 plt_offset--;
10435 else
10436 {
10440 else
10442 }
10444 /* Static relocations always resolve to the .iplt entry. */
10451 /* If there are non-call relocations that resolve to the .iplt
10452 entry, then all dynamic ones must too. */
10454 {
10457 }
10458 }
10459 else
10460 /* We populate the .plt entry in finish_dynamic_symbol. */
10462 }
10463 else
10464 {
10468 }
10470 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we are
10471 resolving a function call relocation. We want to inform the user
10472 that something is wrong. */
10477 /* Calls through a PLT are special: the assembly source code
10478 cannot be annotated with '.type foo(PLT), %function', and
10479 they handled specifically below anyway. */
10481 {
10483 {
10484 /* As an exception, assume that absolute symbols are of the
10485 right kind (Thumb). They are presumably defined in the
10486 linker script, where it is not possible to declare them as
10487 Thumb (and thus are seen as Arm mode). Inform the user with
10488 a warning, though. */
10492 _bfd_error_handler
10496 else
10497 _bfd_error_handler
10501 }
10502 else
10503 /* Otherwise do not silently build a stub, and let the users
10504 know they have to fix their code. Indeed, we could decide
10505 to insert a stub involving Arm code and/or BLX, leading to
10506 a run-time crash. */
10508 }
10510 /* Fail early if branch_type is ST_BRANCH_UNKNOWN and we target a
10511 Thumb-only CPU. We could emit a warning on Arm-capable targets
10512 too, but that would be too verbose (a lot of legacy code does not
10513 use the .type foo, %function directive). */
10518 /* Exception to the rule above: a branch to an undefined weak
10519 symbol is turned into a jump to the next instruction unless a
10520 PLT entry will be created (see below). */
10523 {
10526 _bfd_error_handler
10529 else
10530 _bfd_error_handler
10535 }
10541 {
10543 /* We don't need to find a value for this symbol. It's just a
10544 marker. */
10551 /* Fall through. */
10563 /* Handle relocations which should use the PLT entry. ABS32/REL32
10564 will use the symbol's value, which may point to a PLT entry, but we
10565 don't need to handle that here. If we created a PLT entry, all
10566 branches in this object should go to it, except if the PLT is too
10567 far away, in which case a long branch stub should be inserted. */
10574 {
10575 /* If we've created a .plt section, and assigned a PLT entry
10576 to this function, it must either be a STT_GNU_IFUNC reference
10577 or not be known to bind locally. In other cases, we should
10578 have cleared the PLT entry by now. */
10588 }
10590 /* When generating a shared library or PIE, these relocations
10591 are copied into the output file to be resolved at run time. */
10611 {
10612 Elf_Internal_Rela outrel;
10618 {
10624 _bfd_error_handler
10629 }
10634 {
10640 }
10665 else
10666 {
10669 /* This symbol is local, or marked to become local. */
10672 /* On SVR4-ish systems, the dynamic loader cannot
10673 relocate the text and data segments independently,
10674 so the symbol does not matter. */
10677 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
10678 to the .iplt entry. Instead, every non-call reference
10679 must use an R_ARM_IRELATIVE relocation to obtain the
10680 correct run-time address. */
10684 else
10688 else
10690 }
10694 else
10697 /* If this reloc is against an external symbol, we do not want to
10698 fiddle with the addend. Otherwise, we need to include the symbol
10699 value so that it becomes an addend for the dynamic reloc. */
10706 }
10708 {
10717 {
10721 {
10722 /* Check for Arm calling Arm function. */
10723 /* FIXME: Should we translate the instruction into a BL
10724 instruction instead ? */
10726 _bfd_error_handler
10731 }
10733 {
10734 /* Check for Arm calling Thumb function. */
10736 {
10741 error_message))
10743 else
10745 }
10746 }
10748 /* Check if a stub has to be inserted because the
10749 destination is too far or we are changing mode. */
10753 {
10764 {
10765 /* The target is out of reach, so redirect the
10766 branch to the local stub for this function. */
10770 stub_type);
10771 {
10779 }
10780 }
10781 else
10782 {
10783 /* If the call goes through a PLT entry, make sure to
10784 check distance to the right destination address. */
10786 {
10791 /* The PLT entry is in ARM mode, regardless of the
10792 target function. */
10794 }
10795 }
10796 }
10798 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
10799 where:
10800 S is the address of the symbol in the relocation.
10801 P is address of the instruction being relocated.
10802 A is the addend (extracted from the instruction) in bytes.
10804 S is held in 'value'.
10805 P is the base address of the section containing the
10806 instruction plus the offset of the reloc into that
10807 section, ie:
10808 (input_section->output_section->vma +
10809 input_section->output_offset +
10810 rel->r_offset).
10811 A is the addend, converted into bytes, ie:
10812 (signed_addend * 4)
10814 Note: None of these operations have knowledge of the pipeline
10815 size of the processor, thus it is up to the assembler to
10816 encode this information into the addend. */
10825 /* A branch to an undefined weak symbol is turned into a jump to
10826 the next instruction unless a PLT entry will be created.
10827 Do the same for local undefined symbols (but not for STN_UNDEF).
10828 The jump to the next instruction is optimized as a NOP depending
10829 on the architecture. */
10833 {
10838 else
10840 }
10841 else
10842 {
10843 /* Perform a signed range check. */
10854 {
10855 /* Set the H bit in the BLX instruction. */
10857 {
10860 else
10862 }
10864 /* Select the correct instruction (BL or BLX). */
10865 /* Only if we are not handling a BL to a stub. In this
10866 case, mode switching is performed by the stub. */
10870 {
10873 }
10874 }
10875 }
10876 }
10908 {
10909 /* Check for overflow. */
10912 }
10918 }
10926 /* There is no way to tell whether the user intended to use a signed or
10927 unsigned addend. When checking for overflow we accept either,
10928 as specified by the AAELF. */
10938 /* See comment for R_ARM_ABS8. */
10946 /* Support ldr and str instructions for the thumb. */
10948 {
10949 /* Need to refetch addend. */
10951 /* ??? Need to determine shift amount from operand size. */
10953 }
10956 /* ??? Isn't value unsigned? */
10960 /* ??? Value needs to be properly shifted into place first. */
10966 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
10967 {
10968 bfd_vma insn;
10969 bfd_signed_vma relocation;
10975 {
10980 }
10987 /* PR 21523: Use an absolute value. The user of this reloc will
10988 have already selected an ADD or SUB insn appropriately. */
10994 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
11008 }
11011 /* PR 10073: This reloc is not generated by the GNU toolchain,
11012 but it is supported for compatibility with third party libraries
11013 generated by other compilers, specifically the ARM/IAR. */
11014 {
11015 bfd_vma insn;
11016 bfd_signed_vma relocation;
11030 /* We do not check for overflow of this reloc. Although strictly
11031 speaking this is incorrect, it appears to be necessary in order
11032 to work with IAR generated relocs. Since GCC and GAS do not
11033 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
11034 a problem for them. */
11042 }
11045 /* Corresponds to: ldr.w reg, [pc, #offset]. */
11046 {
11047 bfd_vma insn;
11048 bfd_signed_vma relocation;
11054 {
11058 }
11078 }
11083 /* Thumb BL (branch long instruction). */
11084 {
11085 bfd_vma relocation;
11086 bfd_vma reloc_sign;
11090 bfd_signed_vma reloc_signed_max;
11091 bfd_signed_vma reloc_signed_min;
11092 bfd_vma check;
11093 bfd_signed_vma signed_check;
11098 /* A branch to an undefined weak symbol is turned into a jump to
11099 the next instruction unless a PLT entry will be created.
11100 The jump to the next instruction is optimized as a NOP.W for
11101 Thumb-2 enabled architectures. */
11104 {
11106 {
11109 }
11110 else
11111 {
11114 }
11116 }
11118 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
11119 with Thumb-1) involving the J1 and J2 bits. */
11121 {
11131 /* Sign extend. */
11135 }
11138 {
11139 /* Check for Thumb to Thumb call. */
11140 /* FIXME: Should we translate the instruction into a BL
11141 instruction instead ? */
11143 _bfd_error_handler
11148 }
11149 else
11150 {
11151 /* If it is not a call to Thumb, assume call to Arm.
11152 If it is a call relative to a section name, then it is not a
11153 function call at all, but rather a long jump. Calls through
11154 the PLT do not require stubs. */
11156 {
11158 {
11159 /* Convert BL to BLX. */
11161 }
11164 {
11168 error_message))
11170 else
11172 }
11173 }
11177 {
11178 /* Make sure this is a BL. */
11180 }
11181 }
11185 {
11186 /* Check if a stub has to be inserted because the destination
11187 is too far. */
11199 {
11200 /* The target is out of reach or we are changing modes, so
11201 redirect the branch to the local stub for this
11202 function. */
11206 stub_type);
11208 {
11215 }
11217 /* If this call becomes a call to Arm, force BLX. */
11219 {
11224 }
11225 }
11226 }
11228 /* Handle calls via the PLT. */
11230 {
11238 {
11239 /* If the Thumb BLX instruction is available, convert
11240 the BL to a BLX instruction to call the ARM-mode
11241 PLT entry. */
11244 }
11245 else
11246 {
11248 /* Target the Thumb stub before the ARM PLT entry. */
11251 }
11253 }
11263 /* If this is a signed value, the rightshift just dropped
11264 leading 1 bits (assuming twos complement). */
11267 else
11270 /* Calculate the permissable maximum and minimum values for
11271 this relocation according to whether we're relocating for
11272 Thumb-2 or not. */
11279 /* Assumes two's complement. */
11284 /* For a BLX instruction, make sure that the relocation is rounded up
11285 to a word boundary. This follows the semantics of the instruction
11286 which specifies that bit 1 of the target address will come from bit
11287 1 of the base address. */
11290 /* Put RELOCATION back into the insn. Assumes two's complement.
11291 We use the Thumb-2 encoding, which is safe even if dealing with
11292 a Thumb-1 instruction by virtue of our overflow check above. */
11302 /* Put the relocated value back in the object file: */
11307 }
11311 /* Thumb32 conditional branch instruction. */
11312 {
11313 bfd_vma relocation;
11319 bfd_signed_vma signed_check;
11324 /* Need to refetch the addend, reconstruct the top three bits,
11325 and squish the two 11 bit pieces together. */
11327 {
11341 }
11343 /* Handle calls via the PLT. */
11345 {
11349 /* Target the Thumb stub before the ARM PLT entry. */
11352 }
11361 {
11365 stub_type);
11367 {
11371 }
11372 }
11383 /* Put RELOCATION back into the insn. */
11384 {
11393 }
11395 /* Put the relocated value back in the object file: */
11400 }
11405 /* Thumb B (branch) instruction). */
11406 {
11407 bfd_signed_vma relocation;
11410 bfd_signed_vma signed_check;
11412 /* CZB cannot jump backward. */
11414 {
11418 }
11431 else
11437 /* Assumes two's complement. */
11442 }
11447 {
11448 bfd_vma insn;
11449 bfd_vma relocation;
11453 {
11454 /* Extract the addend. */
11457 }
11467 }
11475 /* Relocation is relative to the start of the
11476 global offset table. */
11482 /* If we are addressing a Thumb function, we need to adjust the
11483 address by one, so that attempts to call the function pointer will
11484 correctly interpret it as Thumb code. */
11488 /* Note that sgot->output_offset is not involved in this
11489 calculation. We always want the start of .got. If we
11490 define _GLOBAL_OFFSET_TABLE in a different way, as is
11491 permitted by the ABI, we might have to change this
11492 calculation. */
11499 /* Use global offset table as symbol value. */
11513 /* Relocation is to the entry for this symbol in the
11514 global offset table. */
11521 {
11522 /* We have a relocation against a locally-binding STT_GNU_IFUNC
11523 symbol, and the relocation resolves directly to the runtime
11524 target rather than to the .iplt entry. This means that any
11525 .got entry would be the same value as the .igot.plt entry,
11526 so there's no point creating both. */
11529 }
11531 {
11532 bfd_vma off;
11537 {
11538 /* We have already processsed one GOT relocation against
11539 this symbol. */
11544 }
11545 else
11546 {
11547 Elf_Internal_Rela outrel;
11552 {
11553 /* If the symbol doesn't resolve locally in a static
11554 object, we have an undefined reference. If the
11555 symbol doesn't resolve locally in a dynamic object,
11556 it should be resolved by the dynamic linker. */
11558 {
11561 }
11562 else
11565 }
11566 else
11567 {
11573 else
11574 {
11578 }
11580 }
11582 /* The GOT entry is initialized to zero by default.
11583 See if we should install a different value. */
11586 {
11590 }
11599 {
11604 }
11607 }
11609 }
11610 else
11611 {
11612 bfd_vma off;
11619 /* The offset must always be a multiple of 4. We use the
11620 least significant bit to record whether we have already
11621 generated the necessary reloc. */
11624 else
11625 {
11626 Elf_Internal_Rela outrel;
11633 else
11634 {
11638 }
11640 /* The GOT entry is initialized to zero by default.
11641 See if we should install a different value. */
11652 {
11658 }
11661 }
11664 }
11681 {
11682 bfd_vma off;
11691 else
11692 {
11693 /* If we don't know the module number, create a relocation
11694 for it. */
11696 {
11697 Elf_Internal_Rela outrel;
11712 }
11713 else
11717 }
11720 {
11726 }
11727 else
11728 {
11736 }
11737 }
11748 {
11756 {
11761 h)
11764 {
11767 }
11771 }
11772 else
11773 {
11777 {
11780 input_bfd,
11782 r_symndx);
11784 }
11788 }
11790 /* Linker relaxations happens from one of the
11791 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
11799 else
11800 {
11802 Elf_Internal_Rela outrel;
11805 /* The GOT entries have not been initialized yet. Do it
11806 now, and emit any relocations. If both an IE GOT and a
11807 GD GOT are necessary, we emit the GD first. */
11814 {
11817 }
11820 {
11823 /* We should have relaxed, unless this is an undefined
11824 weak symbol. */
11833 + offplt
11845 /* For globals, the first word in the relocation gets
11846 the relocation index and the top bit set, or zero,
11847 if we're binding now. For locals, it gets the
11848 symbol's offset in the tls section. */
11856 /* Second word in the relocation is always zero. */
11860 }
11862 {
11864 {
11880 else
11881 {
11884 R_ARM_TLS_DTPOFF32);
11893 }
11894 }
11895 else
11896 {
11897 /* If we are not emitting relocations for a
11898 general dynamic reference, then we must be in a
11899 static link or an executable link with the
11900 symbol binding locally. Mark it as belonging
11901 to module 1, the executable. */
11906 }
11909 }
11912 {
11914 {
11917 else
11929 }
11930 else
11934 }
11938 else
11940 }
11949 {
11950 bfd_signed_vma offset;
11951 /* TLS stubs are arm mode. The original symbol is a
11952 data object, so branch_type is bogus. */
11954 enum elf32_arm_stub_type stub_type
11962 {
11964 = elf32_arm_get_stub_entry
11970 }
11971 else
11977 {
11987 }
11988 else
11989 {
11990 /* Thumb blx encodes the offset in a complicated
11991 fashion. */
12001 {
12003 }
12004 else
12005 {
12007 /* Round up the offset to a word boundary. */
12009 }
12021 }
12022 }
12023 /* These relocations needs special care, as besides the fact
12024 they point somewhere in .gotplt, the addend must be
12025 adjusted accordingly depending on the type of instruction
12026 we refer to. */
12028 {
12037 {
12044 /* bl/blx */
12047 /* add */
12049 else
12050 {
12051 _bfd_error_handler
12052 /* xgettext:c-format */
12054 "unexpected %s instruction '%#lx' "
12059 }
12060 }
12061 else
12062 {
12066 {
12077 _bfd_error_handler
12078 /* xgettext:c-format */
12080 "unexpected %s instruction '%#lx' "
12085 }
12086 }
12094 }
12095 else
12103 {
12104 /* For FDPIC relocations, resolve to the offset of the GOT
12105 entry from the start of GOT. */
12111 }
12112 else
12113 {
12117 }
12118 }
12122 {
12123 _bfd_error_handler
12124 /* xgettext:c-format */
12129 }
12130 else
12139 {
12142 /* Ensure that we have a BX instruction. */
12146 {
12147 /* Branch to veneer. */
12148 bfd_vma glue_addr;
12155 }
12156 else
12157 {
12158 /* Preserve Rm (lowest four bits) and the condition code
12159 (highest four bits). Other bits encode MOV PC,Rm. */
12161 }
12164 }
12171 /* Until we properly support segment-base-relative addressing then
12172 we assume the segment base to be zero, as for the group relocations.
12173 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
12174 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
12178 {
12182 {
12185 }
12207 }
12214 /* Until we properly support segment-base-relative addressing then
12215 we assume the segment base to be zero, as for the above relocations.
12216 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
12217 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
12218 as R_ARM_THM_MOVT_ABS. */
12222 {
12223 bfd_vma insn;
12229 {
12235 }
12261 }
12274 {
12278 /* sb is the origin of the *segment* containing the symbol. */
12280 bfd_vma residual;
12281 bfd_vma g_n;
12282 bfd_signed_vma signed_value;
12285 /* Determine which group of bits to select. */
12287 {
12309 }
12311 /* If REL, extract the addend from the insn. If RELA, it will
12312 have already been fetched for us. */
12314 {
12321 else
12322 {
12323 /* Compensate for the fact that in the instruction, the
12324 rotation is stored in multiples of 2 bits. */
12327 /* Rotate "constant" right by "rotation" bits. */
12330 }
12332 /* Determine if the instruction is an ADD or a SUB.
12333 (For REL, this determines the sign of the addend.) */
12336 {
12337 _bfd_error_handler
12338 /* xgettext:c-format */
12343 }
12346 }
12348 /* Compute the value (X) to go in the place. */
12354 /* PC relative. */
12356 else
12357 /* Section base relative. */
12360 /* If the target symbol is a Thumb function, then set the
12361 Thumb bit in the address. */
12365 /* Calculate the value of the relevant G_n, in encoded
12366 constant-with-rotation format. */
12370 /* Check for overflow if required. */
12377 {
12378 _bfd_error_handler
12379 /* xgettext:c-format */
12386 }
12388 /* Mask out the value and the ADD/SUB part of the opcode; take care
12389 not to destroy the S bit. */
12392 /* Set the opcode according to whether the value to go in the
12393 place is negative. */
12396 else
12399 /* Encode the offset. */
12403 }
12412 {
12416 /* sb is the origin of the *segment* containing the symbol. */
12418 bfd_vma residual;
12419 bfd_signed_vma signed_value;
12422 /* Determine which groups of bits to calculate. */
12424 {
12442 }
12444 /* If REL, extract the addend from the insn. If RELA, it will
12445 have already been fetched for us. */
12447 {
12450 }
12452 /* Compute the value (X) to go in the place. */
12456 /* PC relative. */
12458 else
12459 /* Section base relative. */
12462 /* Calculate the value of the relevant G_{n-1} to obtain
12463 the residual at that stage. */
12467 /* Check for overflow. */
12469 {
12470 _bfd_error_handler
12471 /* xgettext:c-format */
12478 }
12480 /* Mask out the value and U bit. */
12483 /* Set the U bit if the value to go in the place is non-negative. */
12487 /* Encode the offset. */
12491 }
12500 {
12504 /* sb is the origin of the *segment* containing the symbol. */
12506 bfd_vma residual;
12507 bfd_signed_vma signed_value;
12510 /* Determine which groups of bits to calculate. */
12512 {
12530 }
12532 /* If REL, extract the addend from the insn. If RELA, it will
12533 have already been fetched for us. */
12535 {
12538 }
12540 /* Compute the value (X) to go in the place. */
12544 /* PC relative. */
12546 else
12547 /* Section base relative. */
12550 /* Calculate the value of the relevant G_{n-1} to obtain
12551 the residual at that stage. */
12555 /* Check for overflow. */
12557 {
12558 _bfd_error_handler
12559 /* xgettext:c-format */
12566 }
12568 /* Mask out the value and U bit. */
12571 /* Set the U bit if the value to go in the place is non-negative. */
12575 /* Encode the offset. */
12579 }
12588 {
12592 /* sb is the origin of the *segment* containing the symbol. */
12594 bfd_vma residual;
12595 bfd_signed_vma signed_value;
12598 /* Determine which groups of bits to calculate. */
12600 {
12618 }
12620 /* If REL, extract the addend from the insn. If RELA, it will
12621 have already been fetched for us. */
12623 {
12626 }
12628 /* Compute the value (X) to go in the place. */
12632 /* PC relative. */
12634 else
12635 /* Section base relative. */
12638 /* Calculate the value of the relevant G_{n-1} to obtain
12639 the residual at that stage. */
12643 /* Check for overflow. (The absolute value to go in the place must be
12644 divisible by four and, after having been divided by four, must
12645 fit in eight bits.) */
12647 {
12648 _bfd_error_handler
12649 /* xgettext:c-format */
12656 }
12658 /* Mask out the value and U bit. */
12661 /* Set the U bit if the value to go in the place is non-negative. */
12665 /* Encode the offset. */
12669 }
12676 {
12682 /* Compute address. */
12688 /* Clean imm8 insn. */
12690 /* And update with correct part of address. */
12692 /* Update insn. */
12694 }
12700 {
12702 {
12707 {
12710 }
12717 {
12720 }
12722 /* Resolve relocation. */
12725 /* Emit R_ARM_FUNCDESC_VALUE or two fixups on funcdesc if
12726 not done yet. */
12730 }
12731 else
12732 {
12735 bfd_vma addr;
12738 /* For static binaries, sym_sec can be null. */
12740 {
12743 }
12744 else
12745 {
12748 }
12751 {
12754 }
12756 /* This case cannot occur since funcdesc is allocated by
12757 the dynamic loader so we cannot resolve the relocation. */
12759 {
12762 }
12764 /* Resolve relocation. */
12767 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12771 }
12772 }
12777 {
12779 {
12780 Elf_Internal_Rela outrel;
12782 /* Resolve relocation. */
12786 /* Add funcdesc and associated R_ARM_FUNCDESC_VALUE. */
12788 {
12791 bfd_vma addr;
12794 /* For static binaries sym_sec can be null. */
12796 {
12799 }
12800 else
12801 {
12804 }
12806 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12810 }
12812 /* Add a dynamic relocation on GOT entry if not already done. */
12814 {
12816 {
12821 else
12825 sgot->contents
12827 }
12828 else
12829 {
12831 }
12839 else
12842 else
12845 }
12846 }
12847 else
12848 {
12849 /* Such relocation on static function should not have been
12850 emitted by the compiler. */
12852 }
12853 }
12858 {
12860 {
12862 Elf_Internal_Rela outrel;
12866 {
12869 }
12876 {
12879 }
12881 /* Replace static FUNCDESC relocation with a
12882 R_ARM_RELATIVE dynamic relocation or with a rofixup for
12883 executable. */
12890 else
12896 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12900 }
12901 else
12902 {
12904 {
12907 bfd_vma addr;
12909 Elf_Internal_Rela outrel;
12911 /* For static binaries sym_sec can be null. */
12913 {
12916 }
12917 else
12918 {
12921 }
12926 /* Replace static FUNCDESC relocation with a
12927 R_ARM_RELATIVE dynamic relocation. */
12934 else
12940 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12944 }
12945 else
12946 {
12947 Elf_Internal_Rela outrel;
12949 /* Add a dynamic relocation. */
12955 }
12956 }
12957 }
12962 {
12963 bfd_vma relocation;
12968 {
12976 /* Sign extend. */
12978 }
12985 /* Put RELOCATION back into the insn. */
12986 {
12993 }
12995 /* Put the relocated value back in the object file: */
13000 }
13003 {
13004 bfd_vma relocation;
13009 {
13017 /* Sign extend. */
13020 }
13027 /* Put RELOCATION back into the insn. */
13028 {
13035 }
13037 /* Put the relocated value back in the object file: */
13042 }
13045 {
13046 bfd_vma relocation;
13051 {
13059 /* Sign extend. */
13062 }
13069 /* Put RELOCATION back into the insn. */
13070 {
13077 }
13079 /* Put the relocated value back in the object file: */
13084 }
13088 }
13089 }
13091 /* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
13092 static void
13096 bfd_signed_vma increment)
13097 {
13098 bfd_signed_vma addend;
13102 {
13120 }
13121 else
13122 {
13123 bfd_vma contents;
13127 /* Get the (signed) value from the instruction. */
13130 {
13131 bfd_signed_vma mask;
13136 }
13138 /* Add in the increment, (which is a byte value). */
13140 {
13152 /* Should we check for overflow here ? */
13154 /* Drop any undesired bits. */
13157 }
13162 }
13163 }
13165 #define IS_ARM_TLS_RELOC(R_TYPE) \
13166 ((R_TYPE) == R_ARM_TLS_GD32 \
13167 || (R_TYPE) == R_ARM_TLS_GD32_FDPIC \
13168 || (R_TYPE) == R_ARM_TLS_LDO32 \
13169 || (R_TYPE) == R_ARM_TLS_LDM32 \
13170 || (R_TYPE) == R_ARM_TLS_LDM32_FDPIC \
13171 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
13172 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
13173 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
13174 || (R_TYPE) == R_ARM_TLS_LE32 \
13175 || (R_TYPE) == R_ARM_TLS_IE32 \
13176 || (R_TYPE) == R_ARM_TLS_IE32_FDPIC \
13177 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
13179 /* Specific set of relocations for the gnu tls dialect. */
13180 #define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
13181 ((R_TYPE) == R_ARM_TLS_GOTDESC \
13182 || (R_TYPE) == R_ARM_TLS_CALL \
13183 || (R_TYPE) == R_ARM_THM_TLS_CALL \
13184 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
13185 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
13187 /* Relocate an ARM ELF section. */
13189 static int
13198 {
13216 {
13223 bfd_vma relocation;
13224 bfd_reloc_status_type r;
13225 arelent bfd_reloc;
13248 {
13253 /* An object file might have a reference to a local
13254 undefined symbol. This is a daft object file, but we
13255 should at least do something about it. V4BX & NONE
13256 relocations do not use the symbol and are explicitly
13257 allowed to use the undefined symbol, so allow those.
13258 Likewise for relocations against STN_UNDEF. */
13271 {
13278 {
13283 {
13305 {
13306 _bfd_error_handler
13307 /* xgettext:c-format */
13313 }
13317 /* Get the (signed) value from the instruction. */
13320 {
13321 bfd_signed_vma mask;
13326 }
13328 }
13331 addend =
13336 /* Cases here must match those in the preceding
13337 switch statement. */
13339 {
13362 }
13363 }
13364 }
13365 else
13367 }
13368 else
13369 {
13378 }
13385 {
13386 /* This is a relocatable link. We don't have to change
13387 anything, unless the reloc is against a section symbol,
13388 in which case we have to adjust according to where the
13389 section symbol winds up in the output section. */
13391 {
13395 else
13397 }
13399 }
13403 else
13404 {
13405 name = (bfd_elf_string_from_elf_section
13409 }
13417 {
13418 _bfd_error_handler
13420 /* xgettext:c-format */
13422 /* xgettext:c-format */
13424 input_bfd,
13425 input_section,
13428 name);
13429 }
13431 /* We call elf32_arm_final_link_relocate unless we're completely
13432 done, i.e., the relaxation produced the final output we want,
13433 and we won't let anybody mess with it. Also, we have to do
13434 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
13435 both in relaxed and non-relaxed cases. */
13441 {
13444 /* This may have been marked unresolved because it came from
13445 a shared library. But we've just dealt with that. */
13447 }
13448 else
13452 {
13463 }
13465 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
13466 because such sections are not SEC_ALLOC and thus ld.so will
13467 not process them. */
13473 {
13474 _bfd_error_handler
13475 /* xgettext:c-format */
13478 input_bfd,
13479 input_section,
13484 }
13487 {
13489 {
13491 /* If the overflowing reloc was to an undefined symbol,
13492 we have already printed one error message and there
13493 is no point complaining again. */
13514 /* error_message should already be set. */
13519 /* Fall through. */
13521 common_error:
13526 }
13527 }
13528 }
13531 }
13533 /* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
13534 adds the edit to the start of the list. (The list must be built in order of
13535 ascending TINDEX: the function's callers are primarily responsible for
13536 maintaining that condition). */
13538 static void
13541 arm_unwind_edit_type type,
13544 {
13553 {
13563 }
13564 else
13565 {
13572 }
13573 }
13577 /* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
13579 static void
13581 {
13589 /* Adjust size of output section. */
13591 }
13593 /* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
13595 static void
13597 {
13601 add_unwind_table_edit
13609 }
13611 /* Scan .ARM.exidx tables, and create a list describing edits which should be
13612 made to those tables, such that:
13614 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
13615 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
13616 codes which have been inlined into the index).
13618 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
13620 The edits are applied when the tables are written
13621 (in elf32_arm_write_section). */
13623 bool
13628 {
13635 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
13636 text sections. */
13638 {
13642 {
13650 {
13651 Elf_Internal_Shdr *linked_hdr
13659 /* Link this .ARM.exidx section back from the text section it
13660 describes. */
13662 }
13663 }
13664 }
13666 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
13667 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
13668 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
13671 {
13678 bfd_vma j;
13689 {
13690 /* Section has no unwind data. */
13694 /* Ignore zero sized sections. */
13701 }
13703 /* Skip /DISCARD/ sections. */
13720 /* An error? */
13724 {
13726 /* Add cantunwind if first unwind item does not match section
13727 start. */
13729 {
13732 }
13733 }
13736 {
13741 /* An EXIDX_CANTUNWIND entry. */
13743 {
13747 }
13748 /* Inlined unwinding data. Merge if equal to previous. */
13750 {
13756 }
13757 /* Normal table entry. In theory we could merge these too,
13758 but duplicate entries are likely to be much less common. */
13759 else
13763 {
13768 }
13771 }
13773 /* Free contents if we allocated it ourselves. */
13777 /* Record edits to be applied later (in elf32_arm_write_section). */
13786 }
13788 /* Add terminating CANTUNWIND entry. */
13794 }
13796 static bool
13799 {
13815 }
13817 static bool
13819 {
13826 /* Invoke the regular ELF backend linker to do all the work. */
13830 /* Process stub sections (eg BE8 encoding, ...). */
13834 {
13836 /* Only process it once, in its link_sec slot. */
13838 {
13844 }
13845 }
13847 /* Write out any glue sections now that we have created all the
13848 stubs. */
13850 {
13853 ARM2THUMB_GLUE_SECTION_NAME))
13858 THUMB2ARM_GLUE_SECTION_NAME))
13863 VFP11_ERRATUM_VENEER_SECTION_NAME))
13868 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
13873 ARM_BX_GLUE_SECTION_NAME))
13875 }
13878 }
13880 /* Return a best guess for the machine number based on the attributes. */
13882 static unsigned int
13884 {
13888 {
13895 {
13902 {
13910 {
13916 {
13920 }
13921 }
13922 }
13925 }
13959 /* Force entry to be added for any new known Tag_CPU_arch value. */
13962 /* Unknown Tag_CPU_arch value. */
13964 }
13965 }
13967 /* Set the right machine number. */
13969 static bool
13971 {
13981 }
13983 /* Function to keep ARM specific flags in the ELF header. */
13985 static bool
13987 {
13990 {
13992 {
13994 _bfd_error_handler
13995 (_("warning: not setting interworking flag of %pB since it has already been specified as non-interworking"),
13996 abfd);
13997 else
13998 _bfd_error_handler
14000 abfd);
14001 }
14002 }
14003 else
14004 {
14007 }
14010 }
14012 /* Copy backend specific data from one object module to another. */
14014 static bool
14016 {
14017 flagword in_flags;
14018 flagword out_flags;
14029 {
14030 /* Cannot mix APCS26 and APCS32 code. */
14034 /* Cannot mix float APCS and non-float APCS code. */
14038 /* If the src and dest have different interworking flags
14039 then turn off the interworking bit. */
14041 {
14043 _bfd_error_handler
14044 (_("warning: clearing the interworking flag of %pB because non-interworking code in %pB has been linked with it"),
14048 }
14050 /* Likewise for PIC, though don't warn for this case. */
14053 }
14059 }
14061 /* Values for Tag_ABI_PCS_R9_use. */
14062 enum
14063 {
14064 AEABI_R9_V6,
14065 AEABI_R9_SB,
14066 AEABI_R9_TLS,
14067 AEABI_R9_unused
14068 };
14070 /* Values for Tag_ABI_PCS_RW_data. */
14071 enum
14072 {
14073 AEABI_PCS_RW_data_absolute,
14074 AEABI_PCS_RW_data_PCrel,
14075 AEABI_PCS_RW_data_SBrel,
14076 AEABI_PCS_RW_data_unused
14077 };
14079 /* Values for Tag_ABI_enum_size. */
14080 enum
14081 {
14082 AEABI_enum_unused,
14083 AEABI_enum_short,
14084 AEABI_enum_wide,
14085 AEABI_enum_forced_wide
14086 };
14088 /* Determine whether an object attribute tag takes an integer, a
14089 string or both. */
14091 static int
14093 {
14102 else
14104 }
14106 /* The ABI defines that Tag_conformance should be emitted first, and that
14107 Tag_nodefaults should be second (if either is defined). This sets those
14108 two positions, and bumps up the position of all the remaining tags to
14109 compensate. */
14110 static int
14112 {
14122 }
14124 /* Attribute numbers >=64 (mod 128) can be safely ignored. */
14125 static bool
14127 {
14129 {
14130 _bfd_error_handler
14135 }
14136 else
14137 {
14138 _bfd_error_handler
14142 }
14143 }
14145 /* Read the architecture from the Tag_also_compatible_with attribute, if any.
14146 Returns -1 if no architecture could be read. */
14148 static int
14150 {
14154 /* Note: the tag and its argument below are uleb128 values, though
14155 currently-defined values fit in one byte for each. */
14162 /* This tag is "safely ignorable", so don't complain if it looks funny. */
14164 }
14166 /* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
14167 The tag is removed if ARCH is -1. */
14169 static void
14171 {
14176 {
14179 }
14181 /* Note: the tag and its argument below are uleb128 values, though
14182 currently-defined values fit in one byte for each. */
14188 }
14190 /* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
14191 into account. */
14193 static int
14196 {
14197 #define T(X) TAG_CPU_ARCH_##X
14200 {
14210 };
14212 {
14223 };
14225 {
14237 };
14239 {
14252 };
14254 {
14268 };
14270 {
14285 };
14287 {
14310 };
14312 {
14329 };
14331 {
14349 };
14351 {
14370 };
14372 {
14395 };
14397 {
14421 };
14423 {
14448 };
14450 {
14451 v6t2,
14452 v6k,
14453 v7,
14454 v6_m,
14455 v6s_m,
14456 v7e_m,
14457 v8,
14458 v8r,
14459 v8m_baseline,
14460 v8m_mainline,
14461 NULL,
14462 NULL,
14463 NULL,
14464 v8_1m_mainline,
14465 v9,
14466 /* Pseudo-architecture. */
14467 v4t_plus_v6_m
14468 };
14470 /* Check we've not got a higher architecture than we know about. */
14473 {
14476 }
14478 /* Override old tag if we have a Tag_also_compatible_with on the output. */
14484 /* And override the new tag if we have a Tag_also_compatible_with on the
14485 input. */
14494 /* Architectures before V6KZ add features monotonically. */
14500 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
14501 as the canonical version. */
14503 {
14506 }
14507 else
14511 {
14515 }
14518 #undef T
14519 }
14521 /* Query attributes object to see if integer divide instructions may be
14522 present in an object. */
14523 static bool
14525 {
14530 {
14532 /* Integer divide allowed if instruction contained in archetecture. */
14537 else
14541 /* Integer divide explicitly prohibited. */
14545 /* Unrecognised case - treat as allowing divide everywhere. */
14547 /* Integer divide allowed in ARM state. */
14549 }
14550 }
14552 /* Query attributes object to see if integer divide instructions are
14553 forbidden to be in the object. This is not the inverse of
14554 elf32_arm_attributes_accept_div. */
14555 static bool
14557 {
14559 }
14561 /* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
14562 are conflicting attributes. */
14564 static bool
14566 {
14570 /* Some tags have 0 = don't care, 1 = strong requirement,
14571 2 = weak requirement. */
14577 /* Skip the linker stubs file. This preserves previous behavior
14578 of accepting unknown attributes in the first input file - but
14579 is that a bug? */
14583 /* Skip any input that hasn't attribute section.
14584 This enables to link object files without attribute section with
14585 any others. */
14590 {
14591 /* This is the first object. Copy the attributes. */
14596 /* Use the Tag_null value to indicate the attributes have been
14597 initialized. */
14600 /* We do not output objects with Tag_MPextension_use_legacy - we move
14601 the attribute's value to Tag_MPextension_use. */
14603 {
14607 {
14608 _bfd_error_handler
14612 }
14618 }
14620 /* PR 28859 and 28848: Handle the case where the first input file,
14621 eg crti.o, has a Tag_ABI_HardFP_use of 3 but no Tag_FP_arch set.
14622 Using Tag_ABI_HardFP_use in this way is deprecated, so reset the
14623 attribute to zero.
14624 FIXME: Should we handle other non-zero values of Tag_ABI_HardFO_use ? */
14629 }
14633 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
14635 {
14636 /* Ignore mismatches if the object doesn't use floating point or is
14637 floating point ABI independent. */
14644 {
14645 _bfd_error_handler
14650 }
14651 }
14654 {
14655 /* Merge this attribute with existing attributes. */
14657 {
14660 /* These are merged after Tag_CPU_arch. */
14665 /* Use the first value seen. */
14669 {
14674 {
14675 /* These aren't real CPU names, but we can't guess
14676 that from the architecture version alone. */
14700 };
14702 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
14708 secondary_compat,
14709 name_table);
14711 /* Return with error if failed to merge. */
14719 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
14723 {
14724 /* The output architecture has been changed to match the
14725 input architecture. Use the input names. */
14732 }
14733 else
14734 {
14737 }
14739 /* If we still don't have a value for Tag_CPU_name,
14740 make one up now. Tag_CPU_raw_name remains blank. */
14745 }
14752 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
14766 /* Use the largest value specified. */
14773 /* Use the smallest value specified. */
14782 {
14783 /* This error message should be enabled once all non-conformant
14784 binaries in the toolchain have had the attributes set
14785 properly.
14786 _bfd_error_handler
14787 (_("error: %pB: 8-byte data alignment conflicts with %pB"),
14788 obfd, ibfd);
14789 result = false; */
14790 }
14791 /* Fall through. */
14794 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
14795 value if greater than 2 (for future-proofing). */
14803 /* The virtualization tag effectively stores two bits of
14804 information: the intended use of TrustZone (in bit 0), and the
14805 intended use of Virtualization (in bit 1). */
14810 {
14813 else
14814 {
14815 _bfd_error_handler
14820 }
14821 }
14826 {
14827 /* 0 will merge with anything.
14828 'A' and 'S' merge to 'A'.
14829 'R' and 'S' merge to 'R'.
14830 'M' and 'A|R|S' is an error. */
14839 else
14840 {
14841 _bfd_error_handler
14843 ibfd,
14847 }
14848 }
14852 /* No need to change output value if any of:
14853 - pre (<=) ARMv5T input architecture (do not have DSP)
14854 - M input profile not ARMv7E-M and do not have DSP. */
14860 /* Output value should be 0 if DSP part of architecture, ie.
14861 - post (>=) ARMv5te architecture output
14862 - A, R or S profile output or ARMv7E-M output architecture. */
14869 /* Otherwise, DSP instructions are added and not part of output
14870 architecture. */
14871 else
14876 {
14877 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
14878 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
14879 when it's 0. It might mean absence of FP hardware if
14880 Tag_FP_arch is zero. */
14882 #define VFP_VERSION_COUNT 9
14883 static const struct
14884 {
14888 {
14898 };
14903 /* If the output has no requirement about FP hardware,
14904 follow the requirement of the input. */
14906 {
14907 /* This assert is still reasonable, we shouldn't
14908 produce the suspicious build attribute
14909 combination (See below for in_attr). */
14915 }
14916 /* If the input has no requirement about FP hardware, do
14917 nothing. */
14919 {
14920 /* We used to assert that Tag_ABI_HardFP_use was
14921 zero here, but we should never assert when
14922 consuming an object file that has suspicious
14923 build attributes. The single precision variant
14924 of 'no FP architecture' is still 'no FP
14925 architecture', so we just ignore the tag in this
14926 case. */
14928 }
14930 /* Both the input and the output have nonzero Tag_FP_arch.
14931 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
14933 /* If both the input and the output have zero Tag_ABI_HardFP_use,
14934 do nothing. */
14937 ;
14938 /* If the input and the output have different Tag_ABI_HardFP_use,
14939 the combination of them is 0 (implied by Tag_FP_arch). */
14944 /* Now we can handle Tag_FP_arch. */
14946 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
14947 pick the biggest. */
14950 {
14953 }
14954 /* The output uses the superset of input features
14955 (ISA version) and registers. */
14962 /* This assumes all possible supersets are also a valid
14963 options. */
14965 {
14969 }
14971 }
14977 {
14978 /* It's sometimes ok to mix different configs, so this is only
14979 a warning. */
14980 _bfd_error_handler
14982 }
14988 {
14989 _bfd_error_handler
14992 }
15000 {
15001 _bfd_error_handler
15003 ibfd);
15005 }
15006 /* Use the smallest value specified. */
15013 {
15014 _bfd_error_handler
15015 (_("warning: %pB uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
15017 }
15023 {
15026 {
15027 /* The existing object is compatible with anything.
15028 Use whatever requirements the new object has. */
15030 }
15034 {
15045 _bfd_error_handler
15046 (_("warning: %pB uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
15048 }
15049 }
15052 /* Aready done. */
15056 {
15057 _bfd_error_handler
15061 }
15064 /* Merged in target-independent code. */
15067 /* This is handled along with Tag_FP_arch. */
15071 {
15073 {
15074 _bfd_error_handler
15078 }
15079 }
15085 /* A value of zero on input means that the divide instruction may
15086 be used if available in the base architecture as specified via
15087 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
15088 the user did not want divide instructions. A value of 2
15089 explicitly means that divide instructions were allowed in ARM
15090 and Thumb state. */
15104 /* We don't output objects with Tag_MPextension_use_legacy - we
15105 move the value to Tag_MPextension_use. */
15107 {
15109 {
15110 _bfd_error_handler
15113 ibfd);
15115 }
15116 }
15124 /* This tag is set if it exists, but the value is unused (and is
15125 typically zero). We don't actually need to do anything here -
15126 the merge happens automatically when the type flags are merged
15127 below. */
15130 /* Already done in Tag_CPU_arch. */
15133 /* Keep the attribute if it matches. Throw it away otherwise.
15134 No attribute means no claim to conform. */
15141 result
15143 }
15145 /* If out_attr was copied from in_attr then it won't have a type yet. */
15148 }
15150 /* Merge Tag_compatibility attributes and any common GNU ones. */
15154 /* Check for any attributes not known on ARM. */
15158 }
15161 /* Return TRUE if the two EABI versions are incompatible. */
15163 static bool
15165 {
15166 /* v4 and v5 are the same spec before and after it was released,
15167 so allow mixing them. */
15173 }
15175 /* Merge backend specific data from an object file to the output
15176 object file when linking. */
15178 static bool
15181 /* Display the flags field. */
15183 static bool
15185 {
15191 /* Print normal ELF private data. */
15195 /* Ignore init flag - it may not be set, despite the flags field
15196 containing valid data. */
15201 {
15203 /* The following flag bits are GNU extensions and not part of the
15204 official ARM ELF extended ABI. Hence they are only decoded if
15205 the EABI version is not set. */
15211 else
15216 else
15244 else
15255 else
15287 eabi:
15300 }
15321 }
15323 static int
15325 {
15327 {
15332 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
15333 This allows us to distinguish between data used by Thumb instructions
15334 and non-data (which is probably code) inside Thumb regions of an
15335 executable. */
15342 }
15345 }
15353 {
15356 {
15360 }
15363 }
15365 /* Look through the relocs for a section during the first phase. */
15367 static bool
15370 {
15407 {
15419 /* PR 9934: It is possible to have relocations that do not
15420 refer to symbols, thus it is also possible to have an
15421 object file containing relocations but no symbol table. */
15423 {
15425 r_symndx);
15427 }
15432 {
15434 {
15435 /* A local symbol. */
15440 }
15441 else
15442 {
15447 }
15448 }
15456 /* Could be done earlier, if h were already available. */
15459 {
15461 {
15463 {
15470 }
15471 else
15472 {
15474 }
15475 }
15479 {
15481 {
15482 /* Such a relocation is not supposed to be generated
15483 by gcc on a static function. */
15484 /* Anyway if needed it could be handled. */
15486 }
15487 else
15488 {
15490 }
15491 }
15495 {
15497 {
15504 }
15505 else
15506 {
15508 }
15509 }
15523 /* This symbol requires a global offset table entry. */
15524 {
15528 {
15541 }
15547 {
15550 }
15551 else
15552 {
15553 /* This is a global offset table entry for a local symbol. */
15557 {
15559 r_symndx);
15561 }
15565 }
15567 /* If a variable is accessed with both tls methods, two
15568 slots may be created. */
15573 /* We will already have issued an error message if there
15574 is a TLS/non-TLS mismatch, based on the symbol
15575 type. So just combine any TLS types needed. */
15580 /* If the symbol is accessed in both IE and GDESC
15581 method, we're able to relax. Turn off the GDESC flag,
15582 without messing up with any other kind of tls types
15583 that may be involved. */
15588 {
15591 else
15593 }
15594 }
15595 /* Fall through. */
15601 /* Fall through. */
15623 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
15624 ldr __GOTT_INDEX__ offsets. */
15626 {
15629 }
15632 /* Fall through. */
15639 {
15640 _bfd_error_handler
15641 (_("%pB: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
15646 }
15648 /* Fall through. */
15651 jump_over:
15653 {
15655 }
15656 /* Fall through. */
15664 /* Should the interworking branches be listed here? */
15668 {
15671 {
15672 /* In shared libraries and relocatable executables,
15673 we treat local relative references as calls;
15674 see the related SYMBOL_CALLS_LOCAL code in
15675 allocate_dynrelocs. */
15678 }
15679 else
15680 /* We are creating a shared library or relocatable
15681 executable, and this is a reloc against a global symbol,
15682 or a non-PC-relative reloc against a local symbol.
15683 We may need to copy the reloc into the output. */
15685 }
15686 else
15690 /* This relocation describes the C++ object vtable hierarchy.
15691 Reconstruct it for later use during GC. */
15697 /* This relocation describes which C++ vtable entries are actually
15698 used. Record for later use during GC. */
15703 }
15706 {
15708 /* We may need a .plt entry if the function this reloc
15709 refers to is in a different object, regardless of the
15710 symbol's type. We can't tell for sure yet, because
15711 something later might force the symbol local. */
15714 /* If this reloc is in a read-only section, we might
15715 need a copy reloc. We can't check reliably at this
15716 stage whether the section is read-only, as input
15717 sections have not yet been mapped to output sections.
15718 Tentatively set the flag for now, and correct in
15719 adjust_dynamic_symbol. */
15721 }
15725 {
15731 {
15734 }
15735 else
15736 {
15742 }
15744 /* If the symbol is a function that doesn't bind locally,
15745 this relocation will need a PLT entry. */
15752 /* It's too early to use htab->use_blx here, so we have to
15753 record possible blx references separately from
15754 relocs that definitely need a thumb stub. */
15762 }
15765 {
15768 /* Create a reloc section in dynobj. */
15770 {
15771 sreloc = _bfd_elf_make_dynamic_reloc_section
15776 }
15778 /* If this is a global symbol, count the number of
15779 relocations we need for this symbol. */
15782 else
15783 {
15787 }
15791 {
15802 }
15809 {
15810 /* Here we only support R_ARM_ABS32 and R_ARM_ABS32_NOI
15811 that will become rofixup. */
15812 /* This is due to the fact that we suppose all will become rofixup. */
15813 _bfd_error_handler
15818 }
15819 }
15820 }
15823 }
15825 static void
15828 {
15850 {
15853 }
15855 {
15858 }
15859 else
15871 {
15874 {
15877 irela++;
15878 count++;
15879 }
15881 {
15885 bfd_size_type j;
15886 bfd_vma offset;
15902 else
15906 {
15908 {
15910 bfd_vma bias;
15911 bfd_vma reloc_index;
15921 {
15922 bias++;
15924 }
15928 {
15930 irela++;
15931 count++;
15932 }
15935 }
15938 {
15939 /* New relocation entity. */
15948 irela++;
15949 count++;
15950 }
15951 }
15952 else
15953 {
15955 {
15958 irela++;
15959 }
15962 }
15963 }
15964 }
15972 {
15975 irela++;
15976 count--;
15977 }
15981 /* Hashes are no longer valid. */
15984 }
15986 /* Unwinding tables are not referenced directly. This pass marks them as
15987 required if the corresponding code section is marked. Similarly, ARMv8-M
15988 secure entry functions can only be referenced by SG veneers which are
15989 created after the GC process. They need to be marked in case they reside in
15990 their own section (as would be the case if code was compiled with
15991 -ffunction-sections). */
15993 static bool
15995 elf_gc_mark_hook_fn gc_mark_hook)
15996 {
16016 /* Marking EH data may cause additional code sections to be marked,
16017 requiring multiple passes. */
16020 {
16023 {
16031 {
16040 {
16044 }
16045 }
16047 /* Mark section holding ARMv8-M secure entry functions. We mark all
16048 of them so no need for a second browsing. */
16050 {
16059 /* Scan symbols. */
16061 {
16066 /* Assume it is a special symbol. If not, cmse_scan will
16067 warn about it and user can do something about it. */
16069 CMSE_PREFIX))
16070 {
16075 /* The debug sections related to these secure entry
16076 functions are marked on enabling below flag. */
16078 }
16079 }
16082 {
16083 /* Looping over all the sections of the object file containing
16084 Armv8-M secure entry functions and marking all the debug
16085 sections. */
16087 {
16088 /* If not a debug sections, skip it. */
16090 {
16093 }
16094 }
16096 }
16097 }
16098 }
16101 }
16103 /* PR 30354: If we have added extra marks then make sure that any
16104 dependencies of the newly marked sections are also marked. */
16109 }
16111 /* Treat mapping symbols as special target symbols. */
16113 static bool
16115 {
16117 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
16118 }
16120 /* If the ELF symbol SYM might be a function in SEC, return the
16121 function size and set *CODE_OFF to the function's entry point,
16122 otherwise return zero. */
16124 static bfd_size_type
16127 {
16128 bfd_size_type size;
16140 {
16142 /* Ignore symbols created by the annobin plugin for gcc and clang.
16143 These symbols are hidden, local, notype and have a size of 0. */
16148 /* Fall through. */
16151 /* FIXME: Allow STT_GNU_IFUNC as well ? */
16155 }
16159 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
16164 /* Do not return 0 for the function's size. */
16167 }
16169 static bool
16174 {
16180 }
16182 /* Adjust a symbol defined by a dynamic object and referenced by a
16183 regular object. The current definition is in some section of the
16184 dynamic object, but we're not including those sections. We have to
16185 change the definition to something the rest of the link can
16186 understand. */
16188 static bool
16191 {
16203 /* Make sure we know what is going on here. */
16214 /* If this is a function, put it in the procedure linkage table. We
16215 will fill in the contents of the procedure linkage table later,
16216 when we know the address of the .got section. */
16218 {
16219 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
16220 symbol binds locally. */
16226 {
16227 /* This case can occur if we saw a PLT32 reloc in an input
16228 file, but the symbol was never referred to by a dynamic
16229 object, or if all references were garbage collected. In
16230 such a case, we don't actually need to build a procedure
16231 linkage table, and we can just do a PC24 reloc instead. */
16237 }
16240 }
16241 else
16242 {
16243 /* It's possible that we incorrectly decided a .plt reloc was
16244 needed for an R_ARM_PC24 or similar reloc to a non-function sym
16245 in check_relocs. We can't decide accurately between function
16246 and non-function syms in check-relocs; Objects loaded later in
16247 the link may change h->type. So fix it now. */
16252 }
16254 /* If this is a weak symbol, and there is a real definition, the
16255 processor independent code will have arranged for us to see the
16256 real definition first, and we can just use the same value. */
16258 {
16264 }
16266 /* If there are no non-GOT references, we do not need a copy
16267 relocation. */
16271 /* This is a reference to a symbol defined by a dynamic object which
16272 is not a function. */
16274 /* If we are creating a shared library, we must presume that the
16275 only references to the symbol are via the global offset table.
16276 For such cases we need not do anything here; the relocations will
16277 be handled correctly by relocate_section. */
16281 /* We must allocate the symbol in our .dynbss section, which will
16282 become part of the .bss section of the executable. There will be
16283 an entry for this symbol in the .dynsym section. The dynamic
16284 object will contain position independent code, so all references
16285 from the dynamic object to this symbol will go through the global
16286 offset table. The dynamic linker will use the .dynsym entry to
16287 determine the address it must put in the global offset table, so
16288 both the dynamic object and the regular object will refer to the
16289 same memory location for the variable. */
16290 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
16291 linker to copy the initial value out of the dynamic object and into
16292 the runtime process image. We need to remember the offset into the
16293 .rel(a).bss section we are going to use. */
16295 {
16298 }
16299 else
16300 {
16303 }
16307 {
16310 }
16313 }
16315 /* Allocate space in .plt, .got and associated reloc sections for
16316 dynamic relocs. */
16318 static bool
16320 {
16338 {
16339 /* Make sure this symbol is output as a dynamic symbol.
16340 Undefined weak syms won't yet be marked as dynamic. */
16343 {
16346 }
16348 /* If the call in the PLT entry binds locally, the associated
16349 GOT entry should use an R_ARM_IRELATIVE relocation instead of
16350 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
16351 than the .plt section. */
16353 {
16357 /* All non-call references can be resolved directly.
16358 This means that they can (and in some cases, must)
16359 resolve directly to the run-time target, rather than
16360 to the PLT. That in turns means that any .got entry
16361 would be equal to the .igot.plt entry, so there's
16362 no point having both. */
16364 }
16369 {
16372 /* If this symbol is not defined in a regular file, and we are
16373 not generating a shared library, then set the symbol to this
16374 location in the .plt. This is required to make function
16375 pointers compare as equal between the normal executable and
16376 the shared library. */
16379 {
16383 /* Make sure the function is not marked as Thumb, in case
16384 it is the target of an ABS32 relocation, which will
16385 point to the PLT entry. */
16387 }
16389 /* VxWorks executables have a second set of relocations for
16390 each PLT entry. They go in a separate relocation section,
16391 which is processed by the kernel loader. */
16393 {
16394 /* There is a relocation for the initial PLT entry:
16395 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
16399 /* There are two extra relocations for each subsequent
16400 PLT entry: an R_ARM_32 relocation for the GOT entry,
16401 and an R_ARM_32 relocation for the PLT entry. */
16403 }
16404 }
16405 else
16406 {
16409 }
16410 }
16411 else
16412 {
16415 }
16421 {
16427 /* Make sure this symbol is output as a dynamic symbol.
16428 Undefined weak syms won't yet be marked as dynamic. */
16433 {
16436 }
16445 /* Non-TLS symbols need one GOT slot. */
16447 else
16448 {
16450 {
16451 /* R_ARM_TLS_DESC needs 2 GOT slots. */
16452 eh->tlsdesc_got
16457 /* plt.got_offset needs to know there's a TLS_DESC
16458 reloc in the middle of .got.plt. */
16460 }
16463 {
16464 /* R_ARM_TLS_GD32 and R_ARM_TLS_GD32_FDPIC need two
16465 consecutive GOT slots. If the symbol is both GD
16466 and GDESC, got.offset may have been
16467 overwritten. */
16470 }
16473 /* R_ARM_TLS_IE32/R_ARM_TLS_IE32_FDPIC need one GOT
16474 slot. */
16476 }
16490 {
16498 {
16500 /* GDESC needs a trampoline to jump to. */
16502 }
16504 /* Only GD needs it. GDESC just emits one relocation per
16505 2 entries. */
16508 }
16511 {
16513 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
16515 }
16518 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
16519 they all resolve dynamically instead. Reserve room for the
16520 GOT entry's R_ARM_IRELATIVE relocation. */
16524 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
16527 /* Reserve room for rofixup for FDPIC executable. */
16528 /* TLS relocs do not need space since they are completely
16529 resolved. */
16531 }
16532 else
16535 /* FDPIC support. */
16537 {
16538 /* Symbol musn't be exported. */
16542 /* We only allocate one function descriptor with its associated
16543 relocation. */
16545 {
16550 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16553 else
16555 }
16556 }
16559 {
16568 {
16569 /* We only allocate one function descriptor with its
16570 associated relocation. */
16572 {
16576 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two
16577 rofixups. */
16580 else
16582 }
16583 }
16585 /* Add one entry into the GOT and a R_ARM_FUNCDESC or
16586 R_ARM_RELATIVE/rofixup relocation on it. */
16591 else
16593 }
16596 {
16603 {
16604 /* We only allocate one function descriptor with its
16605 associated relocation. */
16607 {
16612 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two
16613 rofixups. */
16616 else
16618 }
16619 }
16621 {
16622 /* For FDPIC executable we replace R_ARM_RELATIVE with a rofixup. */
16624 }
16625 else
16626 {
16627 /* Will need one dynamic reloc per reference. will be either
16628 R_ARM_FUNCDESC or R_ARM_RELATIVE for hidden symbols. */
16631 }
16632 }
16634 /* Allocate stubs for exported Thumb functions on v4t. */
16639 {
16646 /* Create a new symbol to regist the real location of the function. */
16660 /* Point the symbol at the stub. */
16665 }
16670 /* In the shared -Bsymbolic case, discard space allocated for
16671 dynamic pc-relative relocs against symbols which turn out to be
16672 defined in regular objects. For the normal shared case, discard
16673 space for pc-relative relocs that have become local due to symbol
16674 visibility changes. */
16678 {
16679 /* Relocs that use pc_count are PC-relative forms, which will appear
16680 on something like ".long foo - ." or "movw REG, foo - .". We want
16681 calls to protected symbols to resolve directly to the function
16682 rather than going via the plt. If people want function pointer
16683 comparisons to work as expected then they should avoid writing
16684 assembly like ".long foo - .". */
16686 {
16690 {
16695 else
16697 }
16698 }
16701 {
16705 {
16708 else
16710 }
16711 }
16713 /* Also discard relocs on undefined weak syms with non-default
16714 visibility. */
16717 {
16722 /* Make sure undefined weak symbols are output as a dynamic
16723 symbol in PIEs. */
16726 {
16729 }
16730 }
16731 }
16732 else
16733 {
16734 /* For the non-shared case, discard space for relocs against
16735 symbols which turn out to need copy relocs or are not
16736 dynamic. */
16744 {
16745 /* Make sure this symbol is output as a dynamic symbol.
16746 Undefined weak syms won't yet be marked as dynamic. */
16749 {
16752 }
16754 /* If that succeeded, we know we'll be keeping all the
16755 relocs. */
16758 }
16762 keep: ;
16763 }
16765 /* Finally, allocate space. */
16767 {
16779 else
16781 }
16784 }
16786 void
16789 {
16797 }
16799 /* Set the sizes of the dynamic sections. */
16801 static bool
16804 {
16822 {
16823 /* Set the contents of the .interp section to the interpreter. */
16825 {
16831 }
16832 }
16834 /* Set up .got offsets for local syms, and space for local dynamic
16835 relocs. */
16837 {
16843 bfd_size_type locsymcount;
16853 {
16858 {
16861 {
16862 /* Input section has been discarded, either because
16863 it is a copy of a linkonce section or due to
16864 linker script /DISCARD/, so we'll be discarding
16865 the relocs too. */
16866 }
16870 {
16871 /* Relocations in vxworks .tls_vars sections are
16872 handled specially by the loader. */
16873 }
16875 {
16879 else
16883 }
16884 }
16885 }
16904 {
16911 /* FDPIC support. */
16913 {
16915 {
16919 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16922 else
16924 }
16925 }
16928 {
16930 {
16934 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16937 else
16939 }
16941 /* We will add n R_ARM_RELATIVE relocations or n rofixups. */
16944 else
16946 }
16949 {
16953 {
16958 /* All references to the PLT are calls, so all
16959 non-call references can resolve directly to the
16960 run-time target. This means that the .got entry
16961 would be the same as the .igot.plt entry, so there's
16962 no point creating both. */
16964 }
16965 else
16966 {
16969 }
16972 {
16978 else
16980 }
16981 }
16983 {
16988 /* TLS_GD relocs need an 8-byte structure in the GOT. */
16991 {
16996 /* plt.got_offset needs to know there's a TLS_DESC
16997 reloc in the middle of .got.plt. */
16999 }
17004 {
17005 /* If the symbol is both GD and GDESC, *local_got
17006 may have been overwritten. */
17009 }
17012 symndx);
17016 /* If all references to an STT_GNU_IFUNC PLT are calls,
17017 then all non-call references, including this GOT entry,
17018 resolve directly to the run-time target. */
17024 {
17032 {
17036 }
17037 }
17038 }
17039 else
17041 }
17042 }
17045 {
17046 /* Allocate two GOT entries and one dynamic relocation (if necessary)
17047 for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
17052 }
17053 else
17056 /* At the very end of the .rofixup section is a pointer to the GOT,
17057 reserve space for it. */
17061 /* Allocate global sym .plt and .got entries, and space for global
17062 sym dynamic relocs. */
17065 /* Here we rummage through the found bfds to collect glue information. */
17067 {
17071 /* Initialise mapping tables for code/data. */
17078 }
17080 /* Allocate space for the glue sections now that we've sized them. */
17083 /* For every jump slot reserved in the sgotplt, reloc_count is
17084 incremented. However, when we reserve space for TLS descriptors,
17085 it's not incremented, so in order to compute the space reserved
17086 for them, it suffices to multiply the reloc count by the jump
17087 slot size. */
17092 {
17099 /* If we're not using lazy TLS relocations, don't generate the
17100 PLT and GOT entries they require. */
17103 else
17104 {
17110 }
17111 }
17113 /* The check_relocs and adjust_dynamic_symbol entry points have
17114 determined the sizes of the various dynamic sections. Allocate
17115 memory for them. */
17118 {
17124 /* It's OK to base decisions on the section name, because none
17125 of the dynobj section names depend upon the input files. */
17129 {
17130 /* Remember whether there is a PLT. */
17131 ;
17132 }
17134 {
17136 {
17137 /* Remember whether there are any reloc sections other
17138 than .rel(a).plt and .rela.plt.unloaded. */
17142 /* We use the reloc_count field as a counter if we need
17143 to copy relocs into the output file. */
17145 }
17146 }
17154 {
17155 /* It's not one of our sections, so don't allocate space. */
17157 }
17160 {
17161 /* If we don't need this section, strip it from the
17162 output file. This is mostly to handle .rel(a).bss and
17163 .rel(a).plt. We must create both sections in
17164 create_dynamic_sections, because they must be created
17165 before the linker maps input sections to output
17166 sections. The linker does that before
17167 adjust_dynamic_symbol is called, and it is that
17168 function which decides whether anything needs to go
17169 into these sections. */
17172 }
17177 /* Allocate memory for the section contents. */
17182 }
17185 relocs);
17186 }
17188 /* Size sections even though they're not dynamic. We use it to setup
17189 _TLS_MODULE_BASE_, if needed. */
17191 static bool
17193 {
17205 {
17208 tlsbase = elf_link_hash_lookup
17212 {
17228 }
17229 }
17237 }
17239 /* Finish up dynamic symbol handling. We set the contents of various
17240 dynamic sections here. */
17242 static bool
17247 {
17256 {
17258 {
17263 }
17266 {
17267 /* Mark the symbol as undefined, rather than as defined in
17268 the .plt section. */
17270 /* If the symbol is weak we need to clear the value.
17271 Otherwise, the PLT entry would provide a definition for
17272 the symbol even if the symbol wasn't defined anywhere,
17273 and so the symbol would never be NULL. Leave the value if
17274 there were any relocations where pointer equality matters
17275 (this is a clue for the dynamic linker, to make function
17276 pointer comparisons work between an application and shared
17277 library). */
17280 }
17282 {
17283 /* At least one non-call relocation references this .iplt entry,
17284 so the .iplt entry is the function's canonical address. */
17292 }
17293 }
17296 {
17298 Elf_Internal_Rela rel;
17300 /* This symbol needs a copy reloc. Set it up. */
17312 else
17315 }
17317 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
17318 and for FDPIC, the _GLOBAL_OFFSET_TABLE_ symbol is not absolute:
17319 it is relative to the ".got" section. */
17327 }
17329 static void
17333 {
17337 {
17340 /* Emit mov pc,rx if bx is not permitted. */
17344 }
17345 }
17347 /* Install the special first PLT entry for elf32-arm-nacl. Unlike
17348 other variants, NaCl needs this entry in a static executable's
17349 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
17350 zero. For .iplt really only the last bundle is useful, and .iplt
17351 could have a shorter first entry, with each individual PLT entry's
17352 relative branch calculated differently so it targets the last
17353 bundle instead of the instruction before it (labelled .Lplt_tail
17354 above). But it's simpler to keep the size and layout of PLT0
17355 consistent with the dynamic case, at the cost of some dead code at
17356 the start of .iplt and the one dead store to the stack at the start
17357 of .Lplt_tail. */
17358 static void
17361 {
17377 }
17379 /* Finish up the dynamic sections. */
17381 static bool
17383 {
17396 /* A broken linker script might have discarded the dynamic sections.
17397 Catch this here so that we do not seg-fault later on. */
17403 {
17415 {
17416 Elf_Internal_Dyn dyn;
17423 {
17443 get_vma:
17446 {
17447 _bfd_error_handler
17451 }
17483 /* Set the bottom bit of DT_INIT/FINI if the
17484 corresponding function is Thumb. */
17490 get_sym:
17491 /* If it wasn't set by elf_bfd_final_link
17492 then there is nothing to adjust. */
17494 {
17502 {
17505 }
17506 }
17508 }
17509 }
17511 /* Fill in the first entry in the procedure linkage table. */
17513 {
17517 /* Calculate the addresses of the GOT and PLT. */
17522 {
17523 /* The VxWorks GOT is relocated by the dynamic linker.
17524 Therefore, we must emit relocations rather than simply
17525 computing the values now. */
17526 Elf_Internal_Rela rel;
17537 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
17543 }
17548 {
17560 }
17561 else
17562 {
17575 #ifdef FOUR_WORD_PLT
17576 /* The displacement value goes in the otherwise-unused
17577 last word of the second entry. */
17579 #else
17581 #endif
17582 }
17583 }
17585 /* UnixWare sets the entsize of .plt to 4, although that doesn't
17586 really seem like the right value. */
17591 {
17592 bfd_vma got_address
17596 bfd_vma plt_address
17612 }
17615 {
17619 #ifdef FOUR_WORD_PLT
17622 #endif
17623 }
17628 {
17629 /* Correct the .rel(a).plt.unloaded relocations. They will have
17630 incorrect symbol indexes. */
17639 {
17640 Elf_Internal_Rela rel;
17651 }
17652 }
17653 }
17658 /* NaCl uses a special first entry in .iplt too. */
17661 /* Fill in the first three entries in the global offset table. */
17663 {
17665 {
17668 else
17674 }
17677 }
17679 /* At the very end of the .rofixup section is a pointer to the GOT. */
17681 {
17690 /* Make sure we allocated and generated the same number of fixups. */
17692 }
17695 }
17697 static bool
17699 {
17714 {
17721 }
17725 {
17729 else
17731 }
17733 /* Scan segment to set p_flags attribute if it contains only sections with
17734 SHF_ARM_PURECODE flag. */
17736 {
17742 {
17745 }
17747 {
17750 }
17751 }
17753 }
17755 static enum elf_reloc_type_class
17759 {
17764 {
17765 /* Check relocation against STT_GNU_IFUNC symbol if there are
17766 dynamic symbols. */
17771 {
17772 Elf_Internal_Sym sym;
17777 {
17778 /* xgettext:c-format */
17782 /* Ideally an error class should be returned here. */
17783 }
17786 }
17787 }
17790 {
17801 }
17802 }
17804 static void
17806 {
17808 }
17810 static bool
17812 {
17815 }
17817 /* Return TRUE if this is an unwinding table entry. */
17819 static bool
17821 {
17824 }
17827 /* Set the type and flags for an ARM section. We do this by
17828 the section name, which is a hack, but ought to work. */
17830 static bool
17832 {
17838 {
17841 }
17847 }
17849 /* Handle an ARM specific section when reading an object file. This is
17850 called when bfd_section_from_shdr finds a section with an unknown
17851 type. */
17853 static bool
17858 {
17859 /* There ought to be a place to keep ELF backend specific flags, but
17860 at the moment there isn't one. We just keep track of the
17861 sections by their name, instead. Fortunately, the ABI gives
17862 names for all the ARM specific sections, so we will probably get
17863 away with this. */
17865 {
17873 }
17879 }
17883 {
17886 else
17888 }
17891 {
17900 enum map_symbol_type
17901 {
17902 ARM_MAP_ARM,
17903 ARM_MAP_THUMB,
17904 ARM_MAP_DATA
17905 };
17908 /* Output a single mapping symbol. */
17910 static bool
17913 bfd_vma offset)
17914 {
17916 Elf_Internal_Sym sym;
17928 }
17930 /* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
17931 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
17933 static bool
17938 {
17950 {
17953 }
17954 else
17955 {
17958 }
17964 {
17973 }
17975 {
17978 }
17980 {
17982 ? ARM_MAP_THUMB
17995 }
17997 {
18000 }
18001 else
18002 {
18007 {
18010 }
18011 #ifdef FOUR_WORD_PLT
18016 #else
18017 /* A three-word PLT with no Thumb thunk contains only Arm code,
18018 so only need to output a mapping symbol for the first PLT entry and
18019 entries with thumb thunks. */
18021 {
18024 }
18025 #endif
18026 }
18029 }
18031 /* Output mapping symbols for PLT entries associated with H. */
18033 static bool
18035 {
18043 /* When warning symbols are created, they **replace** the "real"
18044 entry in the hash table, thus we never get to see the real
18045 symbol in a hash traversal. So look at it now. */
18051 }
18053 /* Bind a veneered symbol to its veneer identified by its hash entry
18054 STUB_ENTRY. The veneered location thus loose its symbol. */
18056 static void
18058 {
18065 }
18067 /* Output a single local symbol for a generated stub. */
18069 static bool
18072 {
18073 Elf_Internal_Sym sym;
18084 }
18086 static bool
18089 {
18092 bfd_vma addr;
18101 /* Massage our args to the form they really have. */
18107 /* Ensure this stub is attached to the current section being
18108 processed. */
18117 else
18118 {
18121 {
18136 }
18137 }
18142 {
18144 {
18161 }
18164 {
18168 }
18171 {
18188 }
18189 }
18192 }
18194 /* Output mapping symbols for linker generated sections,
18195 and for those data-only sections that do not have a
18196 $d. */
18198 static bool
18203 Elf_Internal_Sym *,
18204 asection *,
18206 {
18207 output_arch_syminfo osi;
18209 bfd_vma offset;
18210 bfd_size_type size;
18228 /* Add a $d mapping symbol to data-only sections that
18229 don't have any mapping symbol. This may result in (harmless) redundant
18230 mapping symbols. */
18234 {
18239 {
18244 == SEC_HAS_CONTENTS
18249 {
18254 }
18255 }
18256 }
18258 /* ARM->Thumb glue. */
18260 {
18262 ARM2THUMB_GLUE_SECTION_NAME);
18271 else
18275 {
18278 }
18279 }
18281 /* Thumb->ARM glue. */
18283 {
18285 THUMB2ARM_GLUE_SECTION_NAME);
18292 {
18295 }
18296 }
18298 /* ARMv4 BX veneers. */
18300 {
18302 ARM_BX_GLUE_SECTION_NAME);
18308 }
18310 /* Long calls stubs. */
18312 {
18318 {
18319 /* Ignore non-stub sections. */
18329 }
18330 }
18332 /* Finally, output mapping symbols for the PLT. */
18334 {
18339 /* Output mapping symbols for the plt header. */
18341 {
18342 /* VxWorks shared libraries have no PLT header. */
18344 {
18349 }
18350 }
18352 {
18355 }
18357 {
18364 }
18366 {
18369 #ifndef FOUR_WORD_PLT
18372 #endif
18373 }
18374 }
18378 {
18379 /* NaCl uses a special first entry in .iplt too. */
18385 }
18388 {
18393 {
18399 {
18402 {
18405 input_bfd,
18407 num_syms);
18409 }
18416 }
18417 }
18418 }
18420 {
18421 /* Mapping symbols for the lazy tls trampoline. */
18429 }
18431 {
18432 /* Mapping symbols for the tls trampoline. */
18435 #ifdef FOUR_WORD_PLT
18439 #endif
18440 }
18443 }
18445 /* Filter normal symbols of CMSE entry functions of ABFD to include in
18446 the import library. All SYMCOUNT symbols of ABFD can be examined
18447 from their pointers in SYMS. Pointers of symbols to keep should be
18448 stored continuously at the beginning of that array.
18450 Returns the number of symbols to keep. */
18452 static unsigned int
18456 {
18471 {
18474 flagword flags;
18489 {
18493 }
18505 }
18511 }
18513 /* Filter symbols of ABFD to include in the import library. All
18514 SYMCOUNT symbols of ABFD can be examined from their pointers in
18515 SYMS. Pointers of symbols to keep should be stored continuously at
18516 the beginning of that array.
18518 Returns the number of symbols to keep. */
18520 static unsigned int
18524 {
18527 /* Requirement 8 of "ARM v8-M Security Extensions: Requirements on
18528 Development Tools" (ARM-ECM-0359818) mandates Secure Gateway import
18529 library to be a relocatable object file. */
18533 else
18535 }
18537 /* Allocate target specific section data. */
18539 static bool
18541 {
18548 }
18551 /* Used to order a list of mapping symbols by address. */
18553 static int
18555 {
18564 /* Ensure results do not depend on the host qsort for objects with
18565 multiple mapping symbols at the same address by sorting on type
18566 after vma. */
18570 else
18572 }
18574 /* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
18576 static unsigned long
18578 {
18580 }
18582 /* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
18583 relocations. */
18585 static void
18587 {
18591 /* High bit of first word is supposed to be zero. */
18595 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
18596 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
18602 }
18604 /* Data for make_branch_to_a8_stub(). */
18606 struct a8_branch_to_stub_data
18607 {
18610 };
18613 /* Helper to insert branches to Cortex-A8 erratum stubs in the right
18614 places for a particular section. */
18616 static bool
18619 {
18625 bfd_signed_vma branch_offset;
18638 /* We use target_section as Cortex-A8 erratum workaround stubs are only
18639 generated when both source and target are in the same section. */
18656 /* We attempt to avoid this condition by setting stubs_always_after_branch
18657 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
18658 This check is just to be on the safe side... */
18660 {
18664 }
18667 {
18678 {
18683 jump24:
18685 {
18686 /* There's not much we can do apart from complain if this
18687 happens. */
18691 }
18693 /* i1 = not(j1 eor s), so:
18694 not i1 = j1 eor s
18695 j1 = (not i1) eor s. */
18707 }
18713 }
18719 }
18721 /* Beginning of stm32l4xx work-around. */
18723 /* Functions encoding instructions necessary for the emission of the
18724 fix-stm32l4xx-629360.
18725 Encoding is extracted from the
18726 ARM (C) Architecture Reference Manual
18727 ARMv7-A and ARMv7-R edition
18728 ARM DDI 0406C.b (ID072512). */
18732 {
18733 /* A8.8.18 B (A8-334)
18734 B target_address (Encoding T4). */
18735 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
18736 /* jump offset is: S:I1:I2:imm10:imm11:0. */
18737 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
18754 }
18758 {
18759 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
18760 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
18767 }
18771 {
18772 /* A8.8.60 LDMDB/LDMEA (A8-402)
18773 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
18780 }
18784 {
18785 /* A8.8.103 MOV (register) (A8-486)
18786 MOV Rd, Rm (Encoding T1). */
18793 }
18797 {
18798 /* A8.8.221 SUB (immediate) (A8-708)
18799 SUB Rd, Rn, #value (Encoding T3). */
18809 }
18814 {
18815 /* A8.8.332 VLDM (A8-922)
18816 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
18825 }
18830 {
18831 /* A8.8.332 VLDM (A8-922)
18832 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
18840 }
18844 {
18845 /* A8.8.247 UDF (A8-758)
18846 Undefined (Encoding T2). */
18852 }
18856 {
18857 /* A8.8.247 UDF (A8-758)
18858 Undefined (Encoding T1). */
18863 }
18865 /* Functions writing an instruction in memory, returning the next
18866 memory position to write to. */
18871 {
18874 }
18879 {
18882 }
18884 /* Function filling up a region in memory with T1 and T2 UDFs taking
18885 care of alignment. */
18893 {
18896 /* Fill the remaining of the stub with deterministic contents : UDF
18897 instructions.
18898 Check if realignment is needed on modulo 4 frontier using T1, to
18899 further use T2. */
18903 current_stub_contents =
18908 current_stub_contents =
18913 }
18915 /* Functions writing the stream of instructions equivalent to the
18916 derived sequence for ldmia, ldmdb, vldm respectively. */
18918 static void
18924 {
18937 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
18938 smaller than 8 registers load sequences that do not cause the
18939 hardware issue. */
18941 {
18942 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
18943 current_stub_contents =
18945 initial_insn);
18947 /* B initial_insn_addr+4. */
18949 current_stub_contents =
18951 create_instruction_branch_absolute
18954 /* Fill the remaining of the stub with deterministic contents. */
18955 current_stub_contents =
18958 base_stub_contents +
18959 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18962 }
18964 /* - reg_list[13] == 0. */
18967 /* - reg_list[14] & reg_list[15] != 1. */
18970 /* - if (wback==1) reg_list[rn] == 0. */
18973 /* - nb_registers > 8. */
18976 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
18978 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
18979 - One with the 7 lowest registers (register mask 0x007F)
18980 This LDM will finally contain between 2 and 7 registers
18981 - One with the 7 highest registers (register mask 0xDF80)
18982 This ldm will finally contain between 2 and 7 registers. */
18986 /* A spare register may be needed during this veneer to temporarily
18987 handle the base register. This register will be restored with the
18988 last LDM operation.
18989 The usable register may be any general purpose register (that
18990 excludes PC, SP, LR : register mask is 0x1FFF). */
18993 /* Generate the stub function. */
18995 {
18996 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
18997 current_stub_contents =
18999 create_instruction_ldmia
19002 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
19003 current_stub_contents =
19005 create_instruction_ldmia
19008 {
19009 /* B initial_insn_addr+4. */
19010 current_stub_contents =
19012 create_instruction_branch_absolute
19014 }
19015 }
19017 {
19020 /* If Rn is not part of the high-register-list, move it there. */
19022 {
19023 /* Choose a Ri in the high-register-list that will be restored. */
19026 /* MOV Ri, Rn. */
19027 current_stub_contents =
19030 }
19032 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
19033 current_stub_contents =
19035 create_instruction_ldmia
19038 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
19039 current_stub_contents =
19041 create_instruction_ldmia
19045 {
19046 /* B initial_insn_addr+4. */
19047 current_stub_contents =
19049 create_instruction_branch_absolute
19051 }
19052 }
19054 /* Fill the remaining of the stub with deterministic contents. */
19055 current_stub_contents =
19058 base_stub_contents +
19059 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19060 }
19062 static void
19068 {
19081 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
19082 smaller than 8 registers load sequences that do not cause the
19083 hardware issue. */
19085 {
19086 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
19087 current_stub_contents =
19089 initial_insn);
19091 /* B initial_insn_addr+4. */
19092 current_stub_contents =
19094 create_instruction_branch_absolute
19097 /* Fill the remaining of the stub with deterministic contents. */
19098 current_stub_contents =
19101 base_stub_contents +
19102 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19105 }
19107 /* - reg_list[13] == 0. */
19110 /* - reg_list[14] & reg_list[15] != 1. */
19113 /* - if (wback==1) reg_list[rn] == 0. */
19116 /* - nb_registers > 8. */
19119 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
19121 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
19122 - One with the 7 lowest registers (register mask 0x007F)
19123 This LDM will finally contain between 2 and 7 registers
19124 - One with the 7 highest registers (register mask 0xDF80)
19125 This ldm will finally contain between 2 and 7 registers. */
19129 /* A spare register may be needed during this veneer to temporarily
19130 handle the base register. This register will be restored with
19131 the last LDM operation.
19132 The usable register may be any general purpose register (that excludes
19133 PC, SP, LR : register mask is 0x1FFF). */
19136 /* Generate the stub function. */
19138 {
19139 /* Choose a Ri in the low-register-list that will be restored. */
19142 /* MOV Ri, Rn. */
19143 current_stub_contents =
19147 /* LDMDB Ri!, {R-high-register-list}. */
19148 current_stub_contents =
19150 create_instruction_ldmdb
19153 /* LDMDB Ri, {R-low-register-list}. */
19154 current_stub_contents =
19156 create_instruction_ldmdb
19159 /* B initial_insn_addr+4. */
19160 current_stub_contents =
19162 create_instruction_branch_absolute
19164 }
19166 {
19167 /* LDMDB Rn!, {R-high-register-list}. */
19168 current_stub_contents =
19170 create_instruction_ldmdb
19173 /* LDMDB Rn!, {R-low-register-list}. */
19174 current_stub_contents =
19176 create_instruction_ldmdb
19179 /* B initial_insn_addr+4. */
19180 current_stub_contents =
19182 create_instruction_branch_absolute
19184 }
19186 {
19187 /* Choose a Ri in the high-register-list that will be restored. */
19190 /* SUB Ri, Rn, #(4*nb_registers). */
19191 current_stub_contents =
19195 /* LDMIA Ri!, {R-low-register-list}. */
19196 current_stub_contents =
19198 create_instruction_ldmia
19201 /* LDMIA Ri, {R-high-register-list}. */
19202 current_stub_contents =
19204 create_instruction_ldmia
19206 }
19208 {
19209 /* Choose a Ri in the high-register-list that will be restored. */
19212 /* SUB Rn, Rn, #(4*nb_registers) */
19213 current_stub_contents =
19217 /* MOV Ri, Rn. */
19218 current_stub_contents =
19222 /* LDMIA Ri!, {R-low-register-list}. */
19223 current_stub_contents =
19225 create_instruction_ldmia
19228 /* LDMIA Ri, {R-high-register-list}. */
19229 current_stub_contents =
19231 create_instruction_ldmia
19233 }
19235 {
19238 {
19239 /* Choose a Ri in the low-register-list that will be restored. */
19242 /* MOV Ri, Rn. */
19243 current_stub_contents =
19246 }
19248 /* LDMDB Ri!, {R-high-register-list}. */
19249 current_stub_contents =
19251 create_instruction_ldmdb
19254 /* LDMDB Ri, {R-low-register-list}. */
19255 current_stub_contents =
19257 create_instruction_ldmdb
19260 /* B initial_insn_addr+4. */
19261 current_stub_contents =
19263 create_instruction_branch_absolute
19265 }
19267 {
19270 {
19271 /* Choose a Ri in the high-register-list that will be restored. */
19273 }
19275 /* SUB Ri, Rn, #(4*nb_registers). */
19276 current_stub_contents =
19280 /* LDMIA Ri!, {R-low-register-list}. */
19281 current_stub_contents =
19283 create_instruction_ldmia
19286 /* LDMIA Ri, {R-high-register-list}. */
19287 current_stub_contents =
19289 create_instruction_ldmia
19291 }
19293 {
19294 /* The assembler should not have accepted to encode this. */
19297 }
19299 /* Fill the remaining of the stub with deterministic contents. */
19300 current_stub_contents =
19303 base_stub_contents +
19304 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19306 }
19308 static void
19314 {
19320 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
19321 smaller than 8 words load sequences that do not cause the
19322 hardware issue. */
19324 {
19325 /* Untouched instruction. */
19326 current_stub_contents =
19328 initial_insn);
19330 /* B initial_insn_addr+4. */
19331 current_stub_contents =
19333 create_instruction_branch_absolute
19335 }
19336 else
19337 {
19347 /* d = UInt (Vd:D);. */
19351 /* Compute the number of 8-words chunks needed to split. */
19355 /* The test coverage has been done assuming the following
19356 hypothesis that exactly one of the previous is_ predicates is
19357 true. */
19361 /* We treat the cutting of the words in one pass for all
19362 cases, then we emit the adjustments:
19364 vldm rx, {...}
19365 -> vldm rx!, {8_words_or_less} for each needed 8_word
19366 -> sub rx, rx, #size (list)
19368 vldm rx!, {...}
19369 -> vldm rx!, {8_words_or_less} for each needed 8_word
19370 This also handles vpop instruction (when rx is sp)
19372 vldmd rx!, {...}
19373 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
19375 {
19379 {
19380 new_insn = create_instruction_vldmia
19382 is_dp,
19387 }
19389 {
19390 new_insn = create_instruction_vldmdb
19392 is_dp,
19396 }
19399 current_stub_contents =
19401 new_insn);
19402 }
19404 /* Only this case requires the base register compensation
19405 subtract. */
19407 {
19408 current_stub_contents =
19410 create_instruction_sub
19412 }
19414 /* B initial_insn_addr+4. */
19415 current_stub_contents =
19417 create_instruction_branch_absolute
19419 }
19421 /* Fill the remaining of the stub with deterministic contents. */
19422 current_stub_contents =
19425 base_stub_contents +
19426 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
19427 }
19429 static void
19435 {
19439 stub_contents);
19443 stub_contents);
19447 stub_contents);
19448 }
19450 /* End of stm32l4xx work-around. */
19453 /* Do code byteswapping. Return FALSE afterwards so that the section is
19454 written out as normal. */
19456 static bool
19461 {
19468 bfd_vma ptr;
19469 bfd_vma end;
19471 bfd_byte tmp;
19477 /* If this section has not been allocated an _arm_elf_section_data
19478 structure then we cannot record anything. */
19488 {
19493 {
19497 {
19499 {
19500 bfd_vma branch_to_veneer;
19501 /* Original condition code of instruction, plus bit mask for
19502 ARM B instruction. */
19506 /* The instruction is before the label. */
19509 /* Above offset included in -4 below. */
19523 }
19527 {
19528 bfd_vma branch_from_veneer;
19531 /* Take size of veneer into account. */
19540 /* Original instruction. */
19547 /* Branch back to insn after original insn. */
19553 }
19558 }
19559 }
19560 }
19563 {
19567 {
19571 {
19573 {
19575 bfd_vma branch_to_veneer =
19580 {
19581 bfd_vma out_of_range =
19587 _bfd_error_handler
19589 "cannot create STM32L4XX veneer; "
19592 output_bfd,
19596 }
19598 insn = create_instruction_branch_absolute
19601 /* The instruction is before the label. */
19606 }
19610 {
19616 veneer_r = veneer
19621 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
19622 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
19623 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
19626 {
19630 }
19632 /* Original instruction. */
19635 stm32l4xx_create_replacing_stub
19637 }
19642 }
19643 }
19644 }
19647 {
19648 arm_unwind_table_edit *edit_node
19650 /* Now, sec->size is the size of the section we will write. The original
19651 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
19652 markers) was sec->rawsize. (This isn't the case if we perform no
19653 edits, then rawsize will be zero and we should use size). */
19662 {
19664 {
19668 {
19671 out_index++;
19672 in_index++;
19673 }
19677 {
19679 {
19681 in_index++;
19686 {
19694 /* Note: this is meant to be equivalent to an
19695 R_ARM_PREL31 relocation. These synthetic
19696 EXIDX_CANTUNWIND markers are not relocated by the
19697 usual BFD method. */
19701 {
19702 /* Here relocation for new EXIDX_CANTUNWIND is
19703 created, so there is no need to
19704 adjust offset by hand. */
19707 }
19709 /* First address we can't unwind. */
19713 /* Code for EXIDX_CANTUNWIND. */
19717 out_index++;
19719 }
19721 }
19724 }
19725 }
19726 else
19727 {
19728 /* No more edits, copy remaining entries verbatim. */
19731 out_index++;
19732 in_index++;
19733 }
19734 }
19738 edited_contents,
19742 }
19744 /* Fix code to point to Cortex-A8 erratum stubs. */
19746 {
19754 }
19760 {
19765 {
19768 else
19772 {
19774 /* Byte swap code words. */
19776 {
19784 }
19788 /* Byte swap code halfwords. */
19790 {
19795 }
19799 /* Leave data alone. */
19801 }
19803 }
19804 }
19812 }
19814 /* Mangle thumb function symbols as we read them in. */
19816 static bool
19821 {
19826 /* New EABI objects mark thumb function symbols by setting the low bit of
19827 the address. */
19830 {
19832 {
19835 ST_BRANCH_TO_THUMB);
19836 }
19837 else
19839 }
19841 {
19844 }
19847 else
19851 }
19854 /* Mangle thumb function symbols as we write them out. */
19856 static void
19861 {
19862 Elf_Internal_Sym newsym;
19864 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
19865 of the address set, as per the new EABI. We do this unconditionally
19866 because objcopy does not set the elf header flags until after
19867 it writes out the symbol table. */
19869 {
19874 {
19875 /* Do this only for defined symbols. At link type, the static
19876 linker will simulate the work of dynamic linker of resolving
19877 symbols and will carry over the thumbness of found symbols to
19878 the output symbol table. It's not clear how it happens, but
19879 the thumbness of undefined symbols can well be different at
19880 runtime, and writing '1' for them will be confusing for users
19881 and possibly for dynamic linker itself.
19882 */
19884 }
19887 }
19889 }
19891 /* Add the PT_ARM_EXIDX program header. */
19893 static bool
19896 {
19902 {
19903 /* If there is already a PT_ARM_EXIDX header, then we do not
19904 want to add another one. This situation arises when running
19905 "strip"; the input binary already has the header. */
19910 {
19921 }
19922 }
19925 }
19927 /* We may add a PT_ARM_EXIDX program header. */
19929 static int
19932 {
19938 else
19940 }
19942 /* Hook called by the linker routine which adds symbols from an object
19943 file. */
19945 static bool
19949 {
19959 }
19961 /* We use this to override swap_symbol_in and swap_symbol_out. */
19963 {
19976 bfd_elf32_write_out_phdrs,
19977 bfd_elf32_write_shdrs_and_ehdr,
19978 bfd_elf32_checksum_contents,
19979 bfd_elf32_write_relocs,
19980 elf32_arm_swap_symbol_in,
19981 elf32_arm_swap_symbol_out,
19982 bfd_elf32_slurp_reloc_table,
19983 bfd_elf32_slurp_symbol_table,
19984 bfd_elf32_swap_dyn_in,
19985 bfd_elf32_swap_dyn_out,
19986 bfd_elf32_swap_reloc_in,
19987 bfd_elf32_swap_reloc_out,
19988 bfd_elf32_swap_reloca_in,
19989 bfd_elf32_swap_reloca_out
19990 };
19992 static bfd_vma
19994 {
19995 /* V7 BE8 code is always little endian. */
20000 }
20002 static bfd_vma
20004 {
20005 /* V7 BE8 code is always little endian. */
20010 }
20012 /* Return size of plt0 entry starting at ADDR
20013 or (bfd_vma) -1 if size can not be determined. */
20015 static bfd_vma
20017 bfd_size_type data_size)
20018 {
20019 bfd_vma first_word;
20020 bfd_vma plt0_size;
20031 else
20032 /* We don't yet handle this PLT format. */
20036 }
20038 /* Return size of plt entry starting at offset OFFSET
20039 of plt section located at address START
20040 or (bfd_vma) -1 if size can not be determined. */
20042 static bfd_vma
20044 bfd_size_type data_size)
20045 {
20046 bfd_vma first_insn;
20049 /* PLT entry size if fixed on Thumb-only platforms. */
20053 /* Respect Thumb stub if necessary. */
20057 {
20059 }
20061 /* Strip immediate from first add. */
20066 #ifdef FOUR_WORD_PLT
20069 #else
20074 #endif
20075 else
20076 /* We don't yet handle this PLT format. */
20080 }
20082 /* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
20084 static long
20091 {
20100 bfd_vma offset;
20135 {
20139 }
20144 {
20147 }
20153 {
20161 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
20162 we are defining a symbol, ensure one of them is set. */
20174 {
20181 ;
20185 }
20190 }
20194 }
20196 static bool
20198 {
20202 }
20204 static flagword
20206 {
20211 }
20213 static unsigned int
20215 {
20220 }
20222 /* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
20223 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
20224 FALSE otherwise. ISECTION is the best guess matching section from the
20225 input bfd IBFD, but it might be NULL. */
20227 static bool
20232 {
20234 {
20236 {
20244 /* The sh_link field must be set to the text section associated with
20245 this index section. Unfortunately the ARM EHABI does not specify
20246 exactly how to determine this association. Our caller does try
20247 to match up OSECTION with its corresponding input section however
20248 so that is a good first guess. */
20259 )
20260 {
20265 }
20268 {
20269 /* Failing that we have to find a matching section ourselves. If
20270 we had the output section name available we could compare that
20271 with input section names. Unfortunately we don't. So instead
20272 we use a simple heuristic and look for the nearest executable
20273 section before this one. */
20285 }
20288 {
20290 /* If the text section was part of a group
20291 then the index section should be too. */
20295 }
20296 }
20308 }
20311 }
20313 /* Returns TRUE if NAME is an ARM mapping symbol.
20314 Traditionally the symbols $a, $d and $t have been used.
20315 The ARM ELF standard also defines $x (for A64 code). It also allows a
20316 period initiated suffix to be added to the symbol: "$[adtx]\.[:sym_char]+".
20317 Other tools might also produce $b (Thumb BL), $f, $p, $m and $v, but we do
20318 not support them here. $t.x indicates the start of ThumbEE instructions. */
20320 static bool
20322 {
20325 the mapping symbols could have acquired a prefix.
20326 We do not support this here, since such symbols no
20327 longer conform to the ARM ELF ABI. */
20330 /* FIXME: Strictly speaking the symbol is only a valid mapping symbol if
20331 any characters that follow the period are legal characters for the body
20332 of a symbol's name. For now we just assume that this is the case. */
20333 }
20335 /* Make sure that mapping symbols in object files are not removed via the
20336 "strip --strip-unneeded" tool. These symbols are needed in order to
20337 correctly generate interworking veneers, and for byte swapping code
20338 regions. Once an object file has been linked, it is safe to remove the
20339 symbols as they will no longer be needed. */
20341 static void
20343 {
20348 }
20350 #undef elf_backend_copy_special_section_fields
20351 #define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
20353 #define ELF_ARCH bfd_arch_arm
20354 #define ELF_TARGET_ID ARM_ELF_DATA
20355 #define ELF_MACHINE_CODE EM_ARM
20356 #define ELF_MAXPAGESIZE 0x1000
20357 #define ELF_COMMONPAGESIZE 0x1000
20359 #define bfd_elf32_mkobject elf32_arm_mkobject
20361 #define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
20362 #define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
20363 #define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
20364 #define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
20365 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
20366 #define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
20367 #define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
20368 #define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
20369 #define bfd_elf32_new_section_hook elf32_arm_new_section_hook
20370 #define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
20371 #define bfd_elf32_bfd_final_link elf32_arm_final_link
20372 #define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
20374 #define elf_backend_get_symbol_type elf32_arm_get_symbol_type
20375 #define elf_backend_maybe_function_sym elf32_arm_maybe_function_sym
20376 #define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
20377 #define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
20378 #define elf_backend_check_relocs elf32_arm_check_relocs
20379 #define elf_backend_update_relocs elf32_arm_update_relocs
20380 #define elf_backend_relocate_section elf32_arm_relocate_section
20381 #define elf_backend_write_section elf32_arm_write_section
20382 #define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
20383 #define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
20384 #define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
20385 #define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
20386 #define elf_backend_late_size_sections elf32_arm_late_size_sections
20387 #define elf_backend_early_size_sections elf32_arm_early_size_sections
20388 #define elf_backend_init_index_section _bfd_elf_init_2_index_sections
20389 #define elf_backend_init_file_header elf32_arm_init_file_header
20390 #define elf_backend_reloc_type_class elf32_arm_reloc_type_class
20391 #define elf_backend_object_p elf32_arm_object_p
20392 #define elf_backend_fake_sections elf32_arm_fake_sections
20393 #define elf_backend_section_from_shdr elf32_arm_section_from_shdr
20394 #define elf_backend_final_write_processing elf32_arm_final_write_processing
20395 #define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
20396 #define elf_backend_size_info elf32_arm_size_info
20397 #define elf_backend_modify_segment_map elf32_arm_modify_segment_map
20398 #define elf_backend_additional_program_headers elf32_arm_additional_program_headers
20399 #define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
20400 #define elf_backend_filter_implib_symbols elf32_arm_filter_implib_symbols
20401 #define elf_backend_begin_write_processing elf32_arm_begin_write_processing
20402 #define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
20403 #define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
20404 #define elf_backend_symbol_processing elf32_arm_backend_symbol_processing
20406 #define elf_backend_can_refcount 1
20407 #define elf_backend_can_gc_sections 1
20408 #define elf_backend_plt_readonly 1
20409 #define elf_backend_want_got_plt 1
20410 #define elf_backend_want_plt_sym 0
20411 #define elf_backend_want_dynrelro 1
20412 #define elf_backend_may_use_rel_p 1
20413 #define elf_backend_may_use_rela_p 0
20414 #define elf_backend_default_use_rela_p 0
20415 #define elf_backend_dtrel_excludes_plt 1
20417 #define elf_backend_got_header_size 12
20418 #define elf_backend_extern_protected_data 0
20420 #undef elf_backend_obj_attrs_vendor
20422 #undef elf_backend_obj_attrs_section
20424 #undef elf_backend_obj_attrs_arg_type
20425 #define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
20426 #undef elf_backend_obj_attrs_section_type
20427 #define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
20428 #define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
20429 #define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
20431 #undef elf_backend_section_flags
20432 #define elf_backend_section_flags elf32_arm_section_flags
20433 #undef elf_backend_lookup_section_flags_hook
20434 #define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
20436 #define elf_backend_linux_prpsinfo32_ugid16 true
20440 /* Native Client targets. */
20442 #undef TARGET_LITTLE_SYM
20443 #define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
20444 #undef TARGET_LITTLE_NAME
20446 #undef TARGET_BIG_SYM
20447 #define TARGET_BIG_SYM arm_elf32_nacl_be_vec
20448 #undef TARGET_BIG_NAME
20451 /* Like elf32_arm_link_hash_table_create -- but overrides
20452 appropriately for NaCl. */
20456 {
20461 {
20467 }
20469 }
20471 /* Since NaCl doesn't use the ARM-specific unwind format, we don't
20472 really need to use elf32_arm_modify_segment_map. But we do it
20473 anyway just to reduce gratuitous differences with the stock ARM backend. */
20475 static bool
20477 {
20480 }
20482 static bool
20484 {
20487 }
20489 static bfd_vma
20492 {
20496 }
20498 #undef elf32_bed
20499 #define elf32_bed elf32_arm_nacl_bed
20500 #undef bfd_elf32_bfd_link_hash_table_create
20501 #define bfd_elf32_bfd_link_hash_table_create \
20502 elf32_arm_nacl_link_hash_table_create
20503 #undef elf_backend_plt_alignment
20504 #define elf_backend_plt_alignment 4
20505 #undef elf_backend_modify_segment_map
20506 #define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
20507 #undef elf_backend_modify_headers
20508 #define elf_backend_modify_headers nacl_modify_headers
20509 #undef elf_backend_final_write_processing
20510 #define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
20511 #undef bfd_elf32_get_synthetic_symtab
20512 #undef elf_backend_plt_sym_val
20513 #define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
20514 #undef elf_backend_copy_special_section_fields
20516 #undef ELF_MINPAGESIZE
20517 #undef ELF_COMMONPAGESIZE
20519 #undef ELF_TARGET_OS
20520 #define ELF_TARGET_OS is_nacl
20524 /* Reset to defaults. */
20525 #undef elf_backend_plt_alignment
20526 #undef elf_backend_modify_segment_map
20527 #define elf_backend_modify_segment_map elf32_arm_modify_segment_map
20528 #undef elf_backend_modify_headers
20529 #undef elf_backend_final_write_processing
20530 #define elf_backend_final_write_processing elf32_arm_final_write_processing
20531 #undef ELF_MINPAGESIZE
20532 #undef ELF_COMMONPAGESIZE
20533 #define ELF_COMMONPAGESIZE 0x1000
20536 /* FDPIC Targets. */
20538 #undef TARGET_LITTLE_SYM
20539 #define TARGET_LITTLE_SYM arm_elf32_fdpic_le_vec
20540 #undef TARGET_LITTLE_NAME
20542 #undef TARGET_BIG_SYM
20543 #define TARGET_BIG_SYM arm_elf32_fdpic_be_vec
20544 #undef TARGET_BIG_NAME
20546 #undef elf_match_priority
20547 #define elf_match_priority 128
20548 #undef ELF_OSABI
20549 #define ELF_OSABI ELFOSABI_ARM_FDPIC
20551 /* Like elf32_arm_link_hash_table_create -- but overrides
20552 appropriately for FDPIC. */
20556 {
20561 {
20565 }
20567 }
20569 /* We need dynamic symbols for every section, since segments can
20570 relocate independently. */
20571 static bool
20574 ATTRIBUTE_UNUSED,
20576 {
20578 {
20581 /* If sh_type is yet undecided, assume it could be
20582 SHT_PROGBITS/SHT_NOBITS. */
20586 /* There shouldn't be section relative relocations
20587 against any other section. */
20590 }
20591 }
20593 #undef elf32_bed
20594 #define elf32_bed elf32_arm_fdpic_bed
20596 #undef bfd_elf32_bfd_link_hash_table_create
20597 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_fdpic_link_hash_table_create
20599 #undef elf_backend_omit_section_dynsym
20600 #define elf_backend_omit_section_dynsym elf32_arm_fdpic_omit_section_dynsym
20602 #undef ELF_TARGET_OS
20606 #undef elf_match_priority
20607 #undef ELF_OSABI
20608 #undef elf_backend_omit_section_dynsym
20610 /* VxWorks Targets. */
20612 #undef TARGET_LITTLE_SYM
20613 #define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
20614 #undef TARGET_LITTLE_NAME
20616 #undef TARGET_BIG_SYM
20617 #define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
20618 #undef TARGET_BIG_NAME
20621 /* Like elf32_arm_link_hash_table_create -- but overrides
20622 appropriately for VxWorks. */
20626 {
20631 {
20635 }
20637 }
20639 static bool
20641 {
20644 }
20646 #undef elf32_bed
20647 #define elf32_bed elf32_arm_vxworks_bed
20649 #undef bfd_elf32_bfd_link_hash_table_create
20650 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
20651 #undef elf_backend_final_write_processing
20652 #define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
20653 #undef elf_backend_emit_relocs
20654 #define elf_backend_emit_relocs elf_vxworks_emit_relocs
20656 #undef elf_backend_may_use_rel_p
20657 #define elf_backend_may_use_rel_p 0
20658 #undef elf_backend_may_use_rela_p
20659 #define elf_backend_may_use_rela_p 1
20660 #undef elf_backend_default_use_rela_p
20661 #define elf_backend_default_use_rela_p 1
20662 #undef elf_backend_want_plt_sym
20663 #define elf_backend_want_plt_sym 1
20664 #undef ELF_MAXPAGESIZE
20665 #define ELF_MAXPAGESIZE 0x1000
20666 #undef ELF_TARGET_OS
20667 #define ELF_TARGET_OS is_vxworks
20672 /* Merge backend specific data from an object file to the output
20673 object file when linking. */
20675 static bool
20677 {
20679 flagword out_flags;
20680 flagword in_flags;
20684 /* Check if we have the same endianness. */
20694 /* The input BFD must have had its flags initialised. */
20695 /* The following seems bogus to me -- The flags are initialized in
20696 the assembler but I don't think an elf_flags_init field is
20697 written into the object. */
20698 /* BFD_ASSERT (elf_flags_init (ibfd)); */
20703 /* In theory there is no reason why we couldn't handle this. However
20704 in practice it isn't even close to working and there is no real
20705 reason to want it. */
20709 {
20711 ibfd);
20713 }
20716 {
20717 /* If the input has no flags set, then do not set the output flags.
20718 This will allow future bfds to determine the desired output flags.
20719 If no input bfds have any flags set, then neither will the output bfd.
20721 Note - we used to restrict this test to when the input architecture
20722 variant was the default variant, but this does not allow for
20723 linker scripts which override the default. See PR 28910 for an
20724 example. */
20736 }
20738 /* Determine what should happen if the input ARM architecture
20739 does not match the output ARM architecture. */
20743 /* Identical flags must be compatible. */
20747 /* Check to see if the input BFD actually contains any sections. If
20748 not, its flags may not have been initialised either, but it
20749 cannot actually cause any incompatiblity. Do not short-circuit
20750 dynamic objects; their section list may be emptied by
20751 elf_link_add_object_symbols.
20753 Also check to see if there are no code sections in the input.
20754 In this case there is no need to check for code specific flags.
20755 XXX - do we need to worry about floating-point format compatability
20756 in data sections ? */
20758 {
20763 {
20764 /* Ignore synthetic glue sections. */
20767 {
20775 }
20776 }
20780 }
20782 /* Complain about various flag mismatches. */
20785 {
20786 _bfd_error_handler
20791 }
20793 /* Not sure what needs to be checked for EABI versions >= 1. */
20794 /* VxWorks libraries do not use these flags. */
20798 {
20800 {
20801 _bfd_error_handler
20806 }
20809 {
20811 _bfd_error_handler
20812 (_("error: %pB passes floats in float registers, whereas %pB passes them in integer registers"),
20814 else
20815 _bfd_error_handler
20816 (_("error: %pB passes floats in integer registers, whereas %pB passes them in float registers"),
20820 }
20823 {
20825 _bfd_error_handler
20828 else
20829 _bfd_error_handler
20834 }
20836 #ifdef EF_ARM_SOFT_FLOAT
20838 {
20839 /* We can allow interworking between code that is VFP format
20840 layout, and uses either soft float or integer regs for
20841 passing floating point arguments and results. We already
20842 know that the APCS_FLOAT flags match; similarly for VFP
20843 flags. */
20846 {
20848 _bfd_error_handler
20851 else
20852 _bfd_error_handler
20857 }
20858 }
20859 #endif
20861 /* Interworking mismatch is only a warning. */
20863 {
20865 {
20866 _bfd_error_handler
20869 }
20870 else
20871 {
20872 _bfd_error_handler
20875 }
20876 }
20877 }
20880 }