1 /* BFD support for handling relocation entries.
2 Copyright (C) 1990-2024 Free Software Foundation, Inc.
3 Written by Cygnus Support.
5 This file is part of BFD, the Binary File Descriptor library.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
26 BFD maintains relocations in much the same way it maintains
27 symbols: they are left alone until required, then read in
28 en-masse and translated into an internal form. A common
29 routine <<bfd_perform_relocation>> acts upon the
30 canonical form to do the fixup.
32 Relocations are maintained on a per section basis,
33 while symbols are maintained on a per BFD basis.
35 All that a back end has to do to fit the BFD interface is to create
36 a <<struct reloc_cache_entry>> for each relocation
37 in a particular section, and fill in the right bits of the structures.
46 /* DO compile in the reloc_code name table from libbfd.h. */
47 #define _BFD_MAKE_TABLE_bfd_reloc_code_real
58 typedef arelent, howto manager, Relocations, Relocations
63 This is the structure of a relocation entry:
66 .typedef enum bfd_reloc_status
68 . {* No errors detected. Note - the value 2 is used so that it
69 . will not be mistaken for the boolean TRUE or FALSE values. *}
72 . {* The relocation was performed, but there was an overflow. *}
75 . {* The address to relocate was not within the section supplied. *}
76 . bfd_reloc_outofrange,
78 . {* Used by special functions. *}
81 . {* Unsupported relocation size requested. *}
82 . bfd_reloc_notsupported,
84 . {* Target specific meaning. *}
87 . {* The symbol to relocate against was undefined. *}
88 . bfd_reloc_undefined,
90 . {* The relocation was performed, but may not be ok. If this type is
91 . returned, the error_message argument to bfd_perform_relocation
95 . bfd_reloc_status_type;
97 .typedef const struct reloc_howto_struct reloc_howto_type;
101 .struct reloc_cache_entry
103 . {* A pointer into the canonical table of pointers. *}
104 . struct bfd_symbol **sym_ptr_ptr;
106 . {* offset in section. *}
107 . bfd_size_type address;
109 . {* addend for relocation value. *}
112 . {* Pointer to how to perform the required relocation. *}
113 . reloc_howto_type *howto;
122 Here is a description of each of the fields within an <<arelent>>:
126 The symbol table pointer points to a pointer to the symbol
127 associated with the relocation request. It is the pointer
128 into the table returned by the back end's
129 <<canonicalize_symtab>> action. @xref{Symbols}. The symbol is
130 referenced through a pointer to a pointer so that tools like
131 the linker can fix up all the symbols of the same name by
132 modifying only one pointer. The relocation routine looks in
133 the symbol and uses the base of the section the symbol is
134 attached to and the value of the symbol as the initial
135 relocation offset. If the symbol pointer is zero, then the
136 section provided is looked up.
140 The <<address>> field gives the offset in bytes from the base of
141 the section data which owns the relocation record to the first
142 byte of relocatable information. The actual data relocated
143 will be relative to this point; for example, a relocation
144 type which modifies the bottom two bytes of a four byte word
145 would not touch the first byte pointed to in a big endian
150 The <<addend>> is a value provided by the back end to be added (!)
151 to the relocation offset. Its interpretation is dependent upon
152 the howto. For example, on the 68k the code:
157 | return foo[0x12345678];
160 Could be compiled into:
163 | moveb @@#12345678,d0
168 This could create a reloc pointing to <<foo>>, but leave the
169 offset in the data, something like:
171 |RELOCATION RECORDS FOR [.text]:
175 |00000000 4e56 fffc ; linkw fp,#-4
176 |00000004 1039 1234 5678 ; moveb @@#12345678,d0
177 |0000000a 49c0 ; extbl d0
178 |0000000c 4e5e ; unlk fp
181 Using coff and an 88k, some instructions don't have enough
182 space in them to represent the full address range, and
183 pointers have to be loaded in two parts. So you'd get something like:
185 | or.u r13,r0,hi16(_foo+0x12345678)
186 | ld.b r2,r13,lo16(_foo+0x12345678)
189 This should create two relocs, both pointing to <<_foo>>, and with
190 0x12340000 in their addend field. The data would consist of:
192 |RELOCATION RECORDS FOR [.text]:
194 |00000002 HVRT16 _foo+0x12340000
195 |00000006 LVRT16 _foo+0x12340000
197 |00000000 5da05678 ; or.u r13,r0,0x5678
198 |00000004 1c4d5678 ; ld.b r2,r13,0x5678
199 |00000008 f400c001 ; jmp r1
201 The relocation routine digs out the value from the data, adds
202 it to the addend to get the original offset, and then adds the
203 value of <<_foo>>. Note that all 32 bits have to be kept around
204 somewhere, to cope with carry from bit 15 to bit 16.
206 One further example is the sparc and the a.out format. The
207 sparc has a similar problem to the 88k, in that some
208 instructions don't have room for an entire offset, but on the
209 sparc the parts are created in odd sized lumps. The designers of
210 the a.out format chose to not use the data within the section
211 for storing part of the offset; all the offset is kept within
212 the reloc. Anything in the data should be ignored.
215 | sethi %hi(_foo+0x12345678),%g2
216 | ldsb [%g2+%lo(_foo+0x12345678)],%i0
220 Both relocs contain a pointer to <<foo>>, and the offsets
223 |RELOCATION RECORDS FOR [.text]:
225 |00000004 HI22 _foo+0x12345678
226 |00000008 LO10 _foo+0x12345678
228 |00000000 9de3bf90 ; save %sp,-112,%sp
229 |00000004 05000000 ; sethi %hi(_foo+0),%g2
230 |00000008 f048a000 ; ldsb [%g2+%lo(_foo+0)],%i0
231 |0000000c 81c7e008 ; ret
232 |00000010 81e80000 ; restore
236 The <<howto>> field can be imagined as a
237 relocation instruction. It is a pointer to a structure which
238 contains information on what to do with all of the other
239 information in the reloc record and data section. A back end
240 would normally have a relocation instruction set and turn
241 relocations into pointers to the correct structure on input -
242 but it would be possible to create each howto field on demand.
248 <<enum complain_overflow>>
250 Indicates what sort of overflow checking should be done when
251 performing a relocation.
254 .enum complain_overflow
256 . {* Do not complain on overflow. *}
257 . complain_overflow_dont,
259 . {* Complain if the value overflows when considered as a signed
260 . number one bit larger than the field. ie. A bitfield of N bits
261 . is allowed to represent -2**n to 2**n-1. *}
262 . complain_overflow_bitfield,
264 . {* Complain if the value overflows when considered as a signed
266 . complain_overflow_signed,
268 . {* Complain if the value overflows when considered as an
269 . unsigned number. *}
270 . complain_overflow_unsigned
279 The <<reloc_howto_type>> is a structure which contains all the
280 information that libbfd needs to know to tie up a back end's data.
283 .struct reloc_howto_struct
285 . {* The type field has mainly a documentary use - the back end can
286 . do what it wants with it, though normally the back end's idea of
287 . an external reloc number is stored in this field. *}
290 . {* The size of the item to be relocated in bytes. *}
291 . unsigned int size:4;
293 . {* The number of bits in the field to be relocated. This is used
294 . when doing overflow checking. *}
295 . unsigned int bitsize:7;
297 . {* The value the final relocation is shifted right by. This drops
298 . unwanted data from the relocation. *}
299 . unsigned int rightshift:6;
301 . {* The bit position of the reloc value in the destination.
302 . The relocated value is left shifted by this amount. *}
303 . unsigned int bitpos:6;
305 . {* What type of overflow error should be checked for when
307 . ENUM_BITFIELD (complain_overflow) complain_on_overflow:2;
309 . {* The relocation value should be negated before applying. *}
310 . unsigned int negate:1;
312 . {* The relocation is relative to the item being relocated. *}
313 . unsigned int pc_relative:1;
315 . {* Some formats record a relocation addend in the section contents
316 . rather than with the relocation. For ELF formats this is the
317 . distinction between USE_REL and USE_RELA (though the code checks
318 . for USE_REL == 1/0). The value of this field is TRUE if the
319 . addend is recorded with the section contents; when performing a
320 . partial link (ld -r) the section contents (the data) will be
321 . modified. The value of this field is FALSE if addends are
322 . recorded with the relocation (in arelent.addend); when performing
323 . a partial link the relocation will be modified.
324 . All relocations for all ELF USE_RELA targets should set this field
325 . to FALSE (values of TRUE should be looked on with suspicion).
326 . However, the converse is not true: not all relocations of all ELF
327 . USE_REL targets set this field to TRUE. Why this is so is peculiar
328 . to each particular target. For relocs that aren't used in partial
329 . links (e.g. GOT stuff) it doesn't matter what this is set to. *}
330 . unsigned int partial_inplace:1;
332 . {* When some formats create PC relative instructions, they leave
333 . the value of the pc of the place being relocated in the offset
334 . slot of the instruction, so that a PC relative relocation can
335 . be made just by adding in an ordinary offset (e.g., sun3 a.out).
336 . Some formats leave the displacement part of an instruction
337 . empty (e.g., ELF); this flag signals the fact. *}
338 . unsigned int pcrel_offset:1;
340 . {* Whether bfd_install_relocation should just install the addend,
341 . or should follow the practice of some older object formats and
342 . install a value including the symbol. *}
343 . unsigned int install_addend:1;
345 . {* src_mask selects the part of the instruction (or data) to be used
346 . in the relocation sum. If the target relocations don't have an
347 . addend in the reloc, eg. ELF USE_REL, src_mask will normally equal
348 . dst_mask to extract the addend from the section contents. If
349 . relocations do have an addend in the reloc, eg. ELF USE_RELA, this
350 . field should normally be zero. Non-zero values for ELF USE_RELA
351 . targets should be viewed with suspicion as normally the value in
352 . the dst_mask part of the section contents should be ignored. *}
355 . {* dst_mask selects which parts of the instruction (or data) are
356 . replaced with a relocated value. *}
359 . {* If this field is non null, then the supplied function is
360 . called rather than the normal function. This allows really
361 . strange relocation methods to be accommodated. *}
362 . bfd_reloc_status_type (*special_function)
363 . (bfd *, arelent *, struct bfd_symbol *, void *, asection *,
366 . {* The textual name of the relocation type. *}
377 The HOWTO macro fills in a reloc_howto_type (a typedef for
378 const struct reloc_howto_struct).
380 .#define HOWTO_INSTALL_ADDEND 0
381 .#define HOWTO_RSIZE(sz) ((sz) < 0 ? -(sz) : (sz))
382 .#define HOWTO(type, right, size, bits, pcrel, left, ovf, func, name, \
383 . inplace, src_mask, dst_mask, pcrel_off) \
384 . { (unsigned) type, HOWTO_RSIZE (size), bits, right, left, ovf, \
385 . size < 0, pcrel, inplace, pcrel_off, HOWTO_INSTALL_ADDEND, \
386 . src_mask, dst_mask, func, name }
389 This is used to fill in an empty howto entry in an array.
391 .#define EMPTY_HOWTO(C) \
392 . HOWTO ((C), 0, 1, 0, false, 0, complain_overflow_dont, NULL, \
393 . NULL, false, 0, 0, false)
395 .static inline unsigned int
396 .bfd_get_reloc_size (reloc_howto_type *howto)
398 . return howto->size;
408 How relocs are tied together in an <<asection>>:
410 .typedef struct relent_chain
413 . struct relent_chain *next;
419 /* N_ONES produces N one bits, without undefined behaviour for N
420 between zero and the number of bits in a bfd_vma. */
421 #define N_ONES(n) ((n) == 0 ? 0 : ((bfd_vma) 1 << ((n) - 1) << 1) - 1)
428 bfd_reloc_status_type bfd_check_overflow
429 (enum complain_overflow how,
430 unsigned int bitsize,
431 unsigned int rightshift,
432 unsigned int addrsize,
436 Perform overflow checking on @var{relocation} which has
437 @var{bitsize} significant bits and will be shifted right by
438 @var{rightshift} bits, on a machine with addresses containing
439 @var{addrsize} significant bits. The result is either of
440 @code{bfd_reloc_ok} or @code{bfd_reloc_overflow}.
444 bfd_reloc_status_type
445 bfd_check_overflow (enum complain_overflow how
,
446 unsigned int bitsize
,
447 unsigned int rightshift
,
448 unsigned int addrsize
,
451 bfd_vma fieldmask
, addrmask
, signmask
, ss
, a
;
452 bfd_reloc_status_type flag
= bfd_reloc_ok
;
457 /* Note: BITSIZE should always be <= ADDRSIZE, but in case it's not,
458 we'll be permissive: extra bits in the field mask will
459 automatically extend the address mask for purposes of the
461 fieldmask
= N_ONES (bitsize
);
462 signmask
= ~fieldmask
;
463 addrmask
= N_ONES (addrsize
) | (fieldmask
<< rightshift
);
464 a
= (relocation
& addrmask
) >> rightshift
;
468 case complain_overflow_dont
:
471 case complain_overflow_signed
:
472 /* If any sign bits are set, all sign bits must be set. That
473 is, A must be a valid negative address after shifting. */
474 signmask
= ~ (fieldmask
>> 1);
477 case complain_overflow_bitfield
:
478 /* Bitfields are sometimes signed, sometimes unsigned. We
479 explicitly allow an address wrap too, which means a bitfield
480 of n bits is allowed to store -2**n to 2**n-1. Thus overflow
481 if the value has some, but not all, bits set outside the
484 if (ss
!= 0 && ss
!= ((addrmask
>> rightshift
) & signmask
))
485 flag
= bfd_reloc_overflow
;
488 case complain_overflow_unsigned
:
489 /* We have an overflow if the address does not fit in the field. */
490 if ((a
& signmask
) != 0)
491 flag
= bfd_reloc_overflow
;
503 bfd_reloc_offset_in_range
506 bool bfd_reloc_offset_in_range
507 (reloc_howto_type *howto,
510 bfd_size_type offset);
513 Returns TRUE if the reloc described by @var{HOWTO} can be
514 applied at @var{OFFSET} octets in @var{SECTION}.
518 /* HOWTO describes a relocation, at offset OCTET. Return whether the
519 relocation field is within SECTION of ABFD. */
522 bfd_reloc_offset_in_range (reloc_howto_type
*howto
,
527 bfd_size_type octet_end
= bfd_get_section_limit_octets (abfd
, section
);
528 bfd_size_type reloc_size
= bfd_get_reloc_size (howto
);
530 /* The reloc field must be contained entirely within the section.
531 Allow zero length fields (marker relocs or NONE relocs where no
532 relocation will be performed) at the end of the section. */
533 return octet
<= octet_end
&& reloc_size
<= octet_end
- octet
;
536 /* Read and return the section contents at DATA converted to a host
537 integer (bfd_vma). The number of bytes read is given by the HOWTO. */
540 read_reloc (bfd
*abfd
, bfd_byte
*data
, reloc_howto_type
*howto
)
542 switch (bfd_get_reloc_size (howto
))
548 return bfd_get_8 (abfd
, data
);
551 return bfd_get_16 (abfd
, data
);
554 return bfd_get_24 (abfd
, data
);
557 return bfd_get_32 (abfd
, data
);
561 return bfd_get_64 (abfd
, data
);
570 /* Convert VAL to target format and write to DATA. The number of
571 bytes written is given by the HOWTO. */
574 write_reloc (bfd
*abfd
, bfd_vma val
, bfd_byte
*data
, reloc_howto_type
*howto
)
576 switch (bfd_get_reloc_size (howto
))
582 bfd_put_8 (abfd
, val
, data
);
586 bfd_put_16 (abfd
, val
, data
);
590 bfd_put_24 (abfd
, val
, data
);
594 bfd_put_32 (abfd
, val
, data
);
599 bfd_put_64 (abfd
, val
, data
);
608 /* Apply RELOCATION value to target bytes at DATA, according to
612 apply_reloc (bfd
*abfd
, bfd_byte
*data
, reloc_howto_type
*howto
,
615 bfd_vma val
= read_reloc (abfd
, data
, howto
);
618 relocation
= -relocation
;
620 val
= ((val
& ~howto
->dst_mask
)
621 | (((val
& howto
->src_mask
) + relocation
) & howto
->dst_mask
));
623 write_reloc (abfd
, val
, data
, howto
);
628 bfd_perform_relocation
631 bfd_reloc_status_type bfd_perform_relocation
633 arelent *reloc_entry,
635 asection *input_section,
637 char **error_message);
640 If @var{output_bfd} is supplied to this function, the
641 generated image will be relocatable; the relocations are
642 copied to the output file after they have been changed to
643 reflect the new state of the world. There are two ways of
644 reflecting the results of partial linkage in an output file:
645 by modifying the output data in place, and by modifying the
646 relocation record. Some native formats (e.g., basic a.out and
647 basic coff) have no way of specifying an addend in the
648 relocation type, so the addend has to go in the output data.
649 This is no big deal since in these formats the output data
650 slot will always be big enough for the addend. Complex reloc
651 types with addends were invented to solve just this problem.
652 The @var{error_message} argument is set to an error message if
653 this return @code{bfd_reloc_dangerous}.
657 bfd_reloc_status_type
658 bfd_perform_relocation (bfd
*abfd
,
659 arelent
*reloc_entry
,
661 asection
*input_section
,
663 char **error_message
)
666 bfd_reloc_status_type flag
= bfd_reloc_ok
;
667 bfd_size_type octets
;
668 bfd_vma output_base
= 0;
669 reloc_howto_type
*howto
= reloc_entry
->howto
;
670 asection
*reloc_target_output_section
;
673 symbol
= *(reloc_entry
->sym_ptr_ptr
);
675 /* If we are not producing relocatable output, return an error if
676 the symbol is not defined. An undefined weak symbol is
677 considered to have a value of zero (SVR4 ABI, p. 4-27). */
678 if (bfd_is_und_section (symbol
->section
)
679 && (symbol
->flags
& BSF_WEAK
) == 0
680 && output_bfd
== NULL
)
681 flag
= bfd_reloc_undefined
;
683 /* If there is a function supplied to handle this relocation type,
684 call it. It'll return `bfd_reloc_continue' if further processing
686 if (howto
&& howto
->special_function
)
688 bfd_reloc_status_type cont
;
690 /* Note - we do not call bfd_reloc_offset_in_range here as the
691 reloc_entry->address field might actually be valid for the
692 backend concerned. It is up to the special_function itself
693 to call bfd_reloc_offset_in_range if needed. */
694 cont
= howto
->special_function (abfd
, reloc_entry
, symbol
, data
,
695 input_section
, output_bfd
,
697 if (cont
!= bfd_reloc_continue
)
701 if (bfd_is_abs_section (symbol
->section
)
702 && output_bfd
!= NULL
)
704 reloc_entry
->address
+= input_section
->output_offset
;
708 /* PR 17512: file: 0f67f69d. */
710 return bfd_reloc_undefined
;
712 /* Is the address of the relocation really within the section? */
713 octets
= reloc_entry
->address
* bfd_octets_per_byte (abfd
, input_section
);
714 if (!bfd_reloc_offset_in_range (howto
, abfd
, input_section
, octets
))
715 return bfd_reloc_outofrange
;
717 /* Work out which section the relocation is targeted at and the
718 initial relocation command value. */
720 /* Get symbol value. (Common symbols are special.) */
721 if (bfd_is_com_section (symbol
->section
))
724 relocation
= symbol
->value
;
726 reloc_target_output_section
= symbol
->section
->output_section
;
728 /* Convert input-section-relative symbol value to absolute. */
729 if ((output_bfd
&& ! howto
->partial_inplace
)
730 || reloc_target_output_section
== NULL
)
733 output_base
= reloc_target_output_section
->vma
;
735 output_base
+= symbol
->section
->output_offset
;
737 /* If symbol addresses are in octets, convert to bytes. */
738 if (bfd_get_flavour (abfd
) == bfd_target_elf_flavour
739 && (symbol
->section
->flags
& SEC_ELF_OCTETS
))
740 output_base
*= bfd_octets_per_byte (abfd
, input_section
);
742 relocation
+= output_base
;
744 /* Add in supplied addend. */
745 relocation
+= reloc_entry
->addend
;
747 /* Here the variable relocation holds the final address of the
748 symbol we are relocating against, plus any addend. */
750 if (howto
->pc_relative
)
752 /* This is a PC relative relocation. We want to set RELOCATION
753 to the distance between the address of the symbol and the
754 location. RELOCATION is already the address of the symbol.
756 We start by subtracting the address of the section containing
759 If pcrel_offset is set, we must further subtract the position
760 of the location within the section. Some targets arrange for
761 the addend to be the negative of the position of the location
762 within the section; for example, i386-aout does this. For
763 i386-aout, pcrel_offset is FALSE. Some other targets do not
764 include the position of the location; for example, ELF.
765 For those targets, pcrel_offset is TRUE.
767 If we are producing relocatable output, then we must ensure
768 that this reloc will be correctly computed when the final
769 relocation is done. If pcrel_offset is FALSE we want to wind
770 up with the negative of the location within the section,
771 which means we must adjust the existing addend by the change
772 in the location within the section. If pcrel_offset is TRUE
773 we do not want to adjust the existing addend at all.
775 FIXME: This seems logical to me, but for the case of
776 producing relocatable output it is not what the code
777 actually does. I don't want to change it, because it seems
778 far too likely that something will break. */
781 input_section
->output_section
->vma
+ input_section
->output_offset
;
783 if (howto
->pcrel_offset
)
784 relocation
-= reloc_entry
->address
;
787 if (output_bfd
!= NULL
)
789 if (! howto
->partial_inplace
)
791 /* This is a partial relocation, and we want to apply the relocation
792 to the reloc entry rather than the raw data. Modify the reloc
793 inplace to reflect what we now know. */
794 reloc_entry
->addend
= relocation
;
795 reloc_entry
->address
+= input_section
->output_offset
;
800 /* This is a partial relocation, but inplace, so modify the
803 If we've relocated with a symbol with a section, change
804 into a ref to the section belonging to the symbol. */
806 reloc_entry
->address
+= input_section
->output_offset
;
809 if (abfd
->xvec
->flavour
== bfd_target_coff_flavour
)
811 /* For m68k-coff, the addend was being subtracted twice during
812 relocation with -r. Removing the line below this comment
813 fixes that problem; see PR 2953.
815 However, Ian wrote the following, regarding removing the line below,
816 which explains why it is still enabled: --djm
818 If you put a patch like that into BFD you need to check all the COFF
819 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
820 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
821 problem in a different way. There may very well be a reason that the
822 code works as it does.
824 Hmmm. The first obvious point is that bfd_perform_relocation should
825 not have any tests that depend upon the flavour. It's seem like
826 entirely the wrong place for such a thing. The second obvious point
827 is that the current code ignores the reloc addend when producing
828 relocatable output for COFF. That's peculiar. In fact, I really
829 have no idea what the point of the line you want to remove is.
831 A typical COFF reloc subtracts the old value of the symbol and adds in
832 the new value to the location in the object file (if it's a pc
833 relative reloc it adds the difference between the symbol value and the
834 location). When relocating we need to preserve that property.
836 BFD handles this by setting the addend to the negative of the old
837 value of the symbol. Unfortunately it handles common symbols in a
838 non-standard way (it doesn't subtract the old value) but that's a
839 different story (we can't change it without losing backward
840 compatibility with old object files) (coff-i386 does subtract the old
841 value, to be compatible with existing coff-i386 targets, like SCO).
843 So everything works fine when not producing relocatable output. When
844 we are producing relocatable output, logically we should do exactly
845 what we do when not producing relocatable output. Therefore, your
846 patch is correct. In fact, it should probably always just set
847 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
848 add the value into the object file. This won't hurt the COFF code,
849 which doesn't use the addend; I'm not sure what it will do to other
850 formats (the thing to check for would be whether any formats both use
851 the addend and set partial_inplace).
853 When I wanted to make coff-i386 produce relocatable output, I ran
854 into the problem that you are running into: I wanted to remove that
855 line. Rather than risk it, I made the coff-i386 relocs use a special
856 function; it's coff_i386_reloc in coff-i386.c. The function
857 specifically adds the addend field into the object file, knowing that
858 bfd_perform_relocation is not going to. If you remove that line, then
859 coff-i386.c will wind up adding the addend field in twice. It's
860 trivial to fix; it just needs to be done.
862 The problem with removing the line is just that it may break some
863 working code. With BFD it's hard to be sure of anything. The right
864 way to deal with this is simply to build and test at least all the
865 supported COFF targets. It should be straightforward if time and disk
866 space consuming. For each target:
868 2) generate some executable, and link it using -r (I would
869 probably use paranoia.o and link against newlib/libc.a, which
870 for all the supported targets would be available in
871 /usr/cygnus/progressive/H-host/target/lib/libc.a).
872 3) make the change to reloc.c
873 4) rebuild the linker
875 6) if the resulting object files are the same, you have at least
877 7) if they are different you have to figure out which version is
880 relocation
-= reloc_entry
->addend
;
881 reloc_entry
->addend
= 0;
885 reloc_entry
->addend
= relocation
;
890 /* FIXME: This overflow checking is incomplete, because the value
891 might have overflowed before we get here. For a correct check we
892 need to compute the value in a size larger than bitsize, but we
893 can't reasonably do that for a reloc the same size as a host
895 FIXME: We should also do overflow checking on the result after
896 adding in the value contained in the object file. */
897 if (howto
->complain_on_overflow
!= complain_overflow_dont
898 && flag
== bfd_reloc_ok
)
899 flag
= bfd_check_overflow (howto
->complain_on_overflow
,
902 bfd_arch_bits_per_address (abfd
),
905 /* Either we are relocating all the way, or we don't want to apply
906 the relocation to the reloc entry (probably because there isn't
907 any room in the output format to describe addends to relocs). */
909 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
910 (OSF version 1.3, compiler version 3.11). It miscompiles the
924 x <<= (unsigned long) s.i0;
928 printf ("succeeded (%lx)\n", x);
932 relocation
>>= (bfd_vma
) howto
->rightshift
;
934 /* Shift everything up to where it's going to be used. */
935 relocation
<<= (bfd_vma
) howto
->bitpos
;
937 /* Wait for the day when all have the mask in them. */
940 i instruction to be left alone
941 o offset within instruction
942 r relocation offset to apply
951 (( i i i i i o o o o o from bfd_get<size>
952 and S S S S S) to get the size offset we want
953 + r r r r r r r r r r) to get the final value to place
954 and D D D D D to chop to right size
955 -----------------------
958 ( i i i i i o o o o o from bfd_get<size>
959 and N N N N N ) get instruction
960 -----------------------
966 -----------------------
967 = R R R R R R R R R R put into bfd_put<size>
970 data
= (bfd_byte
*) data
+ octets
;
971 apply_reloc (abfd
, data
, howto
, relocation
);
977 bfd_install_relocation
980 bfd_reloc_status_type bfd_install_relocation
982 arelent *reloc_entry,
983 void *data, bfd_vma data_start,
984 asection *input_section,
985 char **error_message);
988 This looks remarkably like <<bfd_perform_relocation>>, except it
989 does not expect that the section contents have been filled in.
990 I.e., it's suitable for use when creating, rather than applying
993 For now, this function should be considered reserved for the
997 bfd_reloc_status_type
998 bfd_install_relocation (bfd
*abfd
,
999 arelent
*reloc_entry
,
1001 bfd_vma data_start_offset
,
1002 asection
*input_section
,
1003 char **error_message
)
1006 bfd_reloc_status_type flag
= bfd_reloc_ok
;
1007 bfd_size_type octets
;
1008 bfd_vma output_base
= 0;
1009 reloc_howto_type
*howto
= reloc_entry
->howto
;
1010 asection
*reloc_target_output_section
;
1014 symbol
= *(reloc_entry
->sym_ptr_ptr
);
1016 /* If there is a function supplied to handle this relocation type,
1017 call it. It'll return `bfd_reloc_continue' if further processing
1019 if (howto
&& howto
->special_function
)
1021 bfd_reloc_status_type cont
;
1023 /* Note - we do not call bfd_reloc_offset_in_range here as the
1024 reloc_entry->address field might actually be valid for the
1025 backend concerned. It is up to the special_function itself
1026 to call bfd_reloc_offset_in_range if needed. */
1027 cont
= howto
->special_function (abfd
, reloc_entry
, symbol
,
1028 /* XXX - Non-portable! */
1029 ((bfd_byte
*) data_start
1030 - data_start_offset
),
1031 input_section
, abfd
, error_message
);
1032 if (cont
!= bfd_reloc_continue
)
1036 if (howto
->install_addend
)
1037 relocation
= reloc_entry
->addend
;
1040 if (bfd_is_abs_section (symbol
->section
))
1041 return bfd_reloc_ok
;
1043 /* Work out which section the relocation is targeted at and the
1044 initial relocation command value. */
1046 /* Get symbol value. (Common symbols are special.) */
1047 if (bfd_is_com_section (symbol
->section
))
1050 relocation
= symbol
->value
;
1052 reloc_target_output_section
= symbol
->section
;
1054 /* Convert input-section-relative symbol value to absolute. */
1055 if (! howto
->partial_inplace
)
1058 output_base
= reloc_target_output_section
->vma
;
1060 /* If symbol addresses are in octets, convert to bytes. */
1061 if (bfd_get_flavour (abfd
) == bfd_target_elf_flavour
1062 && (symbol
->section
->flags
& SEC_ELF_OCTETS
))
1063 output_base
*= bfd_octets_per_byte (abfd
, input_section
);
1065 relocation
+= output_base
;
1067 /* Add in supplied addend. */
1068 relocation
+= reloc_entry
->addend
;
1070 /* Here the variable relocation holds the final address of the
1071 symbol we are relocating against, plus any addend. */
1073 if (howto
->pc_relative
)
1075 relocation
-= input_section
->vma
;
1077 if (howto
->pcrel_offset
&& howto
->partial_inplace
)
1078 relocation
-= reloc_entry
->address
;
1082 if (!howto
->partial_inplace
)
1084 reloc_entry
->addend
= relocation
;
1088 if (!howto
->install_addend
1089 && abfd
->xvec
->flavour
== bfd_target_coff_flavour
)
1091 /* This is just weird. We're subtracting out the original
1092 addend, so that for COFF the addend is ignored??? */
1093 relocation
-= reloc_entry
->addend
;
1094 /* FIXME: There should be no target specific code here... */
1095 if (strcmp (abfd
->xvec
->name
, "coff-z8k") != 0)
1096 reloc_entry
->addend
= 0;
1099 reloc_entry
->addend
= relocation
;
1101 /* Is the address of the relocation really within the section? */
1102 octets
= reloc_entry
->address
* bfd_octets_per_byte (abfd
, input_section
);
1103 if (!bfd_reloc_offset_in_range (howto
, abfd
, input_section
, octets
))
1104 return bfd_reloc_outofrange
;
1106 /* FIXME: This overflow checking is incomplete, because the value
1107 might have overflowed before we get here. For a correct check we
1108 need to compute the value in a size larger than bitsize, but we
1109 can't reasonably do that for a reloc the same size as a host
1111 if (howto
->complain_on_overflow
!= complain_overflow_dont
)
1112 flag
= bfd_check_overflow (howto
->complain_on_overflow
,
1115 bfd_arch_bits_per_address (abfd
),
1118 relocation
>>= (bfd_vma
) howto
->rightshift
;
1120 /* Shift everything up to where it's going to be used. */
1121 relocation
<<= (bfd_vma
) howto
->bitpos
;
1123 data
= (bfd_byte
*) data_start
+ (octets
- data_start_offset
);
1124 apply_reloc (abfd
, data
, howto
, relocation
);
1128 /* This relocation routine is used by some of the backend linkers.
1129 They do not construct asymbol or arelent structures, so there is no
1130 reason for them to use bfd_perform_relocation. Also,
1131 bfd_perform_relocation is so hacked up it is easier to write a new
1132 function than to try to deal with it.
1134 This routine does a final relocation. Whether it is useful for a
1135 relocatable link depends upon how the object format defines
1138 FIXME: This routine ignores any special_function in the HOWTO,
1139 since the existing special_function values have been written for
1140 bfd_perform_relocation.
1142 HOWTO is the reloc howto information.
1143 INPUT_BFD is the BFD which the reloc applies to.
1144 INPUT_SECTION is the section which the reloc applies to.
1145 CONTENTS is the contents of the section.
1146 ADDRESS is the address of the reloc within INPUT_SECTION.
1147 VALUE is the value of the symbol the reloc refers to.
1148 ADDEND is the addend of the reloc. */
1150 bfd_reloc_status_type
1151 _bfd_final_link_relocate (reloc_howto_type
*howto
,
1153 asection
*input_section
,
1160 bfd_size_type octets
= (address
1161 * bfd_octets_per_byte (input_bfd
, input_section
));
1163 /* Sanity check the address. */
1164 if (!bfd_reloc_offset_in_range (howto
, input_bfd
, input_section
, octets
))
1165 return bfd_reloc_outofrange
;
1167 /* This function assumes that we are dealing with a basic relocation
1168 against a symbol. We want to compute the value of the symbol to
1169 relocate to. This is just VALUE, the value of the symbol, plus
1170 ADDEND, any addend associated with the reloc. */
1171 relocation
= value
+ addend
;
1173 /* If the relocation is PC relative, we want to set RELOCATION to
1174 the distance between the symbol (currently in RELOCATION) and the
1175 location we are relocating. Some targets (e.g., i386-aout)
1176 arrange for the contents of the section to be the negative of the
1177 offset of the location within the section; for such targets
1178 pcrel_offset is FALSE. Other targets (e.g., ELF) simply leave
1179 the contents of the section as zero; for such targets
1180 pcrel_offset is TRUE. If pcrel_offset is FALSE we do not need to
1181 subtract out the offset of the location within the section (which
1182 is just ADDRESS). */
1183 if (howto
->pc_relative
)
1185 relocation
-= (input_section
->output_section
->vma
1186 + input_section
->output_offset
);
1187 if (howto
->pcrel_offset
)
1188 relocation
-= address
;
1191 return _bfd_relocate_contents (howto
, input_bfd
, relocation
,
1195 /* Relocate a given location using a given value and howto. */
1197 bfd_reloc_status_type
1198 _bfd_relocate_contents (reloc_howto_type
*howto
,
1204 bfd_reloc_status_type flag
;
1205 unsigned int rightshift
= howto
->rightshift
;
1206 unsigned int bitpos
= howto
->bitpos
;
1209 relocation
= -relocation
;
1211 /* Get the value we are going to relocate. */
1212 x
= read_reloc (input_bfd
, location
, howto
);
1214 /* Check for overflow. FIXME: We may drop bits during the addition
1215 which we don't check for. We must either check at every single
1216 operation, which would be tedious, or we must do the computations
1217 in a type larger than bfd_vma, which would be inefficient. */
1218 flag
= bfd_reloc_ok
;
1219 if (howto
->complain_on_overflow
!= complain_overflow_dont
)
1221 bfd_vma addrmask
, fieldmask
, signmask
, ss
;
1224 /* Get the values to be added together. For signed and unsigned
1225 relocations, we assume that all values should be truncated to
1226 the size of an address. For bitfields, all the bits matter.
1227 See also bfd_check_overflow. */
1228 fieldmask
= N_ONES (howto
->bitsize
);
1229 signmask
= ~fieldmask
;
1230 addrmask
= (N_ONES (bfd_arch_bits_per_address (input_bfd
))
1231 | (fieldmask
<< rightshift
));
1232 a
= (relocation
& addrmask
) >> rightshift
;
1233 b
= (x
& howto
->src_mask
& addrmask
) >> bitpos
;
1234 addrmask
>>= rightshift
;
1236 switch (howto
->complain_on_overflow
)
1238 case complain_overflow_signed
:
1239 /* If any sign bits are set, all sign bits must be set.
1240 That is, A must be a valid negative address after
1242 signmask
= ~(fieldmask
>> 1);
1245 case complain_overflow_bitfield
:
1246 /* Much like the signed check, but for a field one bit
1247 wider. We allow a bitfield to represent numbers in the
1248 range -2**n to 2**n-1, where n is the number of bits in the
1249 field. Note that when bfd_vma is 32 bits, a 32-bit reloc
1250 can't overflow, which is exactly what we want. */
1252 if (ss
!= 0 && ss
!= (addrmask
& signmask
))
1253 flag
= bfd_reloc_overflow
;
1255 /* We only need this next bit of code if the sign bit of B
1256 is below the sign bit of A. This would only happen if
1257 SRC_MASK had fewer bits than BITSIZE. Note that if
1258 SRC_MASK has more bits than BITSIZE, we can get into
1259 trouble; we would need to verify that B is in range, as
1260 we do for A above. */
1261 ss
= ((~howto
->src_mask
) >> 1) & howto
->src_mask
;
1264 /* Set all the bits above the sign bit. */
1267 /* Now we can do the addition. */
1270 /* See if the result has the correct sign. Bits above the
1271 sign bit are junk now; ignore them. If the sum is
1272 positive, make sure we did not have all negative inputs;
1273 if the sum is negative, make sure we did not have all
1274 positive inputs. The test below looks only at the sign
1275 bits, and it really just
1276 SIGN (A) == SIGN (B) && SIGN (A) != SIGN (SUM)
1278 We mask with addrmask here to explicitly allow an address
1279 wrap-around. The Linux kernel relies on it, and it is
1280 the only way to write assembler code which can run when
1281 loaded at a location 0x80000000 away from the location at
1282 which it is linked. */
1283 if (((~(a
^ b
)) & (a
^ sum
)) & signmask
& addrmask
)
1284 flag
= bfd_reloc_overflow
;
1287 case complain_overflow_unsigned
:
1288 /* Checking for an unsigned overflow is relatively easy:
1289 trim the addresses and add, and trim the result as well.
1290 Overflow is normally indicated when the result does not
1291 fit in the field. However, we also need to consider the
1292 case when, e.g., fieldmask is 0x7fffffff or smaller, an
1293 input is 0x80000000, and bfd_vma is only 32 bits; then we
1294 will get sum == 0, but there is an overflow, since the
1295 inputs did not fit in the field. Instead of doing a
1296 separate test, we can check for this by or-ing in the
1297 operands when testing for the sum overflowing its final
1299 sum
= (a
+ b
) & addrmask
;
1300 if ((a
| b
| sum
) & signmask
)
1301 flag
= bfd_reloc_overflow
;
1309 /* Put RELOCATION in the right bits. */
1310 relocation
>>= (bfd_vma
) rightshift
;
1311 relocation
<<= (bfd_vma
) bitpos
;
1313 /* Add RELOCATION to the right bits of X. */
1314 x
= ((x
& ~howto
->dst_mask
)
1315 | (((x
& howto
->src_mask
) + relocation
) & howto
->dst_mask
));
1317 /* Put the relocated value back in the object file. */
1318 write_reloc (input_bfd
, x
, location
, howto
);
1322 /* Clear a given location using a given howto, by applying a fixed relocation
1323 value and discarding any in-place addend. This is used for fixed-up
1324 relocations against discarded symbols, to make ignorable debug or unwind
1325 information more obvious. */
1327 bfd_reloc_status_type
1328 _bfd_clear_contents (reloc_howto_type
*howto
,
1330 asection
*input_section
,
1337 if (!bfd_reloc_offset_in_range (howto
, input_bfd
, input_section
, off
))
1338 return bfd_reloc_outofrange
;
1340 /* Get the value we are going to relocate. */
1341 location
= buf
+ off
;
1342 x
= read_reloc (input_bfd
, location
, howto
);
1344 /* Zero out the unwanted bits of X. */
1345 x
&= ~howto
->dst_mask
;
1347 /* For a range list, use 1 instead of 0 as placeholder. 0
1348 would terminate the list, hiding any later entries. */
1349 if (strcmp (bfd_section_name (input_section
), ".debug_ranges") == 0
1350 && (howto
->dst_mask
& 1) != 0)
1353 /* Put the relocated value back in the object file. */
1354 write_reloc (input_bfd
, x
, location
, howto
);
1355 return bfd_reloc_ok
;
1361 howto manager, , typedef arelent, Relocations
1366 When an application wants to create a relocation, but doesn't
1367 know what the target machine might call it, it can find out by
1368 using this bit of code.
1374 bfd_reloc_code_real_type
1377 The insides of a reloc code. The idea is that, eventually, there
1378 will be one enumerator for every type of relocation we ever do.
1379 Pass one of these values to <<bfd_reloc_type_lookup>>, and it'll
1380 return a howto pointer.
1382 This does mean that the application must determine the correct
1383 enumerator value; you can't get a howto pointer from a random set
1404 Basic absolute relocations of N bits.
1419 PC-relative relocations. Sometimes these are relative to the
1420 address of the relocation itself; sometimes they are relative to the
1421 start of the section containing the relocation. It depends on the
1429 Section relative relocations. Some targets need this for DWARF2.
1432 BFD_RELOC_32_GOT_PCREL
1434 BFD_RELOC_16_GOT_PCREL
1436 BFD_RELOC_8_GOT_PCREL
1442 BFD_RELOC_LO16_GOTOFF
1444 BFD_RELOC_HI16_GOTOFF
1446 BFD_RELOC_HI16_S_GOTOFF
1450 BFD_RELOC_64_PLT_PCREL
1452 BFD_RELOC_32_PLT_PCREL
1454 BFD_RELOC_24_PLT_PCREL
1456 BFD_RELOC_16_PLT_PCREL
1458 BFD_RELOC_8_PLT_PCREL
1466 BFD_RELOC_LO16_PLTOFF
1468 BFD_RELOC_HI16_PLTOFF
1470 BFD_RELOC_HI16_S_PLTOFF
1484 BFD_RELOC_68K_GLOB_DAT
1486 BFD_RELOC_68K_JMP_SLOT
1488 BFD_RELOC_68K_RELATIVE
1490 BFD_RELOC_68K_TLS_GD32
1492 BFD_RELOC_68K_TLS_GD16
1494 BFD_RELOC_68K_TLS_GD8
1496 BFD_RELOC_68K_TLS_LDM32
1498 BFD_RELOC_68K_TLS_LDM16
1500 BFD_RELOC_68K_TLS_LDM8
1502 BFD_RELOC_68K_TLS_LDO32
1504 BFD_RELOC_68K_TLS_LDO16
1506 BFD_RELOC_68K_TLS_LDO8
1508 BFD_RELOC_68K_TLS_IE32
1510 BFD_RELOC_68K_TLS_IE16
1512 BFD_RELOC_68K_TLS_IE8
1514 BFD_RELOC_68K_TLS_LE32
1516 BFD_RELOC_68K_TLS_LE16
1518 BFD_RELOC_68K_TLS_LE8
1520 Relocations used by 68K ELF.
1523 BFD_RELOC_32_BASEREL
1525 BFD_RELOC_16_BASEREL
1527 BFD_RELOC_LO16_BASEREL
1529 BFD_RELOC_HI16_BASEREL
1531 BFD_RELOC_HI16_S_BASEREL
1537 Linkage-table relative.
1542 Absolute 8-bit relocation, but used to form an address like 0xFFnn.
1545 BFD_RELOC_32_PCREL_S2
1547 BFD_RELOC_16_PCREL_S2
1549 BFD_RELOC_23_PCREL_S2
1551 These PC-relative relocations are stored as word displacements --
1552 i.e., byte displacements shifted right two bits. The 30-bit word
1553 displacement (<<32_PCREL_S2>> -- 32 bits, shifted 2) is used on the
1554 SPARC. (SPARC tools generally refer to this as <<WDISP30>>.) The
1555 signed 16-bit displacement is used on the MIPS, and the 23-bit
1556 displacement is used on the Alpha.
1563 High 22 bits and low 10 bits of 32-bit value, placed into lower bits
1564 of the target word. These are used on the SPARC.
1571 For systems that allocate a Global Pointer register, these are
1572 displacements off that register. These relocation types are
1573 handled specially, because the value the register will have is
1574 decided relatively late.
1579 BFD_RELOC_SPARC_WDISP22
1585 BFD_RELOC_SPARC_GOT10
1587 BFD_RELOC_SPARC_GOT13
1589 BFD_RELOC_SPARC_GOT22
1591 BFD_RELOC_SPARC_PC10
1593 BFD_RELOC_SPARC_PC22
1595 BFD_RELOC_SPARC_WPLT30
1597 BFD_RELOC_SPARC_COPY
1599 BFD_RELOC_SPARC_GLOB_DAT
1601 BFD_RELOC_SPARC_JMP_SLOT
1603 BFD_RELOC_SPARC_RELATIVE
1605 BFD_RELOC_SPARC_UA16
1607 BFD_RELOC_SPARC_UA32
1609 BFD_RELOC_SPARC_UA64
1611 BFD_RELOC_SPARC_GOTDATA_HIX22
1613 BFD_RELOC_SPARC_GOTDATA_LOX10
1615 BFD_RELOC_SPARC_GOTDATA_OP_HIX22
1617 BFD_RELOC_SPARC_GOTDATA_OP_LOX10
1619 BFD_RELOC_SPARC_GOTDATA_OP
1621 BFD_RELOC_SPARC_JMP_IREL
1623 BFD_RELOC_SPARC_IRELATIVE
1625 SPARC ELF relocations. There is probably some overlap with other
1626 relocation types already defined.
1629 BFD_RELOC_SPARC_BASE13
1631 BFD_RELOC_SPARC_BASE22
1633 I think these are specific to SPARC a.out (e.g., Sun 4).
1643 BFD_RELOC_SPARC_OLO10
1645 BFD_RELOC_SPARC_HH22
1647 BFD_RELOC_SPARC_HM10
1649 BFD_RELOC_SPARC_LM22
1651 BFD_RELOC_SPARC_PC_HH22
1653 BFD_RELOC_SPARC_PC_HM10
1655 BFD_RELOC_SPARC_PC_LM22
1657 BFD_RELOC_SPARC_WDISP16
1659 BFD_RELOC_SPARC_WDISP19
1667 BFD_RELOC_SPARC_DISP64
1670 BFD_RELOC_SPARC_PLT32
1672 BFD_RELOC_SPARC_PLT64
1674 BFD_RELOC_SPARC_HIX22
1676 BFD_RELOC_SPARC_LOX10
1684 BFD_RELOC_SPARC_REGISTER
1688 BFD_RELOC_SPARC_SIZE32
1690 BFD_RELOC_SPARC_SIZE64
1692 BFD_RELOC_SPARC_WDISP10
1694 SPARC64 relocations.
1697 BFD_RELOC_SPARC_REV32
1699 SPARC little endian relocation.
1701 BFD_RELOC_SPARC_TLS_GD_HI22
1703 BFD_RELOC_SPARC_TLS_GD_LO10
1705 BFD_RELOC_SPARC_TLS_GD_ADD
1707 BFD_RELOC_SPARC_TLS_GD_CALL
1709 BFD_RELOC_SPARC_TLS_LDM_HI22
1711 BFD_RELOC_SPARC_TLS_LDM_LO10
1713 BFD_RELOC_SPARC_TLS_LDM_ADD
1715 BFD_RELOC_SPARC_TLS_LDM_CALL
1717 BFD_RELOC_SPARC_TLS_LDO_HIX22
1719 BFD_RELOC_SPARC_TLS_LDO_LOX10
1721 BFD_RELOC_SPARC_TLS_LDO_ADD
1723 BFD_RELOC_SPARC_TLS_IE_HI22
1725 BFD_RELOC_SPARC_TLS_IE_LO10
1727 BFD_RELOC_SPARC_TLS_IE_LD
1729 BFD_RELOC_SPARC_TLS_IE_LDX
1731 BFD_RELOC_SPARC_TLS_IE_ADD
1733 BFD_RELOC_SPARC_TLS_LE_HIX22
1735 BFD_RELOC_SPARC_TLS_LE_LOX10
1737 BFD_RELOC_SPARC_TLS_DTPMOD32
1739 BFD_RELOC_SPARC_TLS_DTPMOD64
1741 BFD_RELOC_SPARC_TLS_DTPOFF32
1743 BFD_RELOC_SPARC_TLS_DTPOFF64
1745 BFD_RELOC_SPARC_TLS_TPOFF32
1747 BFD_RELOC_SPARC_TLS_TPOFF64
1749 SPARC TLS relocations.
1758 BFD_RELOC_SPU_IMM10W
1762 BFD_RELOC_SPU_IMM16W
1766 BFD_RELOC_SPU_PCREL9a
1768 BFD_RELOC_SPU_PCREL9b
1770 BFD_RELOC_SPU_PCREL16
1780 BFD_RELOC_SPU_ADD_PIC
1785 BFD_RELOC_ALPHA_GPDISP_HI16
1787 Alpha ECOFF and ELF relocations. Some of these treat the symbol or
1788 "addend" in some special way.
1789 For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when
1790 writing; when reading, it will be the absolute section symbol. The
1791 addend is the displacement in bytes of the "lda" instruction from
1792 the "ldah" instruction (which is at the address of this reloc).
1794 BFD_RELOC_ALPHA_GPDISP_LO16
1796 For GPDISP_LO16 ("ignore") relocations, the symbol is handled as
1797 with GPDISP_HI16 relocs. The addend is ignored when writing the
1798 relocations out, and is filled in with the file's GP value on
1799 reading, for convenience.
1802 BFD_RELOC_ALPHA_GPDISP
1804 The ELF GPDISP relocation is exactly the same as the GPDISP_HI16
1805 relocation except that there is no accompanying GPDISP_LO16
1809 BFD_RELOC_ALPHA_LITERAL
1811 BFD_RELOC_ALPHA_ELF_LITERAL
1813 BFD_RELOC_ALPHA_LITUSE
1815 The Alpha LITERAL/LITUSE relocs are produced by a symbol reference;
1816 the assembler turns it into a LDQ instruction to load the address of
1817 the symbol, and then fills in a register in the real instruction.
1819 The LITERAL reloc, at the LDQ instruction, refers to the .lita
1820 section symbol. The addend is ignored when writing, but is filled
1821 in with the file's GP value on reading, for convenience, as with the
1824 The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16.
1825 It should refer to the symbol to be referenced, as with 16_GOTOFF,
1826 but it generates output not based on the position within the .got
1827 section, but relative to the GP value chosen for the file during the
1830 The LITUSE reloc, on the instruction using the loaded address, gives
1831 information to the linker that it might be able to use to optimize
1832 away some literal section references. The symbol is ignored (read
1833 as the absolute section symbol), and the "addend" indicates the type
1834 of instruction using the register:
1835 1 - "memory" fmt insn
1836 2 - byte-manipulation (byte offset reg)
1837 3 - jsr (target of branch)
1840 BFD_RELOC_ALPHA_HINT
1842 The HINT relocation indicates a value that should be filled into the
1843 "hint" field of a jmp/jsr/ret instruction, for possible branch-
1844 prediction logic which may be provided on some processors.
1847 BFD_RELOC_ALPHA_LINKAGE
1849 The LINKAGE relocation outputs a linkage pair in the object file,
1850 which is filled by the linker.
1853 BFD_RELOC_ALPHA_CODEADDR
1855 The CODEADDR relocation outputs a STO_CA in the object file,
1856 which is filled by the linker.
1859 BFD_RELOC_ALPHA_GPREL_HI16
1861 BFD_RELOC_ALPHA_GPREL_LO16
1863 The GPREL_HI/LO relocations together form a 32-bit offset from the
1867 BFD_RELOC_ALPHA_BRSGP
1869 Like BFD_RELOC_23_PCREL_S2, except that the source and target must
1870 share a common GP, and the target address is adjusted for
1871 STO_ALPHA_STD_GPLOAD.
1876 The NOP relocation outputs a NOP if the longword displacement
1877 between two procedure entry points is < 2^21.
1882 The BSR relocation outputs a BSR if the longword displacement
1883 between two procedure entry points is < 2^21.
1888 The LDA relocation outputs a LDA if the longword displacement
1889 between two procedure entry points is < 2^16.
1894 The BOH relocation outputs a BSR if the longword displacement
1895 between two procedure entry points is < 2^21, or else a hint.
1898 BFD_RELOC_ALPHA_TLSGD
1900 BFD_RELOC_ALPHA_TLSLDM
1902 BFD_RELOC_ALPHA_DTPMOD64
1904 BFD_RELOC_ALPHA_GOTDTPREL16
1906 BFD_RELOC_ALPHA_DTPREL64
1908 BFD_RELOC_ALPHA_DTPREL_HI16
1910 BFD_RELOC_ALPHA_DTPREL_LO16
1912 BFD_RELOC_ALPHA_DTPREL16
1914 BFD_RELOC_ALPHA_GOTTPREL16
1916 BFD_RELOC_ALPHA_TPREL64
1918 BFD_RELOC_ALPHA_TPREL_HI16
1920 BFD_RELOC_ALPHA_TPREL_LO16
1922 BFD_RELOC_ALPHA_TPREL16
1924 Alpha thread-local storage relocations.
1929 BFD_RELOC_MICROMIPS_JMP
1931 The MIPS jump instruction.
1934 BFD_RELOC_MIPS16_JMP
1936 The MIPS16 jump instruction.
1939 BFD_RELOC_MIPS16_GPREL
1941 MIPS16 GP relative reloc.
1946 High 16 bits of 32-bit value; simple reloc.
1951 High 16 bits of 32-bit value but the low 16 bits will be sign
1952 extended and added to form the final result. If the low 16
1953 bits form a negative number, we need to add one to the high value
1954 to compensate for the borrow when the low bits are added.
1962 BFD_RELOC_HI16_PCREL
1964 High 16 bits of 32-bit pc-relative value.
1966 BFD_RELOC_HI16_S_PCREL
1968 High 16 bits of 32-bit pc-relative value, adjusted.
1970 BFD_RELOC_LO16_PCREL
1972 Low 16 bits of pc-relative value.
1975 BFD_RELOC_MIPS16_GOT16
1977 BFD_RELOC_MIPS16_CALL16
1979 Equivalent of BFD_RELOC_MIPS_*, but with the MIPS16 layout of
1980 16-bit immediate fields.
1982 BFD_RELOC_MIPS16_HI16
1984 MIPS16 high 16 bits of 32-bit value.
1986 BFD_RELOC_MIPS16_HI16_S
1988 MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign
1989 extended and added to form the final result. If the low 16
1990 bits form a negative number, we need to add one to the high value
1991 to compensate for the borrow when the low bits are added.
1993 BFD_RELOC_MIPS16_LO16
1998 BFD_RELOC_MIPS16_TLS_GD
2000 BFD_RELOC_MIPS16_TLS_LDM
2002 BFD_RELOC_MIPS16_TLS_DTPREL_HI16
2004 BFD_RELOC_MIPS16_TLS_DTPREL_LO16
2006 BFD_RELOC_MIPS16_TLS_GOTTPREL
2008 BFD_RELOC_MIPS16_TLS_TPREL_HI16
2010 BFD_RELOC_MIPS16_TLS_TPREL_LO16
2012 MIPS16 TLS relocations.
2015 BFD_RELOC_MIPS_LITERAL
2017 BFD_RELOC_MICROMIPS_LITERAL
2019 Relocation against a MIPS literal section.
2022 BFD_RELOC_MICROMIPS_7_PCREL_S1
2024 BFD_RELOC_MICROMIPS_10_PCREL_S1
2026 BFD_RELOC_MICROMIPS_16_PCREL_S1
2028 microMIPS PC-relative relocations.
2031 BFD_RELOC_MIPS16_16_PCREL_S1
2033 MIPS16 PC-relative relocation.
2036 BFD_RELOC_MIPS_21_PCREL_S2
2038 BFD_RELOC_MIPS_26_PCREL_S2
2040 BFD_RELOC_MIPS_18_PCREL_S3
2042 BFD_RELOC_MIPS_19_PCREL_S2
2044 MIPS PC-relative relocations.
2047 BFD_RELOC_MICROMIPS_GPREL16
2049 BFD_RELOC_MICROMIPS_HI16
2051 BFD_RELOC_MICROMIPS_HI16_S
2053 BFD_RELOC_MICROMIPS_LO16
2055 microMIPS versions of generic BFD relocs.
2058 BFD_RELOC_MIPS_GOT16
2060 BFD_RELOC_MICROMIPS_GOT16
2062 BFD_RELOC_MIPS_CALL16
2064 BFD_RELOC_MICROMIPS_CALL16
2066 BFD_RELOC_MIPS_GOT_HI16
2068 BFD_RELOC_MICROMIPS_GOT_HI16
2070 BFD_RELOC_MIPS_GOT_LO16
2072 BFD_RELOC_MICROMIPS_GOT_LO16
2074 BFD_RELOC_MIPS_CALL_HI16
2076 BFD_RELOC_MICROMIPS_CALL_HI16
2078 BFD_RELOC_MIPS_CALL_LO16
2080 BFD_RELOC_MICROMIPS_CALL_LO16
2084 BFD_RELOC_MICROMIPS_SUB
2086 BFD_RELOC_MIPS_GOT_PAGE
2088 BFD_RELOC_MICROMIPS_GOT_PAGE
2090 BFD_RELOC_MIPS_GOT_OFST
2092 BFD_RELOC_MICROMIPS_GOT_OFST
2094 BFD_RELOC_MIPS_GOT_DISP
2096 BFD_RELOC_MICROMIPS_GOT_DISP
2098 BFD_RELOC_MIPS_SHIFT5
2100 BFD_RELOC_MIPS_SHIFT6
2102 BFD_RELOC_MIPS_INSERT_A
2104 BFD_RELOC_MIPS_INSERT_B
2106 BFD_RELOC_MIPS_DELETE
2108 BFD_RELOC_MIPS_HIGHEST
2110 BFD_RELOC_MICROMIPS_HIGHEST
2112 BFD_RELOC_MIPS_HIGHER
2114 BFD_RELOC_MICROMIPS_HIGHER
2116 BFD_RELOC_MIPS_SCN_DISP
2118 BFD_RELOC_MICROMIPS_SCN_DISP
2122 BFD_RELOC_MIPS_RELGOT
2126 BFD_RELOC_MICROMIPS_JALR
2128 BFD_RELOC_MIPS_TLS_DTPMOD32
2130 BFD_RELOC_MIPS_TLS_DTPREL32
2132 BFD_RELOC_MIPS_TLS_DTPMOD64
2134 BFD_RELOC_MIPS_TLS_DTPREL64
2136 BFD_RELOC_MIPS_TLS_GD
2138 BFD_RELOC_MICROMIPS_TLS_GD
2140 BFD_RELOC_MIPS_TLS_LDM
2142 BFD_RELOC_MICROMIPS_TLS_LDM
2144 BFD_RELOC_MIPS_TLS_DTPREL_HI16
2146 BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
2148 BFD_RELOC_MIPS_TLS_DTPREL_LO16
2150 BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
2152 BFD_RELOC_MIPS_TLS_GOTTPREL
2154 BFD_RELOC_MICROMIPS_TLS_GOTTPREL
2156 BFD_RELOC_MIPS_TLS_TPREL32
2158 BFD_RELOC_MIPS_TLS_TPREL64
2160 BFD_RELOC_MIPS_TLS_TPREL_HI16
2162 BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
2164 BFD_RELOC_MIPS_TLS_TPREL_LO16
2166 BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
2170 MIPS ELF relocations.
2175 BFD_RELOC_MIPS_JUMP_SLOT
2177 MIPS ELF relocations (VxWorks and PLT extensions).
2180 BFD_RELOC_MOXIE_10_PCREL
2182 Moxie ELF relocations.
2193 BFD_RELOC_FT32_RELAX
2201 BFD_RELOC_FT32_DIFF32
2203 FT32 ELF relocations.
2206 BFD_RELOC_FRV_LABEL16
2208 BFD_RELOC_FRV_LABEL24
2214 BFD_RELOC_FRV_GPREL12
2216 BFD_RELOC_FRV_GPRELU12
2218 BFD_RELOC_FRV_GPREL32
2220 BFD_RELOC_FRV_GPRELHI
2222 BFD_RELOC_FRV_GPRELLO
2230 BFD_RELOC_FRV_FUNCDESC
2232 BFD_RELOC_FRV_FUNCDESC_GOT12
2234 BFD_RELOC_FRV_FUNCDESC_GOTHI
2236 BFD_RELOC_FRV_FUNCDESC_GOTLO
2238 BFD_RELOC_FRV_FUNCDESC_VALUE
2240 BFD_RELOC_FRV_FUNCDESC_GOTOFF12
2242 BFD_RELOC_FRV_FUNCDESC_GOTOFFHI
2244 BFD_RELOC_FRV_FUNCDESC_GOTOFFLO
2246 BFD_RELOC_FRV_GOTOFF12
2248 BFD_RELOC_FRV_GOTOFFHI
2250 BFD_RELOC_FRV_GOTOFFLO
2252 BFD_RELOC_FRV_GETTLSOFF
2254 BFD_RELOC_FRV_TLSDESC_VALUE
2256 BFD_RELOC_FRV_GOTTLSDESC12
2258 BFD_RELOC_FRV_GOTTLSDESCHI
2260 BFD_RELOC_FRV_GOTTLSDESCLO
2262 BFD_RELOC_FRV_TLSMOFF12
2264 BFD_RELOC_FRV_TLSMOFFHI
2266 BFD_RELOC_FRV_TLSMOFFLO
2268 BFD_RELOC_FRV_GOTTLSOFF12
2270 BFD_RELOC_FRV_GOTTLSOFFHI
2272 BFD_RELOC_FRV_GOTTLSOFFLO
2274 BFD_RELOC_FRV_TLSOFF
2276 BFD_RELOC_FRV_TLSDESC_RELAX
2278 BFD_RELOC_FRV_GETTLSOFF_RELAX
2280 BFD_RELOC_FRV_TLSOFF_RELAX
2282 BFD_RELOC_FRV_TLSMOFF
2284 Fujitsu Frv Relocations.
2287 BFD_RELOC_MN10300_GOTOFF24
2289 This is a 24bit GOT-relative reloc for the mn10300.
2291 BFD_RELOC_MN10300_GOT32
2293 This is a 32bit GOT-relative reloc for the mn10300, offset by two
2294 bytes in the instruction.
2296 BFD_RELOC_MN10300_GOT24
2298 This is a 24bit GOT-relative reloc for the mn10300, offset by two
2299 bytes in the instruction.
2301 BFD_RELOC_MN10300_GOT16
2303 This is a 16bit GOT-relative reloc for the mn10300, offset by two
2304 bytes in the instruction.
2306 BFD_RELOC_MN10300_COPY
2308 Copy symbol at runtime.
2310 BFD_RELOC_MN10300_GLOB_DAT
2314 BFD_RELOC_MN10300_JMP_SLOT
2318 BFD_RELOC_MN10300_RELATIVE
2320 Adjust by program base.
2322 BFD_RELOC_MN10300_SYM_DIFF
2324 Together with another reloc targeted at the same location, allows
2325 for a value that is the difference of two symbols in the same
2328 BFD_RELOC_MN10300_ALIGN
2330 The addend of this reloc is an alignment power that must be honoured
2331 at the offset's location, regardless of linker relaxation.
2333 BFD_RELOC_MN10300_TLS_GD
2335 BFD_RELOC_MN10300_TLS_LD
2337 BFD_RELOC_MN10300_TLS_LDO
2339 BFD_RELOC_MN10300_TLS_GOTIE
2341 BFD_RELOC_MN10300_TLS_IE
2343 BFD_RELOC_MN10300_TLS_LE
2345 BFD_RELOC_MN10300_TLS_DTPMOD
2347 BFD_RELOC_MN10300_TLS_DTPOFF
2349 BFD_RELOC_MN10300_TLS_TPOFF
2351 Various TLS-related relocations.
2353 BFD_RELOC_MN10300_32_PCREL
2355 This is a 32bit pcrel reloc for the mn10300, offset by two bytes in
2358 BFD_RELOC_MN10300_16_PCREL
2360 This is a 16bit pcrel reloc for the mn10300, offset by two bytes in
2370 BFD_RELOC_386_GLOB_DAT
2372 BFD_RELOC_386_JUMP_SLOT
2374 BFD_RELOC_386_RELATIVE
2376 BFD_RELOC_386_GOTOFF
2380 BFD_RELOC_386_TLS_TPOFF
2382 BFD_RELOC_386_TLS_IE
2384 BFD_RELOC_386_TLS_GOTIE
2386 BFD_RELOC_386_TLS_LE
2388 BFD_RELOC_386_TLS_GD
2390 BFD_RELOC_386_TLS_LDM
2392 BFD_RELOC_386_TLS_LDO_32
2394 BFD_RELOC_386_TLS_IE_32
2396 BFD_RELOC_386_TLS_LE_32
2398 BFD_RELOC_386_TLS_DTPMOD32
2400 BFD_RELOC_386_TLS_DTPOFF32
2402 BFD_RELOC_386_TLS_TPOFF32
2404 BFD_RELOC_386_TLS_GOTDESC
2406 BFD_RELOC_386_TLS_DESC_CALL
2408 BFD_RELOC_386_TLS_DESC
2410 BFD_RELOC_386_IRELATIVE
2412 BFD_RELOC_386_GOT32X
2414 i386/elf relocations.
2417 BFD_RELOC_X86_64_GOT32
2419 BFD_RELOC_X86_64_PLT32
2421 BFD_RELOC_X86_64_COPY
2423 BFD_RELOC_X86_64_GLOB_DAT
2425 BFD_RELOC_X86_64_JUMP_SLOT
2427 BFD_RELOC_X86_64_RELATIVE
2429 BFD_RELOC_X86_64_GOTPCREL
2431 BFD_RELOC_X86_64_32S
2433 BFD_RELOC_X86_64_DTPMOD64
2435 BFD_RELOC_X86_64_DTPOFF64
2437 BFD_RELOC_X86_64_TPOFF64
2439 BFD_RELOC_X86_64_TLSGD
2441 BFD_RELOC_X86_64_TLSLD
2443 BFD_RELOC_X86_64_DTPOFF32
2445 BFD_RELOC_X86_64_GOTTPOFF
2447 BFD_RELOC_X86_64_TPOFF32
2449 BFD_RELOC_X86_64_GOTOFF64
2451 BFD_RELOC_X86_64_GOTPC32
2453 BFD_RELOC_X86_64_GOT64
2455 BFD_RELOC_X86_64_GOTPCREL64
2457 BFD_RELOC_X86_64_GOTPC64
2459 BFD_RELOC_X86_64_GOTPLT64
2461 BFD_RELOC_X86_64_PLTOFF64
2463 BFD_RELOC_X86_64_GOTPC32_TLSDESC
2465 BFD_RELOC_X86_64_TLSDESC_CALL
2467 BFD_RELOC_X86_64_TLSDESC
2469 BFD_RELOC_X86_64_IRELATIVE
2471 BFD_RELOC_X86_64_PC32_BND
2473 BFD_RELOC_X86_64_PLT32_BND
2475 BFD_RELOC_X86_64_GOTPCRELX
2477 BFD_RELOC_X86_64_REX_GOTPCRELX
2479 BFD_RELOC_X86_64_CODE_4_GOTPCRELX
2481 BFD_RELOC_X86_64_CODE_4_GOTTPOFF
2483 BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC
2485 BFD_RELOC_X86_64_CODE_5_GOTPCRELX
2487 BFD_RELOC_X86_64_CODE_5_GOTTPOFF
2489 BFD_RELOC_X86_64_CODE_5_GOTPC32_TLSDESC
2491 BFD_RELOC_X86_64_CODE_6_GOTPCRELX
2493 BFD_RELOC_X86_64_CODE_6_GOTTPOFF
2495 BFD_RELOC_X86_64_CODE_6_GOTPC32_TLSDESC
2497 x86-64/elf relocations.
2500 BFD_RELOC_NS32K_IMM_8
2502 BFD_RELOC_NS32K_IMM_16
2504 BFD_RELOC_NS32K_IMM_32
2506 BFD_RELOC_NS32K_IMM_8_PCREL
2508 BFD_RELOC_NS32K_IMM_16_PCREL
2510 BFD_RELOC_NS32K_IMM_32_PCREL
2512 BFD_RELOC_NS32K_DISP_8
2514 BFD_RELOC_NS32K_DISP_16
2516 BFD_RELOC_NS32K_DISP_32
2518 BFD_RELOC_NS32K_DISP_8_PCREL
2520 BFD_RELOC_NS32K_DISP_16_PCREL
2522 BFD_RELOC_NS32K_DISP_32_PCREL
2527 BFD_RELOC_PDP11_DISP_8_PCREL
2529 BFD_RELOC_PDP11_DISP_6_PCREL
2534 BFD_RELOC_PJ_CODE_HI16
2536 BFD_RELOC_PJ_CODE_LO16
2538 BFD_RELOC_PJ_CODE_DIR16
2540 BFD_RELOC_PJ_CODE_DIR32
2542 BFD_RELOC_PJ_CODE_REL16
2544 BFD_RELOC_PJ_CODE_REL32
2546 Picojava relocs. Not all of these appear in object files.
2555 BFD_RELOC_PPC_TOC16_LO
2557 BFD_RELOC_PPC_TOC16_HI
2561 BFD_RELOC_PPC_B16_BRTAKEN
2563 BFD_RELOC_PPC_B16_BRNTAKEN
2567 BFD_RELOC_PPC_BA16_BRTAKEN
2569 BFD_RELOC_PPC_BA16_BRNTAKEN
2573 BFD_RELOC_PPC_GLOB_DAT
2575 BFD_RELOC_PPC_JMP_SLOT
2577 BFD_RELOC_PPC_RELATIVE
2579 BFD_RELOC_PPC_LOCAL24PC
2581 BFD_RELOC_PPC_EMB_NADDR32
2583 BFD_RELOC_PPC_EMB_NADDR16
2585 BFD_RELOC_PPC_EMB_NADDR16_LO
2587 BFD_RELOC_PPC_EMB_NADDR16_HI
2589 BFD_RELOC_PPC_EMB_NADDR16_HA
2591 BFD_RELOC_PPC_EMB_SDAI16
2593 BFD_RELOC_PPC_EMB_SDA2I16
2595 BFD_RELOC_PPC_EMB_SDA2REL
2597 BFD_RELOC_PPC_EMB_SDA21
2599 BFD_RELOC_PPC_EMB_MRKREF
2601 BFD_RELOC_PPC_EMB_RELSEC16
2603 BFD_RELOC_PPC_EMB_RELST_LO
2605 BFD_RELOC_PPC_EMB_RELST_HI
2607 BFD_RELOC_PPC_EMB_RELST_HA
2609 BFD_RELOC_PPC_EMB_BIT_FLD
2611 BFD_RELOC_PPC_EMB_RELSDA
2613 BFD_RELOC_PPC_VLE_REL8
2615 BFD_RELOC_PPC_VLE_REL15
2617 BFD_RELOC_PPC_VLE_REL24
2619 BFD_RELOC_PPC_VLE_LO16A
2621 BFD_RELOC_PPC_VLE_LO16D
2623 BFD_RELOC_PPC_VLE_HI16A
2625 BFD_RELOC_PPC_VLE_HI16D
2627 BFD_RELOC_PPC_VLE_HA16A
2629 BFD_RELOC_PPC_VLE_HA16D
2631 BFD_RELOC_PPC_VLE_SDA21
2633 BFD_RELOC_PPC_VLE_SDA21_LO
2635 BFD_RELOC_PPC_VLE_SDAREL_LO16A
2637 BFD_RELOC_PPC_VLE_SDAREL_LO16D
2639 BFD_RELOC_PPC_VLE_SDAREL_HI16A
2641 BFD_RELOC_PPC_VLE_SDAREL_HI16D
2643 BFD_RELOC_PPC_VLE_SDAREL_HA16A
2645 BFD_RELOC_PPC_VLE_SDAREL_HA16D
2647 BFD_RELOC_PPC_16DX_HA
2649 BFD_RELOC_PPC_REL16DX_HA
2653 BFD_RELOC_PPC64_HIGHER
2655 BFD_RELOC_PPC64_HIGHER_S
2657 BFD_RELOC_PPC64_HIGHEST
2659 BFD_RELOC_PPC64_HIGHEST_S
2661 BFD_RELOC_PPC64_TOC16_LO
2663 BFD_RELOC_PPC64_TOC16_HI
2665 BFD_RELOC_PPC64_TOC16_HA
2669 BFD_RELOC_PPC64_PLTGOT16
2671 BFD_RELOC_PPC64_PLTGOT16_LO
2673 BFD_RELOC_PPC64_PLTGOT16_HI
2675 BFD_RELOC_PPC64_PLTGOT16_HA
2677 BFD_RELOC_PPC64_ADDR16_DS
2679 BFD_RELOC_PPC64_ADDR16_LO_DS
2681 BFD_RELOC_PPC64_GOT16_DS
2683 BFD_RELOC_PPC64_GOT16_LO_DS
2685 BFD_RELOC_PPC64_PLT16_LO_DS
2687 BFD_RELOC_PPC64_SECTOFF_DS
2689 BFD_RELOC_PPC64_SECTOFF_LO_DS
2691 BFD_RELOC_PPC64_TOC16_DS
2693 BFD_RELOC_PPC64_TOC16_LO_DS
2695 BFD_RELOC_PPC64_PLTGOT16_DS
2697 BFD_RELOC_PPC64_PLTGOT16_LO_DS
2699 BFD_RELOC_PPC64_ADDR16_HIGH
2701 BFD_RELOC_PPC64_ADDR16_HIGHA
2703 BFD_RELOC_PPC64_REL16_HIGH
2705 BFD_RELOC_PPC64_REL16_HIGHA
2707 BFD_RELOC_PPC64_REL16_HIGHER
2709 BFD_RELOC_PPC64_REL16_HIGHERA
2711 BFD_RELOC_PPC64_REL16_HIGHEST
2713 BFD_RELOC_PPC64_REL16_HIGHESTA
2715 BFD_RELOC_PPC64_ADDR64_LOCAL
2717 BFD_RELOC_PPC64_ENTRY
2719 BFD_RELOC_PPC64_REL24_NOTOC
2721 BFD_RELOC_PPC64_REL24_P9NOTOC
2725 BFD_RELOC_PPC64_D34_LO
2727 BFD_RELOC_PPC64_D34_HI30
2729 BFD_RELOC_PPC64_D34_HA30
2731 BFD_RELOC_PPC64_PCREL34
2733 BFD_RELOC_PPC64_GOT_PCREL34
2735 BFD_RELOC_PPC64_PLT_PCREL34
2737 BFD_RELOC_PPC64_ADDR16_HIGHER34
2739 BFD_RELOC_PPC64_ADDR16_HIGHERA34
2741 BFD_RELOC_PPC64_ADDR16_HIGHEST34
2743 BFD_RELOC_PPC64_ADDR16_HIGHESTA34
2745 BFD_RELOC_PPC64_REL16_HIGHER34
2747 BFD_RELOC_PPC64_REL16_HIGHERA34
2749 BFD_RELOC_PPC64_REL16_HIGHEST34
2751 BFD_RELOC_PPC64_REL16_HIGHESTA34
2755 BFD_RELOC_PPC64_PCREL28
2757 Power(rs6000) and PowerPC relocations.
2774 BFD_RELOC_PPC_DTPMOD
2776 BFD_RELOC_PPC_TPREL16
2778 BFD_RELOC_PPC_TPREL16_LO
2780 BFD_RELOC_PPC_TPREL16_HI
2782 BFD_RELOC_PPC_TPREL16_HA
2786 BFD_RELOC_PPC_DTPREL16
2788 BFD_RELOC_PPC_DTPREL16_LO
2790 BFD_RELOC_PPC_DTPREL16_HI
2792 BFD_RELOC_PPC_DTPREL16_HA
2794 BFD_RELOC_PPC_DTPREL
2796 BFD_RELOC_PPC_GOT_TLSGD16
2798 BFD_RELOC_PPC_GOT_TLSGD16_LO
2800 BFD_RELOC_PPC_GOT_TLSGD16_HI
2802 BFD_RELOC_PPC_GOT_TLSGD16_HA
2804 BFD_RELOC_PPC_GOT_TLSLD16
2806 BFD_RELOC_PPC_GOT_TLSLD16_LO
2808 BFD_RELOC_PPC_GOT_TLSLD16_HI
2810 BFD_RELOC_PPC_GOT_TLSLD16_HA
2812 BFD_RELOC_PPC_GOT_TPREL16
2814 BFD_RELOC_PPC_GOT_TPREL16_LO
2816 BFD_RELOC_PPC_GOT_TPREL16_HI
2818 BFD_RELOC_PPC_GOT_TPREL16_HA
2820 BFD_RELOC_PPC_GOT_DTPREL16
2822 BFD_RELOC_PPC_GOT_DTPREL16_LO
2824 BFD_RELOC_PPC_GOT_DTPREL16_HI
2826 BFD_RELOC_PPC_GOT_DTPREL16_HA
2828 BFD_RELOC_PPC64_TLSGD
2830 BFD_RELOC_PPC64_TLSLD
2832 BFD_RELOC_PPC64_TLSLE
2834 BFD_RELOC_PPC64_TLSIE
2836 BFD_RELOC_PPC64_TLSM
2838 BFD_RELOC_PPC64_TLSML
2840 BFD_RELOC_PPC64_TPREL16_DS
2842 BFD_RELOC_PPC64_TPREL16_LO_DS
2844 BFD_RELOC_PPC64_TPREL16_HIGH
2846 BFD_RELOC_PPC64_TPREL16_HIGHA
2848 BFD_RELOC_PPC64_TPREL16_HIGHER
2850 BFD_RELOC_PPC64_TPREL16_HIGHERA
2852 BFD_RELOC_PPC64_TPREL16_HIGHEST
2854 BFD_RELOC_PPC64_TPREL16_HIGHESTA
2856 BFD_RELOC_PPC64_DTPREL16_DS
2858 BFD_RELOC_PPC64_DTPREL16_LO_DS
2860 BFD_RELOC_PPC64_DTPREL16_HIGH
2862 BFD_RELOC_PPC64_DTPREL16_HIGHA
2864 BFD_RELOC_PPC64_DTPREL16_HIGHER
2866 BFD_RELOC_PPC64_DTPREL16_HIGHERA
2868 BFD_RELOC_PPC64_DTPREL16_HIGHEST
2870 BFD_RELOC_PPC64_DTPREL16_HIGHESTA
2872 BFD_RELOC_PPC64_TPREL34
2874 BFD_RELOC_PPC64_DTPREL34
2876 BFD_RELOC_PPC64_GOT_TLSGD_PCREL34
2878 BFD_RELOC_PPC64_GOT_TLSLD_PCREL34
2880 BFD_RELOC_PPC64_GOT_TPREL_PCREL34
2882 BFD_RELOC_PPC64_GOT_DTPREL_PCREL34
2884 BFD_RELOC_PPC64_TLS_PCREL
2886 PowerPC and PowerPC64 thread-local storage relocations.
2891 IBM 370/390 relocations.
2896 The type of reloc used to build a constructor table - at the moment
2897 probably a 32 bit wide absolute relocation, but the target can choose.
2898 It generally does map to one of the other relocation types.
2901 BFD_RELOC_ARM_PCREL_BRANCH
2903 ARM 26 bit pc-relative branch. The lowest two bits must be zero and
2904 are not stored in the instruction.
2906 BFD_RELOC_ARM_PCREL_BLX
2908 ARM 26 bit pc-relative branch. The lowest bit must be zero and is
2909 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
2910 field in the instruction.
2912 BFD_RELOC_THUMB_PCREL_BLX
2914 Thumb 22 bit pc-relative branch. The lowest bit must be zero and is
2915 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
2916 field in the instruction.
2918 BFD_RELOC_ARM_PCREL_CALL
2920 ARM 26-bit pc-relative branch for an unconditional BL or BLX
2923 BFD_RELOC_ARM_PCREL_JUMP
2925 ARM 26-bit pc-relative branch for B or conditional BL instruction.
2928 BFD_RELOC_THUMB_PCREL_BRANCH5
2930 ARM 5-bit pc-relative branch for Branch Future instructions.
2933 BFD_RELOC_THUMB_PCREL_BFCSEL
2935 ARM 6-bit pc-relative branch for BFCSEL instruction.
2938 BFD_RELOC_ARM_THUMB_BF17
2940 ARM 17-bit pc-relative branch for Branch Future instructions.
2943 BFD_RELOC_ARM_THUMB_BF13
2945 ARM 13-bit pc-relative branch for BFCSEL instruction.
2948 BFD_RELOC_ARM_THUMB_BF19
2950 ARM 19-bit pc-relative branch for Branch Future Link instruction.
2953 BFD_RELOC_ARM_THUMB_LOOP12
2955 ARM 12-bit pc-relative branch for Low Overhead Loop instructions.
2958 BFD_RELOC_THUMB_PCREL_BRANCH7
2960 BFD_RELOC_THUMB_PCREL_BRANCH9
2962 BFD_RELOC_THUMB_PCREL_BRANCH12
2964 BFD_RELOC_THUMB_PCREL_BRANCH20
2966 BFD_RELOC_THUMB_PCREL_BRANCH23
2968 BFD_RELOC_THUMB_PCREL_BRANCH25
2970 Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches.
2971 The lowest bit must be zero and is not stored in the instruction.
2972 Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an
2973 "nn" one smaller in all cases. Note further that BRANCH23
2974 corresponds to R_ARM_THM_CALL.
2977 BFD_RELOC_ARM_OFFSET_IMM
2979 12-bit immediate offset, used in ARM-format ldr and str instructions.
2982 BFD_RELOC_ARM_THUMB_OFFSET
2984 5-bit immediate offset, used in Thumb-format ldr and str instructions.
2987 BFD_RELOC_ARM_TARGET1
2989 Pc-relative or absolute relocation depending on target. Used for
2990 entries in .init_array sections.
2992 BFD_RELOC_ARM_ROSEGREL32
2994 Read-only segment base relative address.
2996 BFD_RELOC_ARM_SBREL32
2998 Data segment base relative address.
3000 BFD_RELOC_ARM_TARGET2
3002 This reloc is used for references to RTTI data from exception
3003 handling tables. The actual definition depends on the target. It
3004 may be a pc-relative or some form of GOT-indirect relocation.
3006 BFD_RELOC_ARM_PREL31
3008 31-bit PC relative address.
3014 BFD_RELOC_ARM_MOVW_PCREL
3016 BFD_RELOC_ARM_MOVT_PCREL
3018 BFD_RELOC_ARM_THUMB_MOVW
3020 BFD_RELOC_ARM_THUMB_MOVT
3022 BFD_RELOC_ARM_THUMB_MOVW_PCREL
3024 BFD_RELOC_ARM_THUMB_MOVT_PCREL
3026 Low and High halfword relocations for MOVW and MOVT instructions.
3029 BFD_RELOC_ARM_GOTFUNCDESC
3031 BFD_RELOC_ARM_GOTOFFFUNCDESC
3033 BFD_RELOC_ARM_FUNCDESC
3035 BFD_RELOC_ARM_FUNCDESC_VALUE
3037 BFD_RELOC_ARM_TLS_GD32_FDPIC
3039 BFD_RELOC_ARM_TLS_LDM32_FDPIC
3041 BFD_RELOC_ARM_TLS_IE32_FDPIC
3043 ARM FDPIC specific relocations.
3046 BFD_RELOC_ARM_JUMP_SLOT
3048 BFD_RELOC_ARM_GLOB_DAT
3054 BFD_RELOC_ARM_RELATIVE
3056 BFD_RELOC_ARM_GOTOFF
3060 BFD_RELOC_ARM_GOT_PREL
3062 Relocations for setting up GOTs and PLTs for shared libraries.
3065 BFD_RELOC_ARM_TLS_GD32
3067 BFD_RELOC_ARM_TLS_LDO32
3069 BFD_RELOC_ARM_TLS_LDM32
3071 BFD_RELOC_ARM_TLS_DTPOFF32
3073 BFD_RELOC_ARM_TLS_DTPMOD32
3075 BFD_RELOC_ARM_TLS_TPOFF32
3077 BFD_RELOC_ARM_TLS_IE32
3079 BFD_RELOC_ARM_TLS_LE32
3081 BFD_RELOC_ARM_TLS_GOTDESC
3083 BFD_RELOC_ARM_TLS_CALL
3085 BFD_RELOC_ARM_THM_TLS_CALL
3087 BFD_RELOC_ARM_TLS_DESCSEQ
3089 BFD_RELOC_ARM_THM_TLS_DESCSEQ
3091 BFD_RELOC_ARM_TLS_DESC
3093 ARM thread-local storage relocations.
3096 BFD_RELOC_ARM_ALU_PC_G0_NC
3098 BFD_RELOC_ARM_ALU_PC_G0
3100 BFD_RELOC_ARM_ALU_PC_G1_NC
3102 BFD_RELOC_ARM_ALU_PC_G1
3104 BFD_RELOC_ARM_ALU_PC_G2
3106 BFD_RELOC_ARM_LDR_PC_G0
3108 BFD_RELOC_ARM_LDR_PC_G1
3110 BFD_RELOC_ARM_LDR_PC_G2
3112 BFD_RELOC_ARM_LDRS_PC_G0
3114 BFD_RELOC_ARM_LDRS_PC_G1
3116 BFD_RELOC_ARM_LDRS_PC_G2
3118 BFD_RELOC_ARM_LDC_PC_G0
3120 BFD_RELOC_ARM_LDC_PC_G1
3122 BFD_RELOC_ARM_LDC_PC_G2
3124 BFD_RELOC_ARM_ALU_SB_G0_NC
3126 BFD_RELOC_ARM_ALU_SB_G0
3128 BFD_RELOC_ARM_ALU_SB_G1_NC
3130 BFD_RELOC_ARM_ALU_SB_G1
3132 BFD_RELOC_ARM_ALU_SB_G2
3134 BFD_RELOC_ARM_LDR_SB_G0
3136 BFD_RELOC_ARM_LDR_SB_G1
3138 BFD_RELOC_ARM_LDR_SB_G2
3140 BFD_RELOC_ARM_LDRS_SB_G0
3142 BFD_RELOC_ARM_LDRS_SB_G1
3144 BFD_RELOC_ARM_LDRS_SB_G2
3146 BFD_RELOC_ARM_LDC_SB_G0
3148 BFD_RELOC_ARM_LDC_SB_G1
3150 BFD_RELOC_ARM_LDC_SB_G2
3152 ARM group relocations.
3157 Annotation of BX instructions.
3160 BFD_RELOC_ARM_IRELATIVE
3162 ARM support for STT_GNU_IFUNC.
3165 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
3167 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
3169 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
3171 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
3173 Thumb1 relocations to support execute-only code.
3176 BFD_RELOC_ARM_IMMEDIATE
3178 BFD_RELOC_ARM_ADRL_IMMEDIATE
3180 BFD_RELOC_ARM_T32_IMMEDIATE
3182 BFD_RELOC_ARM_T32_ADD_IMM
3184 BFD_RELOC_ARM_T32_IMM12
3186 BFD_RELOC_ARM_T32_ADD_PC12
3188 BFD_RELOC_ARM_SHIFT_IMM
3198 BFD_RELOC_ARM_CP_OFF_IMM
3200 BFD_RELOC_ARM_CP_OFF_IMM_S2
3202 BFD_RELOC_ARM_T32_CP_OFF_IMM
3204 BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
3206 BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
3208 BFD_RELOC_ARM_ADR_IMM
3210 BFD_RELOC_ARM_LDR_IMM
3212 BFD_RELOC_ARM_LITERAL
3214 BFD_RELOC_ARM_IN_POOL
3216 BFD_RELOC_ARM_OFFSET_IMM8
3218 BFD_RELOC_ARM_T32_OFFSET_U8
3220 BFD_RELOC_ARM_T32_OFFSET_IMM
3222 BFD_RELOC_ARM_HWLITERAL
3224 BFD_RELOC_ARM_THUMB_ADD
3226 BFD_RELOC_ARM_THUMB_IMM
3228 BFD_RELOC_ARM_THUMB_SHIFT
3230 These relocs are only used within the ARM assembler. They are not
3231 (at present) written to any object files.
3234 BFD_RELOC_SH_PCDISP8BY2
3236 BFD_RELOC_SH_PCDISP12BY2
3244 BFD_RELOC_SH_DISP12BY2
3246 BFD_RELOC_SH_DISP12BY4
3248 BFD_RELOC_SH_DISP12BY8
3252 BFD_RELOC_SH_DISP20BY8
3256 BFD_RELOC_SH_IMM4BY2
3258 BFD_RELOC_SH_IMM4BY4
3262 BFD_RELOC_SH_IMM8BY2
3264 BFD_RELOC_SH_IMM8BY4
3266 BFD_RELOC_SH_PCRELIMM8BY2
3268 BFD_RELOC_SH_PCRELIMM8BY4
3270 BFD_RELOC_SH_SWITCH16
3272 BFD_RELOC_SH_SWITCH32
3286 BFD_RELOC_SH_LOOP_START
3288 BFD_RELOC_SH_LOOP_END
3292 BFD_RELOC_SH_GLOB_DAT
3294 BFD_RELOC_SH_JMP_SLOT
3296 BFD_RELOC_SH_RELATIVE
3300 BFD_RELOC_SH_GOT_LOW16
3302 BFD_RELOC_SH_GOT_MEDLOW16
3304 BFD_RELOC_SH_GOT_MEDHI16
3306 BFD_RELOC_SH_GOT_HI16
3308 BFD_RELOC_SH_GOTPLT_LOW16
3310 BFD_RELOC_SH_GOTPLT_MEDLOW16
3312 BFD_RELOC_SH_GOTPLT_MEDHI16
3314 BFD_RELOC_SH_GOTPLT_HI16
3316 BFD_RELOC_SH_PLT_LOW16
3318 BFD_RELOC_SH_PLT_MEDLOW16
3320 BFD_RELOC_SH_PLT_MEDHI16
3322 BFD_RELOC_SH_PLT_HI16
3324 BFD_RELOC_SH_GOTOFF_LOW16
3326 BFD_RELOC_SH_GOTOFF_MEDLOW16
3328 BFD_RELOC_SH_GOTOFF_MEDHI16
3330 BFD_RELOC_SH_GOTOFF_HI16
3332 BFD_RELOC_SH_GOTPC_LOW16
3334 BFD_RELOC_SH_GOTPC_MEDLOW16
3336 BFD_RELOC_SH_GOTPC_MEDHI16
3338 BFD_RELOC_SH_GOTPC_HI16
3342 BFD_RELOC_SH_GLOB_DAT64
3344 BFD_RELOC_SH_JMP_SLOT64
3346 BFD_RELOC_SH_RELATIVE64
3348 BFD_RELOC_SH_GOT10BY4
3350 BFD_RELOC_SH_GOT10BY8
3352 BFD_RELOC_SH_GOTPLT10BY4
3354 BFD_RELOC_SH_GOTPLT10BY8
3356 BFD_RELOC_SH_GOTPLT32
3358 BFD_RELOC_SH_SHMEDIA_CODE
3364 BFD_RELOC_SH_IMMS6BY32
3370 BFD_RELOC_SH_IMMS10BY2
3372 BFD_RELOC_SH_IMMS10BY4
3374 BFD_RELOC_SH_IMMS10BY8
3380 BFD_RELOC_SH_IMM_LOW16
3382 BFD_RELOC_SH_IMM_LOW16_PCREL
3384 BFD_RELOC_SH_IMM_MEDLOW16
3386 BFD_RELOC_SH_IMM_MEDLOW16_PCREL
3388 BFD_RELOC_SH_IMM_MEDHI16
3390 BFD_RELOC_SH_IMM_MEDHI16_PCREL
3392 BFD_RELOC_SH_IMM_HI16
3394 BFD_RELOC_SH_IMM_HI16_PCREL
3398 BFD_RELOC_SH_TLS_GD_32
3400 BFD_RELOC_SH_TLS_LD_32
3402 BFD_RELOC_SH_TLS_LDO_32
3404 BFD_RELOC_SH_TLS_IE_32
3406 BFD_RELOC_SH_TLS_LE_32
3408 BFD_RELOC_SH_TLS_DTPMOD32
3410 BFD_RELOC_SH_TLS_DTPOFF32
3412 BFD_RELOC_SH_TLS_TPOFF32
3416 BFD_RELOC_SH_GOTOFF20
3418 BFD_RELOC_SH_GOTFUNCDESC
3420 BFD_RELOC_SH_GOTFUNCDESC20
3422 BFD_RELOC_SH_GOTOFFFUNCDESC
3424 BFD_RELOC_SH_GOTOFFFUNCDESC20
3426 BFD_RELOC_SH_FUNCDESC
3428 Renesas / SuperH SH relocs. Not all of these appear in object files.
3451 BFD_RELOC_ARC_SECTOFF
3453 BFD_RELOC_ARC_S21H_PCREL
3455 BFD_RELOC_ARC_S21W_PCREL
3457 BFD_RELOC_ARC_S25H_PCREL
3459 BFD_RELOC_ARC_S25W_PCREL
3463 BFD_RELOC_ARC_SDA_LDST
3465 BFD_RELOC_ARC_SDA_LDST1
3467 BFD_RELOC_ARC_SDA_LDST2
3469 BFD_RELOC_ARC_SDA16_LD
3471 BFD_RELOC_ARC_SDA16_LD1
3473 BFD_RELOC_ARC_SDA16_LD2
3475 BFD_RELOC_ARC_S13_PCREL
3481 BFD_RELOC_ARC_32_ME_S
3483 BFD_RELOC_ARC_N32_ME
3485 BFD_RELOC_ARC_SECTOFF_ME
3487 BFD_RELOC_ARC_SDA32_ME
3491 BFD_RELOC_AC_SECTOFF_U8
3493 BFD_RELOC_AC_SECTOFF_U8_1
3495 BFD_RELOC_AC_SECTOFF_U8_2
3497 BFD_RELOC_AC_SECTOFF_S9
3499 BFD_RELOC_AC_SECTOFF_S9_1
3501 BFD_RELOC_AC_SECTOFF_S9_2
3503 BFD_RELOC_ARC_SECTOFF_ME_1
3505 BFD_RELOC_ARC_SECTOFF_ME_2
3507 BFD_RELOC_ARC_SECTOFF_1
3509 BFD_RELOC_ARC_SECTOFF_2
3511 BFD_RELOC_ARC_SDA_12
3513 BFD_RELOC_ARC_SDA16_ST2
3515 BFD_RELOC_ARC_32_PCREL
3521 BFD_RELOC_ARC_GOTPC32
3527 BFD_RELOC_ARC_GLOB_DAT
3529 BFD_RELOC_ARC_JMP_SLOT
3531 BFD_RELOC_ARC_RELATIVE
3533 BFD_RELOC_ARC_GOTOFF
3537 BFD_RELOC_ARC_S21W_PCREL_PLT
3539 BFD_RELOC_ARC_S25H_PCREL_PLT
3541 BFD_RELOC_ARC_TLS_DTPMOD
3543 BFD_RELOC_ARC_TLS_TPOFF
3545 BFD_RELOC_ARC_TLS_GD_GOT
3547 BFD_RELOC_ARC_TLS_GD_LD
3549 BFD_RELOC_ARC_TLS_GD_CALL
3551 BFD_RELOC_ARC_TLS_IE_GOT
3553 BFD_RELOC_ARC_TLS_DTPOFF
3555 BFD_RELOC_ARC_TLS_DTPOFF_S9
3557 BFD_RELOC_ARC_TLS_LE_S9
3559 BFD_RELOC_ARC_TLS_LE_32
3561 BFD_RELOC_ARC_S25W_PCREL_PLT
3563 BFD_RELOC_ARC_S21H_PCREL_PLT
3565 BFD_RELOC_ARC_NPS_CMEM16
3567 BFD_RELOC_ARC_JLI_SECTOFF
3572 BFD_RELOC_BFIN_16_IMM
3574 ADI Blackfin 16 bit immediate absolute reloc.
3576 BFD_RELOC_BFIN_16_HIGH
3578 ADI Blackfin 16 bit immediate absolute reloc higher 16 bits.
3580 BFD_RELOC_BFIN_4_PCREL
3582 ADI Blackfin 'a' part of LSETUP.
3584 BFD_RELOC_BFIN_5_PCREL
3588 BFD_RELOC_BFIN_16_LOW
3590 ADI Blackfin 16 bit immediate absolute reloc lower 16 bits.
3592 BFD_RELOC_BFIN_10_PCREL
3596 BFD_RELOC_BFIN_11_PCREL
3598 ADI Blackfin 'b' part of LSETUP.
3600 BFD_RELOC_BFIN_12_PCREL_JUMP
3604 BFD_RELOC_BFIN_12_PCREL_JUMP_S
3606 ADI Blackfin Short jump, pcrel.
3608 BFD_RELOC_BFIN_24_PCREL_CALL_X
3610 ADI Blackfin Call.x not implemented.
3612 BFD_RELOC_BFIN_24_PCREL_JUMP_L
3614 ADI Blackfin Long Jump pcrel.
3616 BFD_RELOC_BFIN_GOT17M4
3618 BFD_RELOC_BFIN_GOTHI
3620 BFD_RELOC_BFIN_GOTLO
3622 BFD_RELOC_BFIN_FUNCDESC
3624 BFD_RELOC_BFIN_FUNCDESC_GOT17M4
3626 BFD_RELOC_BFIN_FUNCDESC_GOTHI
3628 BFD_RELOC_BFIN_FUNCDESC_GOTLO
3630 BFD_RELOC_BFIN_FUNCDESC_VALUE
3632 BFD_RELOC_BFIN_FUNCDESC_GOTOFF17M4
3634 BFD_RELOC_BFIN_FUNCDESC_GOTOFFHI
3636 BFD_RELOC_BFIN_FUNCDESC_GOTOFFLO
3638 BFD_RELOC_BFIN_GOTOFF17M4
3640 BFD_RELOC_BFIN_GOTOFFHI
3642 BFD_RELOC_BFIN_GOTOFFLO
3644 ADI Blackfin FD-PIC relocations.
3648 ADI Blackfin GOT relocation.
3650 BFD_RELOC_BFIN_PLTPC
3652 ADI Blackfin PLTPC relocation.
3654 BFD_ARELOC_BFIN_PUSH
3656 ADI Blackfin arithmetic relocation.
3658 BFD_ARELOC_BFIN_CONST
3660 ADI Blackfin arithmetic relocation.
3664 ADI Blackfin arithmetic relocation.
3668 ADI Blackfin arithmetic relocation.
3670 BFD_ARELOC_BFIN_MULT
3672 ADI Blackfin arithmetic relocation.
3676 ADI Blackfin arithmetic relocation.
3680 ADI Blackfin arithmetic relocation.
3682 BFD_ARELOC_BFIN_LSHIFT
3684 ADI Blackfin arithmetic relocation.
3686 BFD_ARELOC_BFIN_RSHIFT
3688 ADI Blackfin arithmetic relocation.
3692 ADI Blackfin arithmetic relocation.
3696 ADI Blackfin arithmetic relocation.
3700 ADI Blackfin arithmetic relocation.
3702 BFD_ARELOC_BFIN_LAND
3704 ADI Blackfin arithmetic relocation.
3708 ADI Blackfin arithmetic relocation.
3712 ADI Blackfin arithmetic relocation.
3716 ADI Blackfin arithmetic relocation.
3718 BFD_ARELOC_BFIN_COMP
3720 ADI Blackfin arithmetic relocation.
3722 BFD_ARELOC_BFIN_PAGE
3724 ADI Blackfin arithmetic relocation.
3726 BFD_ARELOC_BFIN_HWPAGE
3728 ADI Blackfin arithmetic relocation.
3730 BFD_ARELOC_BFIN_ADDR
3732 ADI Blackfin arithmetic relocation.
3735 BFD_RELOC_D10V_10_PCREL_R
3737 Mitsubishi D10V relocs.
3738 This is a 10-bit reloc with the right 2 bits assumed to be 0.
3740 BFD_RELOC_D10V_10_PCREL_L
3742 Mitsubishi D10V relocs.
3743 This is a 10-bit reloc with the right 2 bits assumed to be 0. This
3744 is the same as the previous reloc except it is in the left
3745 container, i.e., shifted left 15 bits.
3749 This is an 18-bit reloc with the right 2 bits assumed to be 0.
3751 BFD_RELOC_D10V_18_PCREL
3753 This is an 18-bit reloc with the right 2 bits assumed to be 0.
3758 Mitsubishi D30V relocs.
3759 This is a 6-bit absolute reloc.
3761 BFD_RELOC_D30V_9_PCREL
3763 This is a 6-bit pc-relative reloc with the right 3 bits assumed to
3766 BFD_RELOC_D30V_9_PCREL_R
3768 This is a 6-bit pc-relative reloc with the right 3 bits assumed to
3769 be 0. Same as the previous reloc but on the right side of the
3774 This is a 12-bit absolute reloc with the right 3 bitsassumed to
3777 BFD_RELOC_D30V_15_PCREL
3779 This is a 12-bit pc-relative reloc with the right 3 bits assumed to
3782 BFD_RELOC_D30V_15_PCREL_R
3784 This is a 12-bit pc-relative reloc with the right 3 bits assumed to
3785 be 0. Same as the previous reloc but on the right side of the
3790 This is an 18-bit absolute reloc with the right 3 bits assumed to
3793 BFD_RELOC_D30V_21_PCREL
3795 This is an 18-bit pc-relative reloc with the right 3 bits assumed to
3798 BFD_RELOC_D30V_21_PCREL_R
3800 This is an 18-bit pc-relative reloc with the right 3 bits assumed to
3801 be 0. Same as the previous reloc but on the right side of the
3806 This is a 32-bit absolute reloc.
3808 BFD_RELOC_D30V_32_PCREL
3810 This is a 32-bit pc-relative reloc.
3813 BFD_RELOC_DLX_HI16_S
3824 BFD_RELOC_M32C_RL_JUMP
3826 BFD_RELOC_M32C_RL_1ADDR
3828 BFD_RELOC_M32C_RL_2ADDR
3830 Renesas M16C/M32C Relocations.
3835 Renesas M32R (formerly Mitsubishi M32R) relocs.
3836 This is a 24 bit absolute address.
3838 BFD_RELOC_M32R_10_PCREL
3840 This is a 10-bit pc-relative reloc with the right 2 bits assumed to
3843 BFD_RELOC_M32R_18_PCREL
3845 This is an 18-bit reloc with the right 2 bits assumed to be 0.
3847 BFD_RELOC_M32R_26_PCREL
3849 This is a 26-bit reloc with the right 2 bits assumed to be 0.
3851 BFD_RELOC_M32R_HI16_ULO
3853 This is a 16-bit reloc containing the high 16 bits of an address
3854 used when the lower 16 bits are treated as unsigned.
3856 BFD_RELOC_M32R_HI16_SLO
3858 This is a 16-bit reloc containing the high 16 bits of an address
3859 used when the lower 16 bits are treated as signed.
3863 This is a 16-bit reloc containing the lower 16 bits of an address.
3865 BFD_RELOC_M32R_SDA16
3867 This is a 16-bit reloc containing the small data area offset for use
3868 in add3, load, and store instructions.
3870 BFD_RELOC_M32R_GOT24
3872 BFD_RELOC_M32R_26_PLTREL
3876 BFD_RELOC_M32R_GLOB_DAT
3878 BFD_RELOC_M32R_JMP_SLOT
3880 BFD_RELOC_M32R_RELATIVE
3882 BFD_RELOC_M32R_GOTOFF
3884 BFD_RELOC_M32R_GOTOFF_HI_ULO
3886 BFD_RELOC_M32R_GOTOFF_HI_SLO
3888 BFD_RELOC_M32R_GOTOFF_LO
3890 BFD_RELOC_M32R_GOTPC24
3892 BFD_RELOC_M32R_GOT16_HI_ULO
3894 BFD_RELOC_M32R_GOT16_HI_SLO
3896 BFD_RELOC_M32R_GOT16_LO
3898 BFD_RELOC_M32R_GOTPC_HI_ULO
3900 BFD_RELOC_M32R_GOTPC_HI_SLO
3902 BFD_RELOC_M32R_GOTPC_LO
3911 This is a 20 bit absolute address.
3913 BFD_RELOC_NDS32_9_PCREL
3915 This is a 9-bit pc-relative reloc with the right 1 bit assumed to
3918 BFD_RELOC_NDS32_WORD_9_PCREL
3920 This is a 9-bit pc-relative reloc with the right 1 bit assumed to
3923 BFD_RELOC_NDS32_15_PCREL
3925 This is an 15-bit reloc with the right 1 bit assumed to be 0.
3927 BFD_RELOC_NDS32_17_PCREL
3929 This is an 17-bit reloc with the right 1 bit assumed to be 0.
3931 BFD_RELOC_NDS32_25_PCREL
3933 This is a 25-bit reloc with the right 1 bit assumed to be 0.
3935 BFD_RELOC_NDS32_HI20
3937 This is a 20-bit reloc containing the high 20 bits of an address
3938 used with the lower 12 bits.
3940 BFD_RELOC_NDS32_LO12S3
3942 This is a 12-bit reloc containing the lower 12 bits of an address
3943 then shift right by 3. This is used with ldi,sdi.
3945 BFD_RELOC_NDS32_LO12S2
3947 This is a 12-bit reloc containing the lower 12 bits of an address
3948 then shift left by 2. This is used with lwi,swi.
3950 BFD_RELOC_NDS32_LO12S1
3952 This is a 12-bit reloc containing the lower 12 bits of an address
3953 then shift left by 1. This is used with lhi,shi.
3955 BFD_RELOC_NDS32_LO12S0
3957 This is a 12-bit reloc containing the lower 12 bits of an address
3958 then shift left by 0. This is used with lbisbi.
3960 BFD_RELOC_NDS32_LO12S0_ORI
3962 This is a 12-bit reloc containing the lower 12 bits of an address
3963 then shift left by 0. This is only used with branch relaxations.
3965 BFD_RELOC_NDS32_SDA15S3
3967 This is a 15-bit reloc containing the small data area 18-bit signed
3968 offset and shift left by 3 for use in ldi, sdi.
3970 BFD_RELOC_NDS32_SDA15S2
3972 This is a 15-bit reloc containing the small data area 17-bit signed
3973 offset and shift left by 2 for use in lwi, swi.
3975 BFD_RELOC_NDS32_SDA15S1
3977 This is a 15-bit reloc containing the small data area 16-bit signed
3978 offset and shift left by 1 for use in lhi, shi.
3980 BFD_RELOC_NDS32_SDA15S0
3982 This is a 15-bit reloc containing the small data area 15-bit signed
3983 offset and shift left by 0 for use in lbi, sbi.
3985 BFD_RELOC_NDS32_SDA16S3
3987 This is a 16-bit reloc containing the small data area 16-bit signed
3988 offset and shift left by 3.
3990 BFD_RELOC_NDS32_SDA17S2
3992 This is a 17-bit reloc containing the small data area 17-bit signed
3993 offset and shift left by 2 for use in lwi.gp, swi.gp.
3995 BFD_RELOC_NDS32_SDA18S1
3997 This is a 18-bit reloc containing the small data area 18-bit signed
3998 offset and shift left by 1 for use in lhi.gp, shi.gp.
4000 BFD_RELOC_NDS32_SDA19S0
4002 This is a 19-bit reloc containing the small data area 19-bit signed
4003 offset and shift left by 0 for use in lbi.gp, sbi.gp.
4005 BFD_RELOC_NDS32_GOT20
4007 BFD_RELOC_NDS32_9_PLTREL
4009 BFD_RELOC_NDS32_25_PLTREL
4011 BFD_RELOC_NDS32_COPY
4013 BFD_RELOC_NDS32_GLOB_DAT
4015 BFD_RELOC_NDS32_JMP_SLOT
4017 BFD_RELOC_NDS32_RELATIVE
4019 BFD_RELOC_NDS32_GOTOFF
4021 BFD_RELOC_NDS32_GOTOFF_HI20
4023 BFD_RELOC_NDS32_GOTOFF_LO12
4025 BFD_RELOC_NDS32_GOTPC20
4027 BFD_RELOC_NDS32_GOT_HI20
4029 BFD_RELOC_NDS32_GOT_LO12
4031 BFD_RELOC_NDS32_GOTPC_HI20
4033 BFD_RELOC_NDS32_GOTPC_LO12
4037 BFD_RELOC_NDS32_INSN16
4039 BFD_RELOC_NDS32_LABEL
4041 BFD_RELOC_NDS32_LONGCALL1
4043 BFD_RELOC_NDS32_LONGCALL2
4045 BFD_RELOC_NDS32_LONGCALL3
4047 BFD_RELOC_NDS32_LONGJUMP1
4049 BFD_RELOC_NDS32_LONGJUMP2
4051 BFD_RELOC_NDS32_LONGJUMP3
4053 BFD_RELOC_NDS32_LOADSTORE
4055 BFD_RELOC_NDS32_9_FIXED
4057 BFD_RELOC_NDS32_15_FIXED
4059 BFD_RELOC_NDS32_17_FIXED
4061 BFD_RELOC_NDS32_25_FIXED
4063 BFD_RELOC_NDS32_LONGCALL4
4065 BFD_RELOC_NDS32_LONGCALL5
4067 BFD_RELOC_NDS32_LONGCALL6
4069 BFD_RELOC_NDS32_LONGJUMP4
4071 BFD_RELOC_NDS32_LONGJUMP5
4073 BFD_RELOC_NDS32_LONGJUMP6
4075 BFD_RELOC_NDS32_LONGJUMP7
4079 BFD_RELOC_NDS32_PLTREL_HI20
4081 BFD_RELOC_NDS32_PLTREL_LO12
4083 BFD_RELOC_NDS32_PLT_GOTREL_HI20
4085 BFD_RELOC_NDS32_PLT_GOTREL_LO12
4089 BFD_RELOC_NDS32_SDA12S2_DP
4091 BFD_RELOC_NDS32_SDA12S2_SP
4093 BFD_RELOC_NDS32_LO12S2_DP
4095 BFD_RELOC_NDS32_LO12S2_SP
4099 BFD_RELOC_NDS32_DWARF2_OP1
4101 BFD_RELOC_NDS32_DWARF2_OP2
4103 BFD_RELOC_NDS32_DWARF2_LEB
4105 For dwarf2 debug_line.
4107 BFD_RELOC_NDS32_UPDATE_TA
4109 For eliminating 16-bit instructions.
4111 BFD_RELOC_NDS32_PLT_GOTREL_LO20
4113 BFD_RELOC_NDS32_PLT_GOTREL_LO15
4115 BFD_RELOC_NDS32_PLT_GOTREL_LO19
4117 BFD_RELOC_NDS32_GOT_LO15
4119 BFD_RELOC_NDS32_GOT_LO19
4121 BFD_RELOC_NDS32_GOTOFF_LO15
4123 BFD_RELOC_NDS32_GOTOFF_LO19
4125 BFD_RELOC_NDS32_GOT15S2
4127 BFD_RELOC_NDS32_GOT17S2
4129 For PIC object relaxation.
4134 This is a 5 bit absolute address.
4136 BFD_RELOC_NDS32_10_UPCREL
4138 This is a 10-bit unsigned pc-relative reloc with the right 1 bit
4141 BFD_RELOC_NDS32_SDA_FP7U2_RELA
4143 If fp were omitted, fp can used as another gp.
4145 BFD_RELOC_NDS32_RELAX_ENTRY
4147 BFD_RELOC_NDS32_GOT_SUFF
4149 BFD_RELOC_NDS32_GOTOFF_SUFF
4151 BFD_RELOC_NDS32_PLT_GOT_SUFF
4153 BFD_RELOC_NDS32_MULCALL_SUFF
4157 BFD_RELOC_NDS32_PTR_COUNT
4159 BFD_RELOC_NDS32_PTR_RESOLVED
4161 BFD_RELOC_NDS32_PLTBLOCK
4163 BFD_RELOC_NDS32_RELAX_REGION_BEGIN
4165 BFD_RELOC_NDS32_RELAX_REGION_END
4167 BFD_RELOC_NDS32_MINUEND
4169 BFD_RELOC_NDS32_SUBTRAHEND
4171 BFD_RELOC_NDS32_DIFF8
4173 BFD_RELOC_NDS32_DIFF16
4175 BFD_RELOC_NDS32_DIFF32
4177 BFD_RELOC_NDS32_DIFF_ULEB128
4179 BFD_RELOC_NDS32_EMPTY
4181 Relaxation relative relocation types.
4183 BFD_RELOC_NDS32_25_ABS
4185 This is a 25 bit absolute address.
4187 BFD_RELOC_NDS32_DATA
4189 BFD_RELOC_NDS32_TRAN
4191 BFD_RELOC_NDS32_17IFC_PCREL
4193 BFD_RELOC_NDS32_10IFCU_PCREL
4195 For ex9 and ifc using.
4197 BFD_RELOC_NDS32_TPOFF
4199 BFD_RELOC_NDS32_GOTTPOFF
4201 BFD_RELOC_NDS32_TLS_LE_HI20
4203 BFD_RELOC_NDS32_TLS_LE_LO12
4205 BFD_RELOC_NDS32_TLS_LE_20
4207 BFD_RELOC_NDS32_TLS_LE_15S0
4209 BFD_RELOC_NDS32_TLS_LE_15S1
4211 BFD_RELOC_NDS32_TLS_LE_15S2
4213 BFD_RELOC_NDS32_TLS_LE_ADD
4215 BFD_RELOC_NDS32_TLS_LE_LS
4217 BFD_RELOC_NDS32_TLS_IE_HI20
4219 BFD_RELOC_NDS32_TLS_IE_LO12
4221 BFD_RELOC_NDS32_TLS_IE_LO12S2
4223 BFD_RELOC_NDS32_TLS_IEGP_HI20
4225 BFD_RELOC_NDS32_TLS_IEGP_LO12
4227 BFD_RELOC_NDS32_TLS_IEGP_LO12S2
4229 BFD_RELOC_NDS32_TLS_IEGP_LW
4231 BFD_RELOC_NDS32_TLS_DESC
4233 BFD_RELOC_NDS32_TLS_DESC_HI20
4235 BFD_RELOC_NDS32_TLS_DESC_LO12
4237 BFD_RELOC_NDS32_TLS_DESC_20
4239 BFD_RELOC_NDS32_TLS_DESC_SDA17S2
4241 BFD_RELOC_NDS32_TLS_DESC_ADD
4243 BFD_RELOC_NDS32_TLS_DESC_FUNC
4245 BFD_RELOC_NDS32_TLS_DESC_CALL
4247 BFD_RELOC_NDS32_TLS_DESC_MEM
4249 BFD_RELOC_NDS32_REMOVE
4251 BFD_RELOC_NDS32_GROUP
4257 For floating load store relaxation.
4261 BFD_RELOC_V850_9_PCREL
4263 This is a 9-bit reloc.
4265 BFD_RELOC_V850_22_PCREL
4267 This is a 22-bit reloc.
4270 BFD_RELOC_V850_SDA_16_16_OFFSET
4272 This is a 16 bit offset from the short data area pointer.
4274 BFD_RELOC_V850_SDA_15_16_OFFSET
4276 This is a 16 bit offset (of which only 15 bits are used) from the
4277 short data area pointer.
4279 BFD_RELOC_V850_ZDA_16_16_OFFSET
4281 This is a 16 bit offset from the zero data area pointer.
4283 BFD_RELOC_V850_ZDA_15_16_OFFSET
4285 This is a 16 bit offset (of which only 15 bits are used) from the
4286 zero data area pointer.
4288 BFD_RELOC_V850_TDA_6_8_OFFSET
4290 This is an 8 bit offset (of which only 6 bits are used) from the
4291 tiny data area pointer.
4293 BFD_RELOC_V850_TDA_7_8_OFFSET
4295 This is an 8bit offset (of which only 7 bits are used) from the tiny
4298 BFD_RELOC_V850_TDA_7_7_OFFSET
4300 This is a 7 bit offset from the tiny data area pointer.
4302 BFD_RELOC_V850_TDA_16_16_OFFSET
4304 This is a 16 bit offset from the tiny data area pointer.
4306 BFD_RELOC_V850_TDA_4_5_OFFSET
4308 This is a 5 bit offset (of which only 4 bits are used) from the tiny
4311 BFD_RELOC_V850_TDA_4_4_OFFSET
4313 This is a 4 bit offset from the tiny data area pointer.
4315 BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET
4317 This is a 16 bit offset from the short data area pointer, with the
4318 bits placed non-contiguously in the instruction.
4320 BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET
4322 This is a 16 bit offset from the zero data area pointer, with the
4323 bits placed non-contiguously in the instruction.
4325 BFD_RELOC_V850_CALLT_6_7_OFFSET
4327 This is a 6 bit offset from the call table base pointer.
4329 BFD_RELOC_V850_CALLT_16_16_OFFSET
4331 This is a 16 bit offset from the call table base pointer.
4333 BFD_RELOC_V850_LONGCALL
4335 Used for relaxing indirect function calls.
4337 BFD_RELOC_V850_LONGJUMP
4339 Used for relaxing indirect jumps.
4341 BFD_RELOC_V850_ALIGN
4343 Used to maintain alignment whilst relaxing.
4345 BFD_RELOC_V850_LO16_SPLIT_OFFSET
4347 This is a variation of BFD_RELOC_LO16 that can be used in v850e
4350 BFD_RELOC_V850_16_PCREL
4352 This is a 16-bit reloc.
4354 BFD_RELOC_V850_17_PCREL
4356 This is a 17-bit reloc.
4360 This is a 23-bit reloc.
4362 BFD_RELOC_V850_32_PCREL
4364 This is a 32-bit reloc.
4366 BFD_RELOC_V850_32_ABS
4368 This is a 32-bit reloc.
4370 BFD_RELOC_V850_16_SPLIT_OFFSET
4372 This is a 16-bit reloc.
4374 BFD_RELOC_V850_16_S1
4376 This is a 16-bit reloc.
4378 BFD_RELOC_V850_LO16_S1
4380 Low 16 bits. 16 bit shifted by 1.
4382 BFD_RELOC_V850_CALLT_15_16_OFFSET
4384 This is a 16 bit offset from the call table base pointer.
4386 BFD_RELOC_V850_32_GOTPCREL
4388 BFD_RELOC_V850_16_GOT
4390 BFD_RELOC_V850_32_GOT
4392 BFD_RELOC_V850_22_PLT_PCREL
4394 BFD_RELOC_V850_32_PLT_PCREL
4398 BFD_RELOC_V850_GLOB_DAT
4400 BFD_RELOC_V850_JMP_SLOT
4402 BFD_RELOC_V850_RELATIVE
4404 BFD_RELOC_V850_16_GOTOFF
4406 BFD_RELOC_V850_32_GOTOFF
4421 This is a 8bit DP reloc for the tms320c30, where the most
4422 significant 8 bits of a 24 bit word are placed into the least
4423 significant 8 bits of the opcode.
4426 BFD_RELOC_TIC54X_PARTLS7
4428 This is a 7bit reloc for the tms320c54x, where the least
4429 significant 7 bits of a 16 bit word are placed into the least
4430 significant 7 bits of the opcode.
4433 BFD_RELOC_TIC54X_PARTMS9
4435 This is a 9bit DP reloc for the tms320c54x, where the most
4436 significant 9 bits of a 16 bit word are placed into the least
4437 significant 9 bits of the opcode.
4442 This is an extended address 23-bit reloc for the tms320c54x.
4445 BFD_RELOC_TIC54X_16_OF_23
4447 This is a 16-bit reloc for the tms320c54x, where the least
4448 significant 16 bits of a 23-bit extended address are placed into
4452 BFD_RELOC_TIC54X_MS7_OF_23
4454 This is a reloc for the tms320c54x, where the most
4455 significant 7 bits of a 23-bit extended address are placed into
4459 BFD_RELOC_C6000_PCR_S21
4461 BFD_RELOC_C6000_PCR_S12
4463 BFD_RELOC_C6000_PCR_S10
4465 BFD_RELOC_C6000_PCR_S7
4467 BFD_RELOC_C6000_ABS_S16
4469 BFD_RELOC_C6000_ABS_L16
4471 BFD_RELOC_C6000_ABS_H16
4473 BFD_RELOC_C6000_SBR_U15_B
4475 BFD_RELOC_C6000_SBR_U15_H
4477 BFD_RELOC_C6000_SBR_U15_W
4479 BFD_RELOC_C6000_SBR_S16
4481 BFD_RELOC_C6000_SBR_L16_B
4483 BFD_RELOC_C6000_SBR_L16_H
4485 BFD_RELOC_C6000_SBR_L16_W
4487 BFD_RELOC_C6000_SBR_H16_B
4489 BFD_RELOC_C6000_SBR_H16_H
4491 BFD_RELOC_C6000_SBR_H16_W
4493 BFD_RELOC_C6000_SBR_GOT_U15_W
4495 BFD_RELOC_C6000_SBR_GOT_L16_W
4497 BFD_RELOC_C6000_SBR_GOT_H16_W
4499 BFD_RELOC_C6000_DSBT_INDEX
4501 BFD_RELOC_C6000_PREL31
4503 BFD_RELOC_C6000_COPY
4505 BFD_RELOC_C6000_JUMP_SLOT
4507 BFD_RELOC_C6000_EHTYPE
4509 BFD_RELOC_C6000_PCR_H16
4511 BFD_RELOC_C6000_PCR_L16
4513 BFD_RELOC_C6000_ALIGN
4515 BFD_RELOC_C6000_FPHEAD
4517 BFD_RELOC_C6000_NOCMP
4519 TMS320C6000 relocations.
4524 This is a 48 bit reloc for the FR30 that stores 32 bits.
4528 This is a 32 bit reloc for the FR30 that stores 20 bits split up
4531 BFD_RELOC_FR30_6_IN_4
4533 This is a 16 bit reloc for the FR30 that stores a 6 bit word offset
4536 BFD_RELOC_FR30_8_IN_8
4538 This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset
4541 BFD_RELOC_FR30_9_IN_8
4543 This is a 16 bit reloc for the FR30 that stores a 9 bit short offset
4546 BFD_RELOC_FR30_10_IN_8
4548 This is a 16 bit reloc for the FR30 that stores a 10 bit word offset
4551 BFD_RELOC_FR30_9_PCREL
4553 This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative
4554 short offset into 8 bits.
4556 BFD_RELOC_FR30_12_PCREL
4558 This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative
4559 short offset into 11 bits.
4562 BFD_RELOC_MCORE_PCREL_IMM8BY4
4564 BFD_RELOC_MCORE_PCREL_IMM11BY2
4566 BFD_RELOC_MCORE_PCREL_IMM4BY2
4568 BFD_RELOC_MCORE_PCREL_32
4570 BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2
4574 Motorola Mcore relocations.
4583 BFD_RELOC_MEP_PCREL8A2
4585 BFD_RELOC_MEP_PCREL12A2
4587 BFD_RELOC_MEP_PCREL17A2
4589 BFD_RELOC_MEP_PCREL24A2
4591 BFD_RELOC_MEP_PCABS24A2
4603 BFD_RELOC_MEP_TPREL7
4605 BFD_RELOC_MEP_TPREL7A2
4607 BFD_RELOC_MEP_TPREL7A4
4609 BFD_RELOC_MEP_UIMM24
4611 BFD_RELOC_MEP_ADDR24A4
4613 BFD_RELOC_MEP_GNU_VTINHERIT
4615 BFD_RELOC_MEP_GNU_VTENTRY
4617 Toshiba Media Processor Relocations.
4620 BFD_RELOC_METAG_HIADDR16
4622 BFD_RELOC_METAG_LOADDR16
4624 BFD_RELOC_METAG_RELBRANCH
4626 BFD_RELOC_METAG_GETSETOFF
4628 BFD_RELOC_METAG_HIOG
4630 BFD_RELOC_METAG_LOOG
4632 BFD_RELOC_METAG_REL8
4634 BFD_RELOC_METAG_REL16
4636 BFD_RELOC_METAG_HI16_GOTOFF
4638 BFD_RELOC_METAG_LO16_GOTOFF
4640 BFD_RELOC_METAG_GETSET_GOTOFF
4642 BFD_RELOC_METAG_GETSET_GOT
4644 BFD_RELOC_METAG_HI16_GOTPC
4646 BFD_RELOC_METAG_LO16_GOTPC
4648 BFD_RELOC_METAG_HI16_PLT
4650 BFD_RELOC_METAG_LO16_PLT
4652 BFD_RELOC_METAG_RELBRANCH_PLT
4654 BFD_RELOC_METAG_GOTOFF
4658 BFD_RELOC_METAG_COPY
4660 BFD_RELOC_METAG_JMP_SLOT
4662 BFD_RELOC_METAG_RELATIVE
4664 BFD_RELOC_METAG_GLOB_DAT
4666 BFD_RELOC_METAG_TLS_GD
4668 BFD_RELOC_METAG_TLS_LDM
4670 BFD_RELOC_METAG_TLS_LDO_HI16
4672 BFD_RELOC_METAG_TLS_LDO_LO16
4674 BFD_RELOC_METAG_TLS_LDO
4676 BFD_RELOC_METAG_TLS_IE
4678 BFD_RELOC_METAG_TLS_IENONPIC
4680 BFD_RELOC_METAG_TLS_IENONPIC_HI16
4682 BFD_RELOC_METAG_TLS_IENONPIC_LO16
4684 BFD_RELOC_METAG_TLS_TPOFF
4686 BFD_RELOC_METAG_TLS_DTPMOD
4688 BFD_RELOC_METAG_TLS_DTPOFF
4690 BFD_RELOC_METAG_TLS_LE
4692 BFD_RELOC_METAG_TLS_LE_HI16
4694 BFD_RELOC_METAG_TLS_LE_LO16
4696 Imagination Technologies Meta relocations.
4701 BFD_RELOC_MMIX_GETA_1
4703 BFD_RELOC_MMIX_GETA_2
4705 BFD_RELOC_MMIX_GETA_3
4707 These are relocations for the GETA instruction.
4709 BFD_RELOC_MMIX_CBRANCH
4711 BFD_RELOC_MMIX_CBRANCH_J
4713 BFD_RELOC_MMIX_CBRANCH_1
4715 BFD_RELOC_MMIX_CBRANCH_2
4717 BFD_RELOC_MMIX_CBRANCH_3
4719 These are relocations for a conditional branch instruction.
4721 BFD_RELOC_MMIX_PUSHJ
4723 BFD_RELOC_MMIX_PUSHJ_1
4725 BFD_RELOC_MMIX_PUSHJ_2
4727 BFD_RELOC_MMIX_PUSHJ_3
4729 BFD_RELOC_MMIX_PUSHJ_STUBBABLE
4731 These are relocations for the PUSHJ instruction.
4735 BFD_RELOC_MMIX_JMP_1
4737 BFD_RELOC_MMIX_JMP_2
4739 BFD_RELOC_MMIX_JMP_3
4741 These are relocations for the JMP instruction.
4743 BFD_RELOC_MMIX_ADDR19
4745 This is a relocation for a relative address as in a GETA instruction
4748 BFD_RELOC_MMIX_ADDR27
4750 This is a relocation for a relative address as in a JMP instruction.
4752 BFD_RELOC_MMIX_REG_OR_BYTE
4754 This is a relocation for an instruction field that may be a general
4755 register or a value 0..255.
4759 This is a relocation for an instruction field that may be a general
4762 BFD_RELOC_MMIX_BASE_PLUS_OFFSET
4764 This is a relocation for two instruction fields holding a register
4765 and an offset, the equivalent of the relocation.
4767 BFD_RELOC_MMIX_LOCAL
4769 This relocation is an assertion that the expression is not allocated
4770 as a global register. It does not modify contents.
4773 BFD_RELOC_AVR_7_PCREL
4775 This is a 16 bit reloc for the AVR that stores 8 bit pc relative
4776 short offset into 7 bits.
4778 BFD_RELOC_AVR_13_PCREL
4780 This is a 16 bit reloc for the AVR that stores 13 bit pc relative
4781 short offset into 12 bits.
4785 This is a 16 bit reloc for the AVR that stores 17 bit value (usually
4786 program memory address) into 16 bits.
4788 BFD_RELOC_AVR_LO8_LDI
4790 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
4791 data memory address) into 8 bit immediate value of LDI insn.
4793 BFD_RELOC_AVR_HI8_LDI
4795 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4796 of data memory address) into 8 bit immediate value of LDI insn.
4798 BFD_RELOC_AVR_HH8_LDI
4800 This is a 16 bit reloc for the AVR that stores 8 bit value (most
4801 high 8 bit of program memory address) into 8 bit immediate value of
4804 BFD_RELOC_AVR_MS8_LDI
4806 This is a 16 bit reloc for the AVR that stores 8 bit value (most
4807 high 8 bit of 32 bit value) into 8 bit immediate value of LDI insn.
4809 BFD_RELOC_AVR_LO8_LDI_NEG
4811 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4812 (usually data memory address) into 8 bit immediate value of SUBI insn.
4814 BFD_RELOC_AVR_HI8_LDI_NEG
4816 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4817 (high 8 bit of data memory address) into 8 bit immediate value of
4820 BFD_RELOC_AVR_HH8_LDI_NEG
4822 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4823 (most high 8 bit of program memory address) into 8 bit immediate
4824 value of LDI or SUBI insn.
4826 BFD_RELOC_AVR_MS8_LDI_NEG
4828 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4829 (msb of 32 bit value) into 8 bit immediate value of LDI insn.
4831 BFD_RELOC_AVR_LO8_LDI_PM
4833 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
4834 command address) into 8 bit immediate value of LDI insn.
4836 BFD_RELOC_AVR_LO8_LDI_GS
4838 This is a 16 bit reloc for the AVR that stores 8 bit value
4839 (command address) into 8 bit immediate value of LDI insn. If the
4840 address is beyond the 128k boundary, the linker inserts a jump stub
4841 for this reloc in the lower 128k.
4843 BFD_RELOC_AVR_HI8_LDI_PM
4845 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4846 of command address) into 8 bit immediate value of LDI insn.
4848 BFD_RELOC_AVR_HI8_LDI_GS
4850 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4851 of command address) into 8 bit immediate value of LDI insn. If the
4852 address is beyond the 128k boundary, the linker inserts a jump stub
4853 for this reloc below 128k.
4855 BFD_RELOC_AVR_HH8_LDI_PM
4857 This is a 16 bit reloc for the AVR that stores 8 bit value (most
4858 high 8 bit of command address) into 8 bit immediate value of LDI
4861 BFD_RELOC_AVR_LO8_LDI_PM_NEG
4863 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4864 (usually command address) into 8 bit immediate value of SUBI insn.
4866 BFD_RELOC_AVR_HI8_LDI_PM_NEG
4868 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4869 (high 8 bit of 16 bit command address) into 8 bit immediate value
4872 BFD_RELOC_AVR_HH8_LDI_PM_NEG
4874 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4875 (high 6 bit of 22 bit command address) into 8 bit immediate
4880 This is a 32 bit reloc for the AVR that stores 23 bit value
4885 This is a 16 bit reloc for the AVR that stores all needed bits
4886 for absolute addressing with ldi with overflow check to linktime.
4890 This is a 6 bit reloc for the AVR that stores offset for ldd/std
4893 BFD_RELOC_AVR_6_ADIW
4895 This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw
4900 This is a 8 bit reloc for the AVR that stores bits 0..7 of a symbol
4901 in .byte lo8(symbol).
4905 This is a 8 bit reloc for the AVR that stores bits 8..15 of a symbol
4906 in .byte hi8(symbol).
4910 This is a 8 bit reloc for the AVR that stores bits 16..23 of a symbol
4911 in .byte hlo8(symbol).
4915 BFD_RELOC_AVR_DIFF16
4917 BFD_RELOC_AVR_DIFF32
4919 AVR relocations to mark the difference of two local symbols.
4920 These are only needed to support linker relaxation and can be ignored
4921 when not relaxing. The field is set to the value of the difference
4922 assuming no relaxation. The relocation encodes the position of the
4923 second symbol so the linker can determine whether to adjust the field
4926 BFD_RELOC_AVR_LDS_STS_16
4928 This is a 7 bit reloc for the AVR that stores SRAM address for 16bit
4929 lds and sts instructions supported only tiny core.
4933 This is a 6 bit reloc for the AVR that stores an I/O register
4934 number for the IN and OUT instructions.
4938 This is a 5 bit reloc for the AVR that stores an I/O register
4939 number for the SBIC, SBIS, SBI and CBI instructions.
4942 BFD_RELOC_RISCV_HI20
4944 BFD_RELOC_RISCV_PCREL_HI20
4946 BFD_RELOC_RISCV_PCREL_LO12_I
4948 BFD_RELOC_RISCV_PCREL_LO12_S
4950 BFD_RELOC_RISCV_LO12_I
4952 BFD_RELOC_RISCV_LO12_S
4954 BFD_RELOC_RISCV_GPREL12_I
4956 BFD_RELOC_RISCV_GPREL12_S
4958 BFD_RELOC_RISCV_TPREL_HI20
4960 BFD_RELOC_RISCV_TPREL_LO12_I
4962 BFD_RELOC_RISCV_TPREL_LO12_S
4964 BFD_RELOC_RISCV_TPREL_ADD
4966 BFD_RELOC_RISCV_CALL
4968 BFD_RELOC_RISCV_CALL_PLT
4970 BFD_RELOC_RISCV_ADD8
4972 BFD_RELOC_RISCV_ADD16
4974 BFD_RELOC_RISCV_ADD32
4976 BFD_RELOC_RISCV_ADD64
4978 BFD_RELOC_RISCV_SUB8
4980 BFD_RELOC_RISCV_SUB16
4982 BFD_RELOC_RISCV_SUB32
4984 BFD_RELOC_RISCV_SUB64
4986 BFD_RELOC_RISCV_GOT_HI20
4988 BFD_RELOC_RISCV_TLS_GOT_HI20
4990 BFD_RELOC_RISCV_TLS_GD_HI20
4994 BFD_RELOC_RISCV_TLS_DTPMOD32
4996 BFD_RELOC_RISCV_TLS_DTPREL32
4998 BFD_RELOC_RISCV_TLS_DTPMOD64
5000 BFD_RELOC_RISCV_TLS_DTPREL64
5002 BFD_RELOC_RISCV_TLS_TPREL32
5004 BFD_RELOC_RISCV_TLS_TPREL64
5006 BFD_RELOC_RISCV_TLSDESC_HI20
5008 BFD_RELOC_RISCV_TLSDESC_LOAD_LO12
5010 BFD_RELOC_RISCV_TLSDESC_ADD_LO12
5012 BFD_RELOC_RISCV_TLSDESC_CALL
5014 BFD_RELOC_RISCV_ALIGN
5016 BFD_RELOC_RISCV_RVC_BRANCH
5018 BFD_RELOC_RISCV_RVC_JUMP
5020 BFD_RELOC_RISCV_RELAX
5024 BFD_RELOC_RISCV_SUB6
5026 BFD_RELOC_RISCV_SET6
5028 BFD_RELOC_RISCV_SET8
5030 BFD_RELOC_RISCV_SET16
5032 BFD_RELOC_RISCV_SET32
5034 BFD_RELOC_RISCV_32_PCREL
5036 BFD_RELOC_RISCV_SET_ULEB128
5038 BFD_RELOC_RISCV_SUB_ULEB128
5045 BFD_RELOC_RL78_NEG16
5047 BFD_RELOC_RL78_NEG24
5049 BFD_RELOC_RL78_NEG32
5051 BFD_RELOC_RL78_16_OP
5053 BFD_RELOC_RL78_24_OP
5055 BFD_RELOC_RL78_32_OP
5063 BFD_RELOC_RL78_DIR3U_PCREL
5067 BFD_RELOC_RL78_GPRELB
5069 BFD_RELOC_RL78_GPRELW
5071 BFD_RELOC_RL78_GPRELL
5075 BFD_RELOC_RL78_OP_SUBTRACT
5077 BFD_RELOC_RL78_OP_NEG
5079 BFD_RELOC_RL78_OP_AND
5081 BFD_RELOC_RL78_OP_SHRA
5085 BFD_RELOC_RL78_ABS16
5087 BFD_RELOC_RL78_ABS16_REV
5089 BFD_RELOC_RL78_ABS32
5091 BFD_RELOC_RL78_ABS32_REV
5093 BFD_RELOC_RL78_ABS16U
5095 BFD_RELOC_RL78_ABS16UW
5097 BFD_RELOC_RL78_ABS16UL
5099 BFD_RELOC_RL78_RELAX
5109 BFD_RELOC_RL78_SADDR
5111 Renesas RL78 Relocations.
5134 BFD_RELOC_RX_DIR3U_PCREL
5146 BFD_RELOC_RX_OP_SUBTRACT
5154 BFD_RELOC_RX_ABS16_REV
5158 BFD_RELOC_RX_ABS32_REV
5162 BFD_RELOC_RX_ABS16UW
5164 BFD_RELOC_RX_ABS16UL
5168 Renesas RX Relocations.
5181 32 bit PC relative PLT address.
5185 Copy symbol at runtime.
5187 BFD_RELOC_390_GLOB_DAT
5191 BFD_RELOC_390_JMP_SLOT
5195 BFD_RELOC_390_RELATIVE
5197 Adjust by program base.
5201 32 bit PC relative offset to GOT.
5207 BFD_RELOC_390_PC12DBL
5209 PC relative 12 bit shifted by 1.
5211 BFD_RELOC_390_PLT12DBL
5213 12 bit PC rel. PLT shifted by 1.
5215 BFD_RELOC_390_PC16DBL
5217 PC relative 16 bit shifted by 1.
5219 BFD_RELOC_390_PLT16DBL
5221 16 bit PC rel. PLT shifted by 1.
5223 BFD_RELOC_390_PC24DBL
5225 PC relative 24 bit shifted by 1.
5227 BFD_RELOC_390_PLT24DBL
5229 24 bit PC rel. PLT shifted by 1.
5231 BFD_RELOC_390_PC32DBL
5233 PC relative 32 bit shifted by 1.
5235 BFD_RELOC_390_PLT32DBL
5237 32 bit PC rel. PLT shifted by 1.
5239 BFD_RELOC_390_GOTPCDBL
5241 32 bit PC rel. GOT shifted by 1.
5249 64 bit PC relative PLT address.
5251 BFD_RELOC_390_GOTENT
5253 32 bit rel. offset to GOT entry.
5255 BFD_RELOC_390_GOTOFF64
5257 64 bit offset to GOT.
5259 BFD_RELOC_390_GOTPLT12
5261 12-bit offset to symbol-entry within GOT, with PLT handling.
5263 BFD_RELOC_390_GOTPLT16
5265 16-bit offset to symbol-entry within GOT, with PLT handling.
5267 BFD_RELOC_390_GOTPLT32
5269 32-bit offset to symbol-entry within GOT, with PLT handling.
5271 BFD_RELOC_390_GOTPLT64
5273 64-bit offset to symbol-entry within GOT, with PLT handling.
5275 BFD_RELOC_390_GOTPLTENT
5277 32-bit rel. offset to symbol-entry within GOT, with PLT handling.
5279 BFD_RELOC_390_PLTOFF16
5281 16-bit rel. offset from the GOT to a PLT entry.
5283 BFD_RELOC_390_PLTOFF32
5285 32-bit rel. offset from the GOT to a PLT entry.
5287 BFD_RELOC_390_PLTOFF64
5289 64-bit rel. offset from the GOT to a PLT entry.
5292 BFD_RELOC_390_TLS_LOAD
5294 BFD_RELOC_390_TLS_GDCALL
5296 BFD_RELOC_390_TLS_LDCALL
5298 BFD_RELOC_390_TLS_GD32
5300 BFD_RELOC_390_TLS_GD64
5302 BFD_RELOC_390_TLS_GOTIE12
5304 BFD_RELOC_390_TLS_GOTIE32
5306 BFD_RELOC_390_TLS_GOTIE64
5308 BFD_RELOC_390_TLS_LDM32
5310 BFD_RELOC_390_TLS_LDM64
5312 BFD_RELOC_390_TLS_IE32
5314 BFD_RELOC_390_TLS_IE64
5316 BFD_RELOC_390_TLS_IEENT
5318 BFD_RELOC_390_TLS_LE32
5320 BFD_RELOC_390_TLS_LE64
5322 BFD_RELOC_390_TLS_LDO32
5324 BFD_RELOC_390_TLS_LDO64
5326 BFD_RELOC_390_TLS_DTPMOD
5328 BFD_RELOC_390_TLS_DTPOFF
5330 BFD_RELOC_390_TLS_TPOFF
5332 s390 tls relocations.
5339 BFD_RELOC_390_GOTPLT20
5341 BFD_RELOC_390_TLS_GOTIE20
5343 Long displacement extension.
5346 BFD_RELOC_390_IRELATIVE
5348 STT_GNU_IFUNC relocation.
5351 BFD_RELOC_SCORE_GPREL15
5354 Low 16 bit for load/store.
5356 BFD_RELOC_SCORE_DUMMY2
5360 This is a 24-bit reloc with the right 1 bit assumed to be 0.
5362 BFD_RELOC_SCORE_BRANCH
5364 This is a 19-bit reloc with the right 1 bit assumed to be 0.
5366 BFD_RELOC_SCORE_IMM30
5368 This is a 32-bit reloc for 48-bit instructions.
5370 BFD_RELOC_SCORE_IMM32
5372 This is a 32-bit reloc for 48-bit instructions.
5374 BFD_RELOC_SCORE16_JMP
5376 This is a 11-bit reloc with the right 1 bit assumed to be 0.
5378 BFD_RELOC_SCORE16_BRANCH
5380 This is a 8-bit reloc with the right 1 bit assumed to be 0.
5382 BFD_RELOC_SCORE_BCMP
5384 This is a 9-bit reloc with the right 1 bit assumed to be 0.
5386 BFD_RELOC_SCORE_GOT15
5388 BFD_RELOC_SCORE_GOT_LO16
5390 BFD_RELOC_SCORE_CALL15
5392 BFD_RELOC_SCORE_DUMMY_HI16
5394 Undocumented Score relocs.
5399 Scenix IP2K - 9-bit register number / data address.
5403 Scenix IP2K - 4-bit register/data bank number.
5405 BFD_RELOC_IP2K_ADDR16CJP
5407 Scenix IP2K - low 13 bits of instruction word address.
5409 BFD_RELOC_IP2K_PAGE3
5411 Scenix IP2K - high 3 bits of instruction word address.
5413 BFD_RELOC_IP2K_LO8DATA
5415 BFD_RELOC_IP2K_HI8DATA
5417 BFD_RELOC_IP2K_EX8DATA
5419 Scenix IP2K - ext/low/high 8 bits of data address.
5421 BFD_RELOC_IP2K_LO8INSN
5423 BFD_RELOC_IP2K_HI8INSN
5425 Scenix IP2K - low/high 8 bits of instruction word address.
5427 BFD_RELOC_IP2K_PC_SKIP
5429 Scenix IP2K - even/odd PC modifier to modify snb pcl.0.
5433 Scenix IP2K - 16 bit word address in text section.
5435 BFD_RELOC_IP2K_FR_OFFSET
5437 Scenix IP2K - 7-bit sp or dp offset.
5439 BFD_RELOC_VPE4KMATH_DATA
5441 BFD_RELOC_VPE4KMATH_INSN
5443 Scenix VPE4K coprocessor - data/insn-space addressing.
5446 BFD_RELOC_VTABLE_INHERIT
5448 BFD_RELOC_VTABLE_ENTRY
5450 These two relocations are used by the linker to determine which of
5451 the entries in a C++ virtual function table are actually used. When
5452 the --gc-sections option is given, the linker will zero out the
5453 entries that are not used, so that the code for those functions need
5454 not be included in the output.
5456 VTABLE_INHERIT is a zero-space relocation used to describe to the
5457 linker the inheritance tree of a C++ virtual function table. The
5458 relocation's symbol should be the parent class' vtable, and the
5459 relocation should be located at the child vtable.
5461 VTABLE_ENTRY is a zero-space relocation that describes the use of a
5462 virtual function table entry. The reloc's symbol should refer to
5463 the table of the class mentioned in the code. Off of that base, an
5464 offset describes the entry that is being used. For Rela hosts, this
5465 offset is stored in the reloc's addend. For Rel hosts, we are
5466 forced to put this offset in the reloc's section offset.
5469 BFD_RELOC_IA64_IMM14
5471 BFD_RELOC_IA64_IMM22
5473 BFD_RELOC_IA64_IMM64
5475 BFD_RELOC_IA64_DIR32MSB
5477 BFD_RELOC_IA64_DIR32LSB
5479 BFD_RELOC_IA64_DIR64MSB
5481 BFD_RELOC_IA64_DIR64LSB
5483 BFD_RELOC_IA64_GPREL22
5485 BFD_RELOC_IA64_GPREL64I
5487 BFD_RELOC_IA64_GPREL32MSB
5489 BFD_RELOC_IA64_GPREL32LSB
5491 BFD_RELOC_IA64_GPREL64MSB
5493 BFD_RELOC_IA64_GPREL64LSB
5495 BFD_RELOC_IA64_LTOFF22
5497 BFD_RELOC_IA64_LTOFF64I
5499 BFD_RELOC_IA64_PLTOFF22
5501 BFD_RELOC_IA64_PLTOFF64I
5503 BFD_RELOC_IA64_PLTOFF64MSB
5505 BFD_RELOC_IA64_PLTOFF64LSB
5507 BFD_RELOC_IA64_FPTR64I
5509 BFD_RELOC_IA64_FPTR32MSB
5511 BFD_RELOC_IA64_FPTR32LSB
5513 BFD_RELOC_IA64_FPTR64MSB
5515 BFD_RELOC_IA64_FPTR64LSB
5517 BFD_RELOC_IA64_PCREL21B
5519 BFD_RELOC_IA64_PCREL21BI
5521 BFD_RELOC_IA64_PCREL21M
5523 BFD_RELOC_IA64_PCREL21F
5525 BFD_RELOC_IA64_PCREL22
5527 BFD_RELOC_IA64_PCREL60B
5529 BFD_RELOC_IA64_PCREL64I
5531 BFD_RELOC_IA64_PCREL32MSB
5533 BFD_RELOC_IA64_PCREL32LSB
5535 BFD_RELOC_IA64_PCREL64MSB
5537 BFD_RELOC_IA64_PCREL64LSB
5539 BFD_RELOC_IA64_LTOFF_FPTR22
5541 BFD_RELOC_IA64_LTOFF_FPTR64I
5543 BFD_RELOC_IA64_LTOFF_FPTR32MSB
5545 BFD_RELOC_IA64_LTOFF_FPTR32LSB
5547 BFD_RELOC_IA64_LTOFF_FPTR64MSB
5549 BFD_RELOC_IA64_LTOFF_FPTR64LSB
5551 BFD_RELOC_IA64_SEGREL32MSB
5553 BFD_RELOC_IA64_SEGREL32LSB
5555 BFD_RELOC_IA64_SEGREL64MSB
5557 BFD_RELOC_IA64_SEGREL64LSB
5559 BFD_RELOC_IA64_SECREL32MSB
5561 BFD_RELOC_IA64_SECREL32LSB
5563 BFD_RELOC_IA64_SECREL64MSB
5565 BFD_RELOC_IA64_SECREL64LSB
5567 BFD_RELOC_IA64_REL32MSB
5569 BFD_RELOC_IA64_REL32LSB
5571 BFD_RELOC_IA64_REL64MSB
5573 BFD_RELOC_IA64_REL64LSB
5575 BFD_RELOC_IA64_LTV32MSB
5577 BFD_RELOC_IA64_LTV32LSB
5579 BFD_RELOC_IA64_LTV64MSB
5581 BFD_RELOC_IA64_LTV64LSB
5583 BFD_RELOC_IA64_IPLTMSB
5585 BFD_RELOC_IA64_IPLTLSB
5589 BFD_RELOC_IA64_LTOFF22X
5591 BFD_RELOC_IA64_LDXMOV
5593 BFD_RELOC_IA64_TPREL14
5595 BFD_RELOC_IA64_TPREL22
5597 BFD_RELOC_IA64_TPREL64I
5599 BFD_RELOC_IA64_TPREL64MSB
5601 BFD_RELOC_IA64_TPREL64LSB
5603 BFD_RELOC_IA64_LTOFF_TPREL22
5605 BFD_RELOC_IA64_DTPMOD64MSB
5607 BFD_RELOC_IA64_DTPMOD64LSB
5609 BFD_RELOC_IA64_LTOFF_DTPMOD22
5611 BFD_RELOC_IA64_DTPREL14
5613 BFD_RELOC_IA64_DTPREL22
5615 BFD_RELOC_IA64_DTPREL64I
5617 BFD_RELOC_IA64_DTPREL32MSB
5619 BFD_RELOC_IA64_DTPREL32LSB
5621 BFD_RELOC_IA64_DTPREL64MSB
5623 BFD_RELOC_IA64_DTPREL64LSB
5625 BFD_RELOC_IA64_LTOFF_DTPREL22
5627 Intel IA64 Relocations.
5630 BFD_RELOC_M68HC11_HI8
5632 Motorola 68HC11 reloc.
5633 This is the 8 bit high part of an absolute address.
5635 BFD_RELOC_M68HC11_LO8
5637 Motorola 68HC11 reloc.
5638 This is the 8 bit low part of an absolute address.
5640 BFD_RELOC_M68HC11_3B
5642 Motorola 68HC11 reloc.
5643 This is the 3 bit of a value.
5645 BFD_RELOC_M68HC11_RL_JUMP
5647 Motorola 68HC11 reloc.
5648 This reloc marks the beginning of a jump/call instruction.
5649 It is used for linker relaxation to correctly identify beginning
5650 of instruction and change some branches to use PC-relative
5653 BFD_RELOC_M68HC11_RL_GROUP
5655 Motorola 68HC11 reloc.
5656 This reloc marks a group of several instructions that gcc generates
5657 and for which the linker relaxation pass can modify and/or remove
5660 BFD_RELOC_M68HC11_LO16
5662 Motorola 68HC11 reloc.
5663 This is the 16-bit lower part of an address. It is used for 'call'
5664 instruction to specify the symbol address without any special
5665 transformation (due to memory bank window).
5667 BFD_RELOC_M68HC11_PAGE
5669 Motorola 68HC11 reloc.
5670 This is a 8-bit reloc that specifies the page number of an address.
5671 It is used by 'call' instruction to specify the page number of
5674 BFD_RELOC_M68HC11_24
5676 Motorola 68HC11 reloc.
5677 This is a 24-bit reloc that represents the address with a 16-bit
5678 value and a 8-bit page number. The symbol address is transformed
5679 to follow the 16K memory bank of 68HC12 (seen as mapped in the
5682 BFD_RELOC_M68HC12_5B
5684 Motorola 68HC12 reloc.
5685 This is the 5 bits of a value.
5687 BFD_RELOC_XGATE_RL_JUMP
5689 Freescale XGATE reloc.
5690 This reloc marks the beginning of a bra/jal instruction.
5692 BFD_RELOC_XGATE_RL_GROUP
5694 Freescale XGATE reloc.
5695 This reloc marks a group of several instructions that gcc generates
5696 and for which the linker relaxation pass can modify and/or remove
5699 BFD_RELOC_XGATE_LO16
5701 Freescale XGATE reloc.
5702 This is the 16-bit lower part of an address. It is used for the
5703 '16-bit' instructions.
5705 BFD_RELOC_XGATE_GPAGE
5707 Freescale XGATE reloc.
5711 Freescale XGATE reloc.
5713 BFD_RELOC_XGATE_PCREL_9
5715 Freescale XGATE reloc.
5716 This is a 9-bit pc-relative reloc.
5718 BFD_RELOC_XGATE_PCREL_10
5720 Freescale XGATE reloc.
5721 This is a 10-bit pc-relative reloc.
5723 BFD_RELOC_XGATE_IMM8_LO
5725 Freescale XGATE reloc.
5726 This is the 16-bit lower part of an address. It is used for the
5727 '16-bit' instructions.
5729 BFD_RELOC_XGATE_IMM8_HI
5731 Freescale XGATE reloc.
5732 This is the 16-bit higher part of an address. It is used for the
5733 '16-bit' instructions.
5735 BFD_RELOC_XGATE_IMM3
5737 Freescale XGATE reloc.
5738 This is a 3-bit pc-relative reloc.
5740 BFD_RELOC_XGATE_IMM4
5742 Freescale XGATE reloc.
5743 This is a 4-bit pc-relative reloc.
5745 BFD_RELOC_XGATE_IMM5
5747 Freescale XGATE reloc.
5748 This is a 5-bit pc-relative reloc.
5750 BFD_RELOC_M68HC12_9B
5752 Motorola 68HC12 reloc.
5753 This is the 9 bits of a value.
5755 BFD_RELOC_M68HC12_16B
5757 Motorola 68HC12 reloc.
5758 This is the 16 bits of a value.
5760 BFD_RELOC_M68HC12_9_PCREL
5762 Motorola 68HC12/XGATE reloc.
5763 This is a PCREL9 branch.
5765 BFD_RELOC_M68HC12_10_PCREL
5767 Motorola 68HC12/XGATE reloc.
5768 This is a PCREL10 branch.
5770 BFD_RELOC_M68HC12_LO8XG
5772 Motorola 68HC12/XGATE reloc.
5773 This is the 8 bit low part of an absolute address and immediately
5774 precedes a matching HI8XG part.
5776 BFD_RELOC_M68HC12_HI8XG
5778 Motorola 68HC12/XGATE reloc.
5779 This is the 8 bit high part of an absolute address and immediately
5780 follows a matching LO8XG part.
5782 BFD_RELOC_S12Z_15_PCREL
5784 Freescale S12Z reloc.
5785 This is a 15 bit relative address. If the most significant bits are
5786 all zero then it may be truncated to 8 bits.
5791 BFD_RELOC_CR16_NUM16
5793 BFD_RELOC_CR16_NUM32
5795 BFD_RELOC_CR16_NUM32a
5797 BFD_RELOC_CR16_REGREL0
5799 BFD_RELOC_CR16_REGREL4
5801 BFD_RELOC_CR16_REGREL4a
5803 BFD_RELOC_CR16_REGREL14
5805 BFD_RELOC_CR16_REGREL14a
5807 BFD_RELOC_CR16_REGREL16
5809 BFD_RELOC_CR16_REGREL20
5811 BFD_RELOC_CR16_REGREL20a
5813 BFD_RELOC_CR16_ABS20
5815 BFD_RELOC_CR16_ABS24
5821 BFD_RELOC_CR16_IMM16
5823 BFD_RELOC_CR16_IMM20
5825 BFD_RELOC_CR16_IMM24
5827 BFD_RELOC_CR16_IMM32
5829 BFD_RELOC_CR16_IMM32a
5831 BFD_RELOC_CR16_DISP4
5833 BFD_RELOC_CR16_DISP8
5835 BFD_RELOC_CR16_DISP16
5837 BFD_RELOC_CR16_DISP20
5839 BFD_RELOC_CR16_DISP24
5841 BFD_RELOC_CR16_DISP24a
5843 BFD_RELOC_CR16_SWITCH8
5845 BFD_RELOC_CR16_SWITCH16
5847 BFD_RELOC_CR16_SWITCH32
5849 BFD_RELOC_CR16_GOT_REGREL20
5851 BFD_RELOC_CR16_GOTC_REGREL20
5853 BFD_RELOC_CR16_GLOB_DAT
5855 NS CR16 Relocations.
5862 BFD_RELOC_CRX_REL8_CMP
5870 BFD_RELOC_CRX_REGREL12
5872 BFD_RELOC_CRX_REGREL22
5874 BFD_RELOC_CRX_REGREL28
5876 BFD_RELOC_CRX_REGREL32
5892 BFD_RELOC_CRX_SWITCH8
5894 BFD_RELOC_CRX_SWITCH16
5896 BFD_RELOC_CRX_SWITCH32
5901 BFD_RELOC_CRIS_BDISP8
5903 BFD_RELOC_CRIS_UNSIGNED_5
5905 BFD_RELOC_CRIS_SIGNED_6
5907 BFD_RELOC_CRIS_UNSIGNED_6
5909 BFD_RELOC_CRIS_SIGNED_8
5911 BFD_RELOC_CRIS_UNSIGNED_8
5913 BFD_RELOC_CRIS_SIGNED_16
5915 BFD_RELOC_CRIS_UNSIGNED_16
5917 BFD_RELOC_CRIS_LAPCQ_OFFSET
5919 BFD_RELOC_CRIS_UNSIGNED_4
5921 These relocs are only used within the CRIS assembler. They are not
5922 (at present) written to any object files.
5926 BFD_RELOC_CRIS_GLOB_DAT
5928 BFD_RELOC_CRIS_JUMP_SLOT
5930 BFD_RELOC_CRIS_RELATIVE
5932 Relocs used in ELF shared libraries for CRIS.
5934 BFD_RELOC_CRIS_32_GOT
5936 32-bit offset to symbol-entry within GOT.
5938 BFD_RELOC_CRIS_16_GOT
5940 16-bit offset to symbol-entry within GOT.
5942 BFD_RELOC_CRIS_32_GOTPLT
5944 32-bit offset to symbol-entry within GOT, with PLT handling.
5946 BFD_RELOC_CRIS_16_GOTPLT
5948 16-bit offset to symbol-entry within GOT, with PLT handling.
5950 BFD_RELOC_CRIS_32_GOTREL
5952 32-bit offset to symbol, relative to GOT.
5954 BFD_RELOC_CRIS_32_PLT_GOTREL
5956 32-bit offset to symbol with PLT entry, relative to GOT.
5958 BFD_RELOC_CRIS_32_PLT_PCREL
5960 32-bit offset to symbol with PLT entry, relative to this
5964 BFD_RELOC_CRIS_32_GOT_GD
5966 BFD_RELOC_CRIS_16_GOT_GD
5968 BFD_RELOC_CRIS_32_GD
5972 BFD_RELOC_CRIS_32_DTPREL
5974 BFD_RELOC_CRIS_16_DTPREL
5976 BFD_RELOC_CRIS_32_GOT_TPREL
5978 BFD_RELOC_CRIS_16_GOT_TPREL
5980 BFD_RELOC_CRIS_32_TPREL
5982 BFD_RELOC_CRIS_16_TPREL
5984 BFD_RELOC_CRIS_DTPMOD
5986 BFD_RELOC_CRIS_32_IE
5988 Relocs used in TLS code for CRIS.
5991 BFD_RELOC_OR1K_REL_26
5993 BFD_RELOC_OR1K_SLO16
5995 BFD_RELOC_OR1K_PCREL_PG21
5999 BFD_RELOC_OR1K_SLO13
6001 BFD_RELOC_OR1K_GOTPC_HI16
6003 BFD_RELOC_OR1K_GOTPC_LO16
6005 BFD_RELOC_OR1K_GOT_AHI16
6007 BFD_RELOC_OR1K_GOT16
6009 BFD_RELOC_OR1K_GOT_PG21
6011 BFD_RELOC_OR1K_GOT_LO13
6013 BFD_RELOC_OR1K_PLT26
6015 BFD_RELOC_OR1K_PLTA26
6017 BFD_RELOC_OR1K_GOTOFF_SLO16
6021 BFD_RELOC_OR1K_GLOB_DAT
6023 BFD_RELOC_OR1K_JMP_SLOT
6025 BFD_RELOC_OR1K_RELATIVE
6027 BFD_RELOC_OR1K_TLS_GD_HI16
6029 BFD_RELOC_OR1K_TLS_GD_LO16
6031 BFD_RELOC_OR1K_TLS_GD_PG21
6033 BFD_RELOC_OR1K_TLS_GD_LO13
6035 BFD_RELOC_OR1K_TLS_LDM_HI16
6037 BFD_RELOC_OR1K_TLS_LDM_LO16
6039 BFD_RELOC_OR1K_TLS_LDM_PG21
6041 BFD_RELOC_OR1K_TLS_LDM_LO13
6043 BFD_RELOC_OR1K_TLS_LDO_HI16
6045 BFD_RELOC_OR1K_TLS_LDO_LO16
6047 BFD_RELOC_OR1K_TLS_IE_HI16
6049 BFD_RELOC_OR1K_TLS_IE_AHI16
6051 BFD_RELOC_OR1K_TLS_IE_LO16
6053 BFD_RELOC_OR1K_TLS_IE_PG21
6055 BFD_RELOC_OR1K_TLS_IE_LO13
6057 BFD_RELOC_OR1K_TLS_LE_HI16
6059 BFD_RELOC_OR1K_TLS_LE_AHI16
6061 BFD_RELOC_OR1K_TLS_LE_LO16
6063 BFD_RELOC_OR1K_TLS_LE_SLO16
6065 BFD_RELOC_OR1K_TLS_TPOFF
6067 BFD_RELOC_OR1K_TLS_DTPOFF
6069 BFD_RELOC_OR1K_TLS_DTPMOD
6071 OpenRISC 1000 Relocations.
6074 BFD_RELOC_H8_DIR16A8
6076 BFD_RELOC_H8_DIR16R8
6078 BFD_RELOC_H8_DIR24A8
6080 BFD_RELOC_H8_DIR24R8
6082 BFD_RELOC_H8_DIR32A16
6084 BFD_RELOC_H8_DISP32A16
6089 BFD_RELOC_XSTORMY16_REL_12
6091 BFD_RELOC_XSTORMY16_12
6093 BFD_RELOC_XSTORMY16_24
6095 BFD_RELOC_XSTORMY16_FPTR16
6097 Sony Xstormy16 Relocations.
6102 Self-describing complex relocations.
6105 BFD_RELOC_VAX_GLOB_DAT
6107 BFD_RELOC_VAX_JMP_SLOT
6109 BFD_RELOC_VAX_RELATIVE
6111 Relocations used by VAX ELF.
6116 Morpho MT - 16 bit immediate relocation.
6120 Morpho MT - Hi 16 bits of an address.
6124 Morpho MT - Low 16 bits of an address.
6126 BFD_RELOC_MT_GNU_VTINHERIT
6128 Morpho MT - Used to tell the linker which vtable entries are used.
6130 BFD_RELOC_MT_GNU_VTENTRY
6132 Morpho MT - Used to tell the linker which vtable entries are used.
6134 BFD_RELOC_MT_PCINSN8
6136 Morpho MT - 8 bit immediate relocation.
6139 BFD_RELOC_MSP430_10_PCREL
6141 BFD_RELOC_MSP430_16_PCREL
6145 BFD_RELOC_MSP430_16_PCREL_BYTE
6147 BFD_RELOC_MSP430_16_BYTE
6149 BFD_RELOC_MSP430_2X_PCREL
6151 BFD_RELOC_MSP430_RL_PCREL
6153 BFD_RELOC_MSP430_ABS8
6155 BFD_RELOC_MSP430X_PCR20_EXT_SRC
6157 BFD_RELOC_MSP430X_PCR20_EXT_DST
6159 BFD_RELOC_MSP430X_PCR20_EXT_ODST
6161 BFD_RELOC_MSP430X_ABS20_EXT_SRC
6163 BFD_RELOC_MSP430X_ABS20_EXT_DST
6165 BFD_RELOC_MSP430X_ABS20_EXT_ODST
6167 BFD_RELOC_MSP430X_ABS20_ADR_SRC
6169 BFD_RELOC_MSP430X_ABS20_ADR_DST
6171 BFD_RELOC_MSP430X_PCR16
6173 BFD_RELOC_MSP430X_PCR20_CALL
6175 BFD_RELOC_MSP430X_ABS16
6177 BFD_RELOC_MSP430_ABS_HI16
6179 BFD_RELOC_MSP430_PREL31
6181 BFD_RELOC_MSP430_SYM_DIFF
6183 BFD_RELOC_MSP430_SET_ULEB128
6185 BFD_RELOC_MSP430_SUB_ULEB128
6187 msp430 specific relocation codes.
6194 BFD_RELOC_NIOS2_CALL26
6196 BFD_RELOC_NIOS2_IMM5
6198 BFD_RELOC_NIOS2_CACHE_OPX
6200 BFD_RELOC_NIOS2_IMM6
6202 BFD_RELOC_NIOS2_IMM8
6204 BFD_RELOC_NIOS2_HI16
6206 BFD_RELOC_NIOS2_LO16
6208 BFD_RELOC_NIOS2_HIADJ16
6210 BFD_RELOC_NIOS2_GPREL
6212 BFD_RELOC_NIOS2_UJMP
6214 BFD_RELOC_NIOS2_CJMP
6216 BFD_RELOC_NIOS2_CALLR
6218 BFD_RELOC_NIOS2_ALIGN
6220 BFD_RELOC_NIOS2_GOT16
6222 BFD_RELOC_NIOS2_CALL16
6224 BFD_RELOC_NIOS2_GOTOFF_LO
6226 BFD_RELOC_NIOS2_GOTOFF_HA
6228 BFD_RELOC_NIOS2_PCREL_LO
6230 BFD_RELOC_NIOS2_PCREL_HA
6232 BFD_RELOC_NIOS2_TLS_GD16
6234 BFD_RELOC_NIOS2_TLS_LDM16
6236 BFD_RELOC_NIOS2_TLS_LDO16
6238 BFD_RELOC_NIOS2_TLS_IE16
6240 BFD_RELOC_NIOS2_TLS_LE16
6242 BFD_RELOC_NIOS2_TLS_DTPMOD
6244 BFD_RELOC_NIOS2_TLS_DTPREL
6246 BFD_RELOC_NIOS2_TLS_TPREL
6248 BFD_RELOC_NIOS2_COPY
6250 BFD_RELOC_NIOS2_GLOB_DAT
6252 BFD_RELOC_NIOS2_JUMP_SLOT
6254 BFD_RELOC_NIOS2_RELATIVE
6256 BFD_RELOC_NIOS2_GOTOFF
6258 BFD_RELOC_NIOS2_CALL26_NOAT
6260 BFD_RELOC_NIOS2_GOT_LO
6262 BFD_RELOC_NIOS2_GOT_HA
6264 BFD_RELOC_NIOS2_CALL_LO
6266 BFD_RELOC_NIOS2_CALL_HA
6268 BFD_RELOC_NIOS2_R2_S12
6270 BFD_RELOC_NIOS2_R2_I10_1_PCREL
6272 BFD_RELOC_NIOS2_R2_T1I7_1_PCREL
6274 BFD_RELOC_NIOS2_R2_T1I7_2
6276 BFD_RELOC_NIOS2_R2_T2I4
6278 BFD_RELOC_NIOS2_R2_T2I4_1
6280 BFD_RELOC_NIOS2_R2_T2I4_2
6282 BFD_RELOC_NIOS2_R2_X1I7_2
6284 BFD_RELOC_NIOS2_R2_X2L5
6286 BFD_RELOC_NIOS2_R2_F1I5_2
6288 BFD_RELOC_NIOS2_R2_L5I4X1
6290 BFD_RELOC_NIOS2_R2_T1X1I6
6292 BFD_RELOC_NIOS2_R2_T1X1I6_2
6294 Relocations used by the Altera Nios II core.
6299 PRU LDI 16-bit unsigned data-memory relocation.
6301 BFD_RELOC_PRU_U16_PMEMIMM
6303 PRU LDI 16-bit unsigned instruction-memory relocation.
6307 PRU relocation for two consecutive LDI load instructions that load a
6308 32 bit value into a register. If the higher bits are all zero, then
6309 the second instruction may be relaxed.
6311 BFD_RELOC_PRU_S10_PCREL
6313 PRU QBBx 10-bit signed PC-relative relocation.
6315 BFD_RELOC_PRU_U8_PCREL
6317 PRU 8-bit unsigned relocation used for the LOOP instruction.
6319 BFD_RELOC_PRU_32_PMEM
6321 BFD_RELOC_PRU_16_PMEM
6323 PRU Program Memory relocations. Used to convert from byte
6324 addressing to 32-bit word addressing.
6326 BFD_RELOC_PRU_GNU_DIFF8
6328 BFD_RELOC_PRU_GNU_DIFF16
6330 BFD_RELOC_PRU_GNU_DIFF32
6332 BFD_RELOC_PRU_GNU_DIFF16_PMEM
6334 BFD_RELOC_PRU_GNU_DIFF32_PMEM
6336 PRU relocations to mark the difference of two local symbols.
6337 These are only needed to support linker relaxation and can be
6338 ignored when not relaxing. The field is set to the value of the
6339 difference assuming no relaxation. The relocation encodes the
6340 position of the second symbol so the linker can determine whether to
6341 adjust the field value. The PMEM variants encode the word
6342 difference, instead of byte difference between symbols.
6345 BFD_RELOC_IQ2000_OFFSET_16
6347 BFD_RELOC_IQ2000_OFFSET_21
6349 BFD_RELOC_IQ2000_UHI16
6354 BFD_RELOC_XTENSA_RTLD
6356 Special Xtensa relocation used only by PLT entries in ELF shared
6357 objects to indicate that the runtime linker should set the value
6358 to one of its own internal functions or data structures.
6360 BFD_RELOC_XTENSA_GLOB_DAT
6362 BFD_RELOC_XTENSA_JMP_SLOT
6364 BFD_RELOC_XTENSA_RELATIVE
6366 Xtensa relocations for ELF shared objects.
6368 BFD_RELOC_XTENSA_PLT
6370 Xtensa relocation used in ELF object files for symbols that may
6371 require PLT entries. Otherwise, this is just a generic 32-bit
6374 BFD_RELOC_XTENSA_DIFF8
6376 BFD_RELOC_XTENSA_DIFF16
6378 BFD_RELOC_XTENSA_DIFF32
6380 Xtensa relocations for backward compatibility. These have been
6381 replaced by BFD_RELOC_XTENSA_PDIFF and BFD_RELOC_XTENSA_NDIFF.
6382 Xtensa relocations to mark the difference of two local symbols.
6383 These are only needed to support linker relaxation and can be
6384 ignored when not relaxing. The field is set to the value of the
6385 difference assuming no relaxation. The relocation encodes the
6386 position of the first symbol so the linker can determine whether to
6387 adjust the field value.
6389 BFD_RELOC_XTENSA_SLOT0_OP
6391 BFD_RELOC_XTENSA_SLOT1_OP
6393 BFD_RELOC_XTENSA_SLOT2_OP
6395 BFD_RELOC_XTENSA_SLOT3_OP
6397 BFD_RELOC_XTENSA_SLOT4_OP
6399 BFD_RELOC_XTENSA_SLOT5_OP
6401 BFD_RELOC_XTENSA_SLOT6_OP
6403 BFD_RELOC_XTENSA_SLOT7_OP
6405 BFD_RELOC_XTENSA_SLOT8_OP
6407 BFD_RELOC_XTENSA_SLOT9_OP
6409 BFD_RELOC_XTENSA_SLOT10_OP
6411 BFD_RELOC_XTENSA_SLOT11_OP
6413 BFD_RELOC_XTENSA_SLOT12_OP
6415 BFD_RELOC_XTENSA_SLOT13_OP
6417 BFD_RELOC_XTENSA_SLOT14_OP
6419 Generic Xtensa relocations for instruction operands. Only the slot
6420 number is encoded in the relocation. The relocation applies to the
6421 last PC-relative immediate operand, or if there are no PC-relative
6422 immediates, to the last immediate operand.
6424 BFD_RELOC_XTENSA_SLOT0_ALT
6426 BFD_RELOC_XTENSA_SLOT1_ALT
6428 BFD_RELOC_XTENSA_SLOT2_ALT
6430 BFD_RELOC_XTENSA_SLOT3_ALT
6432 BFD_RELOC_XTENSA_SLOT4_ALT
6434 BFD_RELOC_XTENSA_SLOT5_ALT
6436 BFD_RELOC_XTENSA_SLOT6_ALT
6438 BFD_RELOC_XTENSA_SLOT7_ALT
6440 BFD_RELOC_XTENSA_SLOT8_ALT
6442 BFD_RELOC_XTENSA_SLOT9_ALT
6444 BFD_RELOC_XTENSA_SLOT10_ALT
6446 BFD_RELOC_XTENSA_SLOT11_ALT
6448 BFD_RELOC_XTENSA_SLOT12_ALT
6450 BFD_RELOC_XTENSA_SLOT13_ALT
6452 BFD_RELOC_XTENSA_SLOT14_ALT
6454 Alternate Xtensa relocations. Only the slot is encoded in the
6455 relocation. The meaning of these relocations is opcode-specific.
6457 BFD_RELOC_XTENSA_OP0
6459 BFD_RELOC_XTENSA_OP1
6461 BFD_RELOC_XTENSA_OP2
6463 Xtensa relocations for backward compatibility. These have all been
6464 replaced by BFD_RELOC_XTENSA_SLOT0_OP.
6466 BFD_RELOC_XTENSA_ASM_EXPAND
6468 Xtensa relocation to mark that the assembler expanded the
6469 instructions from an original target. The expansion size is
6470 encoded in the reloc size.
6472 BFD_RELOC_XTENSA_ASM_SIMPLIFY
6474 Xtensa relocation to mark that the linker should simplify
6475 assembler-expanded instructions. This is commonly used
6476 internally by the linker after analysis of a
6477 BFD_RELOC_XTENSA_ASM_EXPAND.
6479 BFD_RELOC_XTENSA_TLSDESC_FN
6481 BFD_RELOC_XTENSA_TLSDESC_ARG
6483 BFD_RELOC_XTENSA_TLS_DTPOFF
6485 BFD_RELOC_XTENSA_TLS_TPOFF
6487 BFD_RELOC_XTENSA_TLS_FUNC
6489 BFD_RELOC_XTENSA_TLS_ARG
6491 BFD_RELOC_XTENSA_TLS_CALL
6493 Xtensa TLS relocations.
6495 BFD_RELOC_XTENSA_PDIFF8
6497 BFD_RELOC_XTENSA_PDIFF16
6499 BFD_RELOC_XTENSA_PDIFF32
6501 BFD_RELOC_XTENSA_NDIFF8
6503 BFD_RELOC_XTENSA_NDIFF16
6505 BFD_RELOC_XTENSA_NDIFF32
6507 Xtensa relocations to mark the difference of two local symbols.
6508 These are only needed to support linker relaxation and can be
6509 ignored when not relaxing. The field is set to the value of the
6510 difference assuming no relaxation. The relocation encodes the
6511 position of the subtracted symbol so the linker can determine
6512 whether to adjust the field value. PDIFF relocations are used for
6513 positive differences, NDIFF relocations are used for negative
6514 differences. The difference value is treated as unsigned with these
6515 relocation types, giving full 8/16 value ranges.
6520 8 bit signed offset in (ix+d) or (iy+d).
6524 First 8 bits of multibyte (32, 24 or 16 bit) value.
6528 Second 8 bits of multibyte (32, 24 or 16 bit) value.
6532 Third 8 bits of multibyte (32 or 24 bit) value.
6536 Fourth 8 bits of multibyte (32 bit) value.
6540 Lowest 16 bits of multibyte (32 or 24 bit) value.
6544 Highest 16 bits of multibyte (32 or 24 bit) value.
6548 Like BFD_RELOC_16 but big-endian.
6566 BFD_RELOC_LM32_BRANCH
6568 BFD_RELOC_LM32_16_GOT
6570 BFD_RELOC_LM32_GOTOFF_HI16
6572 BFD_RELOC_LM32_GOTOFF_LO16
6576 BFD_RELOC_LM32_GLOB_DAT
6578 BFD_RELOC_LM32_JMP_SLOT
6580 BFD_RELOC_LM32_RELATIVE
6582 Lattice Mico32 relocations.
6585 BFD_RELOC_MACH_O_SECTDIFF
6587 Difference between two section addreses. Must be followed by a
6588 BFD_RELOC_MACH_O_PAIR.
6590 BFD_RELOC_MACH_O_LOCAL_SECTDIFF
6592 Like BFD_RELOC_MACH_O_SECTDIFF but with a local symbol.
6594 BFD_RELOC_MACH_O_PAIR
6596 Pair of relocation. Contains the first symbol.
6598 BFD_RELOC_MACH_O_SUBTRACTOR32
6600 Symbol will be substracted. Must be followed by a BFD_RELOC_32.
6602 BFD_RELOC_MACH_O_SUBTRACTOR64
6604 Symbol will be substracted. Must be followed by a BFD_RELOC_64.
6607 BFD_RELOC_MACH_O_X86_64_BRANCH32
6609 BFD_RELOC_MACH_O_X86_64_BRANCH8
6611 PCREL relocations. They are marked as branch to create PLT entry if
6614 BFD_RELOC_MACH_O_X86_64_GOT
6616 Used when referencing a GOT entry.
6618 BFD_RELOC_MACH_O_X86_64_GOT_LOAD
6620 Used when loading a GOT entry with movq. It is specially marked so
6621 that the linker could optimize the movq to a leaq if possible.
6623 BFD_RELOC_MACH_O_X86_64_PCREL32_1
6625 Same as BFD_RELOC_32_PCREL but with an implicit -1 addend.
6627 BFD_RELOC_MACH_O_X86_64_PCREL32_2
6629 Same as BFD_RELOC_32_PCREL but with an implicit -2 addend.
6631 BFD_RELOC_MACH_O_X86_64_PCREL32_4
6633 Same as BFD_RELOC_32_PCREL but with an implicit -4 addend.
6635 BFD_RELOC_MACH_O_X86_64_TLV
6637 Used when referencing a TLV entry.
6641 BFD_RELOC_MACH_O_ARM64_ADDEND
6643 Addend for PAGE or PAGEOFF.
6645 BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGE21
6647 Relative offset to page of GOT slot.
6649 BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGEOFF12
6651 Relative offset within page of GOT slot.
6653 BFD_RELOC_MACH_O_ARM64_POINTER_TO_GOT
6655 Address of a GOT entry.
6658 BFD_RELOC_MICROBLAZE_32_LO
6660 This is a 32 bit reloc for the microblaze that stores the low 16
6663 BFD_RELOC_MICROBLAZE_32_LO_PCREL
6665 This is a 32 bit pc-relative reloc for the microblaze that stores
6666 the low 16 bits of a value.
6668 BFD_RELOC_MICROBLAZE_32_ROSDA
6670 This is a 32 bit reloc for the microblaze that stores a value
6671 relative to the read-only small data area anchor.
6673 BFD_RELOC_MICROBLAZE_32_RWSDA
6675 This is a 32 bit reloc for the microblaze that stores a value
6676 relative to the read-write small data area anchor.
6678 BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM
6680 This is a 32 bit reloc for the microblaze to handle expressions of
6681 the form "Symbol Op Symbol".
6683 BFD_RELOC_MICROBLAZE_32_NONE
6685 This is a 32 bit reloc that stores the 32 bit pc relative value in
6686 two words (with an imm instruction). No relocation is done here -
6687 only used for relaxing.
6689 BFD_RELOC_MICROBLAZE_64_NONE
6691 This is a 64 bit reloc that stores the 32 bit pc relative value in
6692 two words (with an imm instruction). No relocation is done here -
6693 only used for relaxing.
6695 BFD_RELOC_MICROBLAZE_64_GOTPC
6697 This is a 64 bit reloc that stores the 32 bit pc relative value in
6698 two words (with an imm instruction). The relocation is PC-relative
6701 BFD_RELOC_MICROBLAZE_64_GOT
6703 This is a 64 bit reloc that stores the 32 bit pc relative value in
6704 two words (with an imm instruction). The relocation is GOT offset.
6706 BFD_RELOC_MICROBLAZE_64_PLT
6708 This is a 64 bit reloc that stores the 32 bit pc relative value in
6709 two words (with an imm instruction). The relocation is PC-relative
6712 BFD_RELOC_MICROBLAZE_64_GOTOFF
6714 This is a 64 bit reloc that stores the 32 bit GOT relative value in
6715 two words (with an imm instruction). The relocation is relative
6716 offset from _GLOBAL_OFFSET_TABLE_.
6718 BFD_RELOC_MICROBLAZE_32_GOTOFF
6720 This is a 32 bit reloc that stores the 32 bit GOT relative value in
6721 a word. The relocation is relative offset from
6722 _GLOBAL_OFFSET_TABLE_.
6724 BFD_RELOC_MICROBLAZE_COPY
6726 This is used to tell the dynamic linker to copy the value out of
6727 the dynamic object into the runtime process image.
6729 BFD_RELOC_MICROBLAZE_64_TLS
6733 BFD_RELOC_MICROBLAZE_64_TLSGD
6735 This is a 64 bit reloc that stores the 32 bit GOT relative value
6736 of the GOT TLS GD info entry in two words (with an imm instruction).
6737 The relocation is GOT offset.
6739 BFD_RELOC_MICROBLAZE_64_TLSLD
6741 This is a 64 bit reloc that stores the 32 bit GOT relative value
6742 of the GOT TLS LD info entry in two words (with an imm instruction).
6743 The relocation is GOT offset.
6745 BFD_RELOC_MICROBLAZE_32_TLSDTPMOD
6747 This is a 32 bit reloc that stores the Module ID to GOT(n).
6749 BFD_RELOC_MICROBLAZE_32_TLSDTPREL
6751 This is a 32 bit reloc that stores TLS offset to GOT(n+1).
6753 BFD_RELOC_MICROBLAZE_64_TLSDTPREL
6755 This is a 32 bit reloc for storing TLS offset to two words (uses imm
6758 BFD_RELOC_MICROBLAZE_64_TLSGOTTPREL
6760 This is a 64 bit reloc that stores 32-bit thread pointer relative
6761 offset to two words (uses imm instruction).
6763 BFD_RELOC_MICROBLAZE_64_TLSTPREL
6765 This is a 64 bit reloc that stores 32-bit thread pointer relative
6766 offset to two words (uses imm instruction).
6768 BFD_RELOC_MICROBLAZE_64_TEXTPCREL
6770 This is a 64 bit reloc that stores the 32 bit pc relative value in
6771 two words (with an imm instruction). The relocation is PC-relative
6772 offset from start of TEXT.
6774 BFD_RELOC_MICROBLAZE_64_TEXTREL
6776 This is a 64 bit reloc that stores the 32 bit offset value in two
6777 words (with an imm instruction). The relocation is relative offset
6780 BFD_RELOC_KVX_RELOC_START
6782 KVX pseudo relocation code to mark the start of the KVX relocation
6783 enumerators. N.B. the order of the enumerators is important as
6784 several tables in the KVX bfd backend are indexed by these
6785 enumerators; make sure they are all synced.
6789 KVX null relocation code.
6797 BFD_RELOC_KVX_S16_PCREL
6799 BFD_RELOC_KVX_PCREL17
6801 BFD_RELOC_KVX_PCREL27
6803 BFD_RELOC_KVX_32_PCREL
6805 BFD_RELOC_KVX_S37_PCREL_LO10
6807 BFD_RELOC_KVX_S37_PCREL_UP27
6809 BFD_RELOC_KVX_S43_PCREL_LO10
6811 BFD_RELOC_KVX_S43_PCREL_UP27
6813 BFD_RELOC_KVX_S43_PCREL_EX6
6815 BFD_RELOC_KVX_S64_PCREL_LO10
6817 BFD_RELOC_KVX_S64_PCREL_UP27
6819 BFD_RELOC_KVX_S64_PCREL_EX27
6821 BFD_RELOC_KVX_64_PCREL
6825 BFD_RELOC_KVX_S32_LO5
6827 BFD_RELOC_KVX_S32_UP27
6829 BFD_RELOC_KVX_S37_LO10
6831 BFD_RELOC_KVX_S37_UP27
6833 BFD_RELOC_KVX_S37_GOTOFF_LO10
6835 BFD_RELOC_KVX_S37_GOTOFF_UP27
6837 BFD_RELOC_KVX_S43_GOTOFF_LO10
6839 BFD_RELOC_KVX_S43_GOTOFF_UP27
6841 BFD_RELOC_KVX_S43_GOTOFF_EX6
6843 BFD_RELOC_KVX_32_GOTOFF
6845 BFD_RELOC_KVX_64_GOTOFF
6847 BFD_RELOC_KVX_32_GOT
6849 BFD_RELOC_KVX_S37_GOT_LO10
6851 BFD_RELOC_KVX_S37_GOT_UP27
6853 BFD_RELOC_KVX_S43_GOT_LO10
6855 BFD_RELOC_KVX_S43_GOT_UP27
6857 BFD_RELOC_KVX_S43_GOT_EX6
6859 BFD_RELOC_KVX_64_GOT
6861 BFD_RELOC_KVX_GLOB_DAT
6865 BFD_RELOC_KVX_JMP_SLOT
6867 BFD_RELOC_KVX_RELATIVE
6869 BFD_RELOC_KVX_S43_LO10
6871 BFD_RELOC_KVX_S43_UP27
6873 BFD_RELOC_KVX_S43_EX6
6875 BFD_RELOC_KVX_S64_LO10
6877 BFD_RELOC_KVX_S64_UP27
6879 BFD_RELOC_KVX_S64_EX27
6881 BFD_RELOC_KVX_S37_GOTADDR_LO10
6883 BFD_RELOC_KVX_S37_GOTADDR_UP27
6885 BFD_RELOC_KVX_S43_GOTADDR_LO10
6887 BFD_RELOC_KVX_S43_GOTADDR_UP27
6889 BFD_RELOC_KVX_S43_GOTADDR_EX6
6891 BFD_RELOC_KVX_S64_GOTADDR_LO10
6893 BFD_RELOC_KVX_S64_GOTADDR_UP27
6895 BFD_RELOC_KVX_S64_GOTADDR_EX27
6897 BFD_RELOC_KVX_64_DTPMOD
6899 BFD_RELOC_KVX_64_DTPOFF
6901 BFD_RELOC_KVX_S37_TLS_DTPOFF_LO10
6903 BFD_RELOC_KVX_S37_TLS_DTPOFF_UP27
6905 BFD_RELOC_KVX_S43_TLS_DTPOFF_LO10
6907 BFD_RELOC_KVX_S43_TLS_DTPOFF_UP27
6909 BFD_RELOC_KVX_S43_TLS_DTPOFF_EX6
6911 BFD_RELOC_KVX_S37_TLS_GD_LO10
6913 BFD_RELOC_KVX_S37_TLS_GD_UP27
6915 BFD_RELOC_KVX_S43_TLS_GD_LO10
6917 BFD_RELOC_KVX_S43_TLS_GD_UP27
6919 BFD_RELOC_KVX_S43_TLS_GD_EX6
6921 BFD_RELOC_KVX_S37_TLS_LD_LO10
6923 BFD_RELOC_KVX_S37_TLS_LD_UP27
6925 BFD_RELOC_KVX_S43_TLS_LD_LO10
6927 BFD_RELOC_KVX_S43_TLS_LD_UP27
6929 BFD_RELOC_KVX_S43_TLS_LD_EX6
6931 BFD_RELOC_KVX_64_TPOFF
6933 BFD_RELOC_KVX_S37_TLS_IE_LO10
6935 BFD_RELOC_KVX_S37_TLS_IE_UP27
6937 BFD_RELOC_KVX_S43_TLS_IE_LO10
6939 BFD_RELOC_KVX_S43_TLS_IE_UP27
6941 BFD_RELOC_KVX_S43_TLS_IE_EX6
6943 BFD_RELOC_KVX_S37_TLS_LE_LO10
6945 BFD_RELOC_KVX_S37_TLS_LE_UP27
6947 BFD_RELOC_KVX_S43_TLS_LE_LO10
6949 BFD_RELOC_KVX_S43_TLS_LE_UP27
6951 BFD_RELOC_KVX_S43_TLS_LE_EX6
6957 BFD_RELOC_KVX_RELOC_END
6959 KVX pseudo relocation code to mark the end of the KVX relocation
6960 enumerators that have direct mapping to ELF reloc codes. There are
6961 a few more enumerators after this one; those are mainly used by the
6962 KVX assembler for the internal fixup or to select one of the above
6965 BFD_RELOC_AARCH64_RELOC_START
6967 AArch64 pseudo relocation code to mark the start of the AArch64
6968 relocation enumerators. N.B. the order of the enumerators is
6969 important as several tables in the AArch64 bfd backend are indexed
6970 by these enumerators; make sure they are all synced.
6972 BFD_RELOC_AARCH64_NULL
6974 Deprecated AArch64 null relocation code.
6976 BFD_RELOC_AARCH64_NONE
6978 AArch64 null relocation code.
6980 BFD_RELOC_AARCH64_64
6982 BFD_RELOC_AARCH64_32
6984 BFD_RELOC_AARCH64_16
6986 Basic absolute relocations of N bits. These are equivalent to
6987 BFD_RELOC_N and they were added to assist the indexing of the howto
6990 BFD_RELOC_AARCH64_64_PCREL
6992 BFD_RELOC_AARCH64_32_PCREL
6994 BFD_RELOC_AARCH64_16_PCREL
6996 PC-relative relocations. These are equivalent to BFD_RELOC_N_PCREL
6997 and they were added to assist the indexing of the howto table.
6999 BFD_RELOC_AARCH64_MOVW_G0
7001 AArch64 MOV[NZK] instruction with most significant bits 0 to 15 of
7002 an unsigned address/value.
7004 BFD_RELOC_AARCH64_MOVW_G0_NC
7006 AArch64 MOV[NZK] instruction with less significant bits 0 to 15 of
7007 an address/value. No overflow checking.
7009 BFD_RELOC_AARCH64_MOVW_G1
7011 AArch64 MOV[NZK] instruction with most significant bits 16 to 31 of
7012 an unsigned address/value.
7014 BFD_RELOC_AARCH64_MOVW_G1_NC
7016 AArch64 MOV[NZK] instruction with less significant bits 16 to 31 of
7017 an address/value. No overflow checking.
7019 BFD_RELOC_AARCH64_MOVW_G2
7021 AArch64 MOV[NZK] instruction with most significant bits 32 to 47 of
7022 an unsigned address/value.
7024 BFD_RELOC_AARCH64_MOVW_G2_NC
7026 AArch64 MOV[NZK] instruction with less significant bits 32 to 47 of
7027 an address/value. No overflow checking.
7029 BFD_RELOC_AARCH64_MOVW_G3
7031 AArch64 MOV[NZK] instruction with most signficant bits 48 to 64 of a
7032 signed or unsigned address/value.
7034 BFD_RELOC_AARCH64_MOVW_G0_S
7036 AArch64 MOV[NZ] instruction with most significant bits 0 to 15 of a
7037 signed value. Changes instruction to MOVZ or MOVN depending on the
7040 BFD_RELOC_AARCH64_MOVW_G1_S
7042 AArch64 MOV[NZ] instruction with most significant bits 16 to 31 of a
7043 signed value. Changes instruction to MOVZ or MOVN depending on the
7046 BFD_RELOC_AARCH64_MOVW_G2_S
7048 AArch64 MOV[NZ] instruction with most significant bits 32 to 47 of a
7049 signed value. Changes instruction to MOVZ or MOVN depending on the
7052 BFD_RELOC_AARCH64_MOVW_PREL_G0
7054 AArch64 MOV[NZ] instruction with most significant bits 0 to 15 of a
7055 signed value. Changes instruction to MOVZ or MOVN depending on the
7058 BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
7060 AArch64 MOV[NZ] instruction with most significant bits 0 to 15 of a
7061 signed value. Changes instruction to MOVZ or MOVN depending on the
7064 BFD_RELOC_AARCH64_MOVW_PREL_G1
7066 AArch64 MOVK instruction with most significant bits 16 to 31 of a
7069 BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
7071 AArch64 MOVK instruction with most significant bits 16 to 31 of a
7074 BFD_RELOC_AARCH64_MOVW_PREL_G2
7076 AArch64 MOVK instruction with most significant bits 32 to 47 of a
7079 BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
7081 AArch64 MOVK instruction with most significant bits 32 to 47 of a
7084 BFD_RELOC_AARCH64_MOVW_PREL_G3
7086 AArch64 MOVK instruction with most significant bits 47 to 63 of a
7089 BFD_RELOC_AARCH64_LD_LO19_PCREL
7091 AArch64 Load Literal instruction, holding a 19 bit pc-relative word
7092 offset. The lowest two bits must be zero and are not stored in the
7093 instruction, giving a 21 bit signed byte offset.
7095 BFD_RELOC_AARCH64_ADR_LO21_PCREL
7097 AArch64 ADR instruction, holding a simple 21 bit pc-relative byte
7100 BFD_RELOC_AARCH64_ADR_HI21_PCREL
7102 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
7103 offset, giving a 4KB aligned page base address.
7105 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
7107 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
7108 offset, giving a 4KB aligned page base address, but with no overflow
7111 BFD_RELOC_AARCH64_ADD_LO12
7113 AArch64 ADD immediate instruction, holding bits 0 to 11 of the
7114 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7116 BFD_RELOC_AARCH64_LDST8_LO12
7118 AArch64 8-bit load/store instruction, holding bits 0 to 11 of the
7119 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7121 BFD_RELOC_AARCH64_TSTBR14
7123 AArch64 14 bit pc-relative test bit and branch.
7124 The lowest two bits must be zero and are not stored in the
7125 instruction, giving a 16 bit signed byte offset.
7127 BFD_RELOC_AARCH64_BRANCH19
7129 AArch64 19 bit pc-relative conditional branch and compare & branch.
7130 The lowest two bits must be zero and are not stored in the
7131 instruction, giving a 21 bit signed byte offset.
7133 BFD_RELOC_AARCH64_JUMP26
7135 AArch64 26 bit pc-relative unconditional branch.
7136 The lowest two bits must be zero and are not stored in the
7137 instruction, giving a 28 bit signed byte offset.
7139 BFD_RELOC_AARCH64_CALL26
7141 AArch64 26 bit pc-relative unconditional branch and link.
7142 The lowest two bits must be zero and are not stored in the
7143 instruction, giving a 28 bit signed byte offset.
7145 BFD_RELOC_AARCH64_LDST16_LO12
7147 AArch64 16-bit load/store instruction, holding bits 0 to 11 of the
7148 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7150 BFD_RELOC_AARCH64_LDST32_LO12
7152 AArch64 32-bit load/store instruction, holding bits 0 to 11 of the
7153 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7155 BFD_RELOC_AARCH64_LDST64_LO12
7157 AArch64 64-bit load/store instruction, holding bits 0 to 11 of the
7158 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7160 BFD_RELOC_AARCH64_LDST128_LO12
7162 AArch64 128-bit load/store instruction, holding bits 0 to 11 of the
7163 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7165 BFD_RELOC_AARCH64_GOT_LD_PREL19
7167 AArch64 Load Literal instruction, holding a 19 bit PC relative word
7168 offset of the global offset table entry for a symbol. The lowest
7169 two bits must be zero and are not stored in the instruction, giving
7170 a 21 bit signed byte offset. This relocation type requires signed
7173 BFD_RELOC_AARCH64_ADR_GOT_PAGE
7175 Get to the page base of the global offset table entry for a symbol
7176 as part of an ADRP instruction using a 21 bit PC relative value.
7177 Used in conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC.
7179 BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
7181 Unsigned 12 bit byte offset for 64 bit load/store from the page of
7182 the GOT entry for this symbol. Used in conjunction with
7183 BFD_RELOC_AARCH64_ADR_GOT_PAGE. Valid in LP64 ABI only.
7185 BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
7187 Unsigned 12 bit byte offset for 32 bit load/store from the page of
7188 the GOT entry for this symbol. Used in conjunction with
7189 BFD_RELOC_AARCH64_ADR_GOT_PAGE. Valid in ILP32 ABI only.
7191 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
7193 Unsigned 16 bit byte offset for 64 bit load/store from the GOT entry
7194 for this symbol. Valid in LP64 ABI only.
7196 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
7198 Unsigned 16 bit byte higher offset for 64 bit load/store from the
7199 GOT entry for this symbol. Valid in LP64 ABI only.
7201 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
7203 Unsigned 15 bit byte offset for 64 bit load/store from the page of
7204 the GOT entry for this symbol. Valid in LP64 ABI only.
7206 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
7208 Scaled 14 bit byte offset to the page base of the global offset
7211 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
7213 Scaled 15 bit byte offset to the page base of the global offset
7216 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
7218 Get to the page base of the global offset table entry for a symbols
7219 tls_index structure as part of an adrp instruction using a 21 bit PC
7220 relative value. Used in conjunction with
7221 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC.
7223 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
7225 AArch64 TLS General Dynamic.
7227 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
7229 Unsigned 12 bit byte offset to global offset table entry for a
7230 symbol's tls_index structure. Used in conjunction with
7231 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21.
7233 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
7235 AArch64 TLS General Dynamic relocation.
7237 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
7239 AArch64 TLS General Dynamic relocation.
7241 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
7243 AArch64 TLS INITIAL EXEC relocation.
7245 BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
7247 AArch64 TLS INITIAL EXEC relocation.
7249 BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
7251 AArch64 TLS INITIAL EXEC relocation.
7253 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
7255 AArch64 TLS INITIAL EXEC relocation.
7257 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
7259 AArch64 TLS INITIAL EXEC relocation.
7261 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
7263 AArch64 TLS INITIAL EXEC relocation.
7265 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
7267 bit[23:12] of byte offset to module TLS base address.
7269 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
7271 Unsigned 12 bit byte offset to module TLS base address.
7273 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
7275 No overflow check version of
7276 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12.
7278 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
7280 Unsigned 12 bit byte offset to global offset table entry for a
7281 symbol's tls_index structure. Used in conjunction with
7282 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21.
7284 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
7286 GOT entry page address for AArch64 TLS Local Dynamic, used with ADRP
7289 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
7291 GOT entry address for AArch64 TLS Local Dynamic, used with ADR
7294 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
7296 bit[11:1] of byte offset to module TLS base address, encoded in ldst
7299 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
7301 Similar to BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12, but no
7304 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
7306 bit[11:2] of byte offset to module TLS base address, encoded in ldst
7309 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
7311 Similar to BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12, but no
7314 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
7316 bit[11:3] of byte offset to module TLS base address, encoded in ldst
7319 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
7321 Similar to BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12, but no
7324 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
7326 bit[11:0] of byte offset to module TLS base address, encoded in ldst
7329 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
7331 Similar to BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12, but no
7334 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
7336 bit[15:0] of byte offset to module TLS base address.
7338 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
7340 No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0.
7342 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
7344 bit[31:16] of byte offset to module TLS base address.
7346 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
7348 No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1.
7350 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
7352 bit[47:32] of byte offset to module TLS base address.
7354 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
7356 AArch64 TLS LOCAL EXEC relocation.
7358 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
7360 AArch64 TLS LOCAL EXEC relocation.
7362 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
7364 AArch64 TLS LOCAL EXEC relocation.
7366 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
7368 AArch64 TLS LOCAL EXEC relocation.
7370 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
7372 AArch64 TLS LOCAL EXEC relocation.
7374 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
7376 AArch64 TLS LOCAL EXEC relocation.
7378 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
7380 AArch64 TLS LOCAL EXEC relocation.
7382 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
7384 AArch64 TLS LOCAL EXEC relocation.
7386 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
7388 bit[11:1] of byte offset to module TLS base address, encoded in ldst
7391 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
7393 Similar to BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12, but no
7396 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
7398 bit[11:2] of byte offset to module TLS base address, encoded in ldst
7401 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
7403 Similar to BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12, but no
7406 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
7408 bit[11:3] of byte offset to module TLS base address, encoded in ldst
7411 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
7413 Similar to BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12, but no
7416 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
7418 bit[11:0] of byte offset to module TLS base address, encoded in ldst
7421 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
7423 Similar to BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12, but no overflow
7426 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
7428 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
7430 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
7432 BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
7434 BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
7436 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
7438 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
7440 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
7442 BFD_RELOC_AARCH64_TLSDESC_LDR
7444 BFD_RELOC_AARCH64_TLSDESC_ADD
7446 BFD_RELOC_AARCH64_TLSDESC_CALL
7448 AArch64 TLS DESC relocations.
7450 BFD_RELOC_AARCH64_COPY
7452 BFD_RELOC_AARCH64_GLOB_DAT
7454 BFD_RELOC_AARCH64_JUMP_SLOT
7456 BFD_RELOC_AARCH64_RELATIVE
7458 AArch64 DSO relocations.
7460 BFD_RELOC_AARCH64_TLS_DTPMOD
7462 BFD_RELOC_AARCH64_TLS_DTPREL
7464 BFD_RELOC_AARCH64_TLS_TPREL
7466 BFD_RELOC_AARCH64_TLSDESC
7468 AArch64 TLS relocations.
7470 BFD_RELOC_AARCH64_IRELATIVE
7472 AArch64 support for STT_GNU_IFUNC.
7474 BFD_RELOC_AARCH64_RELOC_END
7476 AArch64 pseudo relocation code to mark the end of the AArch64
7477 relocation enumerators that have direct mapping to ELF reloc codes.
7478 There are a few more enumerators after this one; those are mainly
7479 used by the AArch64 assembler for the internal fixup or to select
7480 one of the above enumerators.
7482 BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
7484 AArch64 pseudo relocation code to be used internally by the AArch64
7485 assembler and not (currently) written to any object files.
7487 BFD_RELOC_AARCH64_LDST_LO12
7489 AArch64 unspecified load/store instruction, holding bits 0 to 11 of the
7490 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7492 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
7494 AArch64 pseudo relocation code for TLS local dynamic mode. It's to
7495 be used internally by the AArch64 assembler and not (currently)
7496 written to any object files.
7498 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
7500 Similar to BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12, but no overflow
7503 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
7505 AArch64 pseudo relocation code for TLS local exec mode. It's to be
7506 used internally by the AArch64 assembler and not (currently) written
7507 to any object files.
7509 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
7511 Similar to BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12, but no overflow
7514 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
7516 AArch64 pseudo relocation code to be used internally by the AArch64
7517 assembler and not (currently) written to any object files.
7519 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
7521 AArch64 pseudo relocation code to be used internally by the AArch64
7522 assembler and not (currently) written to any object files.
7524 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
7526 AArch64 pseudo relocation code to be used internally by the AArch64
7527 assembler and not (currently) written to any object files.
7529 BFD_RELOC_TILEPRO_COPY
7531 BFD_RELOC_TILEPRO_GLOB_DAT
7533 BFD_RELOC_TILEPRO_JMP_SLOT
7535 BFD_RELOC_TILEPRO_RELATIVE
7537 BFD_RELOC_TILEPRO_BROFF_X1
7539 BFD_RELOC_TILEPRO_JOFFLONG_X1
7541 BFD_RELOC_TILEPRO_JOFFLONG_X1_PLT
7543 BFD_RELOC_TILEPRO_IMM8_X0
7545 BFD_RELOC_TILEPRO_IMM8_Y0
7547 BFD_RELOC_TILEPRO_IMM8_X1
7549 BFD_RELOC_TILEPRO_IMM8_Y1
7551 BFD_RELOC_TILEPRO_DEST_IMM8_X1
7553 BFD_RELOC_TILEPRO_MT_IMM15_X1
7555 BFD_RELOC_TILEPRO_MF_IMM15_X1
7557 BFD_RELOC_TILEPRO_IMM16_X0
7559 BFD_RELOC_TILEPRO_IMM16_X1
7561 BFD_RELOC_TILEPRO_IMM16_X0_LO
7563 BFD_RELOC_TILEPRO_IMM16_X1_LO
7565 BFD_RELOC_TILEPRO_IMM16_X0_HI
7567 BFD_RELOC_TILEPRO_IMM16_X1_HI
7569 BFD_RELOC_TILEPRO_IMM16_X0_HA
7571 BFD_RELOC_TILEPRO_IMM16_X1_HA
7573 BFD_RELOC_TILEPRO_IMM16_X0_PCREL
7575 BFD_RELOC_TILEPRO_IMM16_X1_PCREL
7577 BFD_RELOC_TILEPRO_IMM16_X0_LO_PCREL
7579 BFD_RELOC_TILEPRO_IMM16_X1_LO_PCREL
7581 BFD_RELOC_TILEPRO_IMM16_X0_HI_PCREL
7583 BFD_RELOC_TILEPRO_IMM16_X1_HI_PCREL
7585 BFD_RELOC_TILEPRO_IMM16_X0_HA_PCREL
7587 BFD_RELOC_TILEPRO_IMM16_X1_HA_PCREL
7589 BFD_RELOC_TILEPRO_IMM16_X0_GOT
7591 BFD_RELOC_TILEPRO_IMM16_X1_GOT
7593 BFD_RELOC_TILEPRO_IMM16_X0_GOT_LO
7595 BFD_RELOC_TILEPRO_IMM16_X1_GOT_LO
7597 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HI
7599 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HI
7601 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HA
7603 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HA
7605 BFD_RELOC_TILEPRO_MMSTART_X0
7607 BFD_RELOC_TILEPRO_MMEND_X0
7609 BFD_RELOC_TILEPRO_MMSTART_X1
7611 BFD_RELOC_TILEPRO_MMEND_X1
7613 BFD_RELOC_TILEPRO_SHAMT_X0
7615 BFD_RELOC_TILEPRO_SHAMT_X1
7617 BFD_RELOC_TILEPRO_SHAMT_Y0
7619 BFD_RELOC_TILEPRO_SHAMT_Y1
7621 BFD_RELOC_TILEPRO_TLS_GD_CALL
7623 BFD_RELOC_TILEPRO_IMM8_X0_TLS_GD_ADD
7625 BFD_RELOC_TILEPRO_IMM8_X1_TLS_GD_ADD
7627 BFD_RELOC_TILEPRO_IMM8_Y0_TLS_GD_ADD
7629 BFD_RELOC_TILEPRO_IMM8_Y1_TLS_GD_ADD
7631 BFD_RELOC_TILEPRO_TLS_IE_LOAD
7633 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD
7635 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD
7637 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_LO
7639 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_LO
7641 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HI
7643 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HI
7645 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HA
7647 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HA
7649 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE
7651 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE
7653 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_LO
7655 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_LO
7657 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HI
7659 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HI
7661 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HA
7663 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HA
7665 BFD_RELOC_TILEPRO_TLS_DTPMOD32
7667 BFD_RELOC_TILEPRO_TLS_DTPOFF32
7669 BFD_RELOC_TILEPRO_TLS_TPOFF32
7671 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE
7673 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE
7675 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_LO
7677 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_LO
7679 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HI
7681 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HI
7683 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HA
7685 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA
7687 Tilera TILEPro Relocations.
7689 BFD_RELOC_TILEGX_HW0
7691 BFD_RELOC_TILEGX_HW1
7693 BFD_RELOC_TILEGX_HW2
7695 BFD_RELOC_TILEGX_HW3
7697 BFD_RELOC_TILEGX_HW0_LAST
7699 BFD_RELOC_TILEGX_HW1_LAST
7701 BFD_RELOC_TILEGX_HW2_LAST
7703 BFD_RELOC_TILEGX_COPY
7705 BFD_RELOC_TILEGX_GLOB_DAT
7707 BFD_RELOC_TILEGX_JMP_SLOT
7709 BFD_RELOC_TILEGX_RELATIVE
7711 BFD_RELOC_TILEGX_BROFF_X1
7713 BFD_RELOC_TILEGX_JUMPOFF_X1
7715 BFD_RELOC_TILEGX_JUMPOFF_X1_PLT
7717 BFD_RELOC_TILEGX_IMM8_X0
7719 BFD_RELOC_TILEGX_IMM8_Y0
7721 BFD_RELOC_TILEGX_IMM8_X1
7723 BFD_RELOC_TILEGX_IMM8_Y1
7725 BFD_RELOC_TILEGX_DEST_IMM8_X1
7727 BFD_RELOC_TILEGX_MT_IMM14_X1
7729 BFD_RELOC_TILEGX_MF_IMM14_X1
7731 BFD_RELOC_TILEGX_MMSTART_X0
7733 BFD_RELOC_TILEGX_MMEND_X0
7735 BFD_RELOC_TILEGX_SHAMT_X0
7737 BFD_RELOC_TILEGX_SHAMT_X1
7739 BFD_RELOC_TILEGX_SHAMT_Y0
7741 BFD_RELOC_TILEGX_SHAMT_Y1
7743 BFD_RELOC_TILEGX_IMM16_X0_HW0
7745 BFD_RELOC_TILEGX_IMM16_X1_HW0
7747 BFD_RELOC_TILEGX_IMM16_X0_HW1
7749 BFD_RELOC_TILEGX_IMM16_X1_HW1
7751 BFD_RELOC_TILEGX_IMM16_X0_HW2
7753 BFD_RELOC_TILEGX_IMM16_X1_HW2
7755 BFD_RELOC_TILEGX_IMM16_X0_HW3
7757 BFD_RELOC_TILEGX_IMM16_X1_HW3
7759 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST
7761 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST
7763 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST
7765 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST
7767 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST
7769 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST
7771 BFD_RELOC_TILEGX_IMM16_X0_HW0_PCREL
7773 BFD_RELOC_TILEGX_IMM16_X1_HW0_PCREL
7775 BFD_RELOC_TILEGX_IMM16_X0_HW1_PCREL
7777 BFD_RELOC_TILEGX_IMM16_X1_HW1_PCREL
7779 BFD_RELOC_TILEGX_IMM16_X0_HW2_PCREL
7781 BFD_RELOC_TILEGX_IMM16_X1_HW2_PCREL
7783 BFD_RELOC_TILEGX_IMM16_X0_HW3_PCREL
7785 BFD_RELOC_TILEGX_IMM16_X1_HW3_PCREL
7787 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PCREL
7789 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PCREL
7791 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PCREL
7793 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PCREL
7795 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PCREL
7797 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PCREL
7799 BFD_RELOC_TILEGX_IMM16_X0_HW0_GOT
7801 BFD_RELOC_TILEGX_IMM16_X1_HW0_GOT
7803 BFD_RELOC_TILEGX_IMM16_X0_HW0_PLT_PCREL
7805 BFD_RELOC_TILEGX_IMM16_X1_HW0_PLT_PCREL
7807 BFD_RELOC_TILEGX_IMM16_X0_HW1_PLT_PCREL
7809 BFD_RELOC_TILEGX_IMM16_X1_HW1_PLT_PCREL
7811 BFD_RELOC_TILEGX_IMM16_X0_HW2_PLT_PCREL
7813 BFD_RELOC_TILEGX_IMM16_X1_HW2_PLT_PCREL
7815 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_GOT
7817 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_GOT
7819 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_GOT
7821 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_GOT
7823 BFD_RELOC_TILEGX_IMM16_X0_HW3_PLT_PCREL
7825 BFD_RELOC_TILEGX_IMM16_X1_HW3_PLT_PCREL
7827 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_GD
7829 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_GD
7831 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_LE
7833 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_LE
7835 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_LE
7837 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_LE
7839 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_LE
7841 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_LE
7843 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_GD
7845 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_GD
7847 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_GD
7849 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_GD
7851 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_IE
7853 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_IE
7855 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL
7857 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL
7859 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL
7861 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL
7863 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL
7865 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL
7867 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_IE
7869 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_IE
7871 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_IE
7873 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_IE
7875 BFD_RELOC_TILEGX_TLS_DTPMOD64
7877 BFD_RELOC_TILEGX_TLS_DTPOFF64
7879 BFD_RELOC_TILEGX_TLS_TPOFF64
7881 BFD_RELOC_TILEGX_TLS_DTPMOD32
7883 BFD_RELOC_TILEGX_TLS_DTPOFF32
7885 BFD_RELOC_TILEGX_TLS_TPOFF32
7887 BFD_RELOC_TILEGX_TLS_GD_CALL
7889 BFD_RELOC_TILEGX_IMM8_X0_TLS_GD_ADD
7891 BFD_RELOC_TILEGX_IMM8_X1_TLS_GD_ADD
7893 BFD_RELOC_TILEGX_IMM8_Y0_TLS_GD_ADD
7895 BFD_RELOC_TILEGX_IMM8_Y1_TLS_GD_ADD
7897 BFD_RELOC_TILEGX_TLS_IE_LOAD
7899 BFD_RELOC_TILEGX_IMM8_X0_TLS_ADD
7901 BFD_RELOC_TILEGX_IMM8_X1_TLS_ADD
7903 BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD
7905 BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD
7907 Tilera TILE-Gx Relocations.
7912 BFD_RELOC_BPF_DISP32
7914 BFD_RELOC_BPF_DISPCALL32
7916 BFD_RELOC_BPF_DISP16
7918 Linux eBPF relocations.
7921 BFD_RELOC_EPIPHANY_SIMM8
7923 Adapteva EPIPHANY - 8 bit signed pc-relative displacement.
7925 BFD_RELOC_EPIPHANY_SIMM24
7927 Adapteva EPIPHANY - 24 bit signed pc-relative displacement.
7929 BFD_RELOC_EPIPHANY_HIGH
7931 Adapteva EPIPHANY - 16 most-significant bits of absolute address.
7933 BFD_RELOC_EPIPHANY_LOW
7935 Adapteva EPIPHANY - 16 least-significant bits of absolute address.
7937 BFD_RELOC_EPIPHANY_SIMM11
7939 Adapteva EPIPHANY - 11 bit signed number - add/sub immediate.
7941 BFD_RELOC_EPIPHANY_IMM11
7943 Adapteva EPIPHANY - 11 bit sign-magnitude number (ld/st
7946 BFD_RELOC_EPIPHANY_IMM8
7948 Adapteva EPIPHANY - 8 bit immediate for 16 bit mov instruction.
7951 BFD_RELOC_VISIUM_HI16
7953 BFD_RELOC_VISIUM_LO16
7955 BFD_RELOC_VISIUM_IM16
7957 BFD_RELOC_VISIUM_REL16
7959 BFD_RELOC_VISIUM_HI16_PCREL
7961 BFD_RELOC_VISIUM_LO16_PCREL
7963 BFD_RELOC_VISIUM_IM16_PCREL
7968 BFD_RELOC_WASM32_LEB128
7970 BFD_RELOC_WASM32_LEB128_GOT
7972 BFD_RELOC_WASM32_LEB128_GOT_CODE
7974 BFD_RELOC_WASM32_LEB128_PLT
7976 BFD_RELOC_WASM32_PLT_INDEX
7978 BFD_RELOC_WASM32_ABS32_CODE
7980 BFD_RELOC_WASM32_COPY
7982 BFD_RELOC_WASM32_CODE_POINTER
7984 BFD_RELOC_WASM32_INDEX
7986 BFD_RELOC_WASM32_PLT_SIG
7988 WebAssembly relocations.
7991 BFD_RELOC_CKCORE_NONE
7993 BFD_RELOC_CKCORE_ADDR32
7995 BFD_RELOC_CKCORE_PCREL_IMM8BY4
7997 BFD_RELOC_CKCORE_PCREL_IMM11BY2
7999 BFD_RELOC_CKCORE_PCREL_IMM4BY2
8001 BFD_RELOC_CKCORE_PCREL32
8003 BFD_RELOC_CKCORE_PCREL_JSR_IMM11BY2
8005 BFD_RELOC_CKCORE_GNU_VTINHERIT
8007 BFD_RELOC_CKCORE_GNU_VTENTRY
8009 BFD_RELOC_CKCORE_RELATIVE
8011 BFD_RELOC_CKCORE_COPY
8013 BFD_RELOC_CKCORE_GLOB_DAT
8015 BFD_RELOC_CKCORE_JUMP_SLOT
8017 BFD_RELOC_CKCORE_GOTOFF
8019 BFD_RELOC_CKCORE_GOTPC
8021 BFD_RELOC_CKCORE_GOT32
8023 BFD_RELOC_CKCORE_PLT32
8025 BFD_RELOC_CKCORE_ADDRGOT
8027 BFD_RELOC_CKCORE_ADDRPLT
8029 BFD_RELOC_CKCORE_PCREL_IMM26BY2
8031 BFD_RELOC_CKCORE_PCREL_IMM16BY2
8033 BFD_RELOC_CKCORE_PCREL_IMM16BY4
8035 BFD_RELOC_CKCORE_PCREL_IMM10BY2
8037 BFD_RELOC_CKCORE_PCREL_IMM10BY4
8039 BFD_RELOC_CKCORE_ADDR_HI16
8041 BFD_RELOC_CKCORE_ADDR_LO16
8043 BFD_RELOC_CKCORE_GOTPC_HI16
8045 BFD_RELOC_CKCORE_GOTPC_LO16
8047 BFD_RELOC_CKCORE_GOTOFF_HI16
8049 BFD_RELOC_CKCORE_GOTOFF_LO16
8051 BFD_RELOC_CKCORE_GOT12
8053 BFD_RELOC_CKCORE_GOT_HI16
8055 BFD_RELOC_CKCORE_GOT_LO16
8057 BFD_RELOC_CKCORE_PLT12
8059 BFD_RELOC_CKCORE_PLT_HI16
8061 BFD_RELOC_CKCORE_PLT_LO16
8063 BFD_RELOC_CKCORE_ADDRGOT_HI16
8065 BFD_RELOC_CKCORE_ADDRGOT_LO16
8067 BFD_RELOC_CKCORE_ADDRPLT_HI16
8069 BFD_RELOC_CKCORE_ADDRPLT_LO16
8071 BFD_RELOC_CKCORE_PCREL_JSR_IMM26BY2
8073 BFD_RELOC_CKCORE_TOFFSET_LO16
8075 BFD_RELOC_CKCORE_DOFFSET_LO16
8077 BFD_RELOC_CKCORE_PCREL_IMM18BY2
8079 BFD_RELOC_CKCORE_DOFFSET_IMM18
8081 BFD_RELOC_CKCORE_DOFFSET_IMM18BY2
8083 BFD_RELOC_CKCORE_DOFFSET_IMM18BY4
8085 BFD_RELOC_CKCORE_GOTOFF_IMM18
8087 BFD_RELOC_CKCORE_GOT_IMM18BY4
8089 BFD_RELOC_CKCORE_PLT_IMM18BY4
8091 BFD_RELOC_CKCORE_PCREL_IMM7BY4
8093 BFD_RELOC_CKCORE_TLS_LE32
8095 BFD_RELOC_CKCORE_TLS_IE32
8097 BFD_RELOC_CKCORE_TLS_GD32
8099 BFD_RELOC_CKCORE_TLS_LDM32
8101 BFD_RELOC_CKCORE_TLS_LDO32
8103 BFD_RELOC_CKCORE_TLS_DTPMOD32
8105 BFD_RELOC_CKCORE_TLS_DTPOFF32
8107 BFD_RELOC_CKCORE_TLS_TPOFF32
8109 BFD_RELOC_CKCORE_PCREL_FLRW_IMM8BY4
8111 BFD_RELOC_CKCORE_NOJSRI
8113 BFD_RELOC_CKCORE_CALLGRAPH
8115 BFD_RELOC_CKCORE_IRELATIVE
8117 BFD_RELOC_CKCORE_PCREL_BLOOP_IMM4BY4
8119 BFD_RELOC_CKCORE_PCREL_BLOOP_IMM12BY4
8129 BFD_RELOC_LARCH_TLS_DTPMOD32
8131 BFD_RELOC_LARCH_TLS_DTPREL32
8133 BFD_RELOC_LARCH_TLS_DTPMOD64
8135 BFD_RELOC_LARCH_TLS_DTPREL64
8137 BFD_RELOC_LARCH_TLS_TPREL32
8139 BFD_RELOC_LARCH_TLS_TPREL64
8141 BFD_RELOC_LARCH_TLS_DESC32
8143 BFD_RELOC_LARCH_TLS_DESC64
8145 BFD_RELOC_LARCH_MARK_LA
8147 BFD_RELOC_LARCH_MARK_PCREL
8149 BFD_RELOC_LARCH_SOP_PUSH_PCREL
8151 BFD_RELOC_LARCH_SOP_PUSH_ABSOLUTE
8153 BFD_RELOC_LARCH_SOP_PUSH_DUP
8155 BFD_RELOC_LARCH_SOP_PUSH_GPREL
8157 BFD_RELOC_LARCH_SOP_PUSH_TLS_TPREL
8159 BFD_RELOC_LARCH_SOP_PUSH_TLS_GOT
8161 BFD_RELOC_LARCH_SOP_PUSH_TLS_GD
8163 BFD_RELOC_LARCH_SOP_PUSH_PLT_PCREL
8165 BFD_RELOC_LARCH_SOP_ASSERT
8167 BFD_RELOC_LARCH_SOP_NOT
8169 BFD_RELOC_LARCH_SOP_SUB
8171 BFD_RELOC_LARCH_SOP_SL
8173 BFD_RELOC_LARCH_SOP_SR
8175 BFD_RELOC_LARCH_SOP_ADD
8177 BFD_RELOC_LARCH_SOP_AND
8179 BFD_RELOC_LARCH_SOP_IF_ELSE
8181 BFD_RELOC_LARCH_SOP_POP_32_S_10_5
8183 BFD_RELOC_LARCH_SOP_POP_32_U_10_12
8185 BFD_RELOC_LARCH_SOP_POP_32_S_10_12
8187 BFD_RELOC_LARCH_SOP_POP_32_S_10_16
8189 BFD_RELOC_LARCH_SOP_POP_32_S_10_16_S2
8191 BFD_RELOC_LARCH_SOP_POP_32_S_5_20
8193 BFD_RELOC_LARCH_SOP_POP_32_S_0_5_10_16_S2
8195 BFD_RELOC_LARCH_SOP_POP_32_S_0_10_10_16_S2
8197 BFD_RELOC_LARCH_SOP_POP_32_U
8199 BFD_RELOC_LARCH_ADD8
8201 BFD_RELOC_LARCH_ADD16
8203 BFD_RELOC_LARCH_ADD24
8205 BFD_RELOC_LARCH_ADD32
8207 BFD_RELOC_LARCH_ADD64
8209 BFD_RELOC_LARCH_SUB8
8211 BFD_RELOC_LARCH_SUB16
8213 BFD_RELOC_LARCH_SUB24
8215 BFD_RELOC_LARCH_SUB32
8217 BFD_RELOC_LARCH_SUB64
8227 BFD_RELOC_LARCH_ABS_HI20
8229 BFD_RELOC_LARCH_ABS_LO12
8231 BFD_RELOC_LARCH_ABS64_LO20
8233 BFD_RELOC_LARCH_ABS64_HI12
8236 BFD_RELOC_LARCH_PCALA_HI20
8238 BFD_RELOC_LARCH_PCALA_LO12
8240 BFD_RELOC_LARCH_PCALA64_LO20
8242 BFD_RELOC_LARCH_PCALA64_HI12
8245 BFD_RELOC_LARCH_GOT_PC_HI20
8247 BFD_RELOC_LARCH_GOT_PC_LO12
8249 BFD_RELOC_LARCH_GOT64_PC_LO20
8251 BFD_RELOC_LARCH_GOT64_PC_HI12
8253 BFD_RELOC_LARCH_GOT_HI20
8255 BFD_RELOC_LARCH_GOT_LO12
8257 BFD_RELOC_LARCH_GOT64_LO20
8259 BFD_RELOC_LARCH_GOT64_HI12
8262 BFD_RELOC_LARCH_TLS_LE_HI20
8264 BFD_RELOC_LARCH_TLS_LE_LO12
8266 BFD_RELOC_LARCH_TLS_LE64_LO20
8268 BFD_RELOC_LARCH_TLS_LE64_HI12
8270 BFD_RELOC_LARCH_TLS_IE_PC_HI20
8272 BFD_RELOC_LARCH_TLS_IE_PC_LO12
8274 BFD_RELOC_LARCH_TLS_IE64_PC_LO20
8276 BFD_RELOC_LARCH_TLS_IE64_PC_HI12
8278 BFD_RELOC_LARCH_TLS_IE_HI20
8280 BFD_RELOC_LARCH_TLS_IE_LO12
8282 BFD_RELOC_LARCH_TLS_IE64_LO20
8284 BFD_RELOC_LARCH_TLS_IE64_HI12
8286 BFD_RELOC_LARCH_TLS_LD_PC_HI20
8288 BFD_RELOC_LARCH_TLS_LD_HI20
8290 BFD_RELOC_LARCH_TLS_GD_PC_HI20
8292 BFD_RELOC_LARCH_TLS_GD_HI20
8295 BFD_RELOC_LARCH_32_PCREL
8298 BFD_RELOC_LARCH_RELAX
8301 BFD_RELOC_LARCH_DELETE
8304 BFD_RELOC_LARCH_ALIGN
8307 BFD_RELOC_LARCH_PCREL20_S2
8313 BFD_RELOC_LARCH_ADD6
8315 BFD_RELOC_LARCH_SUB6
8318 BFD_RELOC_LARCH_ADD_ULEB128
8320 BFD_RELOC_LARCH_SUB_ULEB128
8323 BFD_RELOC_LARCH_64_PCREL
8326 BFD_RELOC_LARCH_CALL36
8329 BFD_RELOC_LARCH_TLS_DESC_PC_HI20
8331 BFD_RELOC_LARCH_TLS_DESC_PC_LO12
8334 BFD_RELOC_LARCH_TLS_DESC64_PC_LO20
8336 BFD_RELOC_LARCH_TLS_DESC64_PC_HI12
8339 BFD_RELOC_LARCH_TLS_DESC_HI20
8341 BFD_RELOC_LARCH_TLS_DESC_LO12
8344 BFD_RELOC_LARCH_TLS_DESC64_LO20
8346 BFD_RELOC_LARCH_TLS_DESC64_HI12
8349 BFD_RELOC_LARCH_TLS_DESC_LD
8351 BFD_RELOC_LARCH_TLS_DESC_CALL
8354 BFD_RELOC_LARCH_TLS_LE_HI20_R
8356 BFD_RELOC_LARCH_TLS_LE_ADD_R
8358 BFD_RELOC_LARCH_TLS_LE_LO12_R
8361 BFD_RELOC_LARCH_TLS_LD_PCREL20_S2
8363 BFD_RELOC_LARCH_TLS_GD_PCREL20_S2
8365 BFD_RELOC_LARCH_TLS_DESC_PCREL20_S2
8374 .typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
8380 bfd_reloc_type_lookup
8381 bfd_reloc_name_lookup
8384 reloc_howto_type *bfd_reloc_type_lookup
8385 (bfd *abfd, bfd_reloc_code_real_type code);
8386 reloc_howto_type *bfd_reloc_name_lookup
8387 (bfd *abfd, const char *reloc_name);
8390 Return a pointer to a howto structure which, when
8391 invoked, will perform the relocation @var{code} on data from the
8396 bfd_reloc_type_lookup (bfd
*abfd
, bfd_reloc_code_real_type code
)
8398 return BFD_SEND (abfd
, reloc_type_lookup
, (abfd
, code
));
8402 bfd_reloc_name_lookup (bfd
*abfd
, const char *reloc_name
)
8404 return BFD_SEND (abfd
, reloc_name_lookup
, (abfd
, reloc_name
));
8407 static reloc_howto_type bfd_howto_32
=
8408 HOWTO (0, 00, 4, 32, false, 0, complain_overflow_dont
, 0, "VRT32", false, 0xffffffff, 0xffffffff, true);
8412 bfd_default_reloc_type_lookup
8415 reloc_howto_type *bfd_default_reloc_type_lookup
8416 (bfd *abfd, bfd_reloc_code_real_type code);
8419 Provides a default relocation lookup routine for any architecture.
8423 bfd_default_reloc_type_lookup (bfd
*abfd
, bfd_reloc_code_real_type code
)
8425 /* Very limited support is provided for relocs in generic targets
8426 such as elf32-little. FIXME: Should we always return NULL? */
8427 if (code
== BFD_RELOC_CTOR
8428 && bfd_arch_bits_per_address (abfd
) == 32)
8429 return &bfd_howto_32
;
8435 bfd_get_reloc_code_name
8438 const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code);
8441 Provides a printable name for the supplied relocation code.
8442 Useful mainly for printing error messages.
8446 bfd_get_reloc_code_name (bfd_reloc_code_real_type code
)
8448 if (code
> BFD_RELOC_UNUSED
)
8450 return bfd_reloc_code_real_names
[code
];
8455 bfd_generic_relax_section
8458 bool bfd_generic_relax_section
8461 struct bfd_link_info *,
8465 Provides default handling for relaxing for back ends which
8470 bfd_generic_relax_section (bfd
*abfd ATTRIBUTE_UNUSED
,
8471 asection
*section ATTRIBUTE_UNUSED
,
8472 struct bfd_link_info
*link_info ATTRIBUTE_UNUSED
,
8475 if (bfd_link_relocatable (link_info
))
8476 (*link_info
->callbacks
->einfo
)
8477 (_("%P%F: --relax and -r may not be used together\n"));
8485 bfd_generic_gc_sections
8488 bool bfd_generic_gc_sections
8489 (bfd *, struct bfd_link_info *);
8492 Provides default handling for relaxing for back ends which
8493 don't do section gc -- i.e., does nothing.
8497 bfd_generic_gc_sections (bfd
*abfd ATTRIBUTE_UNUSED
,
8498 struct bfd_link_info
*info ATTRIBUTE_UNUSED
)
8505 bfd_generic_lookup_section_flags
8508 bool bfd_generic_lookup_section_flags
8509 (struct bfd_link_info *, struct flag_info *, asection *);
8512 Provides default handling for section flags lookup
8513 -- i.e., does nothing.
8514 Returns FALSE if the section should be omitted, otherwise TRUE.
8518 bfd_generic_lookup_section_flags (struct bfd_link_info
*info ATTRIBUTE_UNUSED
,
8519 struct flag_info
*flaginfo
,
8520 asection
*section ATTRIBUTE_UNUSED
)
8522 if (flaginfo
!= NULL
)
8524 _bfd_error_handler (_("INPUT_SECTION_FLAGS are not supported"));
8532 bfd_generic_merge_sections
8535 bool bfd_generic_merge_sections
8536 (bfd *, struct bfd_link_info *);
8539 Provides default handling for SEC_MERGE section merging for back ends
8540 which don't have SEC_MERGE support -- i.e., does nothing.
8544 bfd_generic_merge_sections (bfd
*abfd ATTRIBUTE_UNUSED
,
8545 struct bfd_link_info
*link_info ATTRIBUTE_UNUSED
)
8552 bfd_generic_get_relocated_section_contents
8555 bfd_byte *bfd_generic_get_relocated_section_contents
8557 struct bfd_link_info *link_info,
8558 struct bfd_link_order *link_order,
8564 Provides default handling of relocation effort for back ends
8565 which can't be bothered to do it efficiently.
8569 bfd_generic_get_relocated_section_contents (bfd
*abfd
,
8570 struct bfd_link_info
*link_info
,
8571 struct bfd_link_order
*link_order
,
8576 bfd
*input_bfd
= link_order
->u
.indirect
.section
->owner
;
8577 asection
*input_section
= link_order
->u
.indirect
.section
;
8579 arelent
**reloc_vector
;
8582 reloc_size
= bfd_get_reloc_upper_bound (input_bfd
, input_section
);
8586 /* Read in the section. */
8587 bfd_byte
*orig_data
= data
;
8588 if (!bfd_get_full_section_contents (input_bfd
, input_section
, &data
))
8594 if (reloc_size
== 0)
8597 reloc_vector
= (arelent
**) bfd_malloc (reloc_size
);
8598 if (reloc_vector
== NULL
)
8601 reloc_count
= bfd_canonicalize_reloc (input_bfd
,
8605 if (reloc_count
< 0)
8608 if (reloc_count
> 0)
8612 for (parent
= reloc_vector
; *parent
!= NULL
; parent
++)
8614 char *error_message
= NULL
;
8616 bfd_reloc_status_type r
;
8618 symbol
= *(*parent
)->sym_ptr_ptr
;
8619 /* PR ld/19628: A specially crafted input file
8620 can result in a NULL symbol pointer here. */
8623 link_info
->callbacks
->einfo
8624 /* xgettext:c-format */
8625 (_("%X%P: %pB(%pA): error: relocation for offset %V has no value\n"),
8626 abfd
, input_section
, (* parent
)->address
);
8630 /* Zap reloc field when the symbol is from a discarded
8631 section, ignoring any addend. Do the same when called
8632 from bfd_simple_get_relocated_section_contents for
8633 undefined symbols in debug sections. This is to keep
8634 debug info reasonably sane, in particular so that
8635 DW_FORM_ref_addr to another file's .debug_info isn't
8636 confused with an offset into the current file's
8638 if ((symbol
->section
!= NULL
&& discarded_section (symbol
->section
))
8639 || (symbol
->section
== bfd_und_section_ptr
8640 && (input_section
->flags
& SEC_DEBUGGING
) != 0
8641 && link_info
->input_bfds
== link_info
->output_bfd
))
8644 static reloc_howto_type none_howto
8645 = HOWTO (0, 0, 0, 0, false, 0, complain_overflow_dont
, NULL
,
8646 "unused", false, 0, 0, false);
8648 off
= ((*parent
)->address
8649 * bfd_octets_per_byte (input_bfd
, input_section
));
8650 _bfd_clear_contents ((*parent
)->howto
, input_bfd
,
8651 input_section
, data
, off
);
8652 (*parent
)->sym_ptr_ptr
= bfd_abs_section_ptr
->symbol_ptr_ptr
;
8653 (*parent
)->addend
= 0;
8654 (*parent
)->howto
= &none_howto
;
8658 r
= bfd_perform_relocation (input_bfd
,
8662 relocatable
? abfd
: NULL
,
8667 asection
*os
= input_section
->output_section
;
8669 /* A partial link, so keep the relocs. */
8670 os
->orelocation
[os
->reloc_count
] = *parent
;
8674 if (r
!= bfd_reloc_ok
)
8678 case bfd_reloc_undefined
:
8679 (*link_info
->callbacks
->undefined_symbol
)
8680 (link_info
, bfd_asymbol_name (*(*parent
)->sym_ptr_ptr
),
8681 input_bfd
, input_section
, (*parent
)->address
, true);
8683 case bfd_reloc_dangerous
:
8684 BFD_ASSERT (error_message
!= NULL
);
8685 (*link_info
->callbacks
->reloc_dangerous
)
8686 (link_info
, error_message
,
8687 input_bfd
, input_section
, (*parent
)->address
);
8689 case bfd_reloc_overflow
:
8690 (*link_info
->callbacks
->reloc_overflow
)
8692 bfd_asymbol_name (*(*parent
)->sym_ptr_ptr
),
8693 (*parent
)->howto
->name
, (*parent
)->addend
,
8694 input_bfd
, input_section
, (*parent
)->address
);
8696 case bfd_reloc_outofrange
:
8698 This error can result when processing some partially
8699 complete binaries. Do not abort, but issue an error
8701 link_info
->callbacks
->einfo
8702 /* xgettext:c-format */
8703 (_("%X%P: %pB(%pA): relocation \"%pR\" goes out of range\n"),
8704 abfd
, input_section
, * parent
);
8707 case bfd_reloc_notsupported
:
8709 This error can result when processing a corrupt binary.
8710 Do not abort. Issue an error message instead. */
8711 link_info
->callbacks
->einfo
8712 /* xgettext:c-format */
8713 (_("%X%P: %pB(%pA): relocation \"%pR\" is not supported\n"),
8714 abfd
, input_section
, * parent
);
8718 /* PR 17512; file: 90c2a92e.
8719 Report unexpected results, without aborting. */
8720 link_info
->callbacks
->einfo
8721 /* xgettext:c-format */
8722 (_("%X%P: %pB(%pA): relocation \"%pR\" returns an unrecognized value %x\n"),
8723 abfd
, input_section
, * parent
, r
);
8731 free (reloc_vector
);
8735 free (reloc_vector
);
8736 if (orig_data
== NULL
)
8743 _bfd_generic_set_reloc
8746 void _bfd_generic_set_reloc
8750 unsigned int count);
8753 Installs a new set of internal relocations in SECTION.
8757 _bfd_generic_set_reloc (bfd
*abfd ATTRIBUTE_UNUSED
,
8762 section
->orelocation
= relptr
;
8763 section
->reloc_count
= count
;
8765 section
->flags
|= SEC_RELOC
;
8767 section
->flags
&= ~SEC_RELOC
;
8772 _bfd_unrecognized_reloc
8775 bool _bfd_unrecognized_reloc
8778 unsigned int r_type);
8781 Reports an unrecognized reloc.
8782 Written as a function in order to reduce code duplication.
8783 Returns FALSE so that it can be called from a return statement.
8787 _bfd_unrecognized_reloc (bfd
* abfd
, sec_ptr section
, unsigned int r_type
)
8789 /* xgettext:c-format */
8790 _bfd_error_handler (_("%pB: unrecognized relocation type %#x in section `%pA'"),
8791 abfd
, r_type
, section
);
8793 /* PR 21803: Suggest the most likely cause of this error. */
8794 _bfd_error_handler (_("is this version of the linker - %s - out of date ?"),
8795 BFD_VERSION_STRING
);
8797 bfd_set_error (bfd_error_bad_value
);
8802 _bfd_norelocs_bfd_reloc_type_lookup
8804 bfd_reloc_code_real_type code ATTRIBUTE_UNUSED
)
8806 return (reloc_howto_type
*) _bfd_ptr_bfd_null_error (abfd
);
8810 _bfd_norelocs_bfd_reloc_name_lookup (bfd
*abfd
,
8811 const char *reloc_name ATTRIBUTE_UNUSED
)
8813 return (reloc_howto_type
*) _bfd_ptr_bfd_null_error (abfd
);
8817 _bfd_nodynamic_canonicalize_dynamic_reloc (bfd
*abfd
,
8818 arelent
**relp ATTRIBUTE_UNUSED
,
8819 asymbol
**symp ATTRIBUTE_UNUSED
)
8821 return _bfd_long_bfd_n1_error (abfd
);