gdb/nat/mips-linux-watch.c

   1 /* Copyright (C) 2009-2024 Free Software Foundation, Inc.
   2
   3    This file is part of GDB.
   4
   5    This program is free software; you can redistribute it and/or modify
   6    it under the terms of the GNU General Public License as published by
   7    the Free Software Foundation; either version 3 of the License, or
   8    (at your option) any later version.
   9
  10    This program is distributed in the hope that it will be useful,
  11    but WITHOUT ANY WARRANTY; without even the implied warranty of
  12    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13    GNU General Public License for more details.
  14
  15    You should have received a copy of the GNU General Public License
  16    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  17
  18 #include "nat/gdb_ptrace.h"
  19 #include "mips-linux-watch.h"
  20
  21 /* Assuming usable watch registers REGS, return the irw_mask of
  22    register N.  */
  23
  24 uint32_t
  25 mips_linux_watch_get_irw_mask (struct pt_watch_regs *regs, int n)
  26 {
  27   switch (regs->style)
  28     {
  29     case pt_watch_style_mips32:
  30       return regs->mips32.watch_masks[n] & IRW_MASK;
  31     case pt_watch_style_mips64:
  32       return regs->mips64.watch_masks[n] & IRW_MASK;
  33     default:
  34       internal_error (_("Unrecognized watch register style"));
  35     }
  36 }
  37
  38 /* Assuming usable watch registers REGS, return the reg_mask of
  39    register N.  */
  40
  41 static uint32_t
  42 get_reg_mask (struct pt_watch_regs *regs, int n)
  43 {
  44   switch (regs->style)
  45     {
  46     case pt_watch_style_mips32:
  47       return regs->mips32.watch_masks[n] & ~IRW_MASK;
  48     case pt_watch_style_mips64:
  49       return regs->mips64.watch_masks[n] & ~IRW_MASK;
  50     default:
  51       internal_error (_("Unrecognized watch register style"));
  52     }
  53 }
  54
  55 /* Assuming usable watch registers REGS, return the num_valid.  */
  56
  57 uint32_t
  58 mips_linux_watch_get_num_valid (struct pt_watch_regs *regs)
  59 {
  60   switch (regs->style)
  61     {
  62     case pt_watch_style_mips32:
  63       return regs->mips32.num_valid;
  64     case pt_watch_style_mips64:
  65       return regs->mips64.num_valid;
  66     default:
  67       internal_error (_("Unrecognized watch register style"));
  68     }
  69 }
  70
  71 /* Assuming usable watch registers REGS, return the watchlo of
  72    register N.  */
  73
  74 CORE_ADDR
  75 mips_linux_watch_get_watchlo (struct pt_watch_regs *regs, int n)
  76 {
  77   switch (regs->style)
  78     {
  79     case pt_watch_style_mips32:
  80       return regs->mips32.watchlo[n];
  81     case pt_watch_style_mips64:
  82       return regs->mips64.watchlo[n];
  83     default:
  84       internal_error (_("Unrecognized watch register style"));
  85     }
  86 }
  87
  88 /* Assuming usable watch registers REGS, set watchlo of register N to
  89    VALUE.  */
  90
  91 void
  92 mips_linux_watch_set_watchlo (struct pt_watch_regs *regs, int n,
  93                               CORE_ADDR value)
  94 {
  95   switch (regs->style)
  96     {
  97     case pt_watch_style_mips32:
  98       /*  The cast will never throw away bits as 64 bit addresses can
  99           never be used on a 32 bit kernel.  */
 100       regs->mips32.watchlo[n] = (uint32_t) value;
 101       break;
 102     case pt_watch_style_mips64:
 103       regs->mips64.watchlo[n] = value;
 104       break;
 105     default:
 106       internal_error (_("Unrecognized watch register style"));
 107     }
 108 }
 109
 110 /* Assuming usable watch registers REGS, return the watchhi of
 111    register N.  */
 112
 113 uint32_t
 114 mips_linux_watch_get_watchhi (struct pt_watch_regs *regs, int n)
 115 {
 116   switch (regs->style)
 117     {
 118     case pt_watch_style_mips32:
 119       return regs->mips32.watchhi[n];
 120     case pt_watch_style_mips64:
 121       return regs->mips64.watchhi[n];
 122     default:
 123       internal_error (_("Unrecognized watch register style"));
 124     }
 125 }
 126
 127 /* Assuming usable watch registers REGS, set watchhi of register N to
 128    VALUE.  */
 129
 130 void
 131 mips_linux_watch_set_watchhi (struct pt_watch_regs *regs, int n,
 132                               uint16_t value)
 133 {
 134   switch (regs->style)
 135     {
 136     case pt_watch_style_mips32:
 137       regs->mips32.watchhi[n] = value;
 138       break;
 139     case pt_watch_style_mips64:
 140       regs->mips64.watchhi[n] = value;
 141       break;
 142     default:
 143       internal_error (_("Unrecognized watch register style"));
 144     }
 145 }
 146
 147 /* Read the watch registers of process LWPID and store it in
 148    WATCH_READBACK.  Save true to *WATCH_READBACK_VALID if watch
 149    registers are valid.  Return 1 if watch registers are usable.
 150    Cached information is used unless FORCE is true.  */
 151
 152 int
 153 mips_linux_read_watch_registers (long lwpid,
 154                                  struct pt_watch_regs *watch_readback,
 155                                  int *watch_readback_valid, int force)
 156 {
 157   if (force || *watch_readback_valid == 0)
 158     {
 159       if (ptrace (PTRACE_GET_WATCH_REGS, lwpid, watch_readback, NULL) == -1)
 160         {
 161           *watch_readback_valid = -1;
 162           return 0;
 163         }
 164       switch (watch_readback->style)
 165         {
 166         case pt_watch_style_mips32:
 167           if (watch_readback->mips32.num_valid == 0)
 168             {
 169               *watch_readback_valid = -1;
 170               return 0;
 171             }
 172           break;
 173         case pt_watch_style_mips64:
 174           if (watch_readback->mips64.num_valid == 0)
 175             {
 176               *watch_readback_valid = -1;
 177               return 0;
 178             }
 179           break;
 180         default:
 181           *watch_readback_valid = -1;
 182           return 0;
 183         }
 184       /* Watch registers appear to be usable.  */
 185       *watch_readback_valid = 1;
 186     }
 187   return (*watch_readback_valid == 1) ? 1 : 0;
 188 }
 189
 190 /* Convert GDB's TYPE to an IRW mask.  */
 191
 192 uint32_t
 193 mips_linux_watch_type_to_irw (enum target_hw_bp_type type)
 194 {
 195   switch (type)
 196     {
 197     case hw_write:
 198       return W_MASK;
 199     case hw_read:
 200       return R_MASK;
 201     case hw_access:
 202       return (W_MASK | R_MASK);
 203     default:
 204       return 0;
 205     }
 206 }
 207
 208 /* Set any low order bits in MASK that are not set.  */
 209
 210 static CORE_ADDR
 211 fill_mask (CORE_ADDR mask)
 212 {
 213   CORE_ADDR f = 1;
 214
 215   while (f && f < mask)
 216     {
 217       mask |= f;
 218       f <<= 1;
 219     }
 220   return mask;
 221 }
 222
 223 /* Try to add a single watch to the specified registers REGS.  The
 224    address of added watch is ADDR, the length is LEN, and the mask
 225    is IRW.  Return 1 on success, 0 on failure.  */
 226
 227 int
 228 mips_linux_watch_try_one_watch (struct pt_watch_regs *regs,
 229                                 CORE_ADDR addr, int len, uint32_t irw)
 230 {
 231   CORE_ADDR base_addr, last_byte, break_addr, segment_len;
 232   CORE_ADDR mask_bits, t_low;
 233   uint16_t t_hi;
 234   int i, free_watches;
 235   struct pt_watch_regs regs_copy;
 236
 237   if (len <= 0)
 238     return 0;
 239
 240   last_byte = addr + len - 1;
 241   mask_bits = fill_mask (addr ^ last_byte) | IRW_MASK;
 242   base_addr = addr & ~mask_bits;
 243
 244   /* Check to see if it is covered by current registers.  */
 245   for (i = 0; i < mips_linux_watch_get_num_valid (regs); i++)
 246     {
 247       t_low = mips_linux_watch_get_watchlo (regs, i);
 248       if (t_low != 0 && irw == ((uint32_t) t_low & irw))
 249         {
 250           t_hi = mips_linux_watch_get_watchhi (regs, i) | IRW_MASK;
 251           t_low &= ~(CORE_ADDR) t_hi;
 252           if (addr >= t_low && last_byte <= (t_low + t_hi))
 253             return 1;
 254         }
 255     }
 256   /* Try to find an empty register.  */
 257   free_watches = 0;
 258   for (i = 0; i < mips_linux_watch_get_num_valid (regs); i++)
 259     {
 260       t_low = mips_linux_watch_get_watchlo (regs, i);
 261       if (t_low == 0
 262           && irw == (mips_linux_watch_get_irw_mask (regs, i) & irw))
 263         {
 264           if (mask_bits <= (get_reg_mask (regs, i) | IRW_MASK))
 265             {
 266               /* It fits, we'll take it.  */
 267               mips_linux_watch_set_watchlo (regs, i, base_addr | irw);
 268               mips_linux_watch_set_watchhi (regs, i, mask_bits & ~IRW_MASK);
 269               return 1;
 270             }
 271           else
 272             {
 273               /* It doesn't fit, but has the proper IRW capabilities.  */
 274               free_watches++;
 275             }
 276         }
 277     }
 278   if (free_watches > 1)
 279     {
 280       /* Try to split it across several registers.  */
 281       regs_copy = *regs;
 282       for (i = 0; i < mips_linux_watch_get_num_valid (&regs_copy); i++)
 283         {
 284           t_low = mips_linux_watch_get_watchlo (&regs_copy, i);
 285           t_hi = get_reg_mask (&regs_copy, i) | IRW_MASK;
 286           if (t_low == 0 && irw == (t_hi & irw))
 287             {
 288               t_low = addr & ~(CORE_ADDR) t_hi;
 289               break_addr = t_low + t_hi + 1;
 290               if (break_addr >= addr + len)
 291                 segment_len = len;
 292               else
 293                 segment_len = break_addr - addr;
 294               mask_bits = fill_mask (addr ^ (addr + segment_len - 1));
 295               mips_linux_watch_set_watchlo (&regs_copy, i,
 296                                             (addr & ~mask_bits) | irw);
 297               mips_linux_watch_set_watchhi (&regs_copy, i,
 298                                             mask_bits & ~IRW_MASK);
 299               if (break_addr >= addr + len)
 300                 {
 301                   *regs = regs_copy;
 302                   return 1;
 303                 }
 304               len = addr + len - break_addr;
 305               addr = break_addr;
 306             }
 307         }
 308     }
 309   /* It didn't fit anywhere, we failed.  */
 310   return 0;
 311 }
 312
 313 /* Fill in the watch registers REGS with the currently cached
 314    watches CURRENT_WATCHES.  */
 315
 316 void
 317 mips_linux_watch_populate_regs (struct mips_watchpoint *current_watches,
 318                                 struct pt_watch_regs *regs)
 319 {
 320   struct mips_watchpoint *w;
 321   int i;
 322
 323   /* Clear them out.  */
 324   for (i = 0; i < mips_linux_watch_get_num_valid (regs); i++)
 325     {
 326       mips_linux_watch_set_watchlo (regs, i, 0);
 327       mips_linux_watch_set_watchhi (regs, i, 0);
 328     }
 329
 330   w = current_watches;
 331   while (w)
 332     {
 333       uint32_t irw = mips_linux_watch_type_to_irw (w->type);
 334
 335       i = mips_linux_watch_try_one_watch (regs, w->addr, w->len, irw);
 336       /* They must all fit, because we previously calculated that they
 337          would.  */
 338       gdb_assert (i);
 339       w = w->next;
 340     }
 341 }