gdb/riscv-fbsd-tdep.c

   1 /* Target-dependent code for FreeBSD on RISC-V processors.
   2    Copyright (C) 2018-2024 Free Software Foundation, Inc.
   3
   4    This file is part of GDB.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3 of the License, or
   9    (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  18
  19 #include "extract-store-integer.h"
  20 #include "fbsd-tdep.h"
  21 #include "osabi.h"
  22 #include "riscv-tdep.h"
  23 #include "riscv-fbsd-tdep.h"
  24 #include "solib-svr4.h"
  25 #include "target.h"
  26 #include "trad-frame.h"
  27 #include "tramp-frame.h"
  28 #include "gdbarch.h"
  29 #include "inferior.h"
  30
  31 /* Register maps.  */
  32
  33 static const struct regcache_map_entry riscv_fbsd_gregmap[] =
  34   {
  35     { 1, RISCV_RA_REGNUM, 0 },
  36     { 1, RISCV_SP_REGNUM, 0 },
  37     { 1, RISCV_GP_REGNUM, 0 },
  38     { 1, RISCV_TP_REGNUM, 0 },
  39     { 3, 5, 0 },                /* t0 - t2 */
  40     { 4, 28, 0 },               /* t3 - t6 */
  41     { 2, RISCV_FP_REGNUM, 0 },  /* s0 - s1 */
  42     { 10, 18, 0 },              /* s2 - s11 */
  43     { 8, RISCV_A0_REGNUM, 0 },  /* a0 - a7 */
  44     { 1, RISCV_PC_REGNUM, 0 },
  45     { 1, RISCV_CSR_SSTATUS_REGNUM, 0 },
  46     { 0 }
  47   };
  48
  49 static const struct regcache_map_entry riscv_fbsd_fpregmap[] =
  50   {
  51     { 32, RISCV_FIRST_FP_REGNUM, 16 },
  52     { 1, RISCV_CSR_FCSR_REGNUM, 8 },
  53     { 0 }
  54   };
  55
  56 /* Register set definitions.  */
  57
  58 const struct regset riscv_fbsd_gregset =
  59   {
  60     riscv_fbsd_gregmap, riscv_supply_regset, regcache_collect_regset
  61   };
  62
  63 const struct regset riscv_fbsd_fpregset =
  64   {
  65     riscv_fbsd_fpregmap, riscv_supply_regset, regcache_collect_regset
  66   };
  67
  68 /* Implement the "iterate_over_regset_sections" gdbarch method.  */
  69
  70 static void
  71 riscv_fbsd_iterate_over_regset_sections (struct gdbarch *gdbarch,
  72                                          iterate_over_regset_sections_cb *cb,
  73                                          void *cb_data,
  74                                          const struct regcache *regcache)
  75 {
  76   cb (".reg", RISCV_FBSD_NUM_GREGS * riscv_isa_xlen (gdbarch),
  77       RISCV_FBSD_NUM_GREGS * riscv_isa_xlen (gdbarch),
  78       &riscv_fbsd_gregset, NULL, cb_data);
  79   cb (".reg2", RISCV_FBSD_SIZEOF_FPREGSET, RISCV_FBSD_SIZEOF_FPREGSET,
  80       &riscv_fbsd_fpregset, NULL, cb_data);
  81 }
  82
  83 /* In a signal frame, sp points to a 'struct sigframe' which is
  84    defined as:
  85
  86    struct sigframe {
  87            siginfo_t    sf_si;
  88            ucontext_t   sf_uc;
  89    };
  90
  91    ucontext_t is defined as:
  92
  93    struct __ucontext {
  94            sigset_t     uc_sigmask;
  95            mcontext_t   uc_mcontext;
  96            ...
  97    };
  98
  99    The mcontext_t contains the general purpose register set followed
 100    by the floating point register set.  The floating point register
 101    set is only valid if the _MC_FP_VALID flag is set in mc_flags.  */
 102
 103 #define RISCV_SIGFRAME_UCONTEXT_OFFSET          80
 104 #define RISCV_UCONTEXT_MCONTEXT_OFFSET          16
 105 #define RISCV_MCONTEXT_FLAG_FP_VALID            0x1
 106
 107 /* Implement the "init" method of struct tramp_frame.  */
 108
 109 static void
 110 riscv_fbsd_sigframe_init (const struct tramp_frame *self,
 111                           const frame_info_ptr &this_frame,
 112                           struct trad_frame_cache *this_cache,
 113                           CORE_ADDR func)
 114 {
 115   struct gdbarch *gdbarch = get_frame_arch (this_frame);
 116   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
 117   CORE_ADDR sp = get_frame_register_unsigned (this_frame, RISCV_SP_REGNUM);
 118   CORE_ADDR mcontext_addr
 119     = (sp
 120        + RISCV_SIGFRAME_UCONTEXT_OFFSET
 121        + RISCV_UCONTEXT_MCONTEXT_OFFSET);
 122   gdb_byte buf[4];
 123
 124   trad_frame_set_reg_regmap (this_cache, riscv_fbsd_gregmap, mcontext_addr,
 125                              RISCV_FBSD_NUM_GREGS * riscv_isa_xlen (gdbarch));
 126
 127   CORE_ADDR fpregs_addr
 128     = mcontext_addr + RISCV_FBSD_NUM_GREGS * riscv_isa_xlen (gdbarch);
 129   CORE_ADDR fp_flags_addr
 130     = fpregs_addr + RISCV_FBSD_SIZEOF_FPREGSET;
 131   if (target_read_memory (fp_flags_addr, buf, 4) == 0
 132       && (extract_unsigned_integer (buf, 4, byte_order)
 133           & RISCV_MCONTEXT_FLAG_FP_VALID))
 134     trad_frame_set_reg_regmap (this_cache, riscv_fbsd_fpregmap, fpregs_addr,
 135                                RISCV_FBSD_SIZEOF_FPREGSET);
 136
 137   trad_frame_set_id (this_cache, frame_id_build (sp, func));
 138 }
 139
 140 /* RISC-V supports 16-bit instructions ("C") as well as 32-bit
 141    instructions.  The signal trampoline on FreeBSD uses a mix of
 142    these, but tramp_frame assumes a fixed instruction size.  To cope,
 143    claim that all instructions are 16 bits and use two "slots" for
 144    32-bit instructions.  */
 145
 146 static const struct tramp_frame riscv_fbsd_sigframe =
 147 {
 148   SIGTRAMP_FRAME,
 149   2,
 150   {
 151     {0x850a, ULONGEST_MAX},             /* mov  a0, sp  */
 152     {0x0513, ULONGEST_MAX},             /* addi a0, a0, #SF_UC  */
 153     {0x0505, ULONGEST_MAX},
 154     {0x0293, ULONGEST_MAX},             /* li   t0, #SYS_sigreturn  */
 155     {0x1a10, ULONGEST_MAX},
 156     {0x0073, ULONGEST_MAX},             /* ecall  */
 157     {0x0000, ULONGEST_MAX},
 158     {TRAMP_SENTINEL_INSN, ULONGEST_MAX}
 159   },
 160   riscv_fbsd_sigframe_init
 161 };
 162
 163 /* Implement the "get_thread_local_address" gdbarch method.  */
 164
 165 static CORE_ADDR
 166 riscv_fbsd_get_thread_local_address (struct gdbarch *gdbarch, ptid_t ptid,
 167                                      CORE_ADDR lm_addr, CORE_ADDR offset)
 168 {
 169   regcache *regcache
 170     = get_thread_arch_regcache (current_inferior (), ptid, gdbarch);
 171
 172   target_fetch_registers (regcache, RISCV_TP_REGNUM);
 173
 174   ULONGEST tp;
 175   if (regcache->cooked_read (RISCV_TP_REGNUM, &tp) != REG_VALID)
 176     error (_("Unable to fetch %%tp"));
 177
 178   /* %tp points to the end of the TCB which contains two pointers.
 179       The first pointer in the TCB points to the DTV array.  */
 180   CORE_ADDR dtv_addr = tp - (gdbarch_ptr_bit (gdbarch) / 8) * 2;
 181   return fbsd_get_thread_local_address (gdbarch, dtv_addr, lm_addr, offset);
 182 }
 183
 184 /* Implement the 'init_osabi' method of struct gdb_osabi_handler.  */
 185
 186 static void
 187 riscv_fbsd_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
 188 {
 189   /* Generic FreeBSD support.  */
 190   fbsd_init_abi (info, gdbarch);
 191
 192   set_gdbarch_software_single_step (gdbarch, riscv_software_single_step);
 193
 194   set_solib_svr4_fetch_link_map_offsets (gdbarch,
 195                                          (riscv_isa_xlen (gdbarch) == 4
 196                                           ? svr4_ilp32_fetch_link_map_offsets
 197                                           : svr4_lp64_fetch_link_map_offsets));
 198
 199   tramp_frame_prepend_unwinder (gdbarch, &riscv_fbsd_sigframe);
 200
 201   set_gdbarch_iterate_over_regset_sections
 202     (gdbarch, riscv_fbsd_iterate_over_regset_sections);
 203
 204   set_gdbarch_fetch_tls_load_module_address (gdbarch,
 205                                              svr4_fetch_objfile_link_map);
 206   set_gdbarch_get_thread_local_address (gdbarch,
 207                                         riscv_fbsd_get_thread_local_address);
 208 }
 209
 210 void _initialize_riscv_fbsd_tdep ();
 211 void
 212 _initialize_riscv_fbsd_tdep ()
 213 {
 214   gdbarch_register_osabi (bfd_arch_riscv, 0, GDB_OSABI_FREEBSD,
 215                           riscv_fbsd_init_abi);
 216 }