gdb/testsuite/gdb.arch/vsx-regs.exp

   1 # Copyright (C) 2008-2024 Free Software Foundation, Inc.
   2 #
   3 # This program is free software; you can redistribute it and/or modify
   4 # it under the terms of the GNU General Public License as published by
   5 # the Free Software Foundation; either version 3 of the License, or
   6 # (at your option) any later version.
   7 #
   8 # This program is distributed in the hope that it will be useful,
   9 # but WITHOUT ANY WARRANTY; without even the implied warranty of
  10 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11 # GNU General Public License for more details.
  12 #
  13 # You should have received a copy of the GNU General Public License
  14 # along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15 #
  16
  17 #
  18 # Test the use of VSX registers, for Powerpc.
  19 #
  20
  21
  22 require {istarget "powerpc*"} allow_vsx_tests
  23
  24 standard_testfile
  25
  26 set compile_flags {debug nowarnings quiet}
  27 if [test_compiler_info gcc*] {
  28     set compile_flags "$compile_flags additional_flags=-maltivec additional_flags=-mabi=altivec"
  29 } elseif [test_compiler_info xlc*] {
  30     set compile_flags "$compile_flags additional_flags=-qaltivec"
  31 } else {
  32     warning "unknown compiler"
  33     return -1
  34 }
  35
  36 if  { [gdb_compile ${srcdir}/${subdir}/${srcfile} ${binfile} executable $compile_flags] != "" } {
  37      untested "failed to compile"
  38      return -1
  39 }
  40
  41 gdb_start
  42 gdb_reinitialize_dir $srcdir/$subdir
  43 gdb_load ${binfile}
  44
  45 # Run to `main' where we begin our tests.
  46
  47 if {![runto_main]} {
  48     return 0
  49 }
  50
  51 set endianness [get_endianness]
  52
  53 # Data sets used throughout the test
  54
  55 if {$endianness == "big"} {
  56     set vector_register1 ".float128 = 0x3ff4cccccccccccd0000000000000000, uint128 = 0x3ff4cccccccccccd0000000000000000, v2_double = .0x3ff4cccccccccccd, 0x0., v4_float = .0x3ff4cccc, 0xcccccccd, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccd, 0x0, 0x0., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccd, 0x0, 0x0, 0x0, 0x0., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0.."
  57
  58     set vector_register1_vr ".uint128 = 0x3ff4cccccccccccd0000000100000001, v4_float = .0x3ff4cccc, 0xcccccccd, 0x1, 0x1., v4_int32 = .0x3ff4cccc, 0xcccccccd, 0x1, 0x1., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccd, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcd, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
  59
  60     set vector_register2 ".float128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef., v4_float = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.."
  61
  62     set vector_register2_vr ".uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.."
  63
  64     set vector_register3 ".float128 = 0x1000000010000000100000001, uint128 = 0x1000000010000000100000001, v2_double = .0x100000001, 0x100000001., v4_float = .0x1, 0x1, 0x1, 0x1., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
  65
  66     set vector_register3_vr ".uint128 = 0x1000000010000000100000001, v4_float = .0x1, 0x1, 0x1, 0x1., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
  67 } else {
  68     set vector_register1 ".float128 = 0x3ff4cccccccccccd0000000000000000, uint128 = 0x3ff4cccccccccccd0000000000000000, v2_double = .0x0, 0x3ff4cccccccccccd., v4_float = .0x0, 0x0, 0xcccccccd, 0x3ff4cccc., v4_int32 = .0x0, 0x0, 0xcccccccd, 0x3ff4cccc., v8_int16 = .0x0, 0x0, 0x0, 0x0, 0xcccd, 0xcccc, 0xcccc, 0x3ff4., v16_int8 = .0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xcd, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xf4, 0x3f.."
  69
  70     set vector_register1_vr ".uint128 = 0x3ff4cccccccccccd0000000100000001, v4_float = .0x1, 0x1, 0xcccccccd, 0x3ff4cccc., v4_int32 = .0x1, 0x1, 0xcccccccd, 0x3ff4cccc., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0xcccd, 0xcccc, 0xcccc, 0x3ff4., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0xcd, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xf4, 0x3f.."
  71
  72     set vector_register2 ".float128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef., v4_float = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead., v16_int8 = .0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde.."
  73
  74     set vector_register2_vr ".uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead., v16_int8 = .0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde.."
  75
  76     set vector_register3 ".float128 = 0x1000000010000000100000001, uint128 = 0x1000000010000000100000001, v2_double = .0x100000001, 0x100000001., v4_float = .0x1, 0x1, 0x1, 0x1., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0.."
  77
  78     set vector_register3_vr ".uint128 = 0x1000000010000000100000001, v4_float = .0x1, 0x1, 0x1, 0x1., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0.."
  79 }
  80
  81 set float_register ".raw 0xdeadbeefdeadbeef."
  82
  83 # Note that the F0-F31 registers are shared with the doubleword 0 portion of
  84 # the VS0-VS31 registers, the doubleword 1 portions of VS* remain unchanged
  85 # after updates to F*.
  86 # Since dl_main uses some VS* registers, and per inspection their values are
  87 # no longer zero when our test reaches main(), we need to explicitly
  88 # initialize the VS* registers before we run our tests against the values
  89 # currently in those registers.
  90
  91 # 0: Initialize the (doubleword 0 and 1) portion of the VS0-VS31 registers.
  92 for {set i 0} {$i < 32} {incr i 1} {
  93     gdb_test_no_output "set \$vs$i.v2_double\[0\] = 0"
  94     gdb_test_no_output "set \$vs$i.v2_double\[1\] = 0"
  95 }
  96
  97 # 1: Set F0~F31 registers and check if it reflects on VS0~VS31.
  98 for {set i 0} {$i < 32} {incr i 1} {
  99     gdb_test_no_output "set \$f$i = 1\.3"
 100 }
 101
 102 for {set i 0} {$i < 32} {incr i 1} {
 103     gdb_test "info reg vs$i" "vs$i.*$vector_register1" "info reg vs$i (doubleword 0)"
 104 }
 105
 106 # 2: Set VS0~VS31 registers and check if it reflects on F0~F31.
 107 for {set i 0} {$i < 32} {incr i 1} {
 108         for {set j 0} {$j < 4} {incr j 1} {
 109            gdb_test_no_output "set \$vs$i.v4_int32\[$j\] = 0xdeadbeef"
 110         }
 111 }
 112
 113 for {set i 0} {$i < 32} {incr i 1} {
 114     gdb_test "info reg f$i" "f$i.*$float_register" "info reg f$i"
 115 }
 116
 117 for {set i 0} {$i < 32} {incr i 1} {
 118     gdb_test "info reg vs$i" "vs$i.*$vector_register2" "info reg vs$i (doubleword 1)"
 119 }
 120
 121 # Now run the VR0~VR31/VS32~VS63 tests
 122
 123 # 1: Set VR0~VR31 registers and check if it reflects on VS32~VS63.
 124 for {set i 0} {$i < 32} {incr i 1} {
 125         for {set j 0} {$j < 4} {incr j 1} {
 126            gdb_test_no_output "set \$vr$i.v4_int32\[$j\] = 1"
 127         }
 128 }
 129
 130 for {set i 32} {$i < 64} {incr i 1} {
 131     gdb_test "info reg vs$i" "vs$i.*$vector_register3" "info reg vs$i"
 132 }
 133 # 2: Set VS32~VS63 registers and check if it reflects on VR0~VR31.
 134 for {set i 32} {$i < 64} {incr i 1} {
 135         for {set j 0} {$j < 4} {incr j 1} {
 136            gdb_test_no_output "set \$vs$i.v4_int32\[$j\] = 1"
 137         }
 138 }
 139
 140 for {set i 0} {$i < 32} {incr i 1} {
 141     gdb_test "info reg vr$i" "vr$i.*$vector_register3_vr" "info reg vr$i"
 142     gdb_test "info reg v$i" "v$i.*$vector_register3_vr" "info reg v$i"
 143 }
 144
 145 # Create a core file.  We create the core file before the F32~F63/VR0~VR31 test
 146 # below because then we'll have more interesting register values to verify
 147 # later when loading the core file (i.e., different register values for different
 148 # vector register banks).
 149
 150 set corefile [standard_output_file vsx-core.test]
 151 set core_supported [gdb_gcore_cmd "$corefile" "Save a VSX-enabled corefile"]
 152
 153 # Now run the F32~F63/VR0~VR31 tests.
 154
 155 # 1: Set F32~F63 registers and check if it reflects on VR0~VR31.
 156 for {set i 32} {$i < 64} {incr i 1} {
 157     gdb_test_no_output "set \$f$i = 1\.3"
 158 }
 159
 160 for {set i 0} {$i < 32} {incr i 1} {
 161     gdb_test "info reg vr$i" "vr$i.*$vector_register1_vr" "info reg vr$i (doubleword 0)"
 162     gdb_test "info reg v$i" "v$i.*$vector_register1_vr" "info reg v$i (doubleword 0)"
 163 }
 164
 165 # 2: Set VR0~VR31 registers and check if it reflects on F32~F63.
 166 for {set i 0} {$i < 32} {incr i 1} {
 167         for {set j 0} {$j < 4} {incr j 1} {
 168            gdb_test_no_output "set \$vr$i.v4_int32\[$j\] = 0xdeadbeef"
 169         }
 170 }
 171
 172 for {set i 32} {$i < 64} {incr i 1} {
 173     gdb_test "info reg f$i" "f$i.*$float_register" "info reg f$i"
 174 }
 175
 176 for {set i 0} {$i < 32} {incr i 1} {
 177     gdb_test "info reg vr$i" "vr$i.*$vector_register2_vr" "info reg vr$i (doubleword 1)"
 178     gdb_test "info reg v$i" "v$i.*$vector_register2_vr" "info reg v$i (doubleword 1)"
 179 }
 180
 181 # Test reading the core file.
 182
 183 if {!$core_supported} {
 184   return -1
 185 }
 186
 187 clean_restart $binfile
 188
 189 set core_loaded [gdb_core_cmd "$corefile" "re-load generated corefile"]
 190 if { $core_loaded == -1 } {
 191     # No use proceeding from here.
 192     return
 193 }
 194
 195 for {set i 0} {$i < 32} {incr i 1} {
 196     gdb_test "info reg vs$i" "vs$i.*$vector_register2" "restore vs$i from core file"
 197 }
 198
 199 for {set i 32} {$i < 64} {incr i 1} {
 200     gdb_test "info reg vs$i" "vs$i.*$vector_register3" "restore vs$i from core file"
 201 }