gdb/v850-tdep.c

   1 /* Target-dependent code for the NEC V850 for GDB, the GNU debugger.
   2
   3    Copyright (C) 1996-2024 Free Software Foundation, Inc.
   4
   5    This file is part of GDB.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 #include "extract-store-integer.h"
  21 #include "frame.h"
  22 #include "frame-base.h"
  23 #include "trad-frame.h"
  24 #include "frame-unwind.h"
  25 #include "dwarf2/frame.h"
  26 #include "gdbtypes.h"
  27 #include "inferior.h"
  28 #include "gdbcore.h"
  29 #include "arch-utils.h"
  30 #include "regcache.h"
  31 #include "dis-asm.h"
  32 #include "osabi.h"
  33 #include "elf-bfd.h"
  34 #include "elf/v850.h"
  35 #include "gdbarch.h"
  36
  37 enum
  38   {
  39     /* General purpose registers.  */
  40     E_R0_REGNUM,
  41     E_R1_REGNUM,
  42     E_R2_REGNUM,
  43     E_R3_REGNUM, E_SP_REGNUM = E_R3_REGNUM,
  44     E_R4_REGNUM,
  45     E_R5_REGNUM,
  46     E_R6_REGNUM, E_ARG0_REGNUM = E_R6_REGNUM,
  47     E_R7_REGNUM,
  48     E_R8_REGNUM,
  49     E_R9_REGNUM, E_ARGLAST_REGNUM = E_R9_REGNUM,
  50     E_R10_REGNUM, E_V0_REGNUM = E_R10_REGNUM,
  51     E_R11_REGNUM, E_V1_REGNUM = E_R11_REGNUM,
  52     E_R12_REGNUM,
  53     E_R13_REGNUM,
  54     E_R14_REGNUM,
  55     E_R15_REGNUM,
  56     E_R16_REGNUM,
  57     E_R17_REGNUM,
  58     E_R18_REGNUM,
  59     E_R19_REGNUM,
  60     E_R20_REGNUM,
  61     E_R21_REGNUM,
  62     E_R22_REGNUM,
  63     E_R23_REGNUM,
  64     E_R24_REGNUM,
  65     E_R25_REGNUM,
  66     E_R26_REGNUM,
  67     E_R27_REGNUM,
  68     E_R28_REGNUM,
  69     E_R29_REGNUM, E_FP_REGNUM = E_R29_REGNUM,
  70     E_R30_REGNUM, E_EP_REGNUM = E_R30_REGNUM,
  71     E_R31_REGNUM, E_LP_REGNUM = E_R31_REGNUM,
  72
  73     /* System registers - main banks.  */
  74     E_R32_REGNUM, E_SR0_REGNUM = E_R32_REGNUM,
  75     E_R33_REGNUM,
  76     E_R34_REGNUM,
  77     E_R35_REGNUM,
  78     E_R36_REGNUM,
  79     E_R37_REGNUM, E_PS_REGNUM = E_R37_REGNUM,
  80     E_R38_REGNUM,
  81     E_R39_REGNUM,
  82     E_R40_REGNUM,
  83     E_R41_REGNUM,
  84     E_R42_REGNUM,
  85     E_R43_REGNUM,
  86     E_R44_REGNUM,
  87     E_R45_REGNUM,
  88     E_R46_REGNUM,
  89     E_R47_REGNUM,
  90     E_R48_REGNUM,
  91     E_R49_REGNUM,
  92     E_R50_REGNUM,
  93     E_R51_REGNUM,
  94     E_R52_REGNUM, E_CTBP_REGNUM = E_R52_REGNUM,
  95     E_R53_REGNUM,
  96     E_R54_REGNUM,
  97     E_R55_REGNUM,
  98     E_R56_REGNUM,
  99     E_R57_REGNUM,
 100     E_R58_REGNUM,
 101     E_R59_REGNUM,
 102     E_R60_REGNUM,
 103     E_R61_REGNUM,
 104     E_R62_REGNUM,
 105     E_R63_REGNUM,
 106
 107     /* PC.  */
 108     E_R64_REGNUM, E_PC_REGNUM = E_R64_REGNUM,
 109     E_R65_REGNUM,
 110     E_NUM_OF_V850_REGS,
 111     E_NUM_OF_V850E_REGS = E_NUM_OF_V850_REGS,
 112
 113     /* System registers - MPV (PROT00) bank.  */
 114     E_R66_REGNUM = E_NUM_OF_V850_REGS,
 115     E_R67_REGNUM,
 116     E_R68_REGNUM,
 117     E_R69_REGNUM,
 118     E_R70_REGNUM,
 119     E_R71_REGNUM,
 120     E_R72_REGNUM,
 121     E_R73_REGNUM,
 122     E_R74_REGNUM,
 123     E_R75_REGNUM,
 124     E_R76_REGNUM,
 125     E_R77_REGNUM,
 126     E_R78_REGNUM,
 127     E_R79_REGNUM,
 128     E_R80_REGNUM,
 129     E_R81_REGNUM,
 130     E_R82_REGNUM,
 131     E_R83_REGNUM,
 132     E_R84_REGNUM,
 133     E_R85_REGNUM,
 134     E_R86_REGNUM,
 135     E_R87_REGNUM,
 136     E_R88_REGNUM,
 137     E_R89_REGNUM,
 138     E_R90_REGNUM,
 139     E_R91_REGNUM,
 140     E_R92_REGNUM,
 141     E_R93_REGNUM,
 142
 143     /* System registers - MPU (PROT01) bank.  */
 144     E_R94_REGNUM,
 145     E_R95_REGNUM,
 146     E_R96_REGNUM,
 147     E_R97_REGNUM,
 148     E_R98_REGNUM,
 149     E_R99_REGNUM,
 150     E_R100_REGNUM,
 151     E_R101_REGNUM,
 152     E_R102_REGNUM,
 153     E_R103_REGNUM,
 154     E_R104_REGNUM,
 155     E_R105_REGNUM,
 156     E_R106_REGNUM,
 157     E_R107_REGNUM,
 158     E_R108_REGNUM,
 159     E_R109_REGNUM,
 160     E_R110_REGNUM,
 161     E_R111_REGNUM,
 162     E_R112_REGNUM,
 163     E_R113_REGNUM,
 164     E_R114_REGNUM,
 165     E_R115_REGNUM,
 166     E_R116_REGNUM,
 167     E_R117_REGNUM,
 168     E_R118_REGNUM,
 169     E_R119_REGNUM,
 170     E_R120_REGNUM,
 171     E_R121_REGNUM,
 172
 173     /* FPU system registers.  */
 174     E_R122_REGNUM,
 175     E_R123_REGNUM,
 176     E_R124_REGNUM,
 177     E_R125_REGNUM,
 178     E_R126_REGNUM,
 179     E_R127_REGNUM,
 180     E_R128_REGNUM, E_FPSR_REGNUM = E_R128_REGNUM,
 181     E_R129_REGNUM, E_FPEPC_REGNUM = E_R129_REGNUM,
 182     E_R130_REGNUM, E_FPST_REGNUM = E_R130_REGNUM,
 183     E_R131_REGNUM, E_FPCC_REGNUM = E_R131_REGNUM,
 184     E_R132_REGNUM, E_FPCFG_REGNUM = E_R132_REGNUM,
 185     E_R133_REGNUM,
 186     E_R134_REGNUM,
 187     E_R135_REGNUM,
 188     E_R136_REGNUM,
 189     E_R137_REGNUM,
 190     E_R138_REGNUM,
 191     E_R139_REGNUM,
 192     E_R140_REGNUM,
 193     E_R141_REGNUM,
 194     E_R142_REGNUM,
 195     E_R143_REGNUM,
 196     E_R144_REGNUM,
 197     E_R145_REGNUM,
 198     E_R146_REGNUM,
 199     E_R147_REGNUM,
 200     E_R148_REGNUM,
 201     E_R149_REGNUM,
 202     E_NUM_OF_V850E2_REGS,
 203
 204     /* v850e3v5 system registers, selID 1 through 7.  */
 205     E_SELID_1_R0_REGNUM = E_NUM_OF_V850E2_REGS,
 206     E_SELID_1_R31_REGNUM = E_SELID_1_R0_REGNUM + 31,
 207
 208     E_SELID_2_R0_REGNUM,
 209     E_SELID_2_R31_REGNUM = E_SELID_2_R0_REGNUM + 31,
 210
 211     E_SELID_3_R0_REGNUM,
 212     E_SELID_3_R31_REGNUM = E_SELID_3_R0_REGNUM + 31,
 213
 214     E_SELID_4_R0_REGNUM,
 215     E_SELID_4_R31_REGNUM = E_SELID_4_R0_REGNUM + 31,
 216
 217     E_SELID_5_R0_REGNUM,
 218     E_SELID_5_R31_REGNUM = E_SELID_5_R0_REGNUM + 31,
 219
 220     E_SELID_6_R0_REGNUM,
 221     E_SELID_6_R31_REGNUM = E_SELID_6_R0_REGNUM + 31,
 222
 223     E_SELID_7_R0_REGNUM,
 224     E_SELID_7_R31_REGNUM = E_SELID_7_R0_REGNUM + 31,
 225
 226     /* v850e3v5 vector registers.  */
 227     E_VR0_REGNUM,
 228     E_VR31_REGNUM = E_VR0_REGNUM + 31,
 229
 230     E_NUM_OF_V850E3V5_REGS,
 231
 232     /* Total number of possible registers.  */
 233     E_NUM_REGS = E_NUM_OF_V850E3V5_REGS
 234   };
 235
 236 enum
 237 {
 238   v850_reg_size = 4
 239 };
 240
 241 /* Size of return datatype which fits into all return registers.  */
 242 enum
 243 {
 244   E_MAX_RETTYPE_SIZE_IN_REGS = 2 * v850_reg_size
 245 };
 246
 247 /* When v850 support was added to GCC in the late nineties, the intention
 248    was to follow the Green Hills ABI for v850.  In fact, the authors of
 249    that support at the time thought that they were doing so.  As far as
 250    I can tell, the calling conventions are correct, but the return value
 251    conventions were not quite right.  Over time, the return value code
 252    in this file was modified to mostly reflect what GCC was actually
 253    doing instead of to actually follow the Green Hills ABI as it did
 254    when the code was first written.
 255
 256    Renesas defined the RH850 ABI which they use in their compiler.  It
 257    is similar to the original Green Hills ABI with some minor
 258    differences.  */
 259
 260 enum v850_abi
 261 {
 262   V850_ABI_GCC,
 263   V850_ABI_RH850
 264 };
 265
 266 /* Architecture specific data.  */
 267
 268 struct v850_gdbarch_tdep : gdbarch_tdep_base
 269 {
 270   /* Fields from the ELF header.  */
 271   int e_flags = 0;
 272   int e_machine = 0;
 273
 274   /* Which ABI are we using?  */
 275   enum v850_abi abi {};
 276   int eight_byte_align = 0;
 277 };
 278
 279 struct v850_frame_cache
 280 {
 281   /* Base address.  */
 282   CORE_ADDR base;
 283   LONGEST sp_offset;
 284   CORE_ADDR pc;
 285
 286   /* Flag showing that a frame has been created in the prologue code.  */
 287   int uses_fp;
 288
 289   /* Saved registers.  */
 290   trad_frame_saved_reg *saved_regs;
 291 };
 292
 293 /* Info gleaned from scanning a function's prologue.  */
 294 struct pifsr            /* Info about one saved register.  */
 295 {
 296   int offset;           /* Offset from sp or fp.  */
 297   int cur_frameoffset;  /* Current frameoffset.  */
 298   int reg;              /* Saved register number.  */
 299 };
 300
 301 static const char *
 302 v850_register_name (struct gdbarch *gdbarch, int regnum)
 303 {
 304   static const char *v850_reg_names[] =
 305   { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 306     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 307     "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
 308     "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
 309     "eipc", "eipsw", "fepc", "fepsw", "ecr", "psw", "sr6", "sr7",
 310     "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15",
 311     "sr16", "sr17", "sr18", "sr19", "sr20", "sr21", "sr22", "sr23",
 312     "sr24", "sr25", "sr26", "sr27", "sr28", "sr29", "sr30", "sr31",
 313     "pc", "fp"
 314   };
 315   static_assert (E_NUM_OF_V850_REGS == ARRAY_SIZE (v850_reg_names));
 316   return v850_reg_names[regnum];
 317 }
 318
 319 static const char *
 320 v850e_register_name (struct gdbarch *gdbarch, int regnum)
 321 {
 322   static const char *v850e_reg_names[] =
 323   {
 324     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 325     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 326     "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
 327     "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
 328     "eipc", "eipsw", "fepc", "fepsw", "ecr", "psw", "sr6", "sr7",
 329     "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15",
 330     "ctpc", "ctpsw", "dbpc", "dbpsw", "ctbp", "sr21", "sr22", "sr23",
 331     "sr24", "sr25", "sr26", "sr27", "sr28", "sr29", "sr30", "sr31",
 332     "pc", "fp"
 333   };
 334   static_assert (E_NUM_OF_V850E_REGS == ARRAY_SIZE (v850e_reg_names));
 335   return v850e_reg_names[regnum];
 336 }
 337
 338 static const char *
 339 v850e2_register_name (struct gdbarch *gdbarch, int regnum)
 340 {
 341   static const char *v850e2_reg_names[] =
 342   {
 343     /* General purpose registers.  */
 344     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 345     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 346     "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
 347     "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
 348
 349     /* System registers - main banks.  */
 350     "eipc", "eipsw", "fepc", "fepsw", "ecr", "psw", "pid", "cfg",
 351     "", "", "", "sccfg", "scbp", "eiic", "feic", "dbic",
 352     "ctpc", "ctpsw", "dbpc", "dbpsw", "ctbp", "dir", "", "",
 353     "", "", "", "", "eiwr", "fewr", "dbwr", "bsel",
 354
 355
 356     /* PC.  */
 357     "pc", "",
 358
 359     /* System registers - MPV (PROT00) bank.  */
 360     "vsecr", "vstid", "vsadr", "", "vmecr", "vmtid", "vmadr", "",
 361     "vpecr", "vptid", "vpadr", "", "", "", "", "",
 362     "", "", "", "", "", "", "", "",
 363     "mca", "mcs", "mcc", "mcr",
 364
 365     /* System registers - MPU (PROT01) bank.  */
 366     "mpm", "mpc", "tid", "", "", "", "ipa0l", "ipa0u",
 367     "ipa1l", "ipa1u", "ipa2l", "ipa2u", "ipa3l", "ipa3u", "ipa4l", "ipa4u",
 368     "dpa0l", "dpa0u", "dpa1l", "dpa1u", "dpa2l", "dpa2u", "dpa3l", "dpa3u",
 369     "dpa4l", "dpa4u", "dpa5l", "dpa5u",
 370
 371     /* FPU system registers.  */
 372     "", "", "", "", "", "", "fpsr", "fpepc",
 373     "fpst", "fpcc", "fpcfg", "fpec", "", "", "", "",
 374     "", "", "", "", "", "", "", "",
 375     "", "", "", "fpspc"
 376   };
 377   if (regnum >= E_NUM_OF_V850E2_REGS)
 378     return "";
 379   return v850e2_reg_names[regnum];
 380 }
 381
 382 /* Implement the "register_name" gdbarch method for v850e3v5.  */
 383
 384 static const char *
 385 v850e3v5_register_name (struct gdbarch *gdbarch, int regnum)
 386 {
 387   static const char *v850e3v5_reg_names[] =
 388   {
 389     /* General purpose registers.  */
 390     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 391     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 392     "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
 393     "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
 394
 395     /* selID 0, not including FPU registers.  The FPU registers are
 396        listed later on.  */
 397     "eipc", "eipsw", "fepc", "fepsw",
 398     "", "psw", "" /* fpsr */, "" /* fpepc */,
 399     "" /* fpst */, "" /* fpcc */, "" /* fpcfg */, "" /* fpec */,
 400     "sesr", "eiic", "feic", "",
 401     "ctpc", "ctpsw", "", "", "ctbp", "", "", "",
 402     "", "", "", "", "eiwr", "fewr", "", "bsel",
 403
 404
 405     /* PC.  */
 406     "pc", "",
 407
 408     /* v850e2 MPV bank.  */
 409     "", "", "", "", "", "", "", "",
 410     "", "", "", "", "", "", "", "",
 411     "", "", "", "", "", "", "", "",
 412     "", "", "", "",
 413
 414     /* Skip v850e2 MPU bank.  It's tempting to reuse these, but we need
 415        32 entries for this bank.  */
 416     "", "", "", "", "", "", "", "",
 417     "", "", "", "", "", "", "", "",
 418     "", "", "", "", "", "", "", "",
 419     "", "", "", "",
 420
 421     /* FPU system registers.  These are actually in selID 0, but
 422        are placed here to preserve register numbering compatibility
 423        with previous architectures.  */
 424     "", "", "", "", "", "", "fpsr", "fpepc",
 425     "fpst", "fpcc", "fpcfg", "fpec", "", "", "", "",
 426     "", "", "", "", "", "", "", "",
 427     "", "", "", "",
 428
 429     /* selID 1.  */
 430     "mcfg0", "mcfg1", "rbase", "ebase", "intbp", "mctl", "pid", "fpipr",
 431     "", "", "tcsel", "sccfg", "scbp", "hvccfg", "hvcbp", "vsel",
 432     "vmprt0", "vmprt1", "vmprt2", "", "", "", "", "vmscctl",
 433     "vmsctbl0", "vmsctbl1", "vmsctbl2", "vmsctbl3", "", "", "", "",
 434
 435     /* selID 2.  */
 436     "htcfg0", "", "", "", "", "htctl", "mea", "asid",
 437     "mei", "ispr", "pmr", "icsr", "intcfg", "", "", "",
 438     "tlbsch", "", "", "", "", "", "", "htscctl",
 439     "htsctbl0", "htsctbl1", "htsctbl2", "htsctbl3",
 440     "htsctbl4", "htsctbl5", "htsctbl6", "htsctbl7",
 441
 442     /* selID 3.  */
 443     "", "", "", "", "", "", "", "",
 444     "", "", "", "", "", "", "", "",
 445     "", "", "", "", "", "", "", "",
 446     "", "", "", "", "", "", "", "",
 447
 448     /* selID 4.  */
 449     "tlbidx", "", "", "", "telo0", "telo1", "tehi0", "tehi1",
 450     "", "", "tlbcfg", "", "bwerrl", "bwerrh", "brerrl", "brerrh",
 451     "ictagl", "ictagh", "icdatl", "icdath",
 452     "dctagl", "dctagh", "dcdatl", "dcdath",
 453     "icctrl", "dcctrl", "iccfg", "dccfg", "icerr", "dcerr", "", "",
 454
 455     /* selID 5.  */
 456     "mpm", "mprc", "", "", "mpbrgn", "mptrgn", "", "",
 457     "mca", "mcs", "mcc", "mcr", "", "", "", "",
 458     "", "", "", "", "mpprt0", "mpprt1", "mpprt2", "",
 459     "", "", "", "", "", "", "", "",
 460
 461     /* selID 6.  */
 462     "mpla0", "mpua0", "mpat0", "", "mpla1", "mpua1", "mpat1", "",
 463     "mpla2", "mpua2", "mpat2", "", "mpla3", "mpua3", "mpat3", "",
 464     "mpla4", "mpua4", "mpat4", "", "mpla5", "mpua5", "mpat5", "",
 465     "mpla6", "mpua6", "mpat6", "", "mpla7", "mpua7", "mpat7", "",
 466
 467     /* selID 7.  */
 468     "mpla8", "mpua8", "mpat8", "", "mpla9", "mpua9", "mpat9", "",
 469     "mpla10", "mpua10", "mpat10", "", "mpla11", "mpua11", "mpat11", "",
 470     "mpla12", "mpua12", "mpat12", "", "mpla13", "mpua13", "mpat13", "",
 471     "mpla14", "mpua14", "mpat14", "", "mpla15", "mpua15", "mpat15", "",
 472
 473     /* Vector Registers */
 474     "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
 475     "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
 476     "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
 477     "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31",
 478   };
 479
 480   static_assert (E_NUM_OF_V850E3V5_REGS
 481                      == ARRAY_SIZE (v850e3v5_reg_names));
 482   return v850e3v5_reg_names[regnum];
 483 }
 484
 485 /* Returns the default type for register N.  */
 486
 487 static struct type *
 488 v850_register_type (struct gdbarch *gdbarch, int regnum)
 489 {
 490   if (regnum == E_PC_REGNUM)
 491     return builtin_type (gdbarch)->builtin_func_ptr;
 492   else if (E_VR0_REGNUM <= regnum && regnum <= E_VR31_REGNUM)
 493     return builtin_type (gdbarch)->builtin_uint64;
 494   return builtin_type (gdbarch)->builtin_int32;
 495 }
 496
 497 static int
 498 v850_type_is_scalar (struct type *t)
 499 {
 500   return (t->code () != TYPE_CODE_STRUCT
 501           && t->code () != TYPE_CODE_UNION
 502           && t->code () != TYPE_CODE_ARRAY);
 503 }
 504
 505 /* Should call_function allocate stack space for a struct return?  */
 506
 507 static int
 508 v850_use_struct_convention (struct gdbarch *gdbarch, struct type *type)
 509 {
 510   int i;
 511   struct type *fld_type, *tgt_type;
 512   v850_gdbarch_tdep *tdep = gdbarch_tdep<v850_gdbarch_tdep> (gdbarch);
 513
 514   if (tdep->abi == V850_ABI_RH850)
 515     {
 516       if (v850_type_is_scalar (type) && type->length () <= 8)
 517         return 0;
 518
 519       /* Structs are never returned in registers for this ABI.  */
 520       return 1;
 521     }
 522   /* 1. The value is greater than 8 bytes -> returned by copying.  */
 523   if (type->length () > 8)
 524     return 1;
 525
 526   /* 2. The value is a single basic type -> returned in register.  */
 527   if (v850_type_is_scalar (type))
 528     return 0;
 529
 530   /* The value is a structure or union with a single element and that
 531      element is either a single basic type or an array of a single basic
 532      type whose size is greater than or equal to 4 -> returned in register.  */
 533   if ((type->code () == TYPE_CODE_STRUCT
 534        || type->code () == TYPE_CODE_UNION)
 535        && type->num_fields () == 1)
 536     {
 537       fld_type = type->field (0).type ();
 538       if (v850_type_is_scalar (fld_type) && fld_type->length () >= 4)
 539         return 0;
 540
 541       if (fld_type->code () == TYPE_CODE_ARRAY)
 542         {
 543           tgt_type = fld_type->target_type ();
 544           if (v850_type_is_scalar (tgt_type) && tgt_type->length () >= 4)
 545             return 0;
 546         }
 547     }
 548
 549   /* The value is a structure whose first element is an integer or a float,
 550      and which contains no arrays of more than two elements -> returned in
 551      register.  */
 552   if (type->code () == TYPE_CODE_STRUCT
 553       && v850_type_is_scalar (type->field (0).type ())
 554       && type->field (0).type ()->length () == 4)
 555     {
 556       for (i = 1; i < type->num_fields (); ++i)
 557         {
 558           fld_type = type->field (0).type ();
 559           if (fld_type->code () == TYPE_CODE_ARRAY)
 560             {
 561               tgt_type = fld_type->target_type ();
 562               if (tgt_type->length () > 0
 563                   && fld_type->length () / tgt_type->length () > 2)
 564                 return 1;
 565             }
 566         }
 567       return 0;
 568     }
 569
 570   /* The value is a union which contains at least one field which
 571      would be returned in registers according to these rules ->
 572      returned in register.  */
 573   if (type->code () == TYPE_CODE_UNION)
 574     {
 575       for (i = 0; i < type->num_fields (); ++i)
 576         {
 577           fld_type = type->field (0).type ();
 578           if (!v850_use_struct_convention (gdbarch, fld_type))
 579             return 0;
 580         }
 581     }
 582
 583   return 1;
 584 }
 585
 586 /* Structure for mapping bits in register lists to register numbers.  */
 587
 588 struct reg_list
 589 {
 590   long mask;
 591   int regno;
 592 };
 593
 594 /* Helper function for v850_scan_prologue to handle prepare instruction.  */
 595
 596 static void
 597 v850_handle_prepare (int insn, int insn2, CORE_ADDR * current_pc_ptr,
 598                      struct v850_frame_cache *pi, struct pifsr **pifsr_ptr)
 599 {
 600   CORE_ADDR current_pc = *current_pc_ptr;
 601   struct pifsr *pifsr = *pifsr_ptr;
 602   long next = insn2 & 0xffff;
 603   long list12 = ((insn & 1) << 16) + (next & 0xffe0);
 604   long offset = (insn & 0x3e) << 1;
 605   static struct reg_list reg_table[] =
 606   {
 607     {0x00800, 20},              /* r20 */
 608     {0x00400, 21},              /* r21 */
 609     {0x00200, 22},              /* r22 */
 610     {0x00100, 23},              /* r23 */
 611     {0x08000, 24},              /* r24 */
 612     {0x04000, 25},              /* r25 */
 613     {0x02000, 26},              /* r26 */
 614     {0x01000, 27},              /* r27 */
 615     {0x00080, 28},              /* r28 */
 616     {0x00040, 29},              /* r29 */
 617     {0x10000, 30},              /* ep */
 618     {0x00020, 31},              /* lp */
 619     {0, 0}                      /* end of table */
 620   };
 621   int i;
 622
 623   if ((next & 0x1f) == 0x0b)            /* skip imm16 argument */
 624     current_pc += 2;
 625   else if ((next & 0x1f) == 0x13)       /* skip imm16 argument */
 626     current_pc += 2;
 627   else if ((next & 0x1f) == 0x1b)       /* skip imm32 argument */
 628     current_pc += 4;
 629
 630   /* Calculate the total size of the saved registers, and add it to the
 631      immediate value used to adjust SP.  */
 632   for (i = 0; reg_table[i].mask != 0; i++)
 633     if (list12 & reg_table[i].mask)
 634       offset += v850_reg_size;
 635   pi->sp_offset -= offset;
 636
 637   /* Calculate the offsets of the registers relative to the value the SP
 638      will have after the registers have been pushed and the imm5 value has
 639      been subtracted from it.  */
 640   if (pifsr)
 641     {
 642       for (i = 0; reg_table[i].mask != 0; i++)
 643         {
 644           if (list12 & reg_table[i].mask)
 645             {
 646               int reg = reg_table[i].regno;
 647               offset -= v850_reg_size;
 648               pifsr->reg = reg;
 649               pifsr->offset = offset;
 650               pifsr->cur_frameoffset = pi->sp_offset;
 651               pifsr++;
 652             }
 653         }
 654     }
 655
 656   /* Set result parameters.  */
 657   *current_pc_ptr = current_pc;
 658   *pifsr_ptr = pifsr;
 659 }
 660
 661
 662 /* Helper function for v850_scan_prologue to handle pushm/pushl instructions.
 663    The SR bit of the register list is not supported.  gcc does not generate
 664    this bit.  */
 665
 666 static void
 667 v850_handle_pushm (int insn, int insn2, struct v850_frame_cache *pi,
 668                    struct pifsr **pifsr_ptr)
 669 {
 670   struct pifsr *pifsr = *pifsr_ptr;
 671   long list12 = ((insn & 0x0f) << 16) + (insn2 & 0xfff0);
 672   long offset = 0;
 673   static struct reg_list pushml_reg_table[] =
 674   {
 675     {0x80000, E_PS_REGNUM},     /* PSW */
 676     {0x40000, 1},               /* r1 */
 677     {0x20000, 2},               /* r2 */
 678     {0x10000, 3},               /* r3 */
 679     {0x00800, 4},               /* r4 */
 680     {0x00400, 5},               /* r5 */
 681     {0x00200, 6},               /* r6 */
 682     {0x00100, 7},               /* r7 */
 683     {0x08000, 8},               /* r8 */
 684     {0x04000, 9},               /* r9 */
 685     {0x02000, 10},              /* r10 */
 686     {0x01000, 11},              /* r11 */
 687     {0x00080, 12},              /* r12 */
 688     {0x00040, 13},              /* r13 */
 689     {0x00020, 14},              /* r14 */
 690     {0x00010, 15},              /* r15 */
 691     {0, 0}                      /* end of table */
 692   };
 693   static struct reg_list pushmh_reg_table[] =
 694   {
 695     {0x80000, 16},              /* r16 */
 696     {0x40000, 17},              /* r17 */
 697     {0x20000, 18},              /* r18 */
 698     {0x10000, 19},              /* r19 */
 699     {0x00800, 20},              /* r20 */
 700     {0x00400, 21},              /* r21 */
 701     {0x00200, 22},              /* r22 */
 702     {0x00100, 23},              /* r23 */
 703     {0x08000, 24},              /* r24 */
 704     {0x04000, 25},              /* r25 */
 705     {0x02000, 26},              /* r26 */
 706     {0x01000, 27},              /* r27 */
 707     {0x00080, 28},              /* r28 */
 708     {0x00040, 29},              /* r29 */
 709     {0x00010, 30},              /* r30 */
 710     {0x00020, 31},              /* r31 */
 711     {0, 0}                      /* end of table */
 712   };
 713   struct reg_list *reg_table;
 714   int i;
 715
 716   /* Is this a pushml or a pushmh?  */
 717   if ((insn2 & 7) == 1)
 718     reg_table = pushml_reg_table;
 719   else
 720     reg_table = pushmh_reg_table;
 721
 722   /* Calculate the total size of the saved registers, and add it to the
 723      immediate value used to adjust SP.  */
 724   for (i = 0; reg_table[i].mask != 0; i++)
 725     if (list12 & reg_table[i].mask)
 726       offset += v850_reg_size;
 727   pi->sp_offset -= offset;
 728
 729   /* Calculate the offsets of the registers relative to the value the SP
 730      will have after the registers have been pushed and the imm5 value is
 731      subtracted from it.  */
 732   if (pifsr)
 733     {
 734       for (i = 0; reg_table[i].mask != 0; i++)
 735         {
 736           if (list12 & reg_table[i].mask)
 737             {
 738               int reg = reg_table[i].regno;
 739               offset -= v850_reg_size;
 740               pifsr->reg = reg;
 741               pifsr->offset = offset;
 742               pifsr->cur_frameoffset = pi->sp_offset;
 743               pifsr++;
 744             }
 745         }
 746     }
 747
 748   /* Set result parameters.  */
 749   *pifsr_ptr = pifsr;
 750 }
 751
 752 /* Helper function to evaluate if register is one of the "save" registers.
 753    This allows to simplify conditionals in v850_analyze_prologue a lot.  */
 754
 755 static int
 756 v850_is_save_register (int reg)
 757 {
 758  /* The caller-save registers are R2, R20 - R29 and R31.  All other
 759     registers are either special purpose (PC, SP), argument registers,
 760     or just considered free for use in the caller.  */
 761  return reg == E_R2_REGNUM
 762         || (reg >= E_R20_REGNUM && reg <= E_R29_REGNUM)
 763         || reg == E_R31_REGNUM;
 764 }
 765
 766 /* Scan the prologue of the function that contains PC, and record what
 767    we find in PI.  Returns the pc after the prologue.  Note that the
 768    addresses saved in frame->saved_regs are just frame relative (negative
 769    offsets from the frame pointer).  This is because we don't know the
 770    actual value of the frame pointer yet.  In some circumstances, the
 771    frame pointer can't be determined till after we have scanned the
 772    prologue.  */
 773
 774 static CORE_ADDR
 775 v850_analyze_prologue (struct gdbarch *gdbarch,
 776                        CORE_ADDR func_addr, CORE_ADDR pc,
 777                        struct v850_frame_cache *pi, ULONGEST ctbp)
 778 {
 779   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
 780   CORE_ADDR prologue_end, current_pc;
 781   struct pifsr pifsrs[E_NUM_REGS + 1];
 782   struct pifsr *pifsr, *pifsr_tmp;
 783   int ep_used;
 784   int reg;
 785   CORE_ADDR save_pc, save_end;
 786   int regsave_func_p;
 787   int r12_tmp;
 788
 789   memset (&pifsrs, 0, sizeof pifsrs);
 790   pifsr = &pifsrs[0];
 791
 792   prologue_end = pc;
 793
 794   /* Now, search the prologue looking for instructions that setup fp, save
 795      rp, adjust sp and such.  We also record the frame offset of any saved
 796      registers.  */
 797
 798   pi->sp_offset = 0;
 799   pi->uses_fp = 0;
 800   ep_used = 0;
 801   regsave_func_p = 0;
 802   save_pc = 0;
 803   save_end = 0;
 804   r12_tmp = 0;
 805
 806   for (current_pc = func_addr; current_pc < prologue_end;)
 807     {
 808       int insn;
 809       int insn2 = -1; /* dummy value */
 810
 811       insn = read_memory_integer (current_pc, 2, byte_order);
 812       current_pc += 2;
 813       if ((insn & 0x0780) >= 0x0600)    /* Four byte instruction?  */
 814         {
 815           insn2 = read_memory_integer (current_pc, 2, byte_order);
 816           current_pc += 2;
 817         }
 818
 819       if ((insn & 0xffc0) == ((10 << 11) | 0x0780) && !regsave_func_p)
 820         {                       /* jarl <func>,10 */
 821           long low_disp = insn2 & ~(long) 1;
 822           long disp = (((((insn & 0x3f) << 16) + low_disp)
 823                         & ~(long) 1) ^ 0x00200000) - 0x00200000;
 824
 825           save_pc = current_pc;
 826           save_end = prologue_end;
 827           regsave_func_p = 1;
 828           current_pc += disp - 4;
 829           prologue_end = (current_pc
 830                           + (2 * 3)     /* moves to/from ep */
 831                           + 4           /* addi <const>,sp,sp */
 832                           + 2           /* jmp [r10] */
 833                           + (2 * 12)    /* sst.w to save r2, r20-r29, r31 */
 834                           + 20);        /* slop area */
 835         }
 836       else if ((insn & 0xffc0) == 0x0200 && !regsave_func_p)
 837         {                       /* callt <imm6> */
 838           long adr = ctbp + ((insn & 0x3f) << 1);
 839
 840           save_pc = current_pc;
 841           save_end = prologue_end;
 842           regsave_func_p = 1;
 843           current_pc = ctbp + (read_memory_unsigned_integer (adr, 2, byte_order)
 844                                & 0xffff);
 845           prologue_end = (current_pc
 846                           + (2 * 3)     /* prepare list2,imm5,sp/imm */
 847                           + 4           /* ctret */
 848                           + 20);        /* slop area */
 849           continue;
 850         }
 851       else if ((insn & 0xffc0) == 0x0780)       /* prepare list2,imm5 */
 852         {
 853           v850_handle_prepare (insn, insn2, &current_pc, pi, &pifsr);
 854           continue;
 855         }
 856       else if (insn == 0x07e0 && regsave_func_p && insn2 == 0x0144)
 857         {                       /* ctret after processing register save.  */
 858           current_pc = save_pc;
 859           prologue_end = save_end;
 860           regsave_func_p = 0;
 861           continue;
 862         }
 863       else if ((insn & 0xfff0) == 0x07e0 && (insn2 & 5) == 1)
 864         {                       /* pushml, pushmh */
 865           v850_handle_pushm (insn, insn2, pi, &pifsr);
 866           continue;
 867         }
 868       else if ((insn & 0xffe0) == 0x0060 && regsave_func_p)
 869         {                       /* jmp after processing register save.  */
 870           current_pc = save_pc;
 871           prologue_end = save_end;
 872           regsave_func_p = 0;
 873           continue;
 874         }
 875       else if ((insn & 0x07c0) == 0x0780        /* jarl or jr */
 876                || (insn & 0xffe0) == 0x0060     /* jmp */
 877                || (insn & 0x0780) == 0x0580)    /* branch */
 878         {
 879           break;                /* Ran into end of prologue.  */
 880         }
 881
 882       else if ((insn & 0xffe0) == ((E_SP_REGNUM << 11) | 0x0240))
 883         /* add <imm>,sp */
 884         pi->sp_offset += ((insn & 0x1f) ^ 0x10) - 0x10;
 885       else if (insn == ((E_SP_REGNUM << 11) | 0x0600 | E_SP_REGNUM))
 886         /* addi <imm>,sp,sp */
 887         pi->sp_offset += insn2;
 888       else if (insn == ((E_FP_REGNUM << 11) | 0x0000 | E_SP_REGNUM))
 889         /* mov sp,fp */
 890         pi->uses_fp = 1;
 891       else if (insn == ((E_R12_REGNUM << 11) | 0x0640 | E_R0_REGNUM))
 892         /* movhi hi(const),r0,r12 */
 893         r12_tmp = insn2 << 16;
 894       else if (insn == ((E_R12_REGNUM << 11) | 0x0620 | E_R12_REGNUM))
 895         /* movea lo(const),r12,r12 */
 896         r12_tmp += insn2;
 897       else if (insn == ((E_SP_REGNUM << 11) | 0x01c0 | E_R12_REGNUM) && r12_tmp)
 898         /* add r12,sp */
 899         pi->sp_offset += r12_tmp;
 900       else if (insn == ((E_EP_REGNUM << 11) | 0x0000 | E_SP_REGNUM))
 901         /* mov sp,ep */
 902         ep_used = 1;
 903       else if (insn == ((E_EP_REGNUM << 11) | 0x0000 | E_R1_REGNUM))
 904         /* mov r1,ep */
 905         ep_used = 0;
 906       else if (((insn & 0x07ff) == (0x0760 | E_SP_REGNUM)
 907                 || (pi->uses_fp
 908                     && (insn & 0x07ff) == (0x0760 | E_FP_REGNUM)))
 909                && pifsr
 910                && v850_is_save_register (reg = (insn >> 11) & 0x1f))
 911         {
 912           /* st.w <reg>,<offset>[sp] or st.w <reg>,<offset>[fp] */
 913           pifsr->reg = reg;
 914           pifsr->offset = insn2 & ~1;
 915           pifsr->cur_frameoffset = pi->sp_offset;
 916           pifsr++;
 917         }
 918       else if (ep_used
 919                && ((insn & 0x0781) == 0x0501)
 920                && pifsr
 921                && v850_is_save_register (reg = (insn >> 11) & 0x1f))
 922         {
 923           /* sst.w <reg>,<offset>[ep] */
 924           pifsr->reg = reg;
 925           pifsr->offset = (insn & 0x007e) << 1;
 926           pifsr->cur_frameoffset = pi->sp_offset;
 927           pifsr++;
 928         }
 929     }
 930
 931   /* Fix up any offsets to the final offset.  If a frame pointer was created,
 932      use it instead of the stack pointer.  */
 933   for (pifsr_tmp = pifsrs; pifsr_tmp != pifsr; pifsr_tmp++)
 934     {
 935       pifsr_tmp->offset -= pi->sp_offset - pifsr_tmp->cur_frameoffset;
 936       pi->saved_regs[pifsr_tmp->reg].set_addr (pifsr_tmp->offset);
 937     }
 938
 939   return current_pc;
 940 }
 941
 942 /* Return the address of the first code past the prologue of the function.  */
 943
 944 static CORE_ADDR
 945 v850_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
 946 {
 947   CORE_ADDR func_addr, func_end;
 948
 949   /* See what the symbol table says.  */
 950
 951   if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
 952     {
 953       struct symtab_and_line sal;
 954
 955       sal = find_pc_line (func_addr, 0);
 956       if (sal.line != 0 && sal.end < func_end)
 957         return sal.end;
 958
 959       /* Either there's no line info, or the line after the prologue is after
 960          the end of the function.  In this case, there probably isn't a
 961          prologue.  */
 962       return pc;
 963     }
 964
 965   /* We can't find the start of this function, so there's nothing we
 966      can do.  */
 967   return pc;
 968 }
 969
 970 /* Return 1 if the data structure has any 8-byte fields that'll require
 971    the entire data structure to be aligned.  Otherwise, return 0.  */
 972
 973 static int
 974 v850_eight_byte_align_p (struct type *type)
 975 {
 976   type = check_typedef (type);
 977
 978   if (v850_type_is_scalar (type))
 979     return (type->length () == 8);
 980   else
 981     {
 982       int i;
 983
 984       for (i = 0; i < type->num_fields (); i++)
 985         {
 986           if (v850_eight_byte_align_p (type->field (i).type ()))
 987             return 1;
 988         }
 989     }
 990   return 0;
 991 }
 992
 993 static CORE_ADDR
 994 v850_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
 995 {
 996   return sp & ~3;
 997 }
 998
 999 /* Setup arguments and LP for a call to the target.  First four args
1000    go in R6->R9, subsequent args go into sp + 16 -> sp + ...  Structs
1001    are passed by reference.  64 bit quantities (doubles and long longs)
1002    may be split between the regs and the stack.  When calling a function
1003    that returns a struct, a pointer to the struct is passed in as a secret
1004    first argument (always in R6).
1005
1006    Stack space for the args has NOT been allocated: that job is up to us.  */
1007
1008 static CORE_ADDR
1009 v850_push_dummy_call (struct gdbarch *gdbarch,
1010                       struct value *function,
1011                       struct regcache *regcache,
1012                       CORE_ADDR bp_addr,
1013                       int nargs,
1014                       struct value **args,
1015                       CORE_ADDR sp,
1016                       function_call_return_method return_method,
1017                       CORE_ADDR struct_addr)
1018 {
1019   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1020   int argreg;
1021   int argnum;
1022   int arg_space = 0;
1023   int stack_offset;
1024   v850_gdbarch_tdep *tdep = gdbarch_tdep<v850_gdbarch_tdep> (gdbarch);
1025
1026   if (tdep->abi == V850_ABI_RH850)
1027     stack_offset = 0;
1028   else
1029     {
1030       /* The offset onto the stack at which we will start copying parameters
1031          (after the registers are used up) begins at 16 rather than at zero.
1032          That's how the ABI is defined, though there's no indication that these
1033          16 bytes are used for anything, not even for saving incoming
1034          argument registers.  */
1035       stack_offset = 16;
1036     }
1037
1038   /* Now make space on the stack for the args.  */
1039   for (argnum = 0; argnum < nargs; argnum++)
1040     arg_space += ((args[argnum]->type ()->length () + 3) & ~3);
1041   sp -= arg_space + stack_offset;
1042
1043   argreg = E_ARG0_REGNUM;
1044   /* The struct_return pointer occupies the first parameter register.  */
1045   if (return_method == return_method_struct)
1046     regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
1047
1048   /* Now load as many as possible of the first arguments into
1049      registers, and push the rest onto the stack.  There are 16 bytes
1050      in four registers available.  Loop through args from first to last.  */
1051   for (argnum = 0; argnum < nargs; argnum++)
1052     {
1053       int len;
1054       gdb_byte *val;
1055       gdb_byte valbuf[v850_reg_size];
1056
1057       if (!v850_type_is_scalar ((*args)->type ())
1058           && tdep->abi == V850_ABI_GCC
1059           && (*args)->type ()->length () > E_MAX_RETTYPE_SIZE_IN_REGS)
1060         {
1061           store_unsigned_integer (valbuf, 4, byte_order,
1062                                   (*args)->address ());
1063           len = 4;
1064           val = valbuf;
1065         }
1066       else
1067         {
1068           len = (*args)->type ()->length ();
1069           val = (gdb_byte *) (*args)->contents ().data ();
1070         }
1071
1072       if (tdep->eight_byte_align
1073           && v850_eight_byte_align_p ((*args)->type ()))
1074         {
1075           if (argreg <= E_ARGLAST_REGNUM && (argreg & 1))
1076             argreg++;
1077           else if (stack_offset & 0x4)
1078             stack_offset += 4;
1079         }
1080
1081       while (len > 0)
1082         if (argreg <= E_ARGLAST_REGNUM)
1083           {
1084             CORE_ADDR regval;
1085
1086             regval = extract_unsigned_integer (val, v850_reg_size, byte_order);
1087             regcache_cooked_write_unsigned (regcache, argreg, regval);
1088
1089             len -= v850_reg_size;
1090             val += v850_reg_size;
1091             argreg++;
1092           }
1093         else
1094           {
1095             write_memory (sp + stack_offset, val, 4);
1096
1097             len -= 4;
1098             val += 4;
1099             stack_offset += 4;
1100           }
1101       args++;
1102     }
1103
1104   /* Store return address.  */
1105   regcache_cooked_write_unsigned (regcache, E_LP_REGNUM, bp_addr);
1106
1107   /* Update stack pointer.  */
1108   regcache_cooked_write_unsigned (regcache, E_SP_REGNUM, sp);
1109
1110   return sp;
1111 }
1112
1113 static void
1114 v850_extract_return_value (struct type *type, struct regcache *regcache,
1115                            gdb_byte *valbuf)
1116 {
1117   struct gdbarch *gdbarch = regcache->arch ();
1118   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1119   int len = type->length ();
1120
1121   if (len <= v850_reg_size)
1122     {
1123       ULONGEST val;
1124
1125       regcache_cooked_read_unsigned (regcache, E_V0_REGNUM, &val);
1126       store_unsigned_integer (valbuf, len, byte_order, val);
1127     }
1128   else if (len <= 2 * v850_reg_size)
1129     {
1130       int i, regnum = E_V0_REGNUM;
1131       gdb_byte buf[v850_reg_size];
1132       for (i = 0; len > 0; i += 4, len -= 4)
1133         {
1134           regcache->raw_read (regnum++, buf);
1135           memcpy (valbuf + i, buf, len > 4 ? 4 : len);
1136         }
1137     }
1138 }
1139
1140 static void
1141 v850_store_return_value (struct type *type, struct regcache *regcache,
1142                          const gdb_byte *valbuf)
1143 {
1144   struct gdbarch *gdbarch = regcache->arch ();
1145   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1146   int len = type->length ();
1147
1148   if (len <= v850_reg_size)
1149       regcache_cooked_write_unsigned
1150         (regcache, E_V0_REGNUM,
1151          extract_unsigned_integer (valbuf, len, byte_order));
1152   else if (len <= 2 * v850_reg_size)
1153     {
1154       int i, regnum = E_V0_REGNUM;
1155       for (i = 0; i < len; i += 4)
1156         regcache->raw_write (regnum++, valbuf + i);
1157     }
1158 }
1159
1160 static enum return_value_convention
1161 v850_return_value (struct gdbarch *gdbarch, struct value *function,
1162                    struct type *type, struct regcache *regcache,
1163                    gdb_byte *readbuf, const gdb_byte *writebuf)
1164 {
1165   if (v850_use_struct_convention (gdbarch, type))
1166     return RETURN_VALUE_STRUCT_CONVENTION;
1167   if (writebuf)
1168     v850_store_return_value (type, regcache, writebuf);
1169   else if (readbuf)
1170     v850_extract_return_value (type, regcache, readbuf);
1171   return RETURN_VALUE_REGISTER_CONVENTION;
1172 }
1173
1174 /* Implement the breakpoint_kind_from_pc gdbarch method.  */
1175
1176 static int
1177 v850_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr)
1178 {
1179   return 2;
1180 }
1181
1182 /* Implement the sw_breakpoint_from_kind gdbarch method.  */
1183
1184 static const gdb_byte *
1185 v850_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size)
1186 {
1187   *size = kind;
1188
1189     switch (gdbarch_bfd_arch_info (gdbarch)->mach)
1190     {
1191     case bfd_mach_v850e2:
1192     case bfd_mach_v850e2v3:
1193     case bfd_mach_v850e3v5:
1194       {
1195         /* Implement software breakpoints by using the dbtrap instruction.
1196            Older architectures had no such instruction.  For those, an
1197            unconditional branch to self instruction is used.  */
1198
1199         static unsigned char dbtrap_breakpoint[] = { 0x40, 0xf8 };
1200
1201         return dbtrap_breakpoint;
1202       }
1203       break;
1204     default:
1205       {
1206         static unsigned char breakpoint[] = { 0x85, 0x05 };
1207
1208         return breakpoint;
1209       }
1210       break;
1211     }
1212 }
1213
1214 static struct v850_frame_cache *
1215 v850_alloc_frame_cache (const frame_info_ptr &this_frame)
1216 {
1217   struct v850_frame_cache *cache;
1218
1219   cache = FRAME_OBSTACK_ZALLOC (struct v850_frame_cache);
1220   cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
1221
1222   /* Base address.  */
1223   cache->base = 0;
1224   cache->sp_offset = 0;
1225   cache->pc = 0;
1226
1227   /* Frameless until proven otherwise.  */
1228   cache->uses_fp = 0;
1229
1230   return cache;
1231 }
1232
1233 static struct v850_frame_cache *
1234 v850_frame_cache (const frame_info_ptr &this_frame, void **this_cache)
1235 {
1236   struct gdbarch *gdbarch = get_frame_arch (this_frame);
1237   struct v850_frame_cache *cache;
1238   CORE_ADDR current_pc;
1239   int i;
1240
1241   if (*this_cache)
1242     return (struct v850_frame_cache *) *this_cache;
1243
1244   cache = v850_alloc_frame_cache (this_frame);
1245   *this_cache = cache;
1246
1247   /* In principle, for normal frames, fp holds the frame pointer,
1248      which holds the base address for the current stack frame.
1249      However, for functions that don't need it, the frame pointer is
1250      optional.  For these "frameless" functions the frame pointer is
1251      actually the frame pointer of the calling frame.  */
1252   cache->base = get_frame_register_unsigned (this_frame, E_FP_REGNUM);
1253   if (cache->base == 0)
1254     return cache;
1255
1256   cache->pc = get_frame_func (this_frame);
1257   current_pc = get_frame_pc (this_frame);
1258   if (cache->pc != 0)
1259     {
1260       ULONGEST ctbp;
1261       ctbp = get_frame_register_unsigned (this_frame, E_CTBP_REGNUM);
1262       v850_analyze_prologue (gdbarch, cache->pc, current_pc, cache, ctbp);
1263     }
1264
1265   if (!cache->uses_fp)
1266     {
1267       /* We didn't find a valid frame, which means that CACHE->base
1268          currently holds the frame pointer for our calling frame.  If
1269          we're at the start of a function, or somewhere half-way its
1270          prologue, the function's frame probably hasn't been fully
1271          setup yet.  Try to reconstruct the base address for the stack
1272          frame by looking at the stack pointer.  For truly "frameless"
1273          functions this might work too.  */
1274       cache->base = get_frame_register_unsigned (this_frame, E_SP_REGNUM);
1275     }
1276
1277   /* Now that we have the base address for the stack frame we can
1278      calculate the value of sp in the calling frame.  */
1279   cache->saved_regs[E_SP_REGNUM].set_value (cache->base - cache->sp_offset);
1280
1281   /* Adjust all the saved registers such that they contain addresses
1282      instead of offsets.  */
1283   for (i = 0; i < gdbarch_num_regs (gdbarch); i++)
1284     if (cache->saved_regs[i].is_addr ())
1285       cache->saved_regs[i].set_addr (cache->saved_regs[i].addr ()
1286                                      + cache->base);
1287
1288   /* The call instruction moves the caller's PC in the callee's LP.
1289      Since this is an unwind, do the reverse.  Copy the location of LP
1290      into PC (the address / regnum) so that a request for PC will be
1291      converted into a request for the LP.  */
1292
1293   cache->saved_regs[E_PC_REGNUM] = cache->saved_regs[E_LP_REGNUM];
1294
1295   return cache;
1296 }
1297
1298
1299 static struct value *
1300 v850_frame_prev_register (const frame_info_ptr &this_frame,
1301                           void **this_cache, int regnum)
1302 {
1303   struct v850_frame_cache *cache = v850_frame_cache (this_frame, this_cache);
1304
1305   gdb_assert (regnum >= 0);
1306
1307   return trad_frame_get_prev_register (this_frame, cache->saved_regs, regnum);
1308 }
1309
1310 static void
1311 v850_frame_this_id (const frame_info_ptr &this_frame, void **this_cache,
1312                     struct frame_id *this_id)
1313 {
1314   struct v850_frame_cache *cache = v850_frame_cache (this_frame, this_cache);
1315
1316   /* This marks the outermost frame.  */
1317   if (cache->base == 0)
1318     return;
1319
1320   *this_id = frame_id_build (cache->saved_regs[E_SP_REGNUM].addr (), cache->pc);
1321 }
1322
1323 static const struct frame_unwind v850_frame_unwind = {
1324   "v850 prologue",
1325   NORMAL_FRAME,
1326   default_frame_unwind_stop_reason,
1327   v850_frame_this_id,
1328   v850_frame_prev_register,
1329   NULL,
1330   default_frame_sniffer
1331 };
1332
1333 static CORE_ADDR
1334 v850_frame_base_address (const frame_info_ptr &this_frame, void **this_cache)
1335 {
1336   struct v850_frame_cache *cache = v850_frame_cache (this_frame, this_cache);
1337
1338   return cache->base;
1339 }
1340
1341 static const struct frame_base v850_frame_base = {
1342   &v850_frame_unwind,
1343   v850_frame_base_address,
1344   v850_frame_base_address,
1345   v850_frame_base_address
1346 };
1347
1348 static struct gdbarch *
1349 v850_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1350 {
1351   int e_flags, e_machine;
1352
1353   /* Extract the elf_flags if available.  */
1354   if (info.abfd != NULL
1355       && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
1356     {
1357       e_flags = elf_elfheader (info.abfd)->e_flags;
1358       e_machine = elf_elfheader (info.abfd)->e_machine;
1359     }
1360   else
1361     {
1362       e_flags = 0;
1363       e_machine = 0;
1364     }
1365
1366
1367   /* Try to find the architecture in the list of already defined
1368      architectures.  */
1369   for (arches = gdbarch_list_lookup_by_info (arches, &info);
1370        arches != NULL;
1371        arches = gdbarch_list_lookup_by_info (arches->next, &info))
1372     {
1373       v850_gdbarch_tdep *tdep
1374         = gdbarch_tdep<v850_gdbarch_tdep> (arches->gdbarch);
1375
1376       if (tdep->e_flags != e_flags || tdep->e_machine != e_machine)
1377         continue;
1378
1379       return arches->gdbarch;
1380     }
1381
1382   gdbarch *gdbarch
1383     = gdbarch_alloc (&info, gdbarch_tdep_up (new v850_gdbarch_tdep));
1384   v850_gdbarch_tdep *tdep = gdbarch_tdep<v850_gdbarch_tdep> (gdbarch);
1385
1386   tdep->e_flags = e_flags;
1387   tdep->e_machine = e_machine;
1388
1389   switch (tdep->e_machine)
1390     {
1391     case EM_V800:
1392       tdep->abi = V850_ABI_RH850;
1393       break;
1394     default:
1395       tdep->abi = V850_ABI_GCC;
1396       break;
1397     }
1398
1399   tdep->eight_byte_align = (tdep->e_flags & EF_RH850_DATA_ALIGN8) ? 1 : 0;
1400
1401   switch (info.bfd_arch_info->mach)
1402     {
1403     case bfd_mach_v850:
1404       set_gdbarch_register_name (gdbarch, v850_register_name);
1405       set_gdbarch_num_regs (gdbarch, E_NUM_OF_V850_REGS);
1406       break;
1407     case bfd_mach_v850e:
1408     case bfd_mach_v850e1:
1409       set_gdbarch_register_name (gdbarch, v850e_register_name);
1410       set_gdbarch_num_regs (gdbarch, E_NUM_OF_V850E_REGS);
1411       break;
1412     case bfd_mach_v850e2:
1413     case bfd_mach_v850e2v3:
1414       set_gdbarch_register_name (gdbarch, v850e2_register_name);
1415       set_gdbarch_num_regs (gdbarch, E_NUM_REGS);
1416       break;
1417     case bfd_mach_v850e3v5:
1418       set_gdbarch_register_name (gdbarch, v850e3v5_register_name);
1419       set_gdbarch_num_regs (gdbarch, E_NUM_OF_V850E3V5_REGS);
1420       break;
1421     }
1422
1423   set_gdbarch_num_pseudo_regs (gdbarch, 0);
1424   set_gdbarch_sp_regnum (gdbarch, E_SP_REGNUM);
1425   set_gdbarch_pc_regnum (gdbarch, E_PC_REGNUM);
1426   set_gdbarch_fp0_regnum (gdbarch, -1);
1427
1428   set_gdbarch_register_type (gdbarch, v850_register_type);
1429
1430   set_gdbarch_char_signed (gdbarch, 1);
1431   set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
1432   set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1433   set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1434   set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
1435
1436   set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1437   set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
1438   set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
1439
1440   set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1441   set_gdbarch_addr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1442
1443   set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1444
1445   set_gdbarch_breakpoint_kind_from_pc (gdbarch, v850_breakpoint_kind_from_pc);
1446   set_gdbarch_sw_breakpoint_from_kind (gdbarch, v850_sw_breakpoint_from_kind);
1447   set_gdbarch_return_value (gdbarch, v850_return_value);
1448   set_gdbarch_push_dummy_call (gdbarch, v850_push_dummy_call);
1449   set_gdbarch_skip_prologue (gdbarch, v850_skip_prologue);
1450
1451   set_gdbarch_frame_align (gdbarch, v850_frame_align);
1452   frame_base_set_default (gdbarch, &v850_frame_base);
1453
1454   /* Hook in ABI-specific overrides, if they have been registered.  */
1455   gdbarch_init_osabi (info, gdbarch);
1456
1457   dwarf2_append_unwinders (gdbarch);
1458   frame_unwind_append_unwinder (gdbarch, &v850_frame_unwind);
1459
1460   return gdbarch;
1461 }
1462
1463 void _initialize_v850_tdep ();
1464 void
1465 _initialize_v850_tdep ()
1466 {
1467   gdbarch_register (bfd_arch_v850, v850_gdbarch_init);
1468   gdbarch_register (bfd_arch_v850_rh850, v850_gdbarch_init);
1469 }