opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2025 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40 #include "safe-ctype.h"
  41
  42 typedef struct instr_info instr_info;
  43
  44 static bool dofloat (instr_info *, int);
  45 static int putop (instr_info *, const char *, int);
  46 static void oappend_with_style (instr_info *, const char *,
  47                                 enum disassembler_style);
  48
  49 static bool OP_E (instr_info *, int, int);
  50 static bool OP_E_memory (instr_info *, int, int);
  51 static bool OP_indirE (instr_info *, int, int);
  52 static bool OP_G (instr_info *, int, int);
  53 static bool OP_ST (instr_info *, int, int);
  54 static bool OP_STi (instr_info *, int, int);
  55 static bool OP_Skip_MODRM (instr_info *, int, int);
  56 static bool OP_REG (instr_info *, int, int);
  57 static bool OP_IMREG (instr_info *, int, int);
  58 static bool OP_I (instr_info *, int, int);
  59 static bool OP_I64 (instr_info *, int, int);
  60 static bool OP_sI (instr_info *, int, int);
  61 static bool OP_J (instr_info *, int, int);
  62 static bool OP_SEG (instr_info *, int, int);
  63 static bool OP_DIR (instr_info *, int, int);
  64 static bool OP_OFF (instr_info *, int, int);
  65 static bool OP_OFF64 (instr_info *, int, int);
  66 static bool OP_ESreg (instr_info *, int, int);
  67 static bool OP_DSreg (instr_info *, int, int);
  68 static bool OP_C (instr_info *, int, int);
  69 static bool OP_D (instr_info *, int, int);
  70 static bool OP_T (instr_info *, int, int);
  71 static bool OP_MMX (instr_info *, int, int);
  72 static bool OP_XMM (instr_info *, int, int);
  73 static bool OP_EM (instr_info *, int, int);
  74 static bool OP_EX (instr_info *, int, int);
  75 static bool OP_EMC (instr_info *, int,int);
  76 static bool OP_MXC (instr_info *, int,int);
  77 static bool OP_R (instr_info *, int, int);
  78 static bool OP_M (instr_info *, int, int);
  79 static bool OP_VEX (instr_info *, int, int);
  80 static bool OP_VexR (instr_info *, int, int);
  81 static bool OP_VexW (instr_info *, int, int);
  82 static bool OP_Rounding (instr_info *, int, int);
  83 static bool OP_REG_VexI4 (instr_info *, int, int);
  84 static bool OP_VexI4 (instr_info *, int, int);
  85 static bool OP_0f07 (instr_info *, int, int);
  86 static bool OP_Monitor (instr_info *, int, int);
  87 static bool OP_Mwait (instr_info *, int, int);
  88
  89 static bool PCLMUL_Fixup (instr_info *, int, int);
  90 static bool VPCMP_Fixup (instr_info *, int, int);
  91 static bool VPCOM_Fixup (instr_info *, int, int);
  92 static bool NOP_Fixup (instr_info *, int, int);
  93 static bool MONTMUL_Fixup (instr_info *, int, int);
  94 static bool OP_3DNowSuffix (instr_info *, int, int);
  95 static bool CMP_Fixup (instr_info *, int, int);
  96 static bool REP_Fixup (instr_info *, int, int);
  97 static bool SEP_Fixup (instr_info *, int, int);
  98 static bool BND_Fixup (instr_info *, int, int);
  99 static bool NOTRACK_Fixup (instr_info *, int, int);
 100 static bool HLE_Fixup1 (instr_info *, int, int);
 101 static bool HLE_Fixup2 (instr_info *, int, int);
 102 static bool HLE_Fixup3 (instr_info *, int, int);
 103 static bool CMPXCHG8B_Fixup (instr_info *, int, int);
 104 static bool XMM_Fixup (instr_info *, int, int);
 105 static bool FXSAVE_Fixup (instr_info *, int, int);
 106 static bool MOVSXD_Fixup (instr_info *, int, int);
 107 static bool DistinctDest_Fixup (instr_info *, int, int);
 108 static bool PREFETCHI_Fixup (instr_info *, int, int);
 109 static bool PUSH2_POP2_Fixup (instr_info *, int, int);
 110 static bool JMPABS_Fixup (instr_info *, int, int);
 111 static bool CFCMOV_Fixup (instr_info *, int, int);
 112
 113 static void ATTRIBUTE_PRINTF_3 i386_dis_printf (const disassemble_info *,
 114                                                 enum disassembler_style,
 115                                                 const char *, ...);
 116
 117 /* This character is used to encode style information within the output
 118    buffers.  See oappend_insert_style for more details.  */
 119 #define STYLE_MARKER_CHAR '\002'
 120
 121 /* The maximum operand buffer size.  */
 122 #define MAX_OPERAND_BUFFER_SIZE 128
 123
 124 enum address_mode
 125 {
 126   mode_16bit,
 127   mode_32bit,
 128   mode_64bit
 129 };
 130
 131 static const char *prefix_name (enum address_mode, uint8_t, int);
 132
 133 enum x86_64_isa
 134 {
 135   amd64 = 1,
 136   intel64
 137 };
 138
 139 enum evex_type
 140 {
 141   evex_default = 0,
 142   evex_from_legacy,
 143   evex_from_vex,
 144 };
 145
 146 struct instr_info
 147 {
 148   enum address_mode address_mode;
 149
 150   /* Flags for the prefixes for the current instruction.  See below.  */
 151   int prefixes;
 152
 153   /* REX prefix the current instruction.  See below.  */
 154   uint8_t rex;
 155   /* Bits of REX we've already used.  */
 156   uint8_t rex_used;
 157
 158   /* Record W R4 X4 B4 bits for rex2.  */
 159   unsigned char rex2;
 160   /* Bits of rex2 we've already used.  */
 161   unsigned char rex2_used;
 162   unsigned char rex2_payload;
 163
 164   bool need_modrm;
 165   unsigned char condition_code;
 166   unsigned char need_vex;
 167   bool has_sib;
 168
 169   /* Flags for ins->prefixes which we somehow handled when printing the
 170      current instruction.  */
 171   int used_prefixes;
 172
 173   /* Flags for EVEX bits which we somehow handled when printing the
 174      current instruction.  */
 175   int evex_used;
 176
 177   char obuf[MAX_OPERAND_BUFFER_SIZE];
 178   char *obufp;
 179   char *mnemonicendp;
 180   const uint8_t *start_codep;
 181   uint8_t *codep;
 182   const uint8_t *end_codep;
 183   unsigned char nr_prefixes;
 184   signed char last_lock_prefix;
 185   signed char last_repz_prefix;
 186   signed char last_repnz_prefix;
 187   signed char last_data_prefix;
 188   signed char last_addr_prefix;
 189   signed char last_rex_prefix;
 190   signed char last_rex2_prefix;
 191   signed char last_seg_prefix;
 192   signed char fwait_prefix;
 193   /* The active segment register prefix.  */
 194   unsigned char active_seg_prefix;
 195
 196 #define MAX_CODE_LENGTH 15
 197   /* We can up to 14 ins->prefixes since the maximum instruction length is
 198      15bytes.  */
 199   uint8_t all_prefixes[MAX_CODE_LENGTH - 1];
 200   disassemble_info *info;
 201
 202   struct
 203   {
 204     int mod;
 205     int reg;
 206     int rm;
 207   }
 208   modrm;
 209
 210   struct
 211   {
 212     int scale;
 213     int index;
 214     int base;
 215   }
 216   sib;
 217
 218   struct
 219   {
 220     int register_specifier;
 221     int length;
 222     int prefix;
 223     int mask_register_specifier;
 224     int scc;
 225     int ll;
 226     bool w;
 227     bool evex;
 228     bool v;
 229     bool zeroing;
 230     bool b;
 231     bool no_broadcast;
 232     bool nf;
 233     bool u;
 234   }
 235   vex;
 236
 237 /* For APX EVEX-promoted prefix, EVEX.ND shares the same bit as vex.b.  */
 238 #define nd b
 239
 240   enum evex_type evex_type;
 241
 242   /* Remember if the current op is a jump instruction.  */
 243   bool op_is_jump;
 244
 245   bool two_source_ops;
 246
 247   /* Record whether EVEX masking is used incorrectly.  */
 248   bool illegal_masking;
 249
 250   /* Record whether the modrm byte has been skipped.  */
 251   bool has_skipped_modrm;
 252
 253   unsigned char op_ad;
 254   signed char op_index[MAX_OPERANDS];
 255   bool op_riprel[MAX_OPERANDS];
 256   char *op_out[MAX_OPERANDS];
 257   bfd_vma op_address[MAX_OPERANDS];
 258   bfd_vma start_pc;
 259
 260   /* On the 386's of 1988, the maximum length of an instruction is 15 bytes.
 261    *   (see topic "Redundant ins->prefixes" in the "Differences from 8086"
 262    *   section of the "Virtual 8086 Mode" chapter.)
 263    * 'pc' should be the address of this instruction, it will
 264    *   be used to print the target address if this is a relative jump or call
 265    * The function returns the length of this instruction in bytes.
 266    */
 267   char intel_syntax;
 268   bool intel_mnemonic;
 269   char open_char;
 270   char close_char;
 271   char separator_char;
 272   char scale_char;
 273
 274   enum x86_64_isa isa64;
 275 };
 276
 277 struct dis_private {
 278   bfd_vma insn_start;
 279   int orig_sizeflag;
 280
 281   /* Indexes first byte not fetched.  */
 282   unsigned int fetched;
 283   uint8_t the_buffer[2 * MAX_CODE_LENGTH - 1];
 284 };
 285
 286 /* Mark parts used in the REX prefix.  When we are testing for
 287    empty prefix (for 8bit register REX extension), just mask it
 288    out.  Otherwise test for REX bit is excuse for existence of REX
 289    only in case value is nonzero.  */
 290 #define USED_REX(value)                                 \
 291   {                                                     \
 292     if (value)                                          \
 293       {                                                 \
 294         if (ins->rex & value)                           \
 295           ins->rex_used |= (value) | REX_OPCODE;        \
 296         if (ins->rex2 & value)                          \
 297           {                                             \
 298             ins->rex2_used |= (value);                  \
 299             ins->rex_used |= REX_OPCODE;                \
 300           }                                             \
 301       }                                                 \
 302     else                                                \
 303       ins->rex_used |= REX_OPCODE;                      \
 304   }
 305
 306
 307 #define EVEX_b_used 1
 308 #define EVEX_len_used 2
 309
 310
 311 /* {rex2} is not printed when the REX2_SPECIAL is set.  */
 312 #define REX2_SPECIAL 16
 313
 314 /* Flags stored in PREFIXES.  */
 315 #define PREFIX_REPZ 1
 316 #define PREFIX_REPNZ 2
 317 #define PREFIX_CS 4
 318 #define PREFIX_SS 8
 319 #define PREFIX_DS 0x10
 320 #define PREFIX_ES 0x20
 321 #define PREFIX_FS 0x40
 322 #define PREFIX_GS 0x80
 323 #define PREFIX_LOCK 0x100
 324 #define PREFIX_DATA 0x200
 325 #define PREFIX_ADDR 0x400
 326 #define PREFIX_FWAIT 0x800
 327 #define PREFIX_REX2 0x1000
 328 #define PREFIX_NP_OR_DATA 0x2000
 329 #define NO_PREFIX   0x4000
 330
 331 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 332    to ADDR (exclusive) are valid.  Returns true for success, false
 333    on error.  */
 334 static bool
 335 fetch_code (struct disassemble_info *info, const uint8_t *until)
 336 {
 337   int status = -1;
 338   struct dis_private *priv = info->private_data;
 339   bfd_vma start = priv->insn_start + priv->fetched;
 340   uint8_t *fetch_end = priv->the_buffer + priv->fetched;
 341   ptrdiff_t needed = until - fetch_end;
 342
 343   if (needed <= 0)
 344     return true;
 345
 346   if (priv->fetched + (size_t) needed <= ARRAY_SIZE (priv->the_buffer))
 347     status = (*info->read_memory_func) (start, fetch_end, needed, info);
 348   if (status != 0)
 349     {
 350       /* If we did manage to read at least one byte, then
 351          print_insn_i386 will do something sensible.  Otherwise, print
 352          an error.  We do that here because this is where we know
 353          STATUS.  */
 354       if (!priv->fetched)
 355         (*info->memory_error_func) (status, start, info);
 356       return false;
 357     }
 358
 359   priv->fetched += needed;
 360   return true;
 361 }
 362
 363 static bool
 364 fetch_modrm (instr_info *ins)
 365 {
 366   if (!fetch_code (ins->info, ins->codep + 1))
 367     return false;
 368
 369   ins->modrm.mod = (*ins->codep >> 6) & 3;
 370   ins->modrm.reg = (*ins->codep >> 3) & 7;
 371   ins->modrm.rm = *ins->codep & 7;
 372
 373   return true;
 374 }
 375
 376 static int
 377 fetch_error (const instr_info *ins)
 378 {
 379   /* Getting here means we tried for data but didn't get it.  That
 380      means we have an incomplete instruction of some sort.  Just
 381      print the first byte as a prefix or a .byte pseudo-op.  */
 382   const struct dis_private *priv = ins->info->private_data;
 383   const char *name = NULL;
 384
 385   if (ins->codep <= priv->the_buffer)
 386     return -1;
 387
 388   if (ins->prefixes || ins->fwait_prefix >= 0 || (ins->rex & REX_OPCODE))
 389     name = prefix_name (ins->address_mode, priv->the_buffer[0],
 390                         priv->orig_sizeflag);
 391   if (name != NULL)
 392     i386_dis_printf (ins->info, dis_style_mnemonic, "%s", name);
 393   else
 394     {
 395       /* Just print the first byte as a .byte instruction.  */
 396       i386_dis_printf (ins->info, dis_style_assembler_directive, ".byte ");
 397       i386_dis_printf (ins->info, dis_style_immediate, "%#x",
 398                        (unsigned int) priv->the_buffer[0]);
 399     }
 400
 401   return 1;
 402 }
 403
 404 /* Possible values for prefix requirement.  */
 405 #define PREFIX_IGNORED_SHIFT    16
 406 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 407 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 408 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 409 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 410 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 411 #define PREFIX_REX2_ILLEGAL     (PREFIX_REX2 << PREFIX_IGNORED_SHIFT)
 412
 413 /* Opcode prefixes.  */
 414 #define PREFIX_OPCODE           (PREFIX_REPZ \
 415                                  | PREFIX_REPNZ \
 416                                  | PREFIX_DATA)
 417
 418 /* Prefixes ignored.  */
 419 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 420                                  | PREFIX_IGNORED_REPNZ \
 421                                  | PREFIX_IGNORED_DATA)
 422
 423 #define XX { NULL, 0 }
 424 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 425
 426 #define Eb { OP_E, b_mode }
 427 #define Ebnd { OP_E, bnd_mode }
 428 #define EbS { OP_E, b_swap_mode }
 429 #define EbndS { OP_E, bnd_swap_mode }
 430 #define Ev { OP_E, v_mode }
 431 #define Eva { OP_E, va_mode }
 432 #define Ev_bnd { OP_E, v_bnd_mode }
 433 #define EvS { OP_E, v_swap_mode }
 434 #define Ed { OP_E, d_mode }
 435 #define Edq { OP_E, dq_mode }
 436 #define Edb { OP_E, db_mode }
 437 #define Edw { OP_E, dw_mode }
 438 #define Eq { OP_E, q_mode }
 439 #define indirEv { OP_indirE, indir_v_mode }
 440 #define indirEp { OP_indirE, f_mode }
 441 #define stackEv { OP_E, stack_v_mode }
 442 #define Em { OP_E, m_mode }
 443 #define Ew { OP_E, w_mode }
 444 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 445 #define Ma { OP_M, a_mode }
 446 #define Mb { OP_M, b_mode }
 447 #define Md { OP_M, d_mode }
 448 #define Mdq { OP_M, dq_mode }
 449 #define Mo { OP_M, o_mode }
 450 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 451 #define Mq { OP_M, q_mode }
 452 #define Mv { OP_M, v_mode }
 453 #define Mv_bnd { OP_M, v_bndmk_mode }
 454 #define Mw { OP_M, w_mode }
 455 #define Mx { OP_M, x_mode }
 456 #define Mxmm { OP_M, xmm_mode }
 457 #define Mymm { OP_M, ymm_mode }
 458 #define Gb { OP_G, b_mode }
 459 #define Gbnd { OP_G, bnd_mode }
 460 #define Gv { OP_G, v_mode }
 461 #define Gd { OP_G, d_mode }
 462 #define Gdq { OP_G, dq_mode }
 463 #define Gq { OP_G, q_mode }
 464 #define Gm { OP_G, m_mode }
 465 #define Gva { OP_G, va_mode }
 466 #define Gw { OP_G, w_mode }
 467 #define Ib { OP_I, b_mode }
 468 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 469 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 470 #define Iv { OP_I, v_mode }
 471 #define sIv { OP_sI, v_mode }
 472 #define Iv64 { OP_I64, v_mode }
 473 #define Id { OP_I, d_mode }
 474 #define Iw { OP_I, w_mode }
 475 #define I1 { OP_I, const_1_mode }
 476 #define Jb { OP_J, b_mode }
 477 #define Jv { OP_J, v_mode }
 478 #define Jdqw { OP_J, dqw_mode }
 479 #define Cm { OP_C, m_mode }
 480 #define Dm { OP_D, m_mode }
 481 #define Td { OP_T, d_mode }
 482 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 483
 484 #define RMeAX { OP_REG, eAX_reg }
 485 #define RMeBX { OP_REG, eBX_reg }
 486 #define RMeCX { OP_REG, eCX_reg }
 487 #define RMeDX { OP_REG, eDX_reg }
 488 #define RMeSP { OP_REG, eSP_reg }
 489 #define RMeBP { OP_REG, eBP_reg }
 490 #define RMeSI { OP_REG, eSI_reg }
 491 #define RMeDI { OP_REG, eDI_reg }
 492 #define RMrAX { OP_REG, rAX_reg }
 493 #define RMrBX { OP_REG, rBX_reg }
 494 #define RMrCX { OP_REG, rCX_reg }
 495 #define RMrDX { OP_REG, rDX_reg }
 496 #define RMrSP { OP_REG, rSP_reg }
 497 #define RMrBP { OP_REG, rBP_reg }
 498 #define RMrSI { OP_REG, rSI_reg }
 499 #define RMrDI { OP_REG, rDI_reg }
 500 #define RMAL { OP_REG, al_reg }
 501 #define RMCL { OP_REG, cl_reg }
 502 #define RMDL { OP_REG, dl_reg }
 503 #define RMBL { OP_REG, bl_reg }
 504 #define RMAH { OP_REG, ah_reg }
 505 #define RMCH { OP_REG, ch_reg }
 506 #define RMDH { OP_REG, dh_reg }
 507 #define RMBH { OP_REG, bh_reg }
 508 #define RMAX { OP_REG, ax_reg }
 509 #define RMDX { OP_REG, dx_reg }
 510
 511 #define eAX { OP_IMREG, eAX_reg }
 512 #define AL { OP_IMREG, al_reg }
 513 #define CL { OP_IMREG, cl_reg }
 514 #define zAX { OP_IMREG, z_mode_ax_reg }
 515 #define indirDX { OP_IMREG, indir_dx_reg }
 516
 517 #define Sw { OP_SEG, w_mode }
 518 #define Sv { OP_SEG, v_mode }
 519 #define Ap { OP_DIR, 0 }
 520 #define Ob { OP_OFF64, b_mode }
 521 #define Ov { OP_OFF64, v_mode }
 522 #define Xb { OP_DSreg, eSI_reg }
 523 #define Xv { OP_DSreg, eSI_reg }
 524 #define Xz { OP_DSreg, eSI_reg }
 525 #define Yb { OP_ESreg, eDI_reg }
 526 #define Yv { OP_ESreg, eDI_reg }
 527 #define DSBX { OP_DSreg, eBX_reg }
 528
 529 #define es { OP_REG, es_reg }
 530 #define ss { OP_REG, ss_reg }
 531 #define cs { OP_REG, cs_reg }
 532 #define ds { OP_REG, ds_reg }
 533 #define fs { OP_REG, fs_reg }
 534 #define gs { OP_REG, gs_reg }
 535
 536 #define MX { OP_MMX, 0 }
 537 #define XM { OP_XMM, 0 }
 538 #define XMScalar { OP_XMM, scalar_mode }
 539 #define XMGatherD { OP_XMM, vex_vsib_d_w_dq_mode }
 540 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 541 #define XMM { OP_XMM, xmm_mode }
 542 #define TMM { OP_XMM, tmm_mode }
 543 #define XMxmmq { OP_XMM, xmmq_mode }
 544 #define EM { OP_EM, v_mode }
 545 #define EMS { OP_EM, v_swap_mode }
 546 #define EMd { OP_EM, d_mode }
 547 #define EMx { OP_EM, x_mode }
 548 #define EXbwUnit { OP_EX, bw_unit_mode }
 549 #define EXb { OP_EX, b_mode }
 550 #define EXw { OP_EX, w_mode }
 551 #define EXd { OP_EX, d_mode }
 552 #define EXdS { OP_EX, d_swap_mode }
 553 #define EXwS { OP_EX, w_swap_mode }
 554 #define EXq { OP_EX, q_mode }
 555 #define EXqS { OP_EX, q_swap_mode }
 556 #define EXdq { OP_EX, dq_mode }
 557 #define EXx { OP_EX, x_mode }
 558 #define EXxh { OP_EX, xh_mode }
 559 #define EXxS { OP_EX, x_swap_mode }
 560 #define EXxmm { OP_EX, xmm_mode }
 561 #define EXymm { OP_EX, ymm_mode }
 562 #define EXxmmq { OP_EX, xmmq_mode }
 563 #define EXxmmqh { OP_EX, evex_half_bcst_xmmqh_mode }
 564 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 565 #define EXxmmdw { OP_EX, xmmdw_mode }
 566 #define EXxmmqd { OP_EX, xmmqd_mode }
 567 #define EXxmmqdh { OP_EX, evex_half_bcst_xmmqdh_mode }
 568 #define EXymmq { OP_EX, ymmq_mode }
 569 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 570 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 571 #define Rd { OP_R, d_mode }
 572 #define Rdq { OP_R, dq_mode }
 573 #define Rq { OP_R, q_mode }
 574 #define Nq { OP_R, q_mm_mode }
 575 #define Ux { OP_R, x_mode }
 576 #define Uxmm { OP_R, xmm_mode }
 577 #define Rxmmq { OP_R, xmmq_mode }
 578 #define Rymm { OP_R, ymm_mode }
 579 #define Rtmm { OP_R, tmm_mode }
 580 #define EMCq { OP_EMC, q_mode }
 581 #define MXC { OP_MXC, 0 }
 582 #define OPSUF { OP_3DNowSuffix, 0 }
 583 #define SEP { SEP_Fixup, 0 }
 584 #define CMP { CMP_Fixup, 0 }
 585 #define XMM0 { XMM_Fixup, 0 }
 586 #define FXSAVE { FXSAVE_Fixup, 0 }
 587
 588 #define Vex { OP_VEX, x_mode }
 589 #define VexW { OP_VexW, x_mode }
 590 #define VexScalar { OP_VEX, scalar_mode }
 591 #define VexScalarR { OP_VexR, scalar_mode }
 592 #define VexGatherD { OP_VEX, vex_vsib_d_w_dq_mode }
 593 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 594 #define VexGdq { OP_VEX, dq_mode }
 595 #define VexGb { OP_VEX, b_mode }
 596 #define VexGv { OP_VEX, v_mode }
 597 #define VexTmm { OP_VEX, tmm_mode }
 598 #define XMVexI4 { OP_REG_VexI4, x_mode }
 599 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
 600 #define VexI4 { OP_VexI4, 0 }
 601 #define PCLMUL { PCLMUL_Fixup, 0 }
 602 #define VPCMP { VPCMP_Fixup, 0 }
 603 #define VPCOM { VPCOM_Fixup, 0 }
 604
 605 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 606 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 607 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 608
 609 #define MaskG { OP_G, mask_mode }
 610 #define MaskE { OP_E, mask_mode }
 611 #define MaskR { OP_R, mask_mode }
 612 #define MaskBDE { OP_E, mask_bd_mode }
 613 #define MaskVex { OP_VEX, mask_mode }
 614
 615 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 616 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 617
 618 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
 619
 620 /* Used handle "rep" prefix for string instructions.  */
 621 #define Xbr { REP_Fixup, eSI_reg }
 622 #define Xvr { REP_Fixup, eSI_reg }
 623 #define Ybr { REP_Fixup, eDI_reg }
 624 #define Yvr { REP_Fixup, eDI_reg }
 625 #define Yzr { REP_Fixup, eDI_reg }
 626 #define indirDXr { REP_Fixup, indir_dx_reg }
 627 #define ALr { REP_Fixup, al_reg }
 628 #define eAXr { REP_Fixup, eAX_reg }
 629
 630 /* Used handle HLE prefix for lockable instructions.  */
 631 #define Ebh1 { HLE_Fixup1, b_mode }
 632 #define Evh1 { HLE_Fixup1, v_mode }
 633 #define Ebh2 { HLE_Fixup2, b_mode }
 634 #define Evh2 { HLE_Fixup2, v_mode }
 635 #define Ebh3 { HLE_Fixup3, b_mode }
 636 #define Evh3 { HLE_Fixup3, v_mode }
 637
 638 #define BND { BND_Fixup, 0 }
 639 #define NOTRACK { NOTRACK_Fixup, 0 }
 640
 641 #define cond_jump_flag { NULL, cond_jump_mode }
 642 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 643
 644 /* bits in sizeflag */
 645 #define SUFFIX_ALWAYS 4
 646 #define AFLAG 2
 647 #define DFLAG 1
 648
 649 enum
 650 {
 651   /* byte operand */
 652   b_mode = 1,
 653   /* byte operand with operand swapped */
 654   b_swap_mode,
 655   /* byte operand, sign extend like 'T' suffix */
 656   b_T_mode,
 657   /* operand size depends on prefixes */
 658   v_mode,
 659   /* operand size depends on prefixes with operand swapped */
 660   v_swap_mode,
 661   /* operand size depends on address prefix */
 662   va_mode,
 663   /* word operand */
 664   w_mode,
 665   /* double word operand  */
 666   d_mode,
 667   /* word operand with operand swapped  */
 668   w_swap_mode,
 669   /* double word operand with operand swapped */
 670   d_swap_mode,
 671   /* quad word operand */
 672   q_mode,
 673   /* 8-byte MM operand */
 674   q_mm_mode,
 675   /* quad word operand with operand swapped */
 676   q_swap_mode,
 677   /* ten-byte operand */
 678   t_mode,
 679   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 680      broadcast enabled.  */
 681   x_mode,
 682   /* Similar to x_mode, but with different EVEX mem shifts.  */
 683   evex_x_gscat_mode,
 684   /* Similar to x_mode, but with yet different EVEX mem shifts.  */
 685   bw_unit_mode,
 686   /* Similar to x_mode, but with disabled broadcast.  */
 687   evex_x_nobcst_mode,
 688   /* Similar to x_mode, but with operands swapped and disabled broadcast
 689      in EVEX.  */
 690   x_swap_mode,
 691   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 692      broadcast of 16bit enabled.  */
 693   xh_mode,
 694   /* 16-byte XMM operand */
 695   xmm_mode,
 696   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 697      memory operand (depending on vector length).  Broadcast isn't
 698      allowed.  */
 699   xmmq_mode,
 700   /* Same as xmmq_mode, but broadcast is allowed.  */
 701   evex_half_bcst_xmmq_mode,
 702   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 703      memory operand (depending on vector length).  16bit broadcast.  */
 704   evex_half_bcst_xmmqh_mode,
 705   /* 16-byte XMM, word, double word or quad word operand.  */
 706   xmmdw_mode,
 707   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 708   xmmqd_mode,
 709   /* 16-byte XMM, double word, quad word operand or xmm word operand.
 710      16bit broadcast.  */
 711   evex_half_bcst_xmmqdh_mode,
 712   /* 32-byte YMM operand */
 713   ymm_mode,
 714   /* quad word, ymmword or zmmword memory operand.  */
 715   ymmq_mode,
 716   /* TMM operand */
 717   tmm_mode,
 718   /* d_mode in 32bit, q_mode in 64bit mode.  */
 719   m_mode,
 720   /* pair of v_mode operands */
 721   a_mode,
 722   cond_jump_mode,
 723   loop_jcxz_mode,
 724   movsxd_mode,
 725   v_bnd_mode,
 726   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 727   v_bndmk_mode,
 728   /* operand size depends on REX.W / VEX.W.  */
 729   dq_mode,
 730   /* Displacements like v_mode without considering Intel64 ISA.  */
 731   dqw_mode,
 732   /* bounds operand */
 733   bnd_mode,
 734   /* bounds operand with operand swapped */
 735   bnd_swap_mode,
 736   /* 4- or 6-byte pointer operand */
 737   f_mode,
 738   const_1_mode,
 739   /* v_mode for indirect branch opcodes.  */
 740   indir_v_mode,
 741   /* v_mode for stack-related opcodes.  */
 742   stack_v_mode,
 743   /* non-quad operand size depends on prefixes */
 744   z_mode,
 745   /* 16-byte operand */
 746   o_mode,
 747   /* registers like d_mode, memory like b_mode.  */
 748   db_mode,
 749   /* registers like d_mode, memory like w_mode.  */
 750   dw_mode,
 751
 752   /* Operand size depends on the VEX.W bit, with VSIB dword indices.  */
 753   vex_vsib_d_w_dq_mode,
 754   /* Operand size depends on the VEX.W bit, with VSIB qword indices.  */
 755   vex_vsib_q_w_dq_mode,
 756   /* mandatory non-vector SIB.  */
 757   vex_sibmem_mode,
 758
 759   /* scalar, ignore vector length.  */
 760   scalar_mode,
 761
 762   /* Static rounding.  */
 763   evex_rounding_mode,
 764   /* Static rounding, 64-bit mode only.  */
 765   evex_rounding_64_mode,
 766   /* Supress all exceptions.  */
 767   evex_sae_mode,
 768
 769   /* Mask register operand.  */
 770   mask_mode,
 771   /* Mask register operand.  */
 772   mask_bd_mode,
 773
 774   es_reg,
 775   cs_reg,
 776   ss_reg,
 777   ds_reg,
 778   fs_reg,
 779   gs_reg,
 780
 781   eAX_reg,
 782   eCX_reg,
 783   eDX_reg,
 784   eBX_reg,
 785   eSP_reg,
 786   eBP_reg,
 787   eSI_reg,
 788   eDI_reg,
 789
 790   al_reg,
 791   cl_reg,
 792   dl_reg,
 793   bl_reg,
 794   ah_reg,
 795   ch_reg,
 796   dh_reg,
 797   bh_reg,
 798
 799   ax_reg,
 800   cx_reg,
 801   dx_reg,
 802   bx_reg,
 803   sp_reg,
 804   bp_reg,
 805   si_reg,
 806   di_reg,
 807
 808   rAX_reg,
 809   rCX_reg,
 810   rDX_reg,
 811   rBX_reg,
 812   rSP_reg,
 813   rBP_reg,
 814   rSI_reg,
 815   rDI_reg,
 816
 817   z_mode_ax_reg,
 818   indir_dx_reg
 819 };
 820
 821 enum
 822 {
 823   FLOATCODE = 1,
 824   USE_REG_TABLE,
 825   USE_MOD_TABLE,
 826   USE_RM_TABLE,
 827   USE_PREFIX_TABLE,
 828   USE_X86_64_TABLE,
 829   USE_X86_64_EVEX_FROM_VEX_TABLE,
 830   USE_X86_64_EVEX_PFX_TABLE,
 831   USE_X86_64_EVEX_W_TABLE,
 832   USE_X86_64_EVEX_MEM_W_TABLE,
 833   USE_3BYTE_TABLE,
 834   USE_XOP_8F_TABLE,
 835   USE_VEX_C4_TABLE,
 836   USE_VEX_C5_TABLE,
 837   USE_VEX_LEN_TABLE,
 838   USE_VEX_W_TABLE,
 839   USE_EVEX_TABLE,
 840   USE_EVEX_LEN_TABLE
 841 };
 842
 843 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 844
 845 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 846 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 847 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 848 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 849 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 850 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 851 #define X86_64_EVEX_FROM_VEX_TABLE(I) \
 852   DIS386 (USE_X86_64_EVEX_FROM_VEX_TABLE, (I))
 853 #define X86_64_EVEX_PFX_TABLE(I) DIS386 (USE_X86_64_EVEX_PFX_TABLE, (I))
 854 #define X86_64_EVEX_W_TABLE(I) DIS386 (USE_X86_64_EVEX_W_TABLE, (I))
 855 #define X86_64_EVEX_MEM_W_TABLE(I) DIS386 (USE_X86_64_EVEX_MEM_W_TABLE, (I))
 856 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 857 #define XOP_8F_TABLE()          DIS386 (USE_XOP_8F_TABLE, 0)
 858 #define VEX_C4_TABLE()          DIS386 (USE_VEX_C4_TABLE, 0)
 859 #define VEX_C5_TABLE()          DIS386 (USE_VEX_C5_TABLE, 0)
 860 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 861 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 862 #define EVEX_TABLE()            DIS386 (USE_EVEX_TABLE, 0)
 863 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 864
 865 enum
 866 {
 867   REG_80 = 0,
 868   REG_81,
 869   REG_83,
 870   REG_8F,
 871   REG_C0,
 872   REG_C1,
 873   REG_C6,
 874   REG_C7,
 875   REG_D0,
 876   REG_D1,
 877   REG_D2,
 878   REG_D3,
 879   REG_F6,
 880   REG_F7,
 881   REG_FE,
 882   REG_FF,
 883   REG_0F00,
 884   REG_0F01,
 885   REG_0F0D,
 886   REG_0F18,
 887   REG_0F1C_P_0_MOD_0,
 888   REG_0F1E_P_1_MOD_3,
 889   REG_0F38D8_PREFIX_1,
 890   REG_0F3A0F_P_1,
 891   REG_0F71,
 892   REG_0F72,
 893   REG_0F73,
 894   REG_0FA6,
 895   REG_0FA7,
 896   REG_0FAE,
 897   REG_0FBA,
 898   REG_0FC7,
 899   REG_VEX_0F71,
 900   REG_VEX_0F72,
 901   REG_VEX_0F73,
 902   REG_VEX_0FAE,
 903   REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0,
 904   REG_VEX_0F38F3_L_0_P_0,
 905   REG_VEX_MAP7_F6_L_0_W_0,
 906   REG_VEX_MAP7_F8_L_0_W_0,
 907
 908   REG_XOP_09_01_L_0,
 909   REG_XOP_09_02_L_0,
 910   REG_XOP_09_12_L_0,
 911   REG_XOP_0A_12_L_0,
 912
 913   REG_EVEX_0F71,
 914   REG_EVEX_0F72,
 915   REG_EVEX_0F73,
 916   REG_EVEX_0F38C6_L_2,
 917   REG_EVEX_0F38C7_L_2,
 918   REG_EVEX_MAP4_80,
 919   REG_EVEX_MAP4_81,
 920   REG_EVEX_MAP4_83,
 921   REG_EVEX_MAP4_8F,
 922   REG_EVEX_MAP4_F6,
 923   REG_EVEX_MAP4_F7,
 924   REG_EVEX_MAP4_FE,
 925   REG_EVEX_MAP4_FF,
 926 };
 927
 928 enum
 929 {
 930   MOD_62_32BIT = 0,
 931   MOD_C4_32BIT,
 932   MOD_C5_32BIT,
 933   MOD_0F01_REG_0,
 934   MOD_0F01_REG_1,
 935   MOD_0F01_REG_2,
 936   MOD_0F01_REG_3,
 937   MOD_0F01_REG_5,
 938   MOD_0F01_REG_7,
 939   MOD_0F12_PREFIX_0,
 940   MOD_0F16_PREFIX_0,
 941   MOD_0F18_REG_0,
 942   MOD_0F18_REG_1,
 943   MOD_0F18_REG_2,
 944   MOD_0F18_REG_3,
 945   MOD_0F18_REG_4,
 946   MOD_0F18_REG_6,
 947   MOD_0F18_REG_7,
 948   MOD_0F1A_PREFIX_0,
 949   MOD_0F1B_PREFIX_0,
 950   MOD_0F1B_PREFIX_1,
 951   MOD_0F1C_PREFIX_0,
 952   MOD_0F1E_PREFIX_1,
 953   MOD_0FAE_REG_0,
 954   MOD_0FAE_REG_1,
 955   MOD_0FAE_REG_2,
 956   MOD_0FAE_REG_3,
 957   MOD_0FAE_REG_4,
 958   MOD_0FAE_REG_5,
 959   MOD_0FAE_REG_6,
 960   MOD_0FAE_REG_7,
 961   MOD_0FC7_REG_6,
 962   MOD_0FC7_REG_7,
 963   MOD_0F38DC_PREFIX_1,
 964   MOD_0F38F8,
 965
 966   MOD_VEX_0F3849_X86_64_L_0_W_0,
 967
 968   MOD_EVEX_MAP4_60,
 969   MOD_EVEX_MAP4_61,
 970   MOD_EVEX_MAP4_F8_P_1,
 971   MOD_EVEX_MAP4_F8_P_3,
 972 };
 973
 974 enum
 975 {
 976   RM_C6_REG_7 = 0,
 977   RM_C7_REG_7,
 978   RM_0F01_REG_0,
 979   RM_0F01_REG_1,
 980   RM_0F01_REG_2,
 981   RM_0F01_REG_3,
 982   RM_0F01_REG_5_MOD_3,
 983   RM_0F01_REG_7_MOD_3,
 984   RM_0F1E_P_1_MOD_3_REG_7,
 985   RM_0FAE_REG_6_MOD_3_P_0,
 986   RM_0FAE_REG_7_MOD_3,
 987   RM_0F3A0F_P_1_R_0,
 988
 989   RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0,
 990   RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3,
 991 };
 992
 993 enum
 994 {
 995   PREFIX_90 = 0,
 996   PREFIX_0F00_REG_6_X86_64,
 997   PREFIX_0F01_REG_0_MOD_3_RM_6,
 998   PREFIX_0F01_REG_0_MOD_3_RM_7,
 999   PREFIX_0F01_REG_1_RM_2,
1000   PREFIX_0F01_REG_1_RM_4,
1001   PREFIX_0F01_REG_1_RM_5,
1002   PREFIX_0F01_REG_1_RM_6,
1003   PREFIX_0F01_REG_1_RM_7,
1004   PREFIX_0F01_REG_3_RM_1,
1005   PREFIX_0F01_REG_5_MOD_0,
1006   PREFIX_0F01_REG_5_MOD_3_RM_0,
1007   PREFIX_0F01_REG_5_MOD_3_RM_1,
1008   PREFIX_0F01_REG_5_MOD_3_RM_2,
1009   PREFIX_0F01_REG_5_MOD_3_RM_4,
1010   PREFIX_0F01_REG_5_MOD_3_RM_5,
1011   PREFIX_0F01_REG_5_MOD_3_RM_6,
1012   PREFIX_0F01_REG_5_MOD_3_RM_7,
1013   PREFIX_0F01_REG_7_MOD_3_RM_2,
1014   PREFIX_0F01_REG_7_MOD_3_RM_5,
1015   PREFIX_0F01_REG_7_MOD_3_RM_6,
1016   PREFIX_0F01_REG_7_MOD_3_RM_7,
1017   PREFIX_0F09,
1018   PREFIX_0F10,
1019   PREFIX_0F11,
1020   PREFIX_0F12,
1021   PREFIX_0F16,
1022   PREFIX_0F18_REG_6_MOD_0_X86_64,
1023   PREFIX_0F18_REG_7_MOD_0_X86_64,
1024   PREFIX_0F1A,
1025   PREFIX_0F1B,
1026   PREFIX_0F1C,
1027   PREFIX_0F1E,
1028   PREFIX_0F2A,
1029   PREFIX_0F2B,
1030   PREFIX_0F2C,
1031   PREFIX_0F2D,
1032   PREFIX_0F2E,
1033   PREFIX_0F2F,
1034   PREFIX_0F51,
1035   PREFIX_0F52,
1036   PREFIX_0F53,
1037   PREFIX_0F58,
1038   PREFIX_0F59,
1039   PREFIX_0F5A,
1040   PREFIX_0F5B,
1041   PREFIX_0F5C,
1042   PREFIX_0F5D,
1043   PREFIX_0F5E,
1044   PREFIX_0F5F,
1045   PREFIX_0F60,
1046   PREFIX_0F61,
1047   PREFIX_0F62,
1048   PREFIX_0F6F,
1049   PREFIX_0F70,
1050   PREFIX_0F78,
1051   PREFIX_0F79,
1052   PREFIX_0F7C,
1053   PREFIX_0F7D,
1054   PREFIX_0F7E,
1055   PREFIX_0F7F,
1056   PREFIX_0FA6_REG_0,
1057   PREFIX_0FA6_REG_5,
1058   PREFIX_0FA7_REG_6,
1059   PREFIX_0FAE_REG_0_MOD_3,
1060   PREFIX_0FAE_REG_1_MOD_3,
1061   PREFIX_0FAE_REG_2_MOD_3,
1062   PREFIX_0FAE_REG_3_MOD_3,
1063   PREFIX_0FAE_REG_4_MOD_0,
1064   PREFIX_0FAE_REG_4_MOD_3,
1065   PREFIX_0FAE_REG_5_MOD_3,
1066   PREFIX_0FAE_REG_6_MOD_0,
1067   PREFIX_0FAE_REG_6_MOD_3,
1068   PREFIX_0FAE_REG_7_MOD_0,
1069   PREFIX_0FB8,
1070   PREFIX_0FBC,
1071   PREFIX_0FBD,
1072   PREFIX_0FC2,
1073   PREFIX_0FC7_REG_6_MOD_0,
1074   PREFIX_0FC7_REG_6_MOD_3,
1075   PREFIX_0FC7_REG_7_MOD_3,
1076   PREFIX_0FD0,
1077   PREFIX_0FD6,
1078   PREFIX_0FE6,
1079   PREFIX_0FE7,
1080   PREFIX_0FF0,
1081   PREFIX_0FF7,
1082   PREFIX_0F38D8,
1083   PREFIX_0F38DC,
1084   PREFIX_0F38DD,
1085   PREFIX_0F38DE,
1086   PREFIX_0F38DF,
1087   PREFIX_0F38F0,
1088   PREFIX_0F38F1,
1089   PREFIX_0F38F6,
1090   PREFIX_0F38F8_M_0,
1091   PREFIX_0F38F8_M_1_X86_64,
1092   PREFIX_0F38FA,
1093   PREFIX_0F38FB,
1094   PREFIX_0F38FC,
1095   PREFIX_0F3A0F,
1096   PREFIX_VEX_0F12,
1097   PREFIX_VEX_0F16,
1098   PREFIX_VEX_0F2A,
1099   PREFIX_VEX_0F2C,
1100   PREFIX_VEX_0F2D,
1101   PREFIX_VEX_0F41_L_1_W_0,
1102   PREFIX_VEX_0F41_L_1_W_1,
1103   PREFIX_VEX_0F42_L_1_W_0,
1104   PREFIX_VEX_0F42_L_1_W_1,
1105   PREFIX_VEX_0F44_L_0_W_0,
1106   PREFIX_VEX_0F44_L_0_W_1,
1107   PREFIX_VEX_0F45_L_1_W_0,
1108   PREFIX_VEX_0F45_L_1_W_1,
1109   PREFIX_VEX_0F46_L_1_W_0,
1110   PREFIX_VEX_0F46_L_1_W_1,
1111   PREFIX_VEX_0F47_L_1_W_0,
1112   PREFIX_VEX_0F47_L_1_W_1,
1113   PREFIX_VEX_0F4A_L_1_W_0,
1114   PREFIX_VEX_0F4A_L_1_W_1,
1115   PREFIX_VEX_0F4B_L_1_W_0,
1116   PREFIX_VEX_0F4B_L_1_W_1,
1117   PREFIX_VEX_0F6F,
1118   PREFIX_VEX_0F70,
1119   PREFIX_VEX_0F7E,
1120   PREFIX_VEX_0F7F,
1121   PREFIX_VEX_0F90_L_0_W_0,
1122   PREFIX_VEX_0F90_L_0_W_1,
1123   PREFIX_VEX_0F91_L_0_W_0,
1124   PREFIX_VEX_0F91_L_0_W_1,
1125   PREFIX_VEX_0F92_L_0_W_0,
1126   PREFIX_VEX_0F92_L_0_W_1,
1127   PREFIX_VEX_0F93_L_0_W_0,
1128   PREFIX_VEX_0F93_L_0_W_1,
1129   PREFIX_VEX_0F98_L_0_W_0,
1130   PREFIX_VEX_0F98_L_0_W_1,
1131   PREFIX_VEX_0F99_L_0_W_0,
1132   PREFIX_VEX_0F99_L_0_W_1,
1133   PREFIX_VEX_0F3848_X86_64_L_0_W_0,
1134   PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0,
1135   PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1,
1136   PREFIX_VEX_0F384A_X86_64_W_0_L_0,
1137   PREFIX_VEX_0F384B_X86_64_L_0_W_0,
1138   PREFIX_VEX_0F3850_W_0,
1139   PREFIX_VEX_0F3851_W_0,
1140   PREFIX_VEX_0F385C_X86_64_L_0_W_0,
1141   PREFIX_VEX_0F385E_X86_64_L_0_W_0,
1142   PREFIX_VEX_0F385F_X86_64_L_0_W_0,
1143   PREFIX_VEX_0F386B_X86_64_L_0_W_0,
1144   PREFIX_VEX_0F386C_X86_64_L_0_W_0,
1145   PREFIX_VEX_0F386E_X86_64_L_0_W_0,
1146   PREFIX_VEX_0F386F_X86_64_L_0_W_0,
1147   PREFIX_VEX_0F3872,
1148   PREFIX_VEX_0F38B0_W_0,
1149   PREFIX_VEX_0F38B1_W_0,
1150   PREFIX_VEX_0F38D2_W_0,
1151   PREFIX_VEX_0F38D3_W_0,
1152   PREFIX_VEX_0F38CB,
1153   PREFIX_VEX_0F38CC,
1154   PREFIX_VEX_0F38CD,
1155   PREFIX_VEX_0F38DA_W_0,
1156   PREFIX_VEX_0F38F2_L_0,
1157   PREFIX_VEX_0F38F3_L_0,
1158   PREFIX_VEX_0F38F5_L_0,
1159   PREFIX_VEX_0F38F6_L_0,
1160   PREFIX_VEX_0F38F7_L_0,
1161   PREFIX_VEX_0F3AF0_L_0,
1162   PREFIX_VEX_MAP5_F8_X86_64_L_0_W_0,
1163   PREFIX_VEX_MAP5_F9_X86_64_L_0_W_0,
1164   PREFIX_VEX_MAP5_FD_X86_64_L_0_W_0,
1165   PREFIX_VEX_MAP7_F6_L_0_W_0_R_0_X86_64,
1166   PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64,
1167
1168   PREFIX_EVEX_0F2E,
1169   PREFIX_EVEX_0F2F,
1170   PREFIX_EVEX_0F5B,
1171   PREFIX_EVEX_0F6F,
1172   PREFIX_EVEX_0F70,
1173   PREFIX_EVEX_0F78,
1174   PREFIX_EVEX_0F79,
1175   PREFIX_EVEX_0F7A,
1176   PREFIX_EVEX_0F7B,
1177   PREFIX_EVEX_0F7E,
1178   PREFIX_EVEX_0F7F,
1179   PREFIX_EVEX_0FC2,
1180   PREFIX_EVEX_0FE6,
1181   PREFIX_EVEX_0F3810,
1182   PREFIX_EVEX_0F3811,
1183   PREFIX_EVEX_0F3812,
1184   PREFIX_EVEX_0F3813,
1185   PREFIX_EVEX_0F3814,
1186   PREFIX_EVEX_0F3815,
1187   PREFIX_EVEX_0F3820,
1188   PREFIX_EVEX_0F3821,
1189   PREFIX_EVEX_0F3822,
1190   PREFIX_EVEX_0F3823,
1191   PREFIX_EVEX_0F3824,
1192   PREFIX_EVEX_0F3825,
1193   PREFIX_EVEX_0F3826,
1194   PREFIX_EVEX_0F3827,
1195   PREFIX_EVEX_0F3828,
1196   PREFIX_EVEX_0F3829,
1197   PREFIX_EVEX_0F382A,
1198   PREFIX_EVEX_0F3830,
1199   PREFIX_EVEX_0F3831,
1200   PREFIX_EVEX_0F3832,
1201   PREFIX_EVEX_0F3833,
1202   PREFIX_EVEX_0F3834,
1203   PREFIX_EVEX_0F3835,
1204   PREFIX_EVEX_0F3838,
1205   PREFIX_EVEX_0F3839,
1206   PREFIX_EVEX_0F383A,
1207   PREFIX_EVEX_0F384A_X86_64_W_0_L_2,
1208   PREFIX_EVEX_0F3852,
1209   PREFIX_EVEX_0F3853,
1210   PREFIX_EVEX_0F3868,
1211   PREFIX_EVEX_0F386D_X86_64_W_0_L_2,
1212   PREFIX_EVEX_0F3872,
1213   PREFIX_EVEX_0F3874,
1214   PREFIX_EVEX_0F389A,
1215   PREFIX_EVEX_0F389B,
1216   PREFIX_EVEX_0F38AA,
1217   PREFIX_EVEX_0F38AB,
1218
1219   PREFIX_EVEX_0F3A07_X86_64_W_0_L_2,
1220   PREFIX_EVEX_0F3A08,
1221   PREFIX_EVEX_0F3A0A,
1222   PREFIX_EVEX_0F3A26,
1223   PREFIX_EVEX_0F3A27,
1224   PREFIX_EVEX_0F3A42_W_0,
1225   PREFIX_EVEX_0F3A52,
1226   PREFIX_EVEX_0F3A53,
1227   PREFIX_EVEX_0F3A56,
1228   PREFIX_EVEX_0F3A57,
1229   PREFIX_EVEX_0F3A66,
1230   PREFIX_EVEX_0F3A67,
1231   PREFIX_EVEX_0F3A77_X86_64_W_0_L_2,
1232   PREFIX_EVEX_0F3AC2,
1233
1234   PREFIX_EVEX_MAP4_4x,
1235   PREFIX_EVEX_MAP4_F0,
1236   PREFIX_EVEX_MAP4_F1,
1237   PREFIX_EVEX_MAP4_F2,
1238   PREFIX_EVEX_MAP4_F8,
1239
1240   PREFIX_EVEX_MAP5_10,
1241   PREFIX_EVEX_MAP5_11,
1242   PREFIX_EVEX_MAP5_18,
1243   PREFIX_EVEX_MAP5_1B,
1244   PREFIX_EVEX_MAP5_1D,
1245   PREFIX_EVEX_MAP5_1E,
1246   PREFIX_EVEX_MAP5_2A,
1247   PREFIX_EVEX_MAP5_2C,
1248   PREFIX_EVEX_MAP5_2D,
1249   PREFIX_EVEX_MAP5_2E,
1250   PREFIX_EVEX_MAP5_2F,
1251   PREFIX_EVEX_MAP5_51,
1252   PREFIX_EVEX_MAP5_58,
1253   PREFIX_EVEX_MAP5_59,
1254   PREFIX_EVEX_MAP5_5A,
1255   PREFIX_EVEX_MAP5_5B,
1256   PREFIX_EVEX_MAP5_5C,
1257   PREFIX_EVEX_MAP5_5D,
1258   PREFIX_EVEX_MAP5_5E,
1259   PREFIX_EVEX_MAP5_5F,
1260   PREFIX_EVEX_MAP5_68,
1261   PREFIX_EVEX_MAP5_69,
1262   PREFIX_EVEX_MAP5_6A,
1263   PREFIX_EVEX_MAP5_6B,
1264   PREFIX_EVEX_MAP5_6C,
1265   PREFIX_EVEX_MAP5_6D,
1266   PREFIX_EVEX_MAP5_6E_L_0,
1267   PREFIX_EVEX_MAP5_6F_X86_64,
1268   PREFIX_EVEX_MAP5_74,
1269   PREFIX_EVEX_MAP5_78,
1270   PREFIX_EVEX_MAP5_79,
1271   PREFIX_EVEX_MAP5_7A,
1272   PREFIX_EVEX_MAP5_7B,
1273   PREFIX_EVEX_MAP5_7C,
1274   PREFIX_EVEX_MAP5_7D,
1275   PREFIX_EVEX_MAP5_7E_L_0,
1276
1277   PREFIX_EVEX_MAP6_13,
1278   PREFIX_EVEX_MAP6_2C,
1279   PREFIX_EVEX_MAP6_42,
1280   PREFIX_EVEX_MAP6_4C,
1281   PREFIX_EVEX_MAP6_4E,
1282   PREFIX_EVEX_MAP6_56,
1283   PREFIX_EVEX_MAP6_57,
1284   PREFIX_EVEX_MAP6_98,
1285   PREFIX_EVEX_MAP6_9A,
1286   PREFIX_EVEX_MAP6_9C,
1287   PREFIX_EVEX_MAP6_9E,
1288   PREFIX_EVEX_MAP6_A8,
1289   PREFIX_EVEX_MAP6_AA,
1290   PREFIX_EVEX_MAP6_AC,
1291   PREFIX_EVEX_MAP6_AE,
1292   PREFIX_EVEX_MAP6_B8,
1293   PREFIX_EVEX_MAP6_BA,
1294   PREFIX_EVEX_MAP6_BC,
1295   PREFIX_EVEX_MAP6_BE,
1296   PREFIX_EVEX_MAP6_D6,
1297   PREFIX_EVEX_MAP6_D7,
1298 };
1299
1300 enum
1301 {
1302   X86_64_06 = 0,
1303   X86_64_07,
1304   X86_64_0E,
1305   X86_64_16,
1306   X86_64_17,
1307   X86_64_1E,
1308   X86_64_1F,
1309   X86_64_27,
1310   X86_64_2F,
1311   X86_64_37,
1312   X86_64_3F,
1313   X86_64_60,
1314   X86_64_61,
1315   X86_64_62,
1316   X86_64_63,
1317   X86_64_6D,
1318   X86_64_6F,
1319   X86_64_82,
1320   X86_64_9A,
1321   X86_64_C2,
1322   X86_64_C3,
1323   X86_64_C4,
1324   X86_64_C5,
1325   X86_64_CE,
1326   X86_64_D4,
1327   X86_64_D5,
1328   X86_64_E8,
1329   X86_64_E9,
1330   X86_64_EA,
1331   X86_64_0F00_REG_6,
1332   X86_64_0F01_REG_0,
1333   X86_64_0F01_REG_0_MOD_3_RM_6_P_1,
1334   X86_64_0F01_REG_0_MOD_3_RM_6_P_3,
1335   X86_64_0F01_REG_0_MOD_3_RM_7_P_0,
1336   X86_64_0F01_REG_1,
1337   X86_64_0F01_REG_1_RM_2_PREFIX_1,
1338   X86_64_0F01_REG_1_RM_2_PREFIX_3,
1339   X86_64_0F01_REG_1_RM_5_PREFIX_2,
1340   X86_64_0F01_REG_1_RM_6_PREFIX_2,
1341   X86_64_0F01_REG_1_RM_7_PREFIX_2,
1342   X86_64_0F01_REG_2,
1343   X86_64_0F01_REG_3,
1344   X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
1345   X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
1346   X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
1347   X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
1348   X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1,
1349   X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1,
1350   X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3,
1351   X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1,
1352   X86_64_0F18_REG_6_MOD_0,
1353   X86_64_0F18_REG_7_MOD_0,
1354   X86_64_0F24,
1355   X86_64_0F26,
1356   X86_64_0F388A,
1357   X86_64_0F388B,
1358   X86_64_0F38F8_M_1,
1359   X86_64_0FC7_REG_6_MOD_3_PREFIX_1,
1360
1361   X86_64_VEX_0F3848,
1362   X86_64_VEX_0F3849,
1363   X86_64_VEX_0F384A,
1364   X86_64_VEX_0F384B,
1365   X86_64_VEX_0F385C,
1366   X86_64_VEX_0F385E,
1367   X86_64_VEX_0F385F,
1368   X86_64_VEX_0F386B,
1369   X86_64_VEX_0F386C,
1370   X86_64_VEX_0F386E,
1371   X86_64_VEX_0F386F,
1372   X86_64_VEX_0F38Ex,
1373
1374   X86_64_VEX_MAP5_F8,
1375   X86_64_VEX_MAP5_F9,
1376   X86_64_VEX_MAP5_FD,
1377   X86_64_VEX_MAP7_F6_L_0_W_0_R_0,
1378   X86_64_VEX_MAP7_F8_L_0_W_0_R_0,
1379
1380   X86_64_EVEX_0F384A,
1381   X86_64_EVEX_0F386D,
1382   X86_64_EVEX_0F3A07,
1383   X86_64_EVEX_0F3A77,
1384
1385   X86_64_EVEX_MAP5_6F,
1386 };
1387
1388 enum
1389 {
1390   THREE_BYTE_0F38 = 0,
1391   THREE_BYTE_0F3A
1392 };
1393
1394 enum
1395 {
1396   XOP_08 = 0,
1397   XOP_09,
1398   XOP_0A
1399 };
1400
1401 enum
1402 {
1403   VEX_0F = 0,
1404   VEX_0F38,
1405   VEX_0F3A,
1406   VEX_MAP5,
1407   VEX_MAP7,
1408 };
1409
1410 enum
1411 {
1412   EVEX_0F = 0,
1413   EVEX_0F38,
1414   EVEX_0F3A,
1415   EVEX_MAP4,
1416   EVEX_MAP5,
1417   EVEX_MAP6,
1418   EVEX_MAP7,
1419 };
1420
1421 enum
1422 {
1423   VEX_LEN_0F12_P_0 = 0,
1424   VEX_LEN_0F12_P_2,
1425   VEX_LEN_0F13,
1426   VEX_LEN_0F16_P_0,
1427   VEX_LEN_0F16_P_2,
1428   VEX_LEN_0F17,
1429   VEX_LEN_0F41,
1430   VEX_LEN_0F42,
1431   VEX_LEN_0F44,
1432   VEX_LEN_0F45,
1433   VEX_LEN_0F46,
1434   VEX_LEN_0F47,
1435   VEX_LEN_0F4A,
1436   VEX_LEN_0F4B,
1437   VEX_LEN_0F6E,
1438   VEX_LEN_0F77,
1439   VEX_LEN_0F7E_P_1,
1440   VEX_LEN_0F7E_P_2,
1441   VEX_LEN_0F90,
1442   VEX_LEN_0F91,
1443   VEX_LEN_0F92,
1444   VEX_LEN_0F93,
1445   VEX_LEN_0F98,
1446   VEX_LEN_0F99,
1447   VEX_LEN_0FAE_R_2,
1448   VEX_LEN_0FAE_R_3,
1449   VEX_LEN_0FC4,
1450   VEX_LEN_0FD6,
1451   VEX_LEN_0F3816,
1452   VEX_LEN_0F3819,
1453   VEX_LEN_0F381A,
1454   VEX_LEN_0F3836,
1455   VEX_LEN_0F3841,
1456   VEX_LEN_0F3848_X86_64,
1457   VEX_LEN_0F3849_X86_64,
1458   VEX_LEN_0F384A_X86_64_W_0,
1459   VEX_LEN_0F384B_X86_64,
1460   VEX_LEN_0F385A,
1461   VEX_LEN_0F385C_X86_64,
1462   VEX_LEN_0F385E_X86_64,
1463   VEX_LEN_0F385F_X86_64,
1464   VEX_LEN_0F386B_X86_64,
1465   VEX_LEN_0F386C_X86_64,
1466   VEX_LEN_0F386E_X86_64,
1467   VEX_LEN_0F386F_X86_64,
1468   VEX_LEN_0F38CB_P_3_W_0,
1469   VEX_LEN_0F38CC_P_3_W_0,
1470   VEX_LEN_0F38CD_P_3_W_0,
1471   VEX_LEN_0F38DA_W_0_P_0,
1472   VEX_LEN_0F38DA_W_0_P_2,
1473   VEX_LEN_0F38DB,
1474   VEX_LEN_0F38F2,
1475   VEX_LEN_0F38F3,
1476   VEX_LEN_0F38F5,
1477   VEX_LEN_0F38F6,
1478   VEX_LEN_0F38F7,
1479   VEX_LEN_0F3A00,
1480   VEX_LEN_0F3A01,
1481   VEX_LEN_0F3A06,
1482   VEX_LEN_0F3A14,
1483   VEX_LEN_0F3A15,
1484   VEX_LEN_0F3A16,
1485   VEX_LEN_0F3A17,
1486   VEX_LEN_0F3A18,
1487   VEX_LEN_0F3A19,
1488   VEX_LEN_0F3A20,
1489   VEX_LEN_0F3A21,
1490   VEX_LEN_0F3A22,
1491   VEX_LEN_0F3A30,
1492   VEX_LEN_0F3A31,
1493   VEX_LEN_0F3A32,
1494   VEX_LEN_0F3A33,
1495   VEX_LEN_0F3A38,
1496   VEX_LEN_0F3A39,
1497   VEX_LEN_0F3A41,
1498   VEX_LEN_0F3A46,
1499   VEX_LEN_0F3A60,
1500   VEX_LEN_0F3A61,
1501   VEX_LEN_0F3A62,
1502   VEX_LEN_0F3A63,
1503   VEX_LEN_0F3ADE_W_0,
1504   VEX_LEN_0F3ADF,
1505   VEX_LEN_0F3AF0,
1506   VEX_LEN_MAP5_F8_X86_64,
1507   VEX_LEN_MAP5_F9_X86_64,
1508   VEX_LEN_MAP5_FD_X86_64,
1509   VEX_LEN_MAP7_F6,
1510   VEX_LEN_MAP7_F8,
1511   VEX_LEN_XOP_08_85,
1512   VEX_LEN_XOP_08_86,
1513   VEX_LEN_XOP_08_87,
1514   VEX_LEN_XOP_08_8E,
1515   VEX_LEN_XOP_08_8F,
1516   VEX_LEN_XOP_08_95,
1517   VEX_LEN_XOP_08_96,
1518   VEX_LEN_XOP_08_97,
1519   VEX_LEN_XOP_08_9E,
1520   VEX_LEN_XOP_08_9F,
1521   VEX_LEN_XOP_08_A3,
1522   VEX_LEN_XOP_08_A6,
1523   VEX_LEN_XOP_08_B6,
1524   VEX_LEN_XOP_08_C0,
1525   VEX_LEN_XOP_08_C1,
1526   VEX_LEN_XOP_08_C2,
1527   VEX_LEN_XOP_08_C3,
1528   VEX_LEN_XOP_08_CC,
1529   VEX_LEN_XOP_08_CD,
1530   VEX_LEN_XOP_08_CE,
1531   VEX_LEN_XOP_08_CF,
1532   VEX_LEN_XOP_08_EC,
1533   VEX_LEN_XOP_08_ED,
1534   VEX_LEN_XOP_08_EE,
1535   VEX_LEN_XOP_08_EF,
1536   VEX_LEN_XOP_09_01,
1537   VEX_LEN_XOP_09_02,
1538   VEX_LEN_XOP_09_12,
1539   VEX_LEN_XOP_09_82_W_0,
1540   VEX_LEN_XOP_09_83_W_0,
1541   VEX_LEN_XOP_09_90,
1542   VEX_LEN_XOP_09_91,
1543   VEX_LEN_XOP_09_92,
1544   VEX_LEN_XOP_09_93,
1545   VEX_LEN_XOP_09_94,
1546   VEX_LEN_XOP_09_95,
1547   VEX_LEN_XOP_09_96,
1548   VEX_LEN_XOP_09_97,
1549   VEX_LEN_XOP_09_98,
1550   VEX_LEN_XOP_09_99,
1551   VEX_LEN_XOP_09_9A,
1552   VEX_LEN_XOP_09_9B,
1553   VEX_LEN_XOP_09_C1,
1554   VEX_LEN_XOP_09_C2,
1555   VEX_LEN_XOP_09_C3,
1556   VEX_LEN_XOP_09_C6,
1557   VEX_LEN_XOP_09_C7,
1558   VEX_LEN_XOP_09_CB,
1559   VEX_LEN_XOP_09_D1,
1560   VEX_LEN_XOP_09_D2,
1561   VEX_LEN_XOP_09_D3,
1562   VEX_LEN_XOP_09_D6,
1563   VEX_LEN_XOP_09_D7,
1564   VEX_LEN_XOP_09_DB,
1565   VEX_LEN_XOP_09_E1,
1566   VEX_LEN_XOP_09_E2,
1567   VEX_LEN_XOP_09_E3,
1568   VEX_LEN_XOP_0A_12,
1569 };
1570
1571 enum
1572 {
1573   EVEX_LEN_0F7E_P_1_W_0 = 0,
1574   EVEX_LEN_0FD6_P_2_W_0,
1575   EVEX_LEN_0F3816,
1576   EVEX_LEN_0F3819,
1577   EVEX_LEN_0F381A,
1578   EVEX_LEN_0F381B,
1579   EVEX_LEN_0F3836,
1580   EVEX_LEN_0F384A_X86_64_W_0,
1581   EVEX_LEN_0F385A,
1582   EVEX_LEN_0F385B,
1583   EVEX_LEN_0F386D_X86_64_W_0,
1584   EVEX_LEN_0F38C6,
1585   EVEX_LEN_0F38C7,
1586   EVEX_LEN_0F3A00,
1587   EVEX_LEN_0F3A01,
1588   EVEX_LEN_0F3A07_X86_64_W_0,
1589   EVEX_LEN_0F3A18,
1590   EVEX_LEN_0F3A19,
1591   EVEX_LEN_0F3A1A,
1592   EVEX_LEN_0F3A1B,
1593   EVEX_LEN_0F3A23,
1594   EVEX_LEN_0F3A38,
1595   EVEX_LEN_0F3A39,
1596   EVEX_LEN_0F3A3A,
1597   EVEX_LEN_0F3A3B,
1598   EVEX_LEN_0F3A43,
1599   EVEX_LEN_0F3A77_X86_64_W_0,
1600
1601   EVEX_LEN_MAP5_6E,
1602   EVEX_LEN_MAP5_7E,
1603 };
1604
1605 enum
1606 {
1607   VEX_W_0F41_L_1 = 0,
1608   VEX_W_0F42_L_1,
1609   VEX_W_0F44_L_0,
1610   VEX_W_0F45_L_1,
1611   VEX_W_0F46_L_1,
1612   VEX_W_0F47_L_1,
1613   VEX_W_0F4A_L_1,
1614   VEX_W_0F4B_L_1,
1615   VEX_W_0F90_L_0,
1616   VEX_W_0F91_L_0,
1617   VEX_W_0F92_L_0,
1618   VEX_W_0F93_L_0,
1619   VEX_W_0F98_L_0,
1620   VEX_W_0F99_L_0,
1621   VEX_W_0F380C,
1622   VEX_W_0F380D,
1623   VEX_W_0F380E,
1624   VEX_W_0F380F,
1625   VEX_W_0F3813,
1626   VEX_W_0F3816_L_1,
1627   VEX_W_0F3818,
1628   VEX_W_0F3819_L_1,
1629   VEX_W_0F381A_L_1,
1630   VEX_W_0F382C,
1631   VEX_W_0F382D,
1632   VEX_W_0F382E,
1633   VEX_W_0F382F,
1634   VEX_W_0F3836,
1635   VEX_W_0F3846,
1636   VEX_W_0F3848_X86_64_L_0,
1637   VEX_W_0F3849_X86_64_L_0,
1638   VEX_W_0F384A_X86_64,
1639   VEX_W_0F384B_X86_64_L_0,
1640   VEX_W_0F3850,
1641   VEX_W_0F3851,
1642   VEX_W_0F3852,
1643   VEX_W_0F3853,
1644   VEX_W_0F3858,
1645   VEX_W_0F3859,
1646   VEX_W_0F385A_L_0,
1647   VEX_W_0F385C_X86_64_L_0,
1648   VEX_W_0F385E_X86_64_L_0,
1649   VEX_W_0F385F_X86_64_L_0,
1650   VEX_W_0F386B_X86_64_L_0,
1651   VEX_W_0F386C_X86_64_L_0,
1652   VEX_W_0F386E_X86_64_L_0,
1653   VEX_W_0F386F_X86_64_L_0,
1654   VEX_W_0F3872_P_1,
1655   VEX_W_0F3878,
1656   VEX_W_0F3879,
1657   VEX_W_0F38B0,
1658   VEX_W_0F38B1,
1659   VEX_W_0F38B4,
1660   VEX_W_0F38B5,
1661   VEX_W_0F38CB_P_3,
1662   VEX_W_0F38CC_P_3,
1663   VEX_W_0F38CD_P_3,
1664   VEX_W_0F38CF,
1665   VEX_W_0F38D2,
1666   VEX_W_0F38D3,
1667   VEX_W_0F38DA,
1668   VEX_W_0F3A00_L_1,
1669   VEX_W_0F3A01_L_1,
1670   VEX_W_0F3A02,
1671   VEX_W_0F3A04,
1672   VEX_W_0F3A05,
1673   VEX_W_0F3A06_L_1,
1674   VEX_W_0F3A18_L_1,
1675   VEX_W_0F3A19_L_1,
1676   VEX_W_0F3A1D,
1677   VEX_W_0F3A38_L_1,
1678   VEX_W_0F3A39_L_1,
1679   VEX_W_0F3A46_L_1,
1680   VEX_W_0F3A4A,
1681   VEX_W_0F3A4B,
1682   VEX_W_0F3A4C,
1683   VEX_W_0F3ACE,
1684   VEX_W_0F3ACF,
1685   VEX_W_0F3ADE,
1686   VEX_W_MAP5_F8_X86_64_L_0,
1687   VEX_W_MAP5_F9_X86_64_L_0,
1688   VEX_W_MAP5_FD_X86_64_L_0,
1689   VEX_W_MAP7_F6_L_0,
1690   VEX_W_MAP7_F8_L_0,
1691
1692   VEX_W_XOP_08_85_L_0,
1693   VEX_W_XOP_08_86_L_0,
1694   VEX_W_XOP_08_87_L_0,
1695   VEX_W_XOP_08_8E_L_0,
1696   VEX_W_XOP_08_8F_L_0,
1697   VEX_W_XOP_08_95_L_0,
1698   VEX_W_XOP_08_96_L_0,
1699   VEX_W_XOP_08_97_L_0,
1700   VEX_W_XOP_08_9E_L_0,
1701   VEX_W_XOP_08_9F_L_0,
1702   VEX_W_XOP_08_A6_L_0,
1703   VEX_W_XOP_08_B6_L_0,
1704   VEX_W_XOP_08_C0_L_0,
1705   VEX_W_XOP_08_C1_L_0,
1706   VEX_W_XOP_08_C2_L_0,
1707   VEX_W_XOP_08_C3_L_0,
1708   VEX_W_XOP_08_CC_L_0,
1709   VEX_W_XOP_08_CD_L_0,
1710   VEX_W_XOP_08_CE_L_0,
1711   VEX_W_XOP_08_CF_L_0,
1712   VEX_W_XOP_08_EC_L_0,
1713   VEX_W_XOP_08_ED_L_0,
1714   VEX_W_XOP_08_EE_L_0,
1715   VEX_W_XOP_08_EF_L_0,
1716
1717   VEX_W_XOP_09_80,
1718   VEX_W_XOP_09_81,
1719   VEX_W_XOP_09_82,
1720   VEX_W_XOP_09_83,
1721   VEX_W_XOP_09_C1_L_0,
1722   VEX_W_XOP_09_C2_L_0,
1723   VEX_W_XOP_09_C3_L_0,
1724   VEX_W_XOP_09_C6_L_0,
1725   VEX_W_XOP_09_C7_L_0,
1726   VEX_W_XOP_09_CB_L_0,
1727   VEX_W_XOP_09_D1_L_0,
1728   VEX_W_XOP_09_D2_L_0,
1729   VEX_W_XOP_09_D3_L_0,
1730   VEX_W_XOP_09_D6_L_0,
1731   VEX_W_XOP_09_D7_L_0,
1732   VEX_W_XOP_09_DB_L_0,
1733   VEX_W_XOP_09_E1_L_0,
1734   VEX_W_XOP_09_E2_L_0,
1735   VEX_W_XOP_09_E3_L_0,
1736
1737   EVEX_W_0F5B_P_0,
1738   EVEX_W_0F62,
1739   EVEX_W_0F66,
1740   EVEX_W_0F6A,
1741   EVEX_W_0F6B,
1742   EVEX_W_0F6C,
1743   EVEX_W_0F6D,
1744   EVEX_W_0F6F_P_1,
1745   EVEX_W_0F6F_P_2,
1746   EVEX_W_0F6F_P_3,
1747   EVEX_W_0F70_P_2,
1748   EVEX_W_0F72_R_2,
1749   EVEX_W_0F72_R_4,
1750   EVEX_W_0F72_R_6,
1751   EVEX_W_0F73_R_2,
1752   EVEX_W_0F73_R_6,
1753   EVEX_W_0F76,
1754   EVEX_W_0F78_P_0,
1755   EVEX_W_0F78_P_2,
1756   EVEX_W_0F79_P_0,
1757   EVEX_W_0F79_P_2,
1758   EVEX_W_0F7A_P_1,
1759   EVEX_W_0F7A_P_2,
1760   EVEX_W_0F7A_P_3,
1761   EVEX_W_0F7B_P_2,
1762   EVEX_W_0F7E_P_1,
1763   EVEX_W_0F7F_P_1,
1764   EVEX_W_0F7F_P_2,
1765   EVEX_W_0F7F_P_3,
1766   EVEX_W_0FD2,
1767   EVEX_W_0FD3,
1768   EVEX_W_0FD4,
1769   EVEX_W_0FD6,
1770   EVEX_W_0FE2,
1771   EVEX_W_0FE6_P_1,
1772   EVEX_W_0FE7,
1773   EVEX_W_0FF2,
1774   EVEX_W_0FF3,
1775   EVEX_W_0FF4,
1776   EVEX_W_0FFA,
1777   EVEX_W_0FFB,
1778   EVEX_W_0FFE,
1779
1780   EVEX_W_0F3810_P_1,
1781   EVEX_W_0F3810_P_2,
1782   EVEX_W_0F3811_P_1,
1783   EVEX_W_0F3811_P_2,
1784   EVEX_W_0F3812_P_1,
1785   EVEX_W_0F3812_P_2,
1786   EVEX_W_0F3813_P_1,
1787   EVEX_W_0F3814_P_1,
1788   EVEX_W_0F3815_P_1,
1789   EVEX_W_0F3819_L_n,
1790   EVEX_W_0F381A_L_n,
1791   EVEX_W_0F381B_L_2,
1792   EVEX_W_0F381E,
1793   EVEX_W_0F381F,
1794   EVEX_W_0F3820_P_1,
1795   EVEX_W_0F3821_P_1,
1796   EVEX_W_0F3822_P_1,
1797   EVEX_W_0F3823_P_1,
1798   EVEX_W_0F3824_P_1,
1799   EVEX_W_0F3825_P_1,
1800   EVEX_W_0F3825_P_2,
1801   EVEX_W_0F3828_P_2,
1802   EVEX_W_0F3829_P_2,
1803   EVEX_W_0F382A_P_1,
1804   EVEX_W_0F382A_P_2,
1805   EVEX_W_0F382B,
1806   EVEX_W_0F3830_P_1,
1807   EVEX_W_0F3831_P_1,
1808   EVEX_W_0F3832_P_1,
1809   EVEX_W_0F3833_P_1,
1810   EVEX_W_0F3834_P_1,
1811   EVEX_W_0F3835_P_1,
1812   EVEX_W_0F3835_P_2,
1813   EVEX_W_0F3837,
1814   EVEX_W_0F383A_P_1,
1815   EVEX_W_0F384A_X86_64,
1816   EVEX_W_0F3859,
1817   EVEX_W_0F385A_L_n,
1818   EVEX_W_0F385B_L_2,
1819   EVEX_W_0F386D_X86_64,
1820   EVEX_W_0F3870,
1821   EVEX_W_0F3872_P_2,
1822   EVEX_W_0F387A,
1823   EVEX_W_0F387B,
1824   EVEX_W_0F3883,
1825
1826   EVEX_W_0F3A07_X86_64,
1827   EVEX_W_0F3A18_L_n,
1828   EVEX_W_0F3A19_L_n,
1829   EVEX_W_0F3A1A_L_2,
1830   EVEX_W_0F3A1B_L_2,
1831   EVEX_W_0F3A21,
1832   EVEX_W_0F3A23_L_n,
1833   EVEX_W_0F3A38_L_n,
1834   EVEX_W_0F3A39_L_n,
1835   EVEX_W_0F3A3A_L_2,
1836   EVEX_W_0F3A3B_L_2,
1837   EVEX_W_0F3A42,
1838   EVEX_W_0F3A43_L_n,
1839   EVEX_W_0F3A70,
1840   EVEX_W_0F3A72,
1841   EVEX_W_0F3A77_X86_64,
1842
1843   EVEX_W_MAP4_8F_R_0,
1844   EVEX_W_MAP4_F8_P1_M_1,
1845   EVEX_W_MAP4_F8_P3_M_1,
1846   EVEX_W_MAP4_FF_R_6,
1847
1848   EVEX_W_MAP5_5B_P_0,
1849   EVEX_W_MAP5_6C_P_0,
1850   EVEX_W_MAP5_6C_P_2,
1851   EVEX_W_MAP5_6D_P_0,
1852   EVEX_W_MAP5_6D_P_2,
1853   EVEX_W_MAP5_6E_P_1,
1854   EVEX_W_MAP5_7A_P_3,
1855   EVEX_W_MAP5_7E_P_1,
1856 };
1857
1858 typedef bool (*op_rtn) (instr_info *ins, int bytemode, int sizeflag);
1859
1860 struct dis386 {
1861   const char *name;
1862   struct
1863     {
1864       op_rtn rtn;
1865       int bytemode;
1866     } op[MAX_OPERANDS];
1867   unsigned int prefix_requirement;
1868 };
1869
1870 /* Upper case letters in the instruction names here are macros.
1871    'A' => print 'b' if no (suitable) register operand or suffix_always is true
1872    'B' => print 'b' if suffix_always is true
1873    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1874           size prefix
1875    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1876           suffix_always is true
1877    'E' => print 'e' if 32-bit form of jcxz
1878    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1879    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1880    'H' => print ",pt" or ",pn" branch hint
1881    'I' unused.
1882    'J' unused.
1883    'K' => print 'd' or 'q' if rex prefix is present.
1884    'L' => print 'l' or 'q' if suffix_always is true
1885    'M' => print 'r' if intel_mnemonic is false.
1886    'N' => print 'n' if instruction has no wait "prefix"
1887    'O' => print 'd' or 'o' (or 'q' in Intel mode)
1888    'P' => behave as 'T' except with register operand outside of suffix_always
1889           mode
1890    'Q' => print 'w', 'l' or 'q' if no (suitable) register operand or
1891           suffix_always is true
1892    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1893    'S' => print 'w', 'l' or 'q' if suffix_always is true
1894    'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size
1895           prefix or if suffix_always is true.
1896    'U' unused.
1897    'V' => print 'v' for VEX/EVEX and nothing for legacy encodings.
1898    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1899    'X' => print 's', 'd' depending on data16 prefix (for XMM)
1900    'Y' => no output, mark EVEX.aaa != 0 as bad.
1901    'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true.
1902    '!' => change condition from true to false or from false to true.
1903    '%' => add 1 upper case letter to the macro.
1904    '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
1905           prefix or suffix_always is true (lcall/ljmp).
1906    '@' => in 64bit mode for Intel64 ISA or if instruction
1907           has no operand sizing prefix, print 'q' if suffix_always is true or
1908           nothing otherwise; behave as 'P' in all other cases
1909
1910    2 upper case letter macros:
1911    "CC" => print condition code
1912    "XY" => print 'x' or 'y' if suffix_always is true or no register
1913            operands and no broadcast.
1914    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
1915            register operands and no broadcast.
1916    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1917    "XD" => print 'd' if !EVEX or EVEX.W=1, EVEX.W=0 is not a valid encoding
1918    "XH" => print 'h' if EVEX.W=0, EVEX.W=1 is not a valid encoding (for FP16)
1919    "XB" => print 'bf16' if EVEX.W=0, EVEX.W=1 is not a valid encoding
1920            (for BF16)
1921    "XS" => print 's' if !EVEX or EVEX.W=0, EVEX.W=1 is not a valid encoding
1922    "XV" => print "{vex} " pseudo prefix
1923    "XE" => print "{evex} " pseudo prefix if no EVEX-specific functionality is
1924            is used by an EVEX-encoded (AVX512VL) instruction.
1925    "ME" => Similar to "XE", but only print "{evex} " when there is no
1926            memory operand.
1927    "NF" => print "{nf} " pseudo prefix when EVEX.NF = 1 and print "{evex} "
1928            pseudo prefix when instructions without NF, EGPR and VVVV,
1929    "NE" => don't print "{evex} " pseudo prefix for some special instructions
1930            in MAP4.
1931    "ZU" => print 'zu' if EVEX.ZU=1.
1932    "SC" => print suffix SCC for SCC insns
1933    "YK" keep unused, to avoid ambiguity with the combined use of Y and K.
1934    "YX" keep unused, to avoid ambiguity with the combined use of Y and X.
1935    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
1936            being false, or no operand at all in 64bit mode, or if suffix_always
1937            is true.
1938    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1939    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1940    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1941    "DQ" => print 'd' or 'q' depending on the VEX.W bit
1942    "DF" => print default flag value for SCC insns
1943    "BW" => print 'b' or 'w' depending on the VEX.W bit
1944    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
1945            an operand size prefix, or suffix_always is true.  print
1946            'q' if rex prefix is present.
1947
1948    Many of the above letters print nothing in Intel mode.  See "putop"
1949    for the details.
1950
1951    Braces '{' and '}', and vertical bars '|', indicate alternative
1952    mnemonic strings for AT&T and Intel.  */
1953
1954 static const struct dis386 dis386[] = {
1955   /* 00 */
1956   { "addB",             { Ebh1, Gb }, 0 },
1957   { "addS",             { Evh1, Gv }, 0 },
1958   { "addB",             { Gb, EbS }, 0 },
1959   { "addS",             { Gv, EvS }, 0 },
1960   { "addB",             { AL, Ib }, 0 },
1961   { "addS",             { eAX, Iv }, 0 },
1962   { X86_64_TABLE (X86_64_06) },
1963   { X86_64_TABLE (X86_64_07) },
1964   /* 08 */
1965   { "orB",              { Ebh1, Gb }, 0 },
1966   { "orS",              { Evh1, Gv }, 0 },
1967   { "orB",              { Gb, EbS }, 0 },
1968   { "orS",              { Gv, EvS }, 0 },
1969   { "orB",              { AL, Ib }, 0 },
1970   { "orS",              { eAX, Iv }, 0 },
1971   { X86_64_TABLE (X86_64_0E) },
1972   { Bad_Opcode },       /* 0x0f extended opcode escape */
1973   /* 10 */
1974   { "adcB",             { Ebh1, Gb }, 0 },
1975   { "adcS",             { Evh1, Gv }, 0 },
1976   { "adcB",             { Gb, EbS }, 0 },
1977   { "adcS",             { Gv, EvS }, 0 },
1978   { "adcB",             { AL, Ib }, 0 },
1979   { "adcS",             { eAX, Iv }, 0 },
1980   { X86_64_TABLE (X86_64_16) },
1981   { X86_64_TABLE (X86_64_17) },
1982   /* 18 */
1983   { "sbbB",             { Ebh1, Gb }, 0 },
1984   { "sbbS",             { Evh1, Gv }, 0 },
1985   { "sbbB",             { Gb, EbS }, 0 },
1986   { "sbbS",             { Gv, EvS }, 0 },
1987   { "sbbB",             { AL, Ib }, 0 },
1988   { "sbbS",             { eAX, Iv }, 0 },
1989   { X86_64_TABLE (X86_64_1E) },
1990   { X86_64_TABLE (X86_64_1F) },
1991   /* 20 */
1992   { "andB",             { Ebh1, Gb }, 0 },
1993   { "andS",             { Evh1, Gv }, 0 },
1994   { "andB",             { Gb, EbS }, 0 },
1995   { "andS",             { Gv, EvS }, 0 },
1996   { "andB",             { AL, Ib }, 0 },
1997   { "andS",             { eAX, Iv }, 0 },
1998   { Bad_Opcode },       /* SEG ES prefix */
1999   { X86_64_TABLE (X86_64_27) },
2000   /* 28 */
2001   { "subB",             { Ebh1, Gb }, 0 },
2002   { "subS",             { Evh1, Gv }, 0 },
2003   { "subB",             { Gb, EbS }, 0 },
2004   { "subS",             { Gv, EvS }, 0 },
2005   { "subB",             { AL, Ib }, 0 },
2006   { "subS",             { eAX, Iv }, 0 },
2007   { Bad_Opcode },       /* SEG CS prefix */
2008   { X86_64_TABLE (X86_64_2F) },
2009   /* 30 */
2010   { "xorB",             { Ebh1, Gb }, 0 },
2011   { "xorS",             { Evh1, Gv }, 0 },
2012   { "xorB",             { Gb, EbS }, 0 },
2013   { "xorS",             { Gv, EvS }, 0 },
2014   { "xorB",             { AL, Ib }, 0 },
2015   { "xorS",             { eAX, Iv }, 0 },
2016   { Bad_Opcode },       /* SEG SS prefix */
2017   { X86_64_TABLE (X86_64_37) },
2018   /* 38 */
2019   { "cmpB",             { Eb, Gb }, 0 },
2020   { "cmpS",             { Ev, Gv }, 0 },
2021   { "cmpB",             { Gb, EbS }, 0 },
2022   { "cmpS",             { Gv, EvS }, 0 },
2023   { "cmpB",             { AL, Ib }, 0 },
2024   { "cmpS",             { eAX, Iv }, 0 },
2025   { Bad_Opcode },       /* SEG DS prefix */
2026   { X86_64_TABLE (X86_64_3F) },
2027   /* 40 */
2028   { "inc{S|}",          { RMeAX }, 0 },
2029   { "inc{S|}",          { RMeCX }, 0 },
2030   { "inc{S|}",          { RMeDX }, 0 },
2031   { "inc{S|}",          { RMeBX }, 0 },
2032   { "inc{S|}",          { RMeSP }, 0 },
2033   { "inc{S|}",          { RMeBP }, 0 },
2034   { "inc{S|}",          { RMeSI }, 0 },
2035   { "inc{S|}",          { RMeDI }, 0 },
2036   /* 48 */
2037   { "dec{S|}",          { RMeAX }, 0 },
2038   { "dec{S|}",          { RMeCX }, 0 },
2039   { "dec{S|}",          { RMeDX }, 0 },
2040   { "dec{S|}",          { RMeBX }, 0 },
2041   { "dec{S|}",          { RMeSP }, 0 },
2042   { "dec{S|}",          { RMeBP }, 0 },
2043   { "dec{S|}",          { RMeSI }, 0 },
2044   { "dec{S|}",          { RMeDI }, 0 },
2045   /* 50 */
2046   { "push!P",           { RMrAX }, 0 },
2047   { "push!P",           { RMrCX }, 0 },
2048   { "push!P",           { RMrDX }, 0 },
2049   { "push!P",           { RMrBX }, 0 },
2050   { "push!P",           { RMrSP }, 0 },
2051   { "push!P",           { RMrBP }, 0 },
2052   { "push!P",           { RMrSI }, 0 },
2053   { "push!P",           { RMrDI }, 0 },
2054   /* 58 */
2055   { "pop!P",            { RMrAX }, 0 },
2056   { "pop!P",            { RMrCX }, 0 },
2057   { "pop!P",            { RMrDX }, 0 },
2058   { "pop!P",            { RMrBX }, 0 },
2059   { "pop!P",            { RMrSP }, 0 },
2060   { "pop!P",            { RMrBP }, 0 },
2061   { "pop!P",            { RMrSI }, 0 },
2062   { "pop!P",            { RMrDI }, 0 },
2063   /* 60 */
2064   { X86_64_TABLE (X86_64_60) },
2065   { X86_64_TABLE (X86_64_61) },
2066   { X86_64_TABLE (X86_64_62) },
2067   { X86_64_TABLE (X86_64_63) },
2068   { Bad_Opcode },       /* seg fs */
2069   { Bad_Opcode },       /* seg gs */
2070   { Bad_Opcode },       /* op size prefix */
2071   { Bad_Opcode },       /* adr size prefix */
2072   /* 68 */
2073   { "pushP",            { sIv }, 0 },
2074   { "imulS",            { Gv, Ev, Iv }, 0 },
2075   { "pushP",            { sIbT }, 0 },
2076   { "imulS",            { Gv, Ev, sIb }, 0 },
2077   { "ins{b|}",          { Ybr, indirDX }, 0 },
2078   { X86_64_TABLE (X86_64_6D) },
2079   { "outs{b|}",         { indirDXr, Xb }, 0 },
2080   { X86_64_TABLE (X86_64_6F) },
2081   /* 70 */
2082   { "joH",              { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2083   { "jnoH",             { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2084   { "jbH",              { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2085   { "jaeH",             { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2086   { "jeH",              { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2087   { "jneH",             { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2088   { "jbeH",             { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2089   { "jaH",              { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2090   /* 78 */
2091   { "jsH",              { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2092   { "jnsH",             { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2093   { "jpH",              { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2094   { "jnpH",             { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2095   { "jlH",              { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2096   { "jgeH",             { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2097   { "jleH",             { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2098   { "jgH",              { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2099   /* 80 */
2100   { REG_TABLE (REG_80) },
2101   { REG_TABLE (REG_81) },
2102   { X86_64_TABLE (X86_64_82) },
2103   { REG_TABLE (REG_83) },
2104   { "testB",            { Eb, Gb }, 0 },
2105   { "testS",            { Ev, Gv }, 0 },
2106   { "xchgB",            { Ebh2, Gb }, 0 },
2107   { "xchgS",            { Evh2, Gv }, 0 },
2108   /* 88 */
2109   { "movB",             { Ebh3, Gb }, 0 },
2110   { "movS",             { Evh3, Gv }, 0 },
2111   { "movB",             { Gb, EbS }, 0 },
2112   { "movS",             { Gv, EvS }, 0 },
2113   { "movD",             { Sv, Sw }, 0 },
2114   { "leaS",             { Gv, M }, 0 },
2115   { "movD",             { Sw, Sv }, 0 },
2116   { REG_TABLE (REG_8F) },
2117   /* 90 */
2118   { PREFIX_TABLE (PREFIX_90) },
2119   { "xchgS",            { RMeCX, eAX }, 0 },
2120   { "xchgS",            { RMeDX, eAX }, 0 },
2121   { "xchgS",            { RMeBX, eAX }, 0 },
2122   { "xchgS",            { RMeSP, eAX }, 0 },
2123   { "xchgS",            { RMeBP, eAX }, 0 },
2124   { "xchgS",            { RMeSI, eAX }, 0 },
2125   { "xchgS",            { RMeDI, eAX }, 0 },
2126   /* 98 */
2127   { "cW{t|}R",          { XX }, 0 },
2128   { "cR{t|}O",          { XX }, 0 },
2129   { X86_64_TABLE (X86_64_9A) },
2130   { Bad_Opcode },       /* fwait */
2131   { "pushfP",           { XX }, 0 },
2132   { "popfP",            { XX }, 0 },
2133   { "sahf",             { XX }, 0 },
2134   { "lahf",             { XX }, 0 },
2135   /* a0 */
2136   { "mov%LB",           { AL, Ob }, PREFIX_REX2_ILLEGAL },
2137   { "mov%LS",           { { JMPABS_Fixup, eAX_reg }, { JMPABS_Fixup, v_mode } }, PREFIX_REX2_ILLEGAL },
2138   { "mov%LB",           { Ob, AL }, PREFIX_REX2_ILLEGAL },
2139   { "mov%LS",           { Ov, eAX }, PREFIX_REX2_ILLEGAL },
2140   { "movs{b|}",         { Ybr, Xb }, PREFIX_REX2_ILLEGAL },
2141   { "movs{R|}",         { Yvr, Xv }, PREFIX_REX2_ILLEGAL },
2142   { "cmps{b|}",         { Xb, Yb }, PREFIX_REX2_ILLEGAL },
2143   { "cmps{R|}",         { Xv, Yv }, PREFIX_REX2_ILLEGAL },
2144   /* a8 */
2145   { "testB",            { AL, Ib }, PREFIX_REX2_ILLEGAL },
2146   { "testS",            { eAX, Iv }, PREFIX_REX2_ILLEGAL },
2147   { "stosB",            { Ybr, AL }, PREFIX_REX2_ILLEGAL },
2148   { "stosS",            { Yvr, eAX }, PREFIX_REX2_ILLEGAL },
2149   { "lodsB",            { ALr, Xb }, PREFIX_REX2_ILLEGAL },
2150   { "lodsS",            { eAXr, Xv }, PREFIX_REX2_ILLEGAL },
2151   { "scasB",            { AL, Yb }, PREFIX_REX2_ILLEGAL },
2152   { "scasS",            { eAX, Yv }, PREFIX_REX2_ILLEGAL },
2153   /* b0 */
2154   { "movB",             { RMAL, Ib }, 0 },
2155   { "movB",             { RMCL, Ib }, 0 },
2156   { "movB",             { RMDL, Ib }, 0 },
2157   { "movB",             { RMBL, Ib }, 0 },
2158   { "movB",             { RMAH, Ib }, 0 },
2159   { "movB",             { RMCH, Ib }, 0 },
2160   { "movB",             { RMDH, Ib }, 0 },
2161   { "movB",             { RMBH, Ib }, 0 },
2162   /* b8 */
2163   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2164   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2165   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2166   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2167   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2168   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2169   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2170   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2171   /* c0 */
2172   { REG_TABLE (REG_C0) },
2173   { REG_TABLE (REG_C1) },
2174   { X86_64_TABLE (X86_64_C2) },
2175   { X86_64_TABLE (X86_64_C3) },
2176   { X86_64_TABLE (X86_64_C4) },
2177   { X86_64_TABLE (X86_64_C5) },
2178   { REG_TABLE (REG_C6) },
2179   { REG_TABLE (REG_C7) },
2180   /* c8 */
2181   { "enterP",           { Iw, Ib }, 0 },
2182   { "leaveP",           { XX }, 0 },
2183   { "{l|}ret{|f}%LP",   { Iw }, 0 },
2184   { "{l|}ret{|f}%LP",   { XX }, 0 },
2185   { "int3",             { XX }, 0 },
2186   { "int",              { Ib }, 0 },
2187   { X86_64_TABLE (X86_64_CE) },
2188   { "iret%LP",          { XX }, 0 },
2189   /* d0 */
2190   { REG_TABLE (REG_D0) },
2191   { REG_TABLE (REG_D1) },
2192   { REG_TABLE (REG_D2) },
2193   { REG_TABLE (REG_D3) },
2194   { X86_64_TABLE (X86_64_D4) },
2195   { X86_64_TABLE (X86_64_D5) },
2196   { Bad_Opcode },
2197   { "xlat",             { DSBX }, 0 },
2198   /* d8 */
2199   { FLOAT },
2200   { FLOAT },
2201   { FLOAT },
2202   { FLOAT },
2203   { FLOAT },
2204   { FLOAT },
2205   { FLOAT },
2206   { FLOAT },
2207   /* e0 */
2208   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, PREFIX_REX2_ILLEGAL },
2209   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, PREFIX_REX2_ILLEGAL },
2210   { "loopFH",           { Jb, XX, loop_jcxz_flag }, PREFIX_REX2_ILLEGAL },
2211   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, PREFIX_REX2_ILLEGAL },
2212   { "inB",              { AL, Ib }, PREFIX_REX2_ILLEGAL },
2213   { "inG",              { zAX, Ib }, PREFIX_REX2_ILLEGAL },
2214   { "outB",             { Ib, AL }, PREFIX_REX2_ILLEGAL },
2215   { "outG",             { Ib, zAX }, PREFIX_REX2_ILLEGAL },
2216   /* e8 */
2217   { X86_64_TABLE (X86_64_E8) },
2218   { X86_64_TABLE (X86_64_E9) },
2219   { X86_64_TABLE (X86_64_EA) },
2220   { "jmp",              { Jb, BND }, PREFIX_REX2_ILLEGAL },
2221   { "inB",              { AL, indirDX }, PREFIX_REX2_ILLEGAL },
2222   { "inG",              { zAX, indirDX }, PREFIX_REX2_ILLEGAL },
2223   { "outB",             { indirDX, AL }, PREFIX_REX2_ILLEGAL },
2224   { "outG",             { indirDX, zAX }, PREFIX_REX2_ILLEGAL },
2225   /* f0 */
2226   { Bad_Opcode },       /* lock prefix */
2227   { "int1",             { XX }, 0 },
2228   { Bad_Opcode },       /* repne */
2229   { Bad_Opcode },       /* repz */
2230   { "hlt",              { XX }, 0 },
2231   { "cmc",              { XX }, 0 },
2232   { REG_TABLE (REG_F6) },
2233   { REG_TABLE (REG_F7) },
2234   /* f8 */
2235   { "clc",              { XX }, 0 },
2236   { "stc",              { XX }, 0 },
2237   { "cli",              { XX }, 0 },
2238   { "sti",              { XX }, 0 },
2239   { "cld",              { XX }, 0 },
2240   { "std",              { XX }, 0 },
2241   { REG_TABLE (REG_FE) },
2242   { REG_TABLE (REG_FF) },
2243 };
2244
2245 static const struct dis386 dis386_twobyte[] = {
2246   /* 00 */
2247   { REG_TABLE (REG_0F00 ) },
2248   { REG_TABLE (REG_0F01 ) },
2249   { "larS",             { Gv, Sv }, 0 },
2250   { "lslS",             { Gv, Sv }, 0 },
2251   { Bad_Opcode },
2252   { "syscall",          { XX }, 0 },
2253   { "clts",             { XX }, 0 },
2254   { "sysret%LQ",                { XX }, 0 },
2255   /* 08 */
2256   { "invd",             { XX }, 0 },
2257   { PREFIX_TABLE (PREFIX_0F09) },
2258   { Bad_Opcode },
2259   { "ud2",              { XX }, 0 },
2260   { Bad_Opcode },
2261   { REG_TABLE (REG_0F0D) },
2262   { "femms",            { XX }, 0 },
2263   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2264   /* 10 */
2265   { PREFIX_TABLE (PREFIX_0F10) },
2266   { PREFIX_TABLE (PREFIX_0F11) },
2267   { PREFIX_TABLE (PREFIX_0F12) },
2268   { "movlpX",           { Mq, XM }, PREFIX_OPCODE },
2269   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2270   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2271   { PREFIX_TABLE (PREFIX_0F16) },
2272   { "movhpX",           { Mq, XM }, PREFIX_OPCODE },
2273   /* 18 */
2274   { REG_TABLE (REG_0F18) },
2275   { "nopQ",             { Ev }, 0 },
2276   { PREFIX_TABLE (PREFIX_0F1A) },
2277   { PREFIX_TABLE (PREFIX_0F1B) },
2278   { PREFIX_TABLE (PREFIX_0F1C) },
2279   { "nopQ",             { Ev }, 0 },
2280   { PREFIX_TABLE (PREFIX_0F1E) },
2281   { "nopQ",             { Ev }, 0 },
2282   /* 20 */
2283   { "movZ",             { Em, Cm }, 0 },
2284   { "movZ",             { Em, Dm }, 0 },
2285   { "movZ",             { Cm, Em }, 0 },
2286   { "movZ",             { Dm, Em }, 0 },
2287   { X86_64_TABLE (X86_64_0F24) },
2288   { Bad_Opcode },
2289   { X86_64_TABLE (X86_64_0F26) },
2290   { Bad_Opcode },
2291   /* 28 */
2292   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2293   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2294   { PREFIX_TABLE (PREFIX_0F2A) },
2295   { PREFIX_TABLE (PREFIX_0F2B) },
2296   { PREFIX_TABLE (PREFIX_0F2C) },
2297   { PREFIX_TABLE (PREFIX_0F2D) },
2298   { PREFIX_TABLE (PREFIX_0F2E) },
2299   { PREFIX_TABLE (PREFIX_0F2F) },
2300   /* 30 */
2301   { "wrmsr",            { XX }, PREFIX_REX2_ILLEGAL },
2302   { "rdtsc",            { XX }, PREFIX_REX2_ILLEGAL },
2303   { "rdmsr",            { XX }, PREFIX_REX2_ILLEGAL },
2304   { "rdpmc",            { XX }, PREFIX_REX2_ILLEGAL },
2305   { "sysenter",         { SEP }, PREFIX_REX2_ILLEGAL },
2306   { "sysexit%LQ",       { SEP }, PREFIX_REX2_ILLEGAL },
2307   { Bad_Opcode },
2308   { "getsec",           { XX }, 0 },
2309   /* 38 */
2310   { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
2311   { Bad_Opcode },
2312   { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
2313   { Bad_Opcode },
2314   { Bad_Opcode },
2315   { Bad_Opcode },
2316   { Bad_Opcode },
2317   { Bad_Opcode },
2318   /* 40 */
2319   { "cmovoS",           { Gv, Ev }, 0 },
2320   { "cmovnoS",          { Gv, Ev }, 0 },
2321   { "cmovbS",           { Gv, Ev }, 0 },
2322   { "cmovaeS",          { Gv, Ev }, 0 },
2323   { "cmoveS",           { Gv, Ev }, 0 },
2324   { "cmovneS",          { Gv, Ev }, 0 },
2325   { "cmovbeS",          { Gv, Ev }, 0 },
2326   { "cmovaS",           { Gv, Ev }, 0 },
2327   /* 48 */
2328   { "cmovsS",           { Gv, Ev }, 0 },
2329   { "cmovnsS",          { Gv, Ev }, 0 },
2330   { "cmovpS",           { Gv, Ev }, 0 },
2331   { "cmovnpS",          { Gv, Ev }, 0 },
2332   { "cmovlS",           { Gv, Ev }, 0 },
2333   { "cmovgeS",          { Gv, Ev }, 0 },
2334   { "cmovleS",          { Gv, Ev }, 0 },
2335   { "cmovgS",           { Gv, Ev }, 0 },
2336   /* 50 */
2337   { "movmskpX",         { Gdq, Ux }, PREFIX_OPCODE },
2338   { PREFIX_TABLE (PREFIX_0F51) },
2339   { PREFIX_TABLE (PREFIX_0F52) },
2340   { PREFIX_TABLE (PREFIX_0F53) },
2341   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2342   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2343   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2344   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2345   /* 58 */
2346   { PREFIX_TABLE (PREFIX_0F58) },
2347   { PREFIX_TABLE (PREFIX_0F59) },
2348   { PREFIX_TABLE (PREFIX_0F5A) },
2349   { PREFIX_TABLE (PREFIX_0F5B) },
2350   { PREFIX_TABLE (PREFIX_0F5C) },
2351   { PREFIX_TABLE (PREFIX_0F5D) },
2352   { PREFIX_TABLE (PREFIX_0F5E) },
2353   { PREFIX_TABLE (PREFIX_0F5F) },
2354   /* 60 */
2355   { PREFIX_TABLE (PREFIX_0F60) },
2356   { PREFIX_TABLE (PREFIX_0F61) },
2357   { PREFIX_TABLE (PREFIX_0F62) },
2358   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2359   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2360   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2361   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2362   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2363   /* 68 */
2364   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2365   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2366   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2367   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2368   { "punpcklqdq", { XM, EXx }, PREFIX_DATA },
2369   { "punpckhqdq", { XM, EXx }, PREFIX_DATA },
2370   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2371   { PREFIX_TABLE (PREFIX_0F6F) },
2372   /* 70 */
2373   { PREFIX_TABLE (PREFIX_0F70) },
2374   { REG_TABLE (REG_0F71) },
2375   { REG_TABLE (REG_0F72) },
2376   { REG_TABLE (REG_0F73) },
2377   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2378   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2379   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2380   { "emms",             { XX }, PREFIX_OPCODE },
2381   /* 78 */
2382   { PREFIX_TABLE (PREFIX_0F78) },
2383   { PREFIX_TABLE (PREFIX_0F79) },
2384   { Bad_Opcode },
2385   { Bad_Opcode },
2386   { PREFIX_TABLE (PREFIX_0F7C) },
2387   { PREFIX_TABLE (PREFIX_0F7D) },
2388   { PREFIX_TABLE (PREFIX_0F7E) },
2389   { PREFIX_TABLE (PREFIX_0F7F) },
2390   /* 80 */
2391   { "joH",              { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2392   { "jnoH",             { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2393   { "jbH",              { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2394   { "jaeH",             { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2395   { "jeH",              { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2396   { "jneH",             { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2397   { "jbeH",             { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2398   { "jaH",              { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2399   /* 88 */
2400   { "jsH",              { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2401   { "jnsH",             { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2402   { "jpH",              { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2403   { "jnpH",             { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2404   { "jlH",              { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2405   { "jgeH",             { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2406   { "jleH",             { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2407   { "jgH",              { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2408   /* 90 */
2409   { "seto",             { Eb }, 0 },
2410   { "setno",            { Eb }, 0 },
2411   { "setb",             { Eb }, 0 },
2412   { "setae",            { Eb }, 0 },
2413   { "sete",             { Eb }, 0 },
2414   { "setne",            { Eb }, 0 },
2415   { "setbe",            { Eb }, 0 },
2416   { "seta",             { Eb }, 0 },
2417   /* 98 */
2418   { "sets",             { Eb }, 0 },
2419   { "setns",            { Eb }, 0 },
2420   { "setp",             { Eb }, 0 },
2421   { "setnp",            { Eb }, 0 },
2422   { "setl",             { Eb }, 0 },
2423   { "setge",            { Eb }, 0 },
2424   { "setle",            { Eb }, 0 },
2425   { "setg",             { Eb }, 0 },
2426   /* a0 */
2427   { "pushP",            { fs }, 0 },
2428   { "popP",             { fs }, 0 },
2429   { "cpuid",            { XX }, 0 },
2430   { "btS",              { Ev, Gv }, 0 },
2431   { "shldS",            { Ev, Gv, Ib }, 0 },
2432   { "shldS",            { Ev, Gv, CL }, 0 },
2433   { REG_TABLE (REG_0FA6) },
2434   { REG_TABLE (REG_0FA7) },
2435   /* a8 */
2436   { "pushP",            { gs }, 0 },
2437   { "popP",             { gs }, 0 },
2438   { "rsm",              { XX }, 0 },
2439   { "btsS",             { Evh1, Gv }, 0 },
2440   { "shrdS",            { Ev, Gv, Ib }, 0 },
2441   { "shrdS",            { Ev, Gv, CL }, 0 },
2442   { REG_TABLE (REG_0FAE) },
2443   { "imulS",            { Gv, Ev }, 0 },
2444   /* b0 */
2445   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2446   { "cmpxchgS",         { Evh1, Gv }, 0 },
2447   { "lssS",             { Gv, Mp }, 0 },
2448   { "btrS",             { Evh1, Gv }, 0 },
2449   { "lfsS",             { Gv, Mp }, 0 },
2450   { "lgsS",             { Gv, Mp }, 0 },
2451   { "movz{bR|x}",       { Gv, Eb }, 0 },
2452   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2453   /* b8 */
2454   { PREFIX_TABLE (PREFIX_0FB8) },
2455   { "ud1S",             { Gv, Ev }, 0 },
2456   { REG_TABLE (REG_0FBA) },
2457   { "btcS",             { Evh1, Gv }, 0 },
2458   { PREFIX_TABLE (PREFIX_0FBC) },
2459   { PREFIX_TABLE (PREFIX_0FBD) },
2460   { "movs{bR|x}",       { Gv, Eb }, 0 },
2461   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2462   /* c0 */
2463   { "xaddB",            { Ebh1, Gb }, 0 },
2464   { "xaddS",            { Evh1, Gv }, 0 },
2465   { PREFIX_TABLE (PREFIX_0FC2) },
2466   { "movntiS",          { Mdq, Gdq }, PREFIX_OPCODE },
2467   { "pinsrw",           { MX, Edw, Ib }, PREFIX_OPCODE },
2468   { "pextrw",           { Gd, Nq, Ib }, PREFIX_OPCODE },
2469   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2470   { REG_TABLE (REG_0FC7) },
2471   /* c8 */
2472   { "bswap",            { RMeAX }, 0 },
2473   { "bswap",            { RMeCX }, 0 },
2474   { "bswap",            { RMeDX }, 0 },
2475   { "bswap",            { RMeBX }, 0 },
2476   { "bswap",            { RMeSP }, 0 },
2477   { "bswap",            { RMeBP }, 0 },
2478   { "bswap",            { RMeSI }, 0 },
2479   { "bswap",            { RMeDI }, 0 },
2480   /* d0 */
2481   { PREFIX_TABLE (PREFIX_0FD0) },
2482   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2483   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2484   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2485   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2486   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2487   { PREFIX_TABLE (PREFIX_0FD6) },
2488   { "pmovmskb",         { Gdq, Nq }, PREFIX_OPCODE },
2489   /* d8 */
2490   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2491   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2492   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2493   { "pand",             { MX, EM }, PREFIX_OPCODE },
2494   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2495   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2496   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2497   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2498   /* e0 */
2499   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2500   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2501   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2502   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2503   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2504   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2505   { PREFIX_TABLE (PREFIX_0FE6) },
2506   { PREFIX_TABLE (PREFIX_0FE7) },
2507   /* e8 */
2508   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2509   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2510   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2511   { "por",              { MX, EM }, PREFIX_OPCODE },
2512   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2513   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2514   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2515   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2516   /* f0 */
2517   { PREFIX_TABLE (PREFIX_0FF0) },
2518   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2519   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2520   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2521   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2522   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2523   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2524   { PREFIX_TABLE (PREFIX_0FF7) },
2525   /* f8 */
2526   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2527   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2528   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2529   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2530   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2531   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2532   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2533   { "ud0S",             { Gv, Ev }, 0 },
2534 };
2535
2536 static const bool onebyte_has_modrm[256] = {
2537   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2538   /*       -------------------------------        */
2539   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2540   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2541   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2542   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2543   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2544   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2545   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2546   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2547   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2548   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2549   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2550   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2551   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2552   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2553   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2554   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2555   /*       -------------------------------        */
2556   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2557 };
2558
2559 static const bool twobyte_has_modrm[256] = {
2560   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2561   /*       -------------------------------        */
2562   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2563   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2564   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2565   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2566   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2567   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2568   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2569   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2570   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2571   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2572   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2573   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2574   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2575   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2576   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2577   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2578   /*       -------------------------------        */
2579   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2580 };
2581
2582
2583 struct op
2584   {
2585     const char *name;
2586     unsigned int len;
2587   };
2588
2589 /* If we are accessing mod/rm/reg without need_modrm set, then the
2590    values are stale.  Hitting this abort likely indicates that you
2591    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2592 #define MODRM_CHECK  if (!ins->need_modrm) abort ()
2593
2594 static const char intel_index16[][6] = {
2595   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2596 };
2597
2598 static const char att_names64[][8] = {
2599   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2600   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
2601   "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
2602   "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
2603 };
2604 static const char att_names32[][8] = {
2605   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2606   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d",
2607   "%r16d", "%r17d", "%r18d", "%r19d", "%r20d", "%r21d", "%r22d", "%r23d",
2608   "%r24d", "%r25d", "%r26d", "%r27d", "%r28d", "%r29d", "%r30d", "%r31d",
2609 };
2610 static const char att_names16[][8] = {
2611   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2612   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w",
2613   "%r16w", "%r17w", "%r18w", "%r19w", "%r20w", "%r21w", "%r22w", "%r23w",
2614   "%r24w", "%r25w", "%r26w", "%r27w", "%r28w", "%r29w", "%r30w", "%r31w",
2615 };
2616 static const char att_names8[][8] = {
2617   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2618 };
2619 static const char att_names8rex[][8] = {
2620   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2621   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b",
2622   "%r16b", "%r17b", "%r18b", "%r19b", "%r20b", "%r21b", "%r22b", "%r23b",
2623   "%r24b", "%r25b", "%r26b", "%r27b", "%r28b", "%r29b", "%r30b", "%r31b",
2624 };
2625 static const char att_names_seg[][4] = {
2626   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2627 };
2628 static const char att_index64[] = "%riz";
2629 static const char att_index32[] = "%eiz";
2630 static const char att_index16[][8] = {
2631   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2632 };
2633
2634 static const char att_names_mm[][8] = {
2635   "%mm0", "%mm1", "%mm2", "%mm3",
2636   "%mm4", "%mm5", "%mm6", "%mm7"
2637 };
2638
2639 static const char att_names_bnd[][8] = {
2640   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2641 };
2642
2643 static const char att_names_xmm[][8] = {
2644   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2645   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2646   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2647   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2648   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2649   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
2650   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
2651   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
2652 };
2653
2654 static const char att_names_ymm[][8] = {
2655   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2656   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2657   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2658   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
2659   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
2660   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
2661   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
2662   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
2663 };
2664
2665 static const char att_names_zmm[][8] = {
2666   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
2667   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
2668   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
2669   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
2670   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
2671   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
2672   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
2673   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
2674 };
2675
2676 static const char att_names_tmm[][8] = {
2677   "%tmm0", "%tmm1", "%tmm2", "%tmm3",
2678   "%tmm4", "%tmm5", "%tmm6", "%tmm7"
2679 };
2680
2681 static const char att_names_mask[][8] = {
2682   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
2683 };
2684
2685 static const char *const names_rounding[] =
2686 {
2687   "{rn-",
2688   "{rd-",
2689   "{ru-",
2690   "{rz-"
2691 };
2692
2693 static const struct dis386 reg_table[][8] = {
2694   /* REG_80 */
2695   {
2696     { "addA",   { Ebh1, Ib }, 0 },
2697     { "orA",    { Ebh1, Ib }, 0 },
2698     { "adcA",   { Ebh1, Ib }, 0 },
2699     { "sbbA",   { Ebh1, Ib }, 0 },
2700     { "andA",   { Ebh1, Ib }, 0 },
2701     { "subA",   { Ebh1, Ib }, 0 },
2702     { "xorA",   { Ebh1, Ib }, 0 },
2703     { "cmpA",   { Eb, Ib }, 0 },
2704   },
2705   /* REG_81 */
2706   {
2707     { "addQ",   { Evh1, Iv }, 0 },
2708     { "orQ",    { Evh1, Iv }, 0 },
2709     { "adcQ",   { Evh1, Iv }, 0 },
2710     { "sbbQ",   { Evh1, Iv }, 0 },
2711     { "andQ",   { Evh1, Iv }, 0 },
2712     { "subQ",   { Evh1, Iv }, 0 },
2713     { "xorQ",   { Evh1, Iv }, 0 },
2714     { "cmpQ",   { Ev, Iv }, 0 },
2715   },
2716   /* REG_83 */
2717   {
2718     { "addQ",   { Evh1, sIb }, 0 },
2719     { "orQ",    { Evh1, sIb }, 0 },
2720     { "adcQ",   { Evh1, sIb }, 0 },
2721     { "sbbQ",   { Evh1, sIb }, 0 },
2722     { "andQ",   { Evh1, sIb }, 0 },
2723     { "subQ",   { Evh1, sIb }, 0 },
2724     { "xorQ",   { Evh1, sIb }, 0 },
2725     { "cmpQ",   { Ev, sIb }, 0 },
2726   },
2727   /* REG_8F */
2728   {
2729     { "pop{P|}", { stackEv }, 0 },
2730     { XOP_8F_TABLE () },
2731     { Bad_Opcode },
2732     { Bad_Opcode },
2733     { Bad_Opcode },
2734     { XOP_8F_TABLE () },
2735   },
2736   /* REG_C0 */
2737   {
2738     { "%NFrolA",        { VexGb, Eb, Ib }, NO_PREFIX },
2739     { "%NFrorA",        { VexGb, Eb, Ib }, NO_PREFIX },
2740     { "rclA",   { VexGb, Eb, Ib }, NO_PREFIX },
2741     { "rcrA",   { VexGb, Eb, Ib }, NO_PREFIX },
2742     { "%NFshlA",        { VexGb, Eb, Ib }, NO_PREFIX },
2743     { "%NFshrA",        { VexGb, Eb, Ib }, NO_PREFIX },
2744     { "%NFshlA",        { VexGb, Eb, Ib }, NO_PREFIX },
2745     { "%NFsarA",        { VexGb, Eb, Ib }, NO_PREFIX },
2746   },
2747   /* REG_C1 */
2748   {
2749     { "%NFrolQ",        { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2750     { "%NFrorQ",        { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2751     { "rclQ",   { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2752     { "rcrQ",   { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2753     { "%NFshlQ",        { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2754     { "%NFshrQ",        { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2755     { "%NFshlQ",        { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2756     { "%NFsarQ",        { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2757   },
2758   /* REG_C6 */
2759   {
2760     { "movA",   { Ebh3, Ib }, 0 },
2761     { Bad_Opcode },
2762     { Bad_Opcode },
2763     { Bad_Opcode },
2764     { Bad_Opcode },
2765     { Bad_Opcode },
2766     { Bad_Opcode },
2767     { RM_TABLE (RM_C6_REG_7) },
2768   },
2769   /* REG_C7 */
2770   {
2771     { "movQ",   { Evh3, Iv }, 0 },
2772     { Bad_Opcode },
2773     { Bad_Opcode },
2774     { Bad_Opcode },
2775     { Bad_Opcode },
2776     { Bad_Opcode },
2777     { Bad_Opcode },
2778     { RM_TABLE (RM_C7_REG_7) },
2779   },
2780   /* REG_D0 */
2781   {
2782     { "%NFrolA",        { VexGb, Eb, I1 }, NO_PREFIX },
2783     { "%NFrorA",        { VexGb, Eb, I1 }, NO_PREFIX },
2784     { "rclA",   { VexGb, Eb, I1 }, NO_PREFIX },
2785     { "rcrA",   { VexGb, Eb, I1 }, NO_PREFIX },
2786     { "%NFshlA",        { VexGb, Eb, I1 }, NO_PREFIX },
2787     { "%NFshrA",        { VexGb, Eb, I1 }, NO_PREFIX },
2788     { "%NFshlA",        { VexGb, Eb, I1 }, NO_PREFIX },
2789     { "%NFsarA",        { VexGb, Eb, I1 }, NO_PREFIX },
2790   },
2791   /* REG_D1 */
2792   {
2793     { "%NFrolQ",        { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2794     { "%NFrorQ",        { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2795     { "rclQ",   { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2796     { "rcrQ",   { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2797     { "%NFshlQ",        { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2798     { "%NFshrQ",        { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2799     { "%NFshlQ",        { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2800     { "%NFsarQ",        { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2801   },
2802   /* REG_D2 */
2803   {
2804     { "%NFrolA",        { VexGb, Eb, CL }, NO_PREFIX },
2805     { "%NFrorA",        { VexGb, Eb, CL }, NO_PREFIX },
2806     { "rclA",   { VexGb, Eb, CL }, NO_PREFIX },
2807     { "rcrA",   { VexGb, Eb, CL }, NO_PREFIX },
2808     { "%NFshlA",        { VexGb, Eb, CL }, NO_PREFIX },
2809     { "%NFshrA",        { VexGb, Eb, CL }, NO_PREFIX },
2810     { "%NFshlA",        { VexGb, Eb, CL }, NO_PREFIX },
2811     { "%NFsarA",        { VexGb, Eb, CL }, NO_PREFIX },
2812   },
2813   /* REG_D3 */
2814   {
2815     { "%NFrolQ",        { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2816     { "%NFrorQ",        { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2817     { "rclQ",   { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2818     { "rcrQ",   { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2819     { "%NFshlQ",        { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2820     { "%NFshrQ",        { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2821     { "%NFshlQ",        { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2822     { "%NFsarQ",        { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2823   },
2824   /* REG_F6 */
2825   {
2826     { "testA",  { Eb, Ib }, 0 },
2827     { "testA",  { Eb, Ib }, 0 },
2828     { "notA",   { Ebh1 }, 0 },
2829     { "negA",   { Ebh1 }, 0 },
2830     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
2831     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
2832     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
2833     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
2834   },
2835   /* REG_F7 */
2836   {
2837     { "testQ",  { Ev, Iv }, 0 },
2838     { "testQ",  { Ev, Iv }, 0 },
2839     { "notQ",   { Evh1 }, 0 },
2840     { "negQ",   { Evh1 }, 0 },
2841     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
2842     { "imulQ",  { Ev }, 0 },
2843     { "divQ",   { Ev }, 0 },
2844     { "idivQ",  { Ev }, 0 },
2845   },
2846   /* REG_FE */
2847   {
2848     { "incA",   { Ebh1 }, 0 },
2849     { "decA",   { Ebh1 }, 0 },
2850   },
2851   /* REG_FF */
2852   {
2853     { "incQ",   { Evh1 }, 0 },
2854     { "decQ",   { Evh1 }, 0 },
2855     { "call{@|}", { NOTRACK, indirEv, BND }, 0 },
2856     { "{l|}call^", { indirEp }, 0 },
2857     { "jmp{@|}", { NOTRACK, indirEv, BND }, 0 },
2858     { "{l|}jmp^", { indirEp }, 0 },
2859     { "push{P|}", { stackEv }, 0 },
2860     { Bad_Opcode },
2861   },
2862   /* REG_0F00 */
2863   {
2864     { "sldtD",  { Sv }, 0 },
2865     { "strD",   { Sv }, 0 },
2866     { "lldtD",  { Sv }, 0 },
2867     { "ltrD",   { Sv }, 0 },
2868     { "verrD",  { Sv }, 0 },
2869     { "verwD",  { Sv }, 0 },
2870     { X86_64_TABLE (X86_64_0F00_REG_6) },
2871     { Bad_Opcode },
2872   },
2873   /* REG_0F01 */
2874   {
2875     { MOD_TABLE (MOD_0F01_REG_0) },
2876     { MOD_TABLE (MOD_0F01_REG_1) },
2877     { MOD_TABLE (MOD_0F01_REG_2) },
2878     { MOD_TABLE (MOD_0F01_REG_3) },
2879     { "smswD",  { Sv }, 0 },
2880     { MOD_TABLE (MOD_0F01_REG_5) },
2881     { "lmsw",   { Ew }, 0 },
2882     { MOD_TABLE (MOD_0F01_REG_7) },
2883   },
2884   /* REG_0F0D */
2885   {
2886     { "prefetch",       { Mb }, 0 },
2887     { "prefetchw",      { Mb }, 0 },
2888     { "prefetchwt1",    { Mb }, 0 },
2889     { "prefetch",       { Mb }, 0 },
2890     { "prefetch",       { Mb }, 0 },
2891     { "prefetch",       { Mb }, 0 },
2892     { "prefetch",       { Mb }, 0 },
2893     { "prefetch",       { Mb }, 0 },
2894   },
2895   /* REG_0F18 */
2896   {
2897     { MOD_TABLE (MOD_0F18_REG_0) },
2898     { MOD_TABLE (MOD_0F18_REG_1) },
2899     { MOD_TABLE (MOD_0F18_REG_2) },
2900     { MOD_TABLE (MOD_0F18_REG_3) },
2901     { MOD_TABLE (MOD_0F18_REG_4) },
2902     { "nopQ",           { Ev }, 0 },
2903     { MOD_TABLE (MOD_0F18_REG_6) },
2904     { MOD_TABLE (MOD_0F18_REG_7) },
2905   },
2906   /* REG_0F1C_P_0_MOD_0 */
2907   {
2908     { "cldemote",       { Mb }, 0 },
2909     { "nopQ",           { Ev }, 0 },
2910     { "nopQ",           { Ev }, 0 },
2911     { "nopQ",           { Ev }, 0 },
2912     { "nopQ",           { Ev }, 0 },
2913     { "nopQ",           { Ev }, 0 },
2914     { "nopQ",           { Ev }, 0 },
2915     { "nopQ",           { Ev }, 0 },
2916   },
2917   /* REG_0F1E_P_1_MOD_3 */
2918   {
2919     { "nopQ",           { Ev }, PREFIX_IGNORED },
2920     { "rdsspK",         { Edq }, 0 },
2921     { "nopQ",           { Ev }, PREFIX_IGNORED },
2922     { "nopQ",           { Ev }, PREFIX_IGNORED },
2923     { "nopQ",           { Ev }, PREFIX_IGNORED },
2924     { "nopQ",           { Ev }, PREFIX_IGNORED },
2925     { "nopQ",           { Ev }, PREFIX_IGNORED },
2926     { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
2927   },
2928   /* REG_0F38D8_PREFIX_1 */
2929   {
2930     { "aesencwide128kl",        { M }, 0 },
2931     { "aesdecwide128kl",        { M }, 0 },
2932     { "aesencwide256kl",        { M }, 0 },
2933     { "aesdecwide256kl",        { M }, 0 },
2934   },
2935   /* REG_0F3A0F_P_1 */
2936   {
2937     { RM_TABLE (RM_0F3A0F_P_1_R_0) },
2938   },
2939   /* REG_0F71 */
2940   {
2941     { Bad_Opcode },
2942     { Bad_Opcode },
2943     { "psrlw",          { Nq, Ib }, PREFIX_OPCODE },
2944     { Bad_Opcode },
2945     { "psraw",          { Nq, Ib }, PREFIX_OPCODE },
2946     { Bad_Opcode },
2947     { "psllw",          { Nq, Ib }, PREFIX_OPCODE },
2948   },
2949   /* REG_0F72 */
2950   {
2951     { Bad_Opcode },
2952     { Bad_Opcode },
2953     { "psrld",          { Nq, Ib }, PREFIX_OPCODE },
2954     { Bad_Opcode },
2955     { "psrad",          { Nq, Ib }, PREFIX_OPCODE },
2956     { Bad_Opcode },
2957     { "pslld",          { Nq, Ib }, PREFIX_OPCODE },
2958   },
2959   /* REG_0F73 */
2960   {
2961     { Bad_Opcode },
2962     { Bad_Opcode },
2963     { "psrlq",          { Nq, Ib }, PREFIX_OPCODE },
2964     { "psrldq",         { Ux, Ib }, PREFIX_DATA },
2965     { Bad_Opcode },
2966     { Bad_Opcode },
2967     { "psllq",          { Nq, Ib }, PREFIX_OPCODE },
2968     { "pslldq",         { Ux, Ib }, PREFIX_DATA },
2969   },
2970   /* REG_0FA6 */
2971   {
2972     { PREFIX_TABLE (PREFIX_0FA6_REG_0) },
2973     { "xsha1",          { { OP_0f07, 0 } }, 0 },
2974     { "xsha256",        { { OP_0f07, 0 } }, 0 },
2975     { "xsha384",        { { OP_0f07, 0 } }, 0 },
2976     { "xsha512",        { { OP_0f07, 0 } }, 0 },
2977     { PREFIX_TABLE (PREFIX_0FA6_REG_5) },
2978   },
2979   /* REG_0FA7 */
2980   {
2981     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
2982     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
2983     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
2984     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
2985     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
2986     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
2987     { PREFIX_TABLE (PREFIX_0FA7_REG_6) },
2988     { "xrng2",          { { OP_0f07, 0 } }, 0 },
2989   },
2990   /* REG_0FAE */
2991   {
2992     { MOD_TABLE (MOD_0FAE_REG_0) },
2993     { MOD_TABLE (MOD_0FAE_REG_1) },
2994     { MOD_TABLE (MOD_0FAE_REG_2) },
2995     { MOD_TABLE (MOD_0FAE_REG_3) },
2996     { MOD_TABLE (MOD_0FAE_REG_4) },
2997     { MOD_TABLE (MOD_0FAE_REG_5) },
2998     { MOD_TABLE (MOD_0FAE_REG_6) },
2999     { MOD_TABLE (MOD_0FAE_REG_7) },
3000   },
3001   /* REG_0FBA */
3002   {
3003     { Bad_Opcode },
3004     { Bad_Opcode },
3005     { Bad_Opcode },
3006     { Bad_Opcode },
3007     { "btQ",    { Ev, Ib }, 0 },
3008     { "btsQ",   { Evh1, Ib }, 0 },
3009     { "btrQ",   { Evh1, Ib }, 0 },
3010     { "btcQ",   { Evh1, Ib }, 0 },
3011   },
3012   /* REG_0FC7 */
3013   {
3014     { Bad_Opcode },
3015     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3016     { Bad_Opcode },
3017     { "xrstors", { FXSAVE }, PREFIX_REX2_ILLEGAL },
3018     { "xsavec", { FXSAVE }, PREFIX_REX2_ILLEGAL },
3019     { "xsaves", { FXSAVE }, PREFIX_REX2_ILLEGAL },
3020     { MOD_TABLE (MOD_0FC7_REG_6) },
3021     { MOD_TABLE (MOD_0FC7_REG_7) },
3022   },
3023   /* REG_VEX_0F71 */
3024   {
3025     { Bad_Opcode },
3026     { Bad_Opcode },
3027     { "vpsrlw",         { Vex, Ux, Ib }, PREFIX_DATA },
3028     { Bad_Opcode },
3029     { "vpsraw",         { Vex, Ux, Ib }, PREFIX_DATA },
3030     { Bad_Opcode },
3031     { "vpsllw",         { Vex, Ux, Ib }, PREFIX_DATA },
3032   },
3033   /* REG_VEX_0F72 */
3034   {
3035     { Bad_Opcode },
3036     { Bad_Opcode },
3037     { "vpsrld",         { Vex, Ux, Ib }, PREFIX_DATA },
3038     { Bad_Opcode },
3039     { "vpsrad",         { Vex, Ux, Ib }, PREFIX_DATA },
3040     { Bad_Opcode },
3041     { "vpslld",         { Vex, Ux, Ib }, PREFIX_DATA },
3042   },
3043   /* REG_VEX_0F73 */
3044   {
3045     { Bad_Opcode },
3046     { Bad_Opcode },
3047     { "vpsrlq",         { Vex, Ux, Ib }, PREFIX_DATA },
3048     { "vpsrldq",        { Vex, Ux, Ib }, PREFIX_DATA },
3049     { Bad_Opcode },
3050     { Bad_Opcode },
3051     { "vpsllq",         { Vex, Ux, Ib }, PREFIX_DATA },
3052     { "vpslldq",        { Vex, Ux, Ib }, PREFIX_DATA },
3053   },
3054   /* REG_VEX_0FAE */
3055   {
3056     { Bad_Opcode },
3057     { Bad_Opcode },
3058     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2) },
3059     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3) },
3060   },
3061   /* REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0 */
3062   {
3063     { RM_TABLE (RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0) },
3064   },
3065   /* REG_VEX_0F38F3_L_0_P_0 */
3066   {
3067     { Bad_Opcode },
3068     { "%NFblsrS",               { VexGdq, Edq }, 0 },
3069     { "%NFblsmskS",             { VexGdq, Edq }, 0 },
3070     { "%NFblsiS",               { VexGdq, Edq }, 0 },
3071   },
3072   /* REG_VEX_MAP7_F6_L_0_W_0 */
3073   {
3074     { X86_64_TABLE (X86_64_VEX_MAP7_F6_L_0_W_0_R_0) },
3075   },
3076   /* REG_VEX_MAP7_F8_L_0_W_0 */
3077   {
3078     { X86_64_TABLE (X86_64_VEX_MAP7_F8_L_0_W_0_R_0) },
3079   },
3080   /* REG_XOP_09_01_L_0 */
3081   {
3082     { Bad_Opcode },
3083     { "blcfill",        { VexGdq, Edq }, 0 },
3084     { "blsfill",        { VexGdq, Edq }, 0 },
3085     { "blcs",   { VexGdq, Edq }, 0 },
3086     { "tzmsk",  { VexGdq, Edq }, 0 },
3087     { "blcic",  { VexGdq, Edq }, 0 },
3088     { "blsic",  { VexGdq, Edq }, 0 },
3089     { "t1mskc", { VexGdq, Edq }, 0 },
3090   },
3091   /* REG_XOP_09_02_L_0 */
3092   {
3093     { Bad_Opcode },
3094     { "blcmsk", { VexGdq, Edq }, 0 },
3095     { Bad_Opcode },
3096     { Bad_Opcode },
3097     { Bad_Opcode },
3098     { Bad_Opcode },
3099     { "blci",   { VexGdq, Edq }, 0 },
3100   },
3101   /* REG_XOP_09_12_L_0 */
3102   {
3103     { "llwpcb", { Rdq }, 0 },
3104     { "slwpcb", { Rdq }, 0 },
3105   },
3106   /* REG_XOP_0A_12_L_0 */
3107   {
3108     { "lwpins", { VexGdq, Ed, Id }, 0 },
3109     { "lwpval", { VexGdq, Ed, Id }, 0 },
3110   },
3111
3112 #include "i386-dis-evex-reg.h"
3113 };
3114
3115 static const struct dis386 prefix_table[][4] = {
3116   /* PREFIX_90 */
3117   {
3118     { "xchgS", { { NOP_Fixup, 0 }, { NOP_Fixup, 1 } }, 0 },
3119     { "pause", { XX }, 0 },
3120     { "xchgS", { { NOP_Fixup, 0 }, { NOP_Fixup, 1 } }, 0 },
3121     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3122   },
3123
3124   /* PREFIX_0F00_REG_6_X86_64 */
3125   {
3126     { Bad_Opcode },
3127     { Bad_Opcode },
3128     { Bad_Opcode },
3129     { "lkgsD", { Sv }, 0 },
3130   },
3131
3132   /* PREFIX_0F01_REG_0_MOD_3_RM_6 */
3133   {
3134     { "wrmsrns",        { Skip_MODRM }, 0 },
3135     { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_1) },
3136     { Bad_Opcode },
3137     { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_3) },
3138   },
3139
3140   /* PREFIX_0F01_REG_0_MOD_3_RM_7 */
3141   {
3142     { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_7_P_0) },
3143   },
3144
3145   /* PREFIX_0F01_REG_1_RM_2 */
3146   {
3147     { "clac",           { Skip_MODRM }, 0 },
3148     { X86_64_TABLE (X86_64_0F01_REG_1_RM_2_PREFIX_1) },
3149     { Bad_Opcode },
3150     { X86_64_TABLE (X86_64_0F01_REG_1_RM_2_PREFIX_3)},
3151   },
3152
3153   /* PREFIX_0F01_REG_1_RM_4 */
3154   {
3155     { Bad_Opcode },
3156     { Bad_Opcode },
3157     { "tdcall",         { Skip_MODRM }, 0 },
3158     { Bad_Opcode },
3159   },
3160
3161   /* PREFIX_0F01_REG_1_RM_5 */
3162   {
3163     { Bad_Opcode },
3164     { Bad_Opcode },
3165     { X86_64_TABLE (X86_64_0F01_REG_1_RM_5_PREFIX_2) },
3166     { Bad_Opcode },
3167   },
3168
3169   /* PREFIX_0F01_REG_1_RM_6 */
3170   {
3171     { Bad_Opcode },
3172     { Bad_Opcode },
3173     { X86_64_TABLE (X86_64_0F01_REG_1_RM_6_PREFIX_2) },
3174     { Bad_Opcode },
3175   },
3176
3177   /* PREFIX_0F01_REG_1_RM_7 */
3178   {
3179     { "encls",          { Skip_MODRM }, 0 },
3180     { Bad_Opcode },
3181     { X86_64_TABLE (X86_64_0F01_REG_1_RM_7_PREFIX_2) },
3182     { Bad_Opcode },
3183   },
3184
3185   /* PREFIX_0F01_REG_3_RM_1 */
3186   {
3187     { "vmmcall",        { Skip_MODRM }, 0 },
3188     { "vmgexit",        { Skip_MODRM }, 0 },
3189     { Bad_Opcode },
3190     { "vmgexit",        { Skip_MODRM }, 0 },
3191   },
3192
3193   /* PREFIX_0F01_REG_5_MOD_0 */
3194   {
3195     { Bad_Opcode },
3196     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3197   },
3198
3199   /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3200   {
3201     { "serialize",      { Skip_MODRM }, PREFIX_OPCODE },
3202     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3203     { Bad_Opcode },
3204     { "xsusldtrk",      { Skip_MODRM }, PREFIX_OPCODE },
3205   },
3206
3207   /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3208   {
3209     { Bad_Opcode },
3210     { Bad_Opcode },
3211     { Bad_Opcode },
3212     { "xresldtrk",     { Skip_MODRM }, PREFIX_OPCODE },
3213   },
3214
3215   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3216   {
3217     { Bad_Opcode },
3218     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3219   },
3220
3221   /* PREFIX_0F01_REG_5_MOD_3_RM_4 */
3222   {
3223     { Bad_Opcode },
3224     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1) },
3225   },
3226
3227   /* PREFIX_0F01_REG_5_MOD_3_RM_5 */
3228   {
3229     { Bad_Opcode },
3230     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1) },
3231   },
3232
3233   /* PREFIX_0F01_REG_5_MOD_3_RM_6 */
3234   {
3235     { "rdpkru", { Skip_MODRM }, 0 },
3236     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1) },
3237   },
3238
3239   /* PREFIX_0F01_REG_5_MOD_3_RM_7 */
3240   {
3241     { "wrpkru", { Skip_MODRM }, 0 },
3242     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1) },
3243   },
3244
3245   /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3246   {
3247     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
3248     { "mcommit",        { Skip_MODRM }, 0 },
3249   },
3250
3251   /* PREFIX_0F01_REG_7_MOD_3_RM_5 */
3252   {
3253     { "rdpru", { Skip_MODRM }, 0 },
3254     { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1) },
3255   },
3256
3257   /* PREFIX_0F01_REG_7_MOD_3_RM_6 */
3258   {
3259     { "invlpgb",        { Skip_MODRM }, 0 },
3260     { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1) },
3261     { Bad_Opcode },
3262     { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3) },
3263   },
3264
3265   /* PREFIX_0F01_REG_7_MOD_3_RM_7 */
3266   {
3267     { "tlbsync",        { Skip_MODRM }, 0 },
3268     { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1) },
3269     { Bad_Opcode },
3270     { "pvalidate",      { Skip_MODRM }, 0 },
3271   },
3272
3273   /* PREFIX_0F09 */
3274   {
3275     { "wbinvd",   { XX }, 0 },
3276     { "wbnoinvd", { XX }, 0 },
3277   },
3278
3279   /* PREFIX_0F10 */
3280   {
3281     { "%XEVmovupX",     { XM, EXEvexXNoBcst }, 0 },
3282     { "%XEVmovs%XS",    { XMScalar, VexScalarR, EXd }, 0 },
3283     { "%XEVmovupX",     { XM, EXEvexXNoBcst }, 0 },
3284     { "%XEVmovs%XD",    { XMScalar, VexScalarR, EXq }, 0 },
3285   },
3286
3287   /* PREFIX_0F11 */
3288   {
3289     { "%XEVmovupX",     { EXxS, XM }, 0 },
3290     { "%XEVmovs%XS",    { EXdS, VexScalarR, XMScalar }, 0 },
3291     { "%XEVmovupX",     { EXxS, XM }, 0 },
3292     { "%XEVmovs%XD",    { EXqS, VexScalarR, XMScalar }, 0 },
3293   },
3294
3295   /* PREFIX_0F12 */
3296   {
3297     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3298     { "movsldup",       { XM, EXx }, 0 },
3299     { "%XEVmovlpYX",    { XM, Vex, Mq }, 0 },
3300     { "movddup",        { XM, EXq }, 0 },
3301   },
3302
3303   /* PREFIX_0F16 */
3304   {
3305     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3306     { "movshdup",       { XM, EXx }, 0 },
3307     { "%XEVmovhpYX",    { XM, Vex, Mq }, 0 },
3308   },
3309
3310   /* PREFIX_0F18_REG_6_MOD_0_X86_64 */
3311   {
3312     { "prefetchit1",    { { PREFETCHI_Fixup, b_mode } }, 0 },
3313     { "nopQ",           { Ev }, 0 },
3314     { "nopQ",           { Ev }, 0 },
3315     { "nopQ",           { Ev }, 0 },
3316   },
3317
3318   /* PREFIX_0F18_REG_7_MOD_0_X86_64 */
3319   {
3320     { "prefetchit0",    { { PREFETCHI_Fixup, b_mode } }, 0 },
3321     { "nopQ",           { Ev }, 0 },
3322     { "nopQ",           { Ev }, 0 },
3323     { "nopQ",           { Ev }, 0 },
3324   },
3325
3326   /* PREFIX_0F1A */
3327   {
3328     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3329     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3330     { "bndmov", { Gbnd, Ebnd }, 0 },
3331     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3332   },
3333
3334   /* PREFIX_0F1B */
3335   {
3336     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3337     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3338     { "bndmov", { EbndS, Gbnd }, 0 },
3339     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3340   },
3341
3342   /* PREFIX_0F1C */
3343   {
3344     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3345     { "nopQ",   { Ev }, PREFIX_IGNORED },
3346     { "nopQ",   { Ev }, 0 },
3347     { "nopQ",   { Ev }, PREFIX_IGNORED },
3348   },
3349
3350   /* PREFIX_0F1E */
3351   {
3352     { "nopQ",   { Ev }, 0 },
3353     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3354     { "nopQ",   { Ev }, 0 },
3355     { NULL,     { XX }, PREFIX_IGNORED },
3356   },
3357
3358   /* PREFIX_0F2A */
3359   {
3360     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3361     { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE },
3362     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3363     { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 },
3364   },
3365
3366   /* PREFIX_0F2B */
3367   {
3368     { "movntps", { Mx, XM }, 0 },
3369     { "movntss", { Md, XM }, 0 },
3370     { "movntpd", { Mx, XM }, 0 },
3371     { "movntsd", { Mq, XM }, 0 },
3372   },
3373
3374   /* PREFIX_0F2C */
3375   {
3376     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3377     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3378     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3379     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3380   },
3381
3382   /* PREFIX_0F2D */
3383   {
3384     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3385     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3386     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3387     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3388   },
3389
3390   /* PREFIX_0F2E */
3391   {
3392     { "VucomisYX",      { XMScalar, EXd, EXxEVexS }, 0 },
3393     { Bad_Opcode },
3394     { "VucomisYX",      { XMScalar, EXq, EXxEVexS }, 0 },
3395   },
3396
3397   /* PREFIX_0F2F */
3398   {
3399     { "VcomisYX",       { XMScalar, EXd, EXxEVexS }, 0 },
3400     { Bad_Opcode },
3401     { "VcomisYX",       { XMScalar, EXq, EXxEVexS }, 0 },
3402   },
3403
3404   /* PREFIX_0F51 */
3405   {
3406     { "%XEVsqrtpX",     { XM, EXx, EXxEVexR }, 0 },
3407     { "%XEVsqrts%XS",   { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3408     { "%XEVsqrtpX",     { XM, EXx, EXxEVexR }, 0 },
3409     { "%XEVsqrts%XD",   { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3410   },
3411
3412   /* PREFIX_0F52 */
3413   {
3414     { "Vrsqrtps",       { XM, EXx }, 0 },
3415     { "Vrsqrtss",       { XMScalar, VexScalar, EXd }, 0 },
3416   },
3417
3418   /* PREFIX_0F53 */
3419   {
3420     { "Vrcpps",         { XM, EXx }, 0 },
3421     { "Vrcpss",         { XMScalar, VexScalar, EXd }, 0 },
3422   },
3423
3424   /* PREFIX_0F58 */
3425   {
3426     { "%XEVaddpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3427     { "%XEVadds%XS",    { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3428     { "%XEVaddpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3429     { "%XEVadds%XD",    { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3430   },
3431
3432   /* PREFIX_0F59 */
3433   {
3434     { "%XEVmulpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3435     { "%XEVmuls%XS",    { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3436     { "%XEVmulpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3437     { "%XEVmuls%XD",    { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3438   },
3439
3440   /* PREFIX_0F5A */
3441   {
3442     { "%XEVcvtp%XS2pd", { XM, EXEvexHalfBcstXmmq, EXxEVexS }, 0 },
3443     { "%XEVcvts%XS2sd", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3444     { "%XEVcvtp%XD2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
3445     { "%XEVcvts%XD2ss", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3446   },
3447
3448   /* PREFIX_0F5B */
3449   {
3450     { "Vcvtdq2ps",      { XM, EXx }, 0 },
3451     { "Vcvttps2dq",     { XM, EXx }, 0 },
3452     { "Vcvtps2dq",      { XM, EXx }, 0 },
3453   },
3454
3455   /* PREFIX_0F5C */
3456   {
3457     { "%XEVsubpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3458     { "%XEVsubs%XS",    { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3459     { "%XEVsubpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3460     { "%XEVsubs%XD",    { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3461   },
3462
3463   /* PREFIX_0F5D */
3464   {
3465     { "%XEVminpX",      { XM, Vex, EXx, EXxEVexS }, 0 },
3466     { "%XEVmins%XS",    { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3467     { "%XEVminpX",      { XM, Vex, EXx, EXxEVexS }, 0 },
3468     { "%XEVmins%XD",    { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
3469   },
3470
3471   /* PREFIX_0F5E */
3472   {
3473     { "%XEVdivpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3474     { "%XEVdivs%XS",    { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3475     { "%XEVdivpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3476     { "%XEVdivs%XD",    { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3477   },
3478
3479   /* PREFIX_0F5F */
3480   {
3481     { "%XEVmaxpX",      { XM, Vex, EXx, EXxEVexS }, 0 },
3482     { "%XEVmaxs%XS",    { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3483     { "%XEVmaxpX",      { XM, Vex, EXx, EXxEVexS }, 0 },
3484     { "%XEVmaxs%XD",    { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
3485   },
3486
3487   /* PREFIX_0F60 */
3488   {
3489     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3490     { Bad_Opcode },
3491     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3492   },
3493
3494   /* PREFIX_0F61 */
3495   {
3496     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3497     { Bad_Opcode },
3498     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3499   },
3500
3501   /* PREFIX_0F62 */
3502   {
3503     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3504     { Bad_Opcode },
3505     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3506   },
3507
3508   /* PREFIX_0F6F */
3509   {
3510     { "movq",   { MX, EM }, PREFIX_OPCODE },
3511     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3512     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3513   },
3514
3515   /* PREFIX_0F70 */
3516   {
3517     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3518     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3519     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3520     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3521   },
3522
3523   /* PREFIX_0F78 */
3524   {
3525     {"vmread",  { Em, Gm }, 0 },
3526     { Bad_Opcode },
3527     {"extrq",   { Uxmm, Ib, Ib }, 0 },
3528     {"insertq", { XM, Uxmm, Ib, Ib }, 0 },
3529   },
3530
3531   /* PREFIX_0F79 */
3532   {
3533     {"vmwrite", { Gm, Em }, 0 },
3534     { Bad_Opcode },
3535     {"extrq",   { XM, Uxmm }, 0 },
3536     {"insertq", { XM, Uxmm }, 0 },
3537   },
3538
3539   /* PREFIX_0F7C */
3540   {
3541     { Bad_Opcode },
3542     { Bad_Opcode },
3543     { "Vhaddpd",        { XM, Vex, EXx }, 0 },
3544     { "Vhaddps",        { XM, Vex, EXx }, 0 },
3545   },
3546
3547   /* PREFIX_0F7D */
3548   {
3549     { Bad_Opcode },
3550     { Bad_Opcode },
3551     { "Vhsubpd",        { XM, Vex, EXx }, 0 },
3552     { "Vhsubps",        { XM, Vex, EXx }, 0 },
3553   },
3554
3555   /* PREFIX_0F7E */
3556   {
3557     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3558     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3559     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3560   },
3561
3562   /* PREFIX_0F7F */
3563   {
3564     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3565     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3566     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3567   },
3568
3569   /* PREFIX_0FA6_REG_0 */
3570   {
3571     { Bad_Opcode },
3572     { "montmul",        { { MONTMUL_Fixup, 0 } }, 0},
3573     { Bad_Opcode },
3574     { "sm2",    { Skip_MODRM }, 0 },
3575   },
3576
3577   /* PREFIX_0FA6_REG_5 */
3578   {
3579     { Bad_Opcode },
3580     { "sm3",    { Skip_MODRM }, 0 },
3581   },
3582
3583   /* PREFIX_0FA7_REG_6 */
3584   {
3585     { Bad_Opcode },
3586     { "sm4",    { Skip_MODRM }, 0 },
3587   },
3588
3589   /* PREFIX_0FAE_REG_0_MOD_3 */
3590   {
3591     { Bad_Opcode },
3592     { "rdfsbase", { Ev }, 0 },
3593   },
3594
3595   /* PREFIX_0FAE_REG_1_MOD_3 */
3596   {
3597     { Bad_Opcode },
3598     { "rdgsbase", { Ev }, 0 },
3599   },
3600
3601   /* PREFIX_0FAE_REG_2_MOD_3 */
3602   {
3603     { Bad_Opcode },
3604     { "wrfsbase", { Ev }, 0 },
3605   },
3606
3607   /* PREFIX_0FAE_REG_3_MOD_3 */
3608   {
3609     { Bad_Opcode },
3610     { "wrgsbase", { Ev }, 0 },
3611   },
3612
3613   /* PREFIX_0FAE_REG_4_MOD_0 */
3614   {
3615     { "xsave",  { FXSAVE }, PREFIX_REX2_ILLEGAL },
3616     { "ptwrite{%LQ|}", { Edq }, 0 },
3617   },
3618
3619   /* PREFIX_0FAE_REG_4_MOD_3 */
3620   {
3621     { Bad_Opcode },
3622     { "ptwrite{%LQ|}", { Edq }, 0 },
3623   },
3624
3625   /* PREFIX_0FAE_REG_5_MOD_3 */
3626   {
3627     { "lfence",         { Skip_MODRM }, 0 },
3628     { "incsspK",        { Edq }, PREFIX_OPCODE },
3629   },
3630
3631   /* PREFIX_0FAE_REG_6_MOD_0 */
3632   {
3633     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE | PREFIX_REX2_ILLEGAL },
3634     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
3635     { "clwb",   { Mb }, PREFIX_OPCODE },
3636   },
3637
3638   /* PREFIX_0FAE_REG_6_MOD_3 */
3639   {
3640     { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3641     { "umonitor",       { Eva }, PREFIX_OPCODE },
3642     { "tpause", { Edq }, PREFIX_OPCODE },
3643     { "umwait", { Edq }, PREFIX_OPCODE },
3644   },
3645
3646   /* PREFIX_0FAE_REG_7_MOD_0 */
3647   {
3648     { "clflush",        { Mb }, 0 },
3649     { Bad_Opcode },
3650     { "clflushopt",     { Mb }, 0 },
3651   },
3652
3653   /* PREFIX_0FB8 */
3654   {
3655     { Bad_Opcode },
3656     { "popcntS", { Gv, Ev }, 0 },
3657   },
3658
3659   /* PREFIX_0FBC */
3660   {
3661     { "bsfS",   { Gv, Ev }, 0 },
3662     { "tzcntS", { Gv, Ev }, 0 },
3663     { "bsfS",   { Gv, Ev }, 0 },
3664   },
3665
3666   /* PREFIX_0FBD */
3667   {
3668     { "bsrS",   { Gv, Ev }, 0 },
3669     { "lzcntS", { Gv, Ev }, 0 },
3670     { "bsrS",   { Gv, Ev }, 0 },
3671   },
3672
3673   /* PREFIX_0FC2 */
3674   {
3675     { "VcmppX", { XM, Vex, EXx, CMP }, 0 },
3676     { "Vcmpss", { XMScalar, VexScalar, EXd, CMP }, 0 },
3677     { "VcmppX", { XM, Vex, EXx, CMP }, 0 },
3678     { "Vcmpsd", { XMScalar, VexScalar, EXq, CMP }, 0 },
3679   },
3680
3681   /* PREFIX_0FC7_REG_6_MOD_0 */
3682   {
3683     { "vmptrld",{ Mq }, 0 },
3684     { "vmxon",  { Mq }, 0 },
3685     { "vmclear",{ Mq }, 0 },
3686   },
3687
3688   /* PREFIX_0FC7_REG_6_MOD_3 */
3689   {
3690     { "rdrand", { Ev }, 0 },
3691     { X86_64_TABLE (X86_64_0FC7_REG_6_MOD_3_PREFIX_1) },
3692     { "rdrand", { Ev }, 0 }
3693   },
3694
3695   /* PREFIX_0FC7_REG_7_MOD_3 */
3696   {
3697     { "rdseed", { Ev }, 0 },
3698     { "rdpid",  { Em }, 0 },
3699     { "rdseed", { Ev }, 0 },
3700   },
3701
3702   /* PREFIX_0FD0 */
3703   {
3704     { Bad_Opcode },
3705     { Bad_Opcode },
3706     { "VaddsubpX",      { XM, Vex, EXx }, 0 },
3707     { "VaddsubpX",      { XM, Vex, EXx }, 0 },
3708   },
3709
3710   /* PREFIX_0FD6 */
3711   {
3712     { Bad_Opcode },
3713     { "movq2dq",{ XM, Nq }, 0 },
3714     { "movq",   { EXqS, XM }, 0 },
3715     { "movdq2q",{ MX, Ux }, 0 },
3716   },
3717
3718   /* PREFIX_0FE6 */
3719   {
3720     { Bad_Opcode },
3721     { "Vcvtdq2pd",      { XM, EXxmmq }, 0 },
3722     { "Vcvttpd2dq%XY",  { XMM, EXx }, 0 },
3723     { "Vcvtpd2dq%XY",   { XMM, EXx }, 0 },
3724   },
3725
3726   /* PREFIX_0FE7 */
3727   {
3728     { "movntq",         { Mq, MX }, 0 },
3729     { Bad_Opcode },
3730     { "movntdq",        { Mx, XM }, 0 },
3731   },
3732
3733   /* PREFIX_0FF0 */
3734   {
3735     { Bad_Opcode },
3736     { Bad_Opcode },
3737     { Bad_Opcode },
3738     { "Vlddqu",         { XM, M }, 0 },
3739   },
3740
3741   /* PREFIX_0FF7 */
3742   {
3743     { "maskmovq", { MX, Nq }, PREFIX_OPCODE },
3744     { Bad_Opcode },
3745     { "maskmovdqu", { XM, Ux }, PREFIX_OPCODE },
3746   },
3747
3748   /* PREFIX_0F38D8 */
3749   {
3750     { Bad_Opcode },
3751     { REG_TABLE (REG_0F38D8_PREFIX_1) },
3752   },
3753
3754   /* PREFIX_0F38DC */
3755   {
3756     { Bad_Opcode },
3757     { MOD_TABLE (MOD_0F38DC_PREFIX_1) },
3758     { "aesenc", { XM, EXx }, 0 },
3759   },
3760
3761   /* PREFIX_0F38DD */
3762   {
3763     { Bad_Opcode },
3764     { "aesdec128kl", { XM, M }, 0 },
3765     { "aesenclast", { XM, EXx }, 0 },
3766   },
3767
3768   /* PREFIX_0F38DE */
3769   {
3770     { Bad_Opcode },
3771     { "aesenc256kl", { XM, M }, 0 },
3772     { "aesdec", { XM, EXx }, 0 },
3773   },
3774
3775   /* PREFIX_0F38DF */
3776   {
3777     { Bad_Opcode },
3778     { "aesdec256kl", { XM, M }, 0 },
3779     { "aesdeclast", { XM, EXx }, 0 },
3780   },
3781
3782   /* PREFIX_0F38F0 */
3783   {
3784     { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3785     { Bad_Opcode },
3786     { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3787     { "crc32A", { Gdq, Eb }, PREFIX_OPCODE },
3788   },
3789
3790   /* PREFIX_0F38F1 */
3791   {
3792     { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3793     { Bad_Opcode },
3794     { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3795     { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE },
3796   },
3797
3798   /* PREFIX_0F38F6 */
3799   {
3800     { "wrssK",  { M, Gdq }, 0 },
3801     { "adoxL",  { VexGdq, Gdq, Edq }, 0 },
3802     { "adcxL",  { VexGdq, Gdq, Edq }, 0 },
3803     { Bad_Opcode },
3804   },
3805
3806   /* PREFIX_0F38F8_M_0 */
3807   {
3808     { Bad_Opcode },
3809     { "enqcmds", { Gva, M }, 0 },
3810     { "movdir64b", { Gva, M }, 0 },
3811     { "enqcmd", { Gva, M }, 0 },
3812   },
3813
3814   /* PREFIX_0F38F8_M_1_X86_64 */
3815   {
3816     { Bad_Opcode },
3817     { "uwrmsr",         { Gq, Rq }, 0 },
3818     { Bad_Opcode },
3819     { "urdmsr",         { Rq, Gq }, 0 },
3820   },
3821
3822   /* PREFIX_0F38FA */
3823   {
3824     { Bad_Opcode },
3825     { "encodekey128", { Gd, Rd }, 0 },
3826   },
3827
3828   /* PREFIX_0F38FB */
3829   {
3830     { Bad_Opcode },
3831     { "encodekey256", { Gd, Rd }, 0 },
3832   },
3833
3834   /* PREFIX_0F38FC */
3835   {
3836     { "aadd",   { Mdq, Gdq }, 0 },
3837     { "axor",   { Mdq, Gdq }, 0 },
3838     { "aand",   { Mdq, Gdq }, 0 },
3839     { "aor",    { Mdq, Gdq }, 0 },
3840   },
3841
3842   /* PREFIX_0F3A0F */
3843   {
3844     { Bad_Opcode },
3845     { REG_TABLE (REG_0F3A0F_P_1) },
3846   },
3847
3848   /* PREFIX_VEX_0F12 */
3849   {
3850     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0) },
3851     { "%XEvmov%XSldup", { XM, EXEvexXNoBcst }, 0 },
3852     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
3853     { "%XEvmov%XDdup",  { XM, EXymmq }, 0 },
3854   },
3855
3856   /* PREFIX_VEX_0F16 */
3857   {
3858     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0) },
3859     { "%XEvmov%XShdup", { XM, EXEvexXNoBcst }, 0 },
3860     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
3861   },
3862
3863   /* PREFIX_VEX_0F2A */
3864   {
3865     { Bad_Opcode },
3866     { "%XEvcvtsi2ssY{%LQ|}",    { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
3867     { Bad_Opcode },
3868     { "%XEvcvtsi2sdY{%LQ|}",    { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
3869   },
3870
3871   /* PREFIX_VEX_0F2C */
3872   {
3873     { Bad_Opcode },
3874     { "%XEvcvttss2si",  { Gdq, EXd, EXxEVexS }, 0 },
3875     { Bad_Opcode },
3876     { "%XEvcvttsd2si",  { Gdq, EXq, EXxEVexS }, 0 },
3877   },
3878
3879   /* PREFIX_VEX_0F2D */
3880   {
3881     { Bad_Opcode },
3882     { "%XEvcvtss2si",   { Gdq, EXd, EXxEVexR }, 0 },
3883     { Bad_Opcode },
3884     { "%XEvcvtsd2si",   { Gdq, EXq, EXxEVexR }, 0 },
3885   },
3886
3887   /* PREFIX_VEX_0F41_L_1_W_0 */
3888   {
3889     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
3890     { Bad_Opcode },
3891     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
3892   },
3893
3894   /* PREFIX_VEX_0F41_L_1_W_1 */
3895   {
3896     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
3897     { Bad_Opcode },
3898     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
3899   },
3900
3901   /* PREFIX_VEX_0F42_L_1_W_0 */
3902   {
3903     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
3904     { Bad_Opcode },
3905     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
3906   },
3907
3908   /* PREFIX_VEX_0F42_L_1_W_1 */
3909   {
3910     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
3911     { Bad_Opcode },
3912     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
3913   },
3914
3915   /* PREFIX_VEX_0F44_L_0_W_0 */
3916   {
3917     { "knotw",          { MaskG, MaskR }, 0 },
3918     { Bad_Opcode },
3919     { "knotb",          { MaskG, MaskR }, 0 },
3920   },
3921
3922   /* PREFIX_VEX_0F44_L_0_W_1 */
3923   {
3924     { "knotq",          { MaskG, MaskR }, 0 },
3925     { Bad_Opcode },
3926     { "knotd",          { MaskG, MaskR }, 0 },
3927   },
3928
3929   /* PREFIX_VEX_0F45_L_1_W_0 */
3930   {
3931     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
3932     { Bad_Opcode },
3933     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
3934   },
3935
3936   /* PREFIX_VEX_0F45_L_1_W_1 */
3937   {
3938     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
3939     { Bad_Opcode },
3940     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
3941   },
3942
3943   /* PREFIX_VEX_0F46_L_1_W_0 */
3944   {
3945     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
3946     { Bad_Opcode },
3947     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
3948   },
3949
3950   /* PREFIX_VEX_0F46_L_1_W_1 */
3951   {
3952     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
3953     { Bad_Opcode },
3954     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
3955   },
3956
3957   /* PREFIX_VEX_0F47_L_1_W_0 */
3958   {
3959     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
3960     { Bad_Opcode },
3961     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
3962   },
3963
3964   /* PREFIX_VEX_0F47_L_1_W_1 */
3965   {
3966     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
3967     { Bad_Opcode },
3968     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
3969   },
3970
3971   /* PREFIX_VEX_0F4A_L_1_W_0 */
3972   {
3973     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
3974     { Bad_Opcode },
3975     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
3976   },
3977
3978   /* PREFIX_VEX_0F4A_L_1_W_1 */
3979   {
3980     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
3981     { Bad_Opcode },
3982     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
3983   },
3984
3985   /* PREFIX_VEX_0F4B_L_1_W_0 */
3986   {
3987     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
3988     { Bad_Opcode },
3989     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
3990   },
3991
3992   /* PREFIX_VEX_0F4B_L_1_W_1 */
3993   {
3994     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
3995   },
3996
3997   /* PREFIX_VEX_0F6F */
3998   {
3999     { Bad_Opcode },
4000     { "vmovdqu",        { XM, EXx }, 0 },
4001     { "vmovdqa",        { XM, EXx }, 0 },
4002   },
4003
4004   /* PREFIX_VEX_0F70 */
4005   {
4006     { Bad_Opcode },
4007     { "vpshufhw",       { XM, EXx, Ib }, 0 },
4008     { "vpshufd",        { XM, EXx, Ib }, 0 },
4009     { "vpshuflw",       { XM, EXx, Ib }, 0 },
4010   },
4011
4012   /* PREFIX_VEX_0F7E */
4013   {
4014     { Bad_Opcode },
4015     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
4016     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
4017   },
4018
4019   /* PREFIX_VEX_0F7F */
4020   {
4021     { Bad_Opcode },
4022     { "vmovdqu",        { EXxS, XM }, 0 },
4023     { "vmovdqa",        { EXxS, XM }, 0 },
4024   },
4025
4026   /* PREFIX_VEX_0F90_L_0_W_0 */
4027   {
4028     { "%XEkmovw",               { MaskG, MaskE }, 0 },
4029     { Bad_Opcode },
4030     { "%XEkmovb",               { MaskG, MaskBDE }, 0 },
4031   },
4032
4033   /* PREFIX_VEX_0F90_L_0_W_1 */
4034   {
4035     { "%XEkmovq",               { MaskG, MaskE }, 0 },
4036     { Bad_Opcode },
4037     { "%XEkmovd",               { MaskG, MaskBDE }, 0 },
4038   },
4039
4040   /* PREFIX_VEX_0F91_L_0_W_0 */
4041   {
4042     { "%XEkmovw",               { Mw, MaskG }, 0 },
4043     { Bad_Opcode },
4044     { "%XEkmovb",               { Mb, MaskG }, 0 },
4045   },
4046
4047   /* PREFIX_VEX_0F91_L_0_W_1 */
4048   {
4049     { "%XEkmovq",               { Mq, MaskG }, 0 },
4050     { Bad_Opcode },
4051     { "%XEkmovd",               { Md, MaskG }, 0 },
4052   },
4053
4054   /* PREFIX_VEX_0F92_L_0_W_0 */
4055   {
4056     { "%XEkmovw",               { MaskG, Rdq }, 0 },
4057     { Bad_Opcode },
4058     { "%XEkmovb",               { MaskG, Rdq }, 0 },
4059     { "%XEkmovd",               { MaskG, Rdq }, 0 },
4060   },
4061
4062   /* PREFIX_VEX_0F92_L_0_W_1 */
4063   {
4064     { Bad_Opcode },
4065     { Bad_Opcode },
4066     { Bad_Opcode },
4067     { "%XEkmovK",               { MaskG, Rdq }, 0 },
4068   },
4069
4070   /* PREFIX_VEX_0F93_L_0_W_0 */
4071   {
4072     { "%XEkmovw",               { Gdq, MaskR }, 0 },
4073     { Bad_Opcode },
4074     { "%XEkmovb",               { Gdq, MaskR }, 0 },
4075     { "%XEkmovd",               { Gdq, MaskR }, 0 },
4076   },
4077
4078   /* PREFIX_VEX_0F93_L_0_W_1 */
4079   {
4080     { Bad_Opcode },
4081     { Bad_Opcode },
4082     { Bad_Opcode },
4083     { "%XEkmovK",               { Gdq, MaskR }, 0 },
4084   },
4085
4086   /* PREFIX_VEX_0F98_L_0_W_0 */
4087   {
4088     { "kortestw", { MaskG, MaskR }, 0 },
4089     { Bad_Opcode },
4090     { "kortestb", { MaskG, MaskR }, 0 },
4091   },
4092
4093   /* PREFIX_VEX_0F98_L_0_W_1 */
4094   {
4095     { "kortestq", { MaskG, MaskR }, 0 },
4096     { Bad_Opcode },
4097     { "kortestd", { MaskG, MaskR }, 0 },
4098   },
4099
4100   /* PREFIX_VEX_0F99_L_0_W_0 */
4101   {
4102     { "ktestw", { MaskG, MaskR }, 0 },
4103     { Bad_Opcode },
4104     { "ktestb", { MaskG, MaskR }, 0 },
4105   },
4106
4107   /* PREFIX_VEX_0F99_L_0_W_1 */
4108   {
4109     { "ktestq", { MaskG, MaskR }, 0 },
4110     { Bad_Opcode },
4111     { "ktestd", { MaskG, MaskR }, 0 },
4112   },
4113
4114   /* PREFIX_VEX_0F3848_X86_64_L_0_W_0 */
4115   {
4116     { "ttmmultf32ps",   { TMM, Rtmm, VexTmm }, 0 },
4117     { Bad_Opcode },
4118     { "tmmultf32ps",    { TMM, Rtmm, VexTmm }, 0 },
4119   },
4120
4121   /* PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0 */
4122   {
4123     { "ldtilecfg", { M }, 0 },
4124     { Bad_Opcode },
4125     { "sttilecfg", { M }, 0 },
4126   },
4127
4128   /* PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1 */
4129   {
4130     { REG_TABLE (REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0) },
4131     { Bad_Opcode },
4132     { Bad_Opcode },
4133     { RM_TABLE (RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3) },
4134   },
4135
4136   /* PREFIX_VEX_0F384A_X86_64_W_0_L_0 */
4137   {
4138     { Bad_Opcode },
4139     { Bad_Opcode },
4140     { "tileloaddrst1",  { TMM, MVexSIBMEM }, 0 },
4141     { "tileloaddrs",    { TMM, MVexSIBMEM }, 0 },
4142   },
4143
4144   /* PREFIX_VEX_0F384B_X86_64_L_0_W_0 */
4145   {
4146     { Bad_Opcode },
4147     { "tilestored",     { MVexSIBMEM, TMM }, 0 },
4148     { "tileloaddt1",    { TMM, MVexSIBMEM }, 0 },
4149     { "tileloadd",      { TMM, MVexSIBMEM }, 0 },
4150   },
4151
4152   /* PREFIX_VEX_0F3850_W_0 */
4153   {
4154     { "%XEvpdpbuud",    { XM, Vex, EXx }, 0 },
4155     { "%XEvpdpbsud",    { XM, Vex, EXx }, 0 },
4156     { "%XVvpdpbusd",    { XM, Vex, EXx }, 0 },
4157     { "%XEvpdpbssd",    { XM, Vex, EXx }, 0 },
4158   },
4159
4160   /* PREFIX_VEX_0F3851_W_0 */
4161   {
4162     { "%XEvpdpbuuds",   { XM, Vex, EXx }, 0 },
4163     { "%XEvpdpbsuds",   { XM, Vex, EXx }, 0 },
4164     { "%XVvpdpbusds",   { XM, Vex, EXx }, 0 },
4165     { "%XEvpdpbssds",   { XM, Vex, EXx }, 0 },
4166   },
4167   /* PREFIX_VEX_0F385C_X86_64_L_0_W_0 */
4168   {
4169     { Bad_Opcode },
4170     { "tdpbf16ps", { TMM, Rtmm, VexTmm }, 0 },
4171     { Bad_Opcode },
4172     { "tdpfp16ps", { TMM, Rtmm, VexTmm }, 0 },
4173   },
4174
4175   /* PREFIX_VEX_0F385E_X86_64_L_0_W_0 */
4176   {
4177     { "tdpbuud", {TMM, Rtmm, VexTmm }, 0 },
4178     { "tdpbsud", {TMM, Rtmm, VexTmm }, 0 },
4179     { "tdpbusd", {TMM, Rtmm, VexTmm }, 0 },
4180     { "tdpbssd", {TMM, Rtmm, VexTmm }, 0 },
4181   },
4182
4183   /* PREFIX_VEX_0F385F_X86_64_L_0_W_0 */
4184   {
4185     { Bad_Opcode },
4186     { "ttransposed",    { TMM, Rtmm }, 0 },
4187   },
4188
4189   /* PREFIX_VEX_0F386B_X86_64_L_0_W_0 */
4190   {
4191     { "tconjtcmmimfp16ps",      { TMM, Rtmm, VexTmm }, 0 },
4192     { "ttcmmrlfp16ps",  { TMM, Rtmm, VexTmm }, 0 },
4193     { "tconjtfp16",     { TMM, Rtmm }, 0 },
4194     { "ttcmmimfp16ps",  { TMM, Rtmm, VexTmm }, 0 },
4195   },
4196
4197   /* PREFIX_VEX_0F386C_X86_64_L_0_W_0 */
4198   {
4199     { "tcmmrlfp16ps",   { TMM, Rtmm, VexTmm }, 0 },
4200     { "ttdpbf16ps",     { TMM, Rtmm, VexTmm }, 0 },
4201     { "tcmmimfp16ps",   { TMM, Rtmm, VexTmm }, 0 },
4202     { "ttdpfp16ps",     { TMM, Rtmm, VexTmm }, 0 },
4203   },
4204
4205   /* PREFIX_VEX_0F386E_X86_64_L_0_W_0 */
4206   {
4207     { "t2rpntlvwz0",    { TMM, MVexSIBMEM }, 0 },
4208     { Bad_Opcode },
4209     { "t2rpntlvwz1",    { TMM, MVexSIBMEM }, 0 },
4210   },
4211
4212   /* PREFIX_VEX_0F386F_X86_64_L_0_W_0 */
4213   {
4214     { "t2rpntlvwz0t1",  { TMM, MVexSIBMEM }, 0 },
4215     { Bad_Opcode },
4216     { "t2rpntlvwz1t1",  { TMM, MVexSIBMEM }, 0 },
4217   },
4218
4219   /* PREFIX_VEX_0F3872 */
4220   {
4221     { Bad_Opcode },
4222     { VEX_W_TABLE (VEX_W_0F3872_P_1) },
4223   },
4224
4225   /* PREFIX_VEX_0F38B0_W_0 */
4226   {
4227     { "vcvtneoph2ps", { XM, Mx }, 0 },
4228     { "vcvtneebf162ps", { XM, Mx }, 0 },
4229     { "vcvtneeph2ps", { XM, Mx }, 0 },
4230     { "vcvtneobf162ps", { XM, Mx }, 0 },
4231   },
4232
4233   /* PREFIX_VEX_0F38B1_W_0 */
4234   {
4235     { Bad_Opcode },
4236     { "vbcstnebf162ps", { XM, Mw }, 0 },
4237     { "vbcstnesh2ps", { XM, Mw }, 0 },
4238   },
4239
4240   /* PREFIX_VEX_0F38D2_W_0 */
4241   {
4242     { "%XEvpdpwuud",    { XM, Vex, EXx }, 0 },
4243     { "%XEvpdpwsud",    { XM, Vex, EXx }, 0 },
4244     { "%XEvpdpwusd",    { XM, Vex, EXx }, 0 },
4245   },
4246
4247   /* PREFIX_VEX_0F38D3_W_0 */
4248   {
4249     { "%XEvpdpwuuds",   { XM, Vex, EXx }, 0 },
4250     { "%XEvpdpwsuds",   { XM, Vex, EXx }, 0 },
4251     { "%XEvpdpwusds",   { XM, Vex, EXx }, 0 },
4252   },
4253
4254   /* PREFIX_VEX_0F38CB */
4255   {
4256     { Bad_Opcode },
4257     { Bad_Opcode },
4258     { Bad_Opcode },
4259     { VEX_W_TABLE (VEX_W_0F38CB_P_3) },
4260   },
4261
4262   /* PREFIX_VEX_0F38CC */
4263   {
4264     { Bad_Opcode },
4265     { Bad_Opcode },
4266     { Bad_Opcode },
4267     { VEX_W_TABLE (VEX_W_0F38CC_P_3) },
4268   },
4269
4270   /* PREFIX_VEX_0F38CD */
4271   {
4272     { Bad_Opcode },
4273     { Bad_Opcode },
4274     { Bad_Opcode },
4275     { VEX_W_TABLE (VEX_W_0F38CD_P_3) },
4276   },
4277
4278   /* PREFIX_VEX_0F38DA_W_0 */
4279   {
4280     { VEX_LEN_TABLE (VEX_LEN_0F38DA_W_0_P_0) },
4281     { "%XEvsm4key4",    { XM, Vex, EXx }, 0 },
4282     { VEX_LEN_TABLE (VEX_LEN_0F38DA_W_0_P_2) },
4283     { "%XEvsm4rnds4",   { XM, Vex, EXx }, 0 },
4284   },
4285
4286   /* PREFIX_VEX_0F38F2_L_0 */
4287   {
4288     { "%NFandnS",          { Gdq, VexGdq, Edq }, 0 },
4289   },
4290
4291   /* PREFIX_VEX_0F38F3_L_0 */
4292   {
4293     { REG_TABLE (REG_VEX_0F38F3_L_0_P_0) },
4294   },
4295
4296   /* PREFIX_VEX_0F38F5_L_0 */
4297   {
4298     { "%NFbzhiS",       { Gdq, Edq, VexGdq }, 0 },
4299     { "%XEpextS",               { Gdq, VexGdq, Edq }, 0 },
4300     { Bad_Opcode },
4301     { "%XEpdepS",               { Gdq, VexGdq, Edq }, 0 },
4302   },
4303
4304   /* PREFIX_VEX_0F38F6_L_0 */
4305   {
4306     { Bad_Opcode },
4307     { Bad_Opcode },
4308     { Bad_Opcode },
4309     { "%XEmulxS",               { Gdq, VexGdq, Edq }, 0 },
4310   },
4311
4312   /* PREFIX_VEX_0F38F7_L_0 */
4313   {
4314     { "%NFbextrS",      { Gdq, Edq, VexGdq }, 0 },
4315     { "%XEsarxS",               { Gdq, Edq, VexGdq }, 0 },
4316     { "%XEshlxS",               { Gdq, Edq, VexGdq }, 0 },
4317     { "%XEshrxS",               { Gdq, Edq, VexGdq }, 0 },
4318   },
4319
4320   /* PREFIX_VEX_0F3AF0_L_0 */
4321   {
4322     { Bad_Opcode },
4323     { Bad_Opcode },
4324     { Bad_Opcode },
4325     { "%XErorxS",               { Gdq, Edq, Ib }, 0 },
4326   },
4327
4328   /* PREFIX_VEX_MAP5_F8_X86_64_L_0_W_0 */
4329   {
4330     { "t2rpntlvwz0rs",  { TMM, MVexSIBMEM }, 0 },
4331     { Bad_Opcode },
4332     { "t2rpntlvwz1rs",  { TMM, MVexSIBMEM }, 0 },
4333   },
4334
4335   /* PREFIX_VEX_MAP5_F9_X86_64_L_0_W_0 */
4336   {
4337     { "t2rpntlvwz0rst1",        { TMM, MVexSIBMEM }, 0 },
4338     { Bad_Opcode },
4339     { "t2rpntlvwz1rst1",        { TMM, MVexSIBMEM }, 0 },
4340   },
4341
4342   /* PREFIX_VEX_MAP5_FD_X86_64_L_0_W_0 */
4343   {
4344     { "tdpbf8ps",       { TMM, Rtmm, VexTmm }, 0 },
4345     { "tdphbf8ps",      { TMM, Rtmm, VexTmm }, 0 },
4346     { "tdphf8ps",       { TMM, Rtmm, VexTmm }, 0 },
4347     { "tdpbhf8ps",      { TMM, Rtmm, VexTmm }, 0 },
4348   },
4349
4350   /* PREFIX_VEX_MAP7_F6_L_0_W_0_R_0_X86_64 */
4351   {
4352     { Bad_Opcode },
4353     { "wrmsrns",        { Skip_MODRM, Id, Rq }, 0 },
4354     { Bad_Opcode },
4355     { "rdmsr",          { Rq, Id }, 0 },
4356   },
4357
4358   /* PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64 */
4359   {
4360     { Bad_Opcode },
4361     { "uwrmsr", { Skip_MODRM, Id, Rq }, 0 },
4362     { Bad_Opcode },
4363     { "urdmsr", { Rq, Id }, 0 },
4364   },
4365
4366 #include "i386-dis-evex-prefix.h"
4367 };
4368
4369 static const struct dis386 x86_64_table[][2] = {
4370   /* X86_64_06 */
4371   {
4372     { "pushP", { es }, 0 },
4373   },
4374
4375   /* X86_64_07 */
4376   {
4377     { "popP", { es }, 0 },
4378   },
4379
4380   /* X86_64_0E */
4381   {
4382     { "pushP", { cs }, 0 },
4383   },
4384
4385   /* X86_64_16 */
4386   {
4387     { "pushP", { ss }, 0 },
4388   },
4389
4390   /* X86_64_17 */
4391   {
4392     { "popP", { ss }, 0 },
4393   },
4394
4395   /* X86_64_1E */
4396   {
4397     { "pushP", { ds }, 0 },
4398   },
4399
4400   /* X86_64_1F */
4401   {
4402     { "popP", { ds }, 0 },
4403   },
4404
4405   /* X86_64_27 */
4406   {
4407     { "daa", { XX }, 0 },
4408   },
4409
4410   /* X86_64_2F */
4411   {
4412     { "das", { XX }, 0 },
4413   },
4414
4415   /* X86_64_37 */
4416   {
4417     { "aaa", { XX }, 0 },
4418   },
4419
4420   /* X86_64_3F */
4421   {
4422     { "aas", { XX }, 0 },
4423   },
4424
4425   /* X86_64_60 */
4426   {
4427     { "pushaP", { XX }, 0 },
4428   },
4429
4430   /* X86_64_61 */
4431   {
4432     { "popaP", { XX }, 0 },
4433   },
4434
4435   /* X86_64_62 */
4436   {
4437     { MOD_TABLE (MOD_62_32BIT) },
4438     { EVEX_TABLE () },
4439   },
4440
4441   /* X86_64_63 */
4442   {
4443     { "arplS", { Sv, Gv }, 0 },
4444     { "movs", { Gv, { MOVSXD_Fixup, movsxd_mode } }, 0 },
4445   },
4446
4447   /* X86_64_6D */
4448   {
4449     { "ins{R|}", { Yzr, indirDX }, 0 },
4450     { "ins{G|}", { Yzr, indirDX }, 0 },
4451   },
4452
4453   /* X86_64_6F */
4454   {
4455     { "outs{R|}", { indirDXr, Xz }, 0 },
4456     { "outs{G|}", { indirDXr, Xz }, 0 },
4457   },
4458
4459   /* X86_64_82 */
4460   {
4461     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
4462     { REG_TABLE (REG_80) },
4463   },
4464
4465   /* X86_64_9A */
4466   {
4467     { "{l|}call{P|}", { Ap }, 0 },
4468   },
4469
4470   /* X86_64_C2 */
4471   {
4472     { "retP",           { Iw, BND }, 0 },
4473     { "ret@",           { Iw, BND }, 0 },
4474   },
4475
4476   /* X86_64_C3 */
4477   {
4478     { "retP",           { BND }, 0 },
4479     { "ret@",           { BND }, 0 },
4480   },
4481
4482   /* X86_64_C4 */
4483   {
4484     { MOD_TABLE (MOD_C4_32BIT) },
4485     { VEX_C4_TABLE () },
4486   },
4487
4488   /* X86_64_C5 */
4489   {
4490     { MOD_TABLE (MOD_C5_32BIT) },
4491     { VEX_C5_TABLE () },
4492   },
4493
4494   /* X86_64_CE */
4495   {
4496     { "into", { XX }, 0 },
4497   },
4498
4499   /* X86_64_D4 */
4500   {
4501     { "aam", { Ib }, 0 },
4502   },
4503
4504   /* X86_64_D5 */
4505   {
4506     { "aad", { Ib }, 0 },
4507   },
4508
4509   /* X86_64_E8 */
4510   {
4511     { "callP",          { Jv, BND }, 0 },
4512     { "call@",          { Jv, BND }, PREFIX_REX2_ILLEGAL }
4513   },
4514
4515   /* X86_64_E9 */
4516   {
4517     { "jmpP",           { Jv, BND }, 0 },
4518     { "jmp@",           { Jv, BND }, PREFIX_REX2_ILLEGAL }
4519   },
4520
4521   /* X86_64_EA */
4522   {
4523     { "{l|}jmp{P|}", { Ap }, 0 },
4524   },
4525
4526   /* X86_64_0F00_REG_6 */
4527   {
4528     { Bad_Opcode },
4529     { PREFIX_TABLE (PREFIX_0F00_REG_6_X86_64) },
4530   },
4531
4532   /* X86_64_0F01_REG_0 */
4533   {
4534     { "sgdt{Q|Q}", { M }, 0 },
4535     { "sgdt", { M }, 0 },
4536   },
4537
4538   /* X86_64_0F01_REG_0_MOD_3_RM_6_P_1 */
4539   {
4540     { Bad_Opcode },
4541     { "wrmsrlist",      { Skip_MODRM }, 0 },
4542   },
4543
4544   /* X86_64_0F01_REG_0_MOD_3_RM_6_P_3 */
4545   {
4546     { Bad_Opcode },
4547     { "rdmsrlist",      { Skip_MODRM }, 0 },
4548   },
4549
4550   /* X86_64_0F01_REG_0_MOD_3_RM_7_P_0 */
4551   {
4552     { Bad_Opcode },
4553     { "pbndkb",         { Skip_MODRM }, 0 },
4554   },
4555
4556   /* X86_64_0F01_REG_1 */
4557   {
4558     { "sidt{Q|Q}", { M }, 0 },
4559     { "sidt", { M }, 0 },
4560   },
4561
4562   /* X86_64_0F01_REG_1_RM_2_PREFIX_1 */
4563   {
4564     { Bad_Opcode },
4565     { "eretu",          { Skip_MODRM }, 0 },
4566   },
4567
4568   /* X86_64_0F01_REG_1_RM_2_PREFIX_3 */
4569   {
4570     { Bad_Opcode },
4571     { "erets",          { Skip_MODRM }, 0 },
4572   },
4573
4574   /* X86_64_0F01_REG_1_RM_5_PREFIX_2 */
4575   {
4576     { Bad_Opcode },
4577     { "seamret",        { Skip_MODRM }, 0 },
4578   },
4579
4580   /* X86_64_0F01_REG_1_RM_6_PREFIX_2 */
4581   {
4582     { Bad_Opcode },
4583     { "seamops",        { Skip_MODRM }, 0 },
4584   },
4585
4586   /* X86_64_0F01_REG_1_RM_7_PREFIX_2 */
4587   {
4588     { Bad_Opcode },
4589     { "seamcall",       { Skip_MODRM }, 0 },
4590   },
4591
4592   /* X86_64_0F01_REG_2 */
4593   {
4594     { "lgdt{Q|Q}", { M }, 0 },
4595     { "lgdt", { M }, 0 },
4596   },
4597
4598   /* X86_64_0F01_REG_3 */
4599   {
4600     { "lidt{Q|Q}", { M }, 0 },
4601     { "lidt", { M }, 0 },
4602   },
4603
4604   /* X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1 */
4605   {
4606     { Bad_Opcode },
4607     { "uiret",  { Skip_MODRM }, 0 },
4608   },
4609
4610   /* X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1 */
4611   {
4612     { Bad_Opcode },
4613     { "testui", { Skip_MODRM }, 0 },
4614   },
4615
4616   /* X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1 */
4617   {
4618     { Bad_Opcode },
4619     { "clui",   { Skip_MODRM }, 0 },
4620   },
4621
4622   /* X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1 */
4623   {
4624     { Bad_Opcode },
4625     { "stui",   { Skip_MODRM }, 0 },
4626   },
4627
4628   /* X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1 */
4629   {
4630     { Bad_Opcode },
4631     { "rmpquery", { Skip_MODRM }, 0 },
4632   },
4633
4634   /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1 */
4635   {
4636     { Bad_Opcode },
4637     { "rmpadjust",      { Skip_MODRM }, 0 },
4638   },
4639
4640   /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3 */
4641   {
4642     { Bad_Opcode },
4643     { "rmpupdate",      { Skip_MODRM }, 0 },
4644   },
4645
4646   /* X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1 */
4647   {
4648     { Bad_Opcode },
4649     { "psmash", { Skip_MODRM }, 0 },
4650   },
4651
4652   /* X86_64_0F18_REG_6_MOD_0 */
4653   {
4654     { "nopQ",           { Ev }, 0 },
4655     { PREFIX_TABLE (PREFIX_0F18_REG_6_MOD_0_X86_64) },
4656   },
4657
4658   /* X86_64_0F18_REG_7_MOD_0 */
4659   {
4660     { "nopQ",           { Ev }, 0 },
4661     { PREFIX_TABLE (PREFIX_0F18_REG_7_MOD_0_X86_64) },
4662   },
4663
4664   {
4665     /* X86_64_0F24 */
4666     { "movZ",           { Em, Td }, 0 },
4667   },
4668
4669   {
4670     /* X86_64_0F26 */
4671     { "movZ",           { Td, Em }, 0 },
4672   },
4673
4674   {
4675     /* X86_64_0F388A */
4676     { Bad_Opcode },
4677     { "movrsB",         { Gb, Mb }, PREFIX_OPCODE },
4678   },
4679
4680   {
4681     /* X86_64_0F388B */
4682     { Bad_Opcode },
4683     { "movrsS",         { Gv, Mv }, PREFIX_OPCODE },
4684   },
4685
4686   {
4687     /* X86_64_0F38F8_M_1 */
4688     { Bad_Opcode },
4689     { PREFIX_TABLE (PREFIX_0F38F8_M_1_X86_64) },
4690   },
4691
4692   /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */
4693   {
4694     { Bad_Opcode },
4695     { "senduipi",       { Eq }, 0 },
4696   },
4697
4698   /* X86_64_VEX_0F3848 */
4699   {
4700     { Bad_Opcode },
4701     { VEX_LEN_TABLE (VEX_LEN_0F3848_X86_64) },
4702   },
4703
4704   /* X86_64_VEX_0F3849 */
4705   {
4706     { Bad_Opcode },
4707     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64) },
4708   },
4709
4710   /* X86_64_VEX_0F384A */
4711   {
4712     { Bad_Opcode },
4713     { VEX_W_TABLE (VEX_W_0F384A_X86_64) },
4714   },
4715
4716   /* X86_64_VEX_0F384B */
4717   {
4718     { Bad_Opcode },
4719     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64) },
4720   },
4721
4722   /* X86_64_VEX_0F385C */
4723   {
4724     { Bad_Opcode },
4725     { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64) },
4726   },
4727
4728   /* X86_64_VEX_0F385E */
4729   {
4730     { Bad_Opcode },
4731     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64) },
4732   },
4733
4734   /* X86_64_VEX_0F385F */
4735   {
4736     { Bad_Opcode },
4737     { VEX_LEN_TABLE (VEX_LEN_0F385F_X86_64) },
4738   },
4739
4740   /* X86_64_VEX_0F386B */
4741   {
4742     { Bad_Opcode },
4743     { VEX_LEN_TABLE (VEX_LEN_0F386B_X86_64) },
4744   },
4745
4746   /* X86_64_VEX_0F386C */
4747   {
4748     { Bad_Opcode },
4749     { VEX_LEN_TABLE (VEX_LEN_0F386C_X86_64) },
4750   },
4751
4752   /* X86_64_VEX_0F386E */
4753   {
4754     { Bad_Opcode },
4755     { VEX_LEN_TABLE (VEX_LEN_0F386E_X86_64) },
4756   },
4757
4758   /* X86_64_VEX_0F386F */
4759   {
4760     { Bad_Opcode },
4761     { VEX_LEN_TABLE (VEX_LEN_0F386F_X86_64) },
4762   },
4763
4764   /* X86_64_VEX_0F38Ex */
4765   {
4766     { Bad_Opcode },
4767     { "%XEcmp%CCxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4768   },
4769
4770   /* X86_64_VEX_MAP5_F8 */
4771   {
4772     { Bad_Opcode },
4773     { VEX_LEN_TABLE (VEX_LEN_MAP5_F8_X86_64) },
4774   },
4775
4776   /* X86_64_VEX_MAP5_F9 */
4777   {
4778     { Bad_Opcode },
4779     { VEX_LEN_TABLE (VEX_LEN_MAP5_F9_X86_64) },
4780   },
4781
4782   /* X86_64_VEX_MAP5_FD */
4783   {
4784     { Bad_Opcode },
4785     { VEX_LEN_TABLE (VEX_LEN_MAP5_FD_X86_64) },
4786   },
4787
4788   /* X86_64_VEX_MAP7_F6_L_0_W_0_R_0 */
4789   {
4790     { Bad_Opcode },
4791     { PREFIX_TABLE (PREFIX_VEX_MAP7_F6_L_0_W_0_R_0_X86_64) },
4792   },
4793
4794   /* X86_64_VEX_MAP7_F8_L_0_W_0_R_0 */
4795   {
4796     { Bad_Opcode },
4797     { PREFIX_TABLE (PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64) },
4798   },
4799
4800 #include "i386-dis-evex-x86-64.h"
4801 };
4802
4803 static const struct dis386 three_byte_table[][256] = {
4804
4805   /* THREE_BYTE_0F38 */
4806   {
4807     /* 00 */
4808     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
4809     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
4810     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
4811     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
4812     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
4813     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
4814     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
4815     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
4816     /* 08 */
4817     { "psignb",         { MX, EM }, PREFIX_OPCODE },
4818     { "psignw",         { MX, EM }, PREFIX_OPCODE },
4819     { "psignd",         { MX, EM }, PREFIX_OPCODE },
4820     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
4821     { Bad_Opcode },
4822     { Bad_Opcode },
4823     { Bad_Opcode },
4824     { Bad_Opcode },
4825     /* 10 */
4826     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_DATA },
4827     { Bad_Opcode },
4828     { Bad_Opcode },
4829     { Bad_Opcode },
4830     { "blendvps", { XM, EXx, XMM0 }, PREFIX_DATA },
4831     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_DATA },
4832     { Bad_Opcode },
4833     { "ptest",  { XM, EXx }, PREFIX_DATA },
4834     /* 18 */
4835     { Bad_Opcode },
4836     { Bad_Opcode },
4837     { Bad_Opcode },
4838     { Bad_Opcode },
4839     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
4840     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
4841     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
4842     { Bad_Opcode },
4843     /* 20 */
4844     { "pmovsxbw", { XM, EXq }, PREFIX_DATA },
4845     { "pmovsxbd", { XM, EXd }, PREFIX_DATA },
4846     { "pmovsxbq", { XM, EXw }, PREFIX_DATA },
4847     { "pmovsxwd", { XM, EXq }, PREFIX_DATA },
4848     { "pmovsxwq", { XM, EXd }, PREFIX_DATA },
4849     { "pmovsxdq", { XM, EXq }, PREFIX_DATA },
4850     { Bad_Opcode },
4851     { Bad_Opcode },
4852     /* 28 */
4853     { "pmuldq", { XM, EXx }, PREFIX_DATA },
4854     { "pcmpeqq", { XM, EXx }, PREFIX_DATA },
4855     { "movntdqa", { XM, Mx }, PREFIX_DATA },
4856     { "packusdw", { XM, EXx }, PREFIX_DATA },
4857     { Bad_Opcode },
4858     { Bad_Opcode },
4859     { Bad_Opcode },
4860     { Bad_Opcode },
4861     /* 30 */
4862     { "pmovzxbw", { XM, EXq }, PREFIX_DATA },
4863     { "pmovzxbd", { XM, EXd }, PREFIX_DATA },
4864     { "pmovzxbq", { XM, EXw }, PREFIX_DATA },
4865     { "pmovzxwd", { XM, EXq }, PREFIX_DATA },
4866     { "pmovzxwq", { XM, EXd }, PREFIX_DATA },
4867     { "pmovzxdq", { XM, EXq }, PREFIX_DATA },
4868     { Bad_Opcode },
4869     { "pcmpgtq", { XM, EXx }, PREFIX_DATA },
4870     /* 38 */
4871     { "pminsb", { XM, EXx }, PREFIX_DATA },
4872     { "pminsd", { XM, EXx }, PREFIX_DATA },
4873     { "pminuw", { XM, EXx }, PREFIX_DATA },
4874     { "pminud", { XM, EXx }, PREFIX_DATA },
4875     { "pmaxsb", { XM, EXx }, PREFIX_DATA },
4876     { "pmaxsd", { XM, EXx }, PREFIX_DATA },
4877     { "pmaxuw", { XM, EXx }, PREFIX_DATA },
4878     { "pmaxud", { XM, EXx }, PREFIX_DATA },
4879     /* 40 */
4880     { "pmulld", { XM, EXx }, PREFIX_DATA },
4881     { "phminposuw", { XM, EXx }, PREFIX_DATA },
4882     { Bad_Opcode },
4883     { Bad_Opcode },
4884     { Bad_Opcode },
4885     { Bad_Opcode },
4886     { Bad_Opcode },
4887     { Bad_Opcode },
4888     /* 48 */
4889     { Bad_Opcode },
4890     { Bad_Opcode },
4891     { Bad_Opcode },
4892     { Bad_Opcode },
4893     { Bad_Opcode },
4894     { Bad_Opcode },
4895     { Bad_Opcode },
4896     { Bad_Opcode },
4897     /* 50 */
4898     { Bad_Opcode },
4899     { Bad_Opcode },
4900     { Bad_Opcode },
4901     { Bad_Opcode },
4902     { Bad_Opcode },
4903     { Bad_Opcode },
4904     { Bad_Opcode },
4905     { Bad_Opcode },
4906     /* 58 */
4907     { Bad_Opcode },
4908     { Bad_Opcode },
4909     { Bad_Opcode },
4910     { Bad_Opcode },
4911     { Bad_Opcode },
4912     { Bad_Opcode },
4913     { Bad_Opcode },
4914     { Bad_Opcode },
4915     /* 60 */
4916     { Bad_Opcode },
4917     { Bad_Opcode },
4918     { Bad_Opcode },
4919     { Bad_Opcode },
4920     { Bad_Opcode },
4921     { Bad_Opcode },
4922     { Bad_Opcode },
4923     { Bad_Opcode },
4924     /* 68 */
4925     { Bad_Opcode },
4926     { Bad_Opcode },
4927     { Bad_Opcode },
4928     { Bad_Opcode },
4929     { Bad_Opcode },
4930     { Bad_Opcode },
4931     { Bad_Opcode },
4932     { Bad_Opcode },
4933     /* 70 */
4934     { Bad_Opcode },
4935     { Bad_Opcode },
4936     { Bad_Opcode },
4937     { Bad_Opcode },
4938     { Bad_Opcode },
4939     { Bad_Opcode },
4940     { Bad_Opcode },
4941     { Bad_Opcode },
4942     /* 78 */
4943     { Bad_Opcode },
4944     { Bad_Opcode },
4945     { Bad_Opcode },
4946     { Bad_Opcode },
4947     { Bad_Opcode },
4948     { Bad_Opcode },
4949     { Bad_Opcode },
4950     { Bad_Opcode },
4951     /* 80 */
4952     { "invept", { Gm, Mo }, PREFIX_DATA },
4953     { "invvpid", { Gm, Mo }, PREFIX_DATA },
4954     { "invpcid", { Gm, M }, PREFIX_DATA },
4955     { Bad_Opcode },
4956     { Bad_Opcode },
4957     { Bad_Opcode },
4958     { Bad_Opcode },
4959     { Bad_Opcode },
4960     /* 88 */
4961     { Bad_Opcode },
4962     { Bad_Opcode },
4963     { X86_64_TABLE (X86_64_0F388A) },
4964     { X86_64_TABLE (X86_64_0F388B) },
4965     { Bad_Opcode },
4966     { Bad_Opcode },
4967     { Bad_Opcode },
4968     { Bad_Opcode },
4969     /* 90 */
4970     { Bad_Opcode },
4971     { Bad_Opcode },
4972     { Bad_Opcode },
4973     { Bad_Opcode },
4974     { Bad_Opcode },
4975     { Bad_Opcode },
4976     { Bad_Opcode },
4977     { Bad_Opcode },
4978     /* 98 */
4979     { Bad_Opcode },
4980     { Bad_Opcode },
4981     { Bad_Opcode },
4982     { Bad_Opcode },
4983     { Bad_Opcode },
4984     { Bad_Opcode },
4985     { Bad_Opcode },
4986     { Bad_Opcode },
4987     /* a0 */
4988     { Bad_Opcode },
4989     { Bad_Opcode },
4990     { Bad_Opcode },
4991     { Bad_Opcode },
4992     { Bad_Opcode },
4993     { Bad_Opcode },
4994     { Bad_Opcode },
4995     { Bad_Opcode },
4996     /* a8 */
4997     { Bad_Opcode },
4998     { Bad_Opcode },
4999     { Bad_Opcode },
5000     { Bad_Opcode },
5001     { Bad_Opcode },
5002     { Bad_Opcode },
5003     { Bad_Opcode },
5004     { Bad_Opcode },
5005     /* b0 */
5006     { Bad_Opcode },
5007     { Bad_Opcode },
5008     { Bad_Opcode },
5009     { Bad_Opcode },
5010     { Bad_Opcode },
5011     { Bad_Opcode },
5012     { Bad_Opcode },
5013     { Bad_Opcode },
5014     /* b8 */
5015     { Bad_Opcode },
5016     { Bad_Opcode },
5017     { Bad_Opcode },
5018     { Bad_Opcode },
5019     { Bad_Opcode },
5020     { Bad_Opcode },
5021     { Bad_Opcode },
5022     { Bad_Opcode },
5023     /* c0 */
5024     { Bad_Opcode },
5025     { Bad_Opcode },
5026     { Bad_Opcode },
5027     { Bad_Opcode },
5028     { Bad_Opcode },
5029     { Bad_Opcode },
5030     { Bad_Opcode },
5031     { Bad_Opcode },
5032     /* c8 */
5033     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
5034     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
5035     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
5036     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
5037     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
5038     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
5039     { Bad_Opcode },
5040     { "gf2p8mulb", { XM, EXxmm }, PREFIX_DATA },
5041     /* d0 */
5042     { Bad_Opcode },
5043     { Bad_Opcode },
5044     { Bad_Opcode },
5045     { Bad_Opcode },
5046     { Bad_Opcode },
5047     { Bad_Opcode },
5048     { Bad_Opcode },
5049     { Bad_Opcode },
5050     /* d8 */
5051     { PREFIX_TABLE (PREFIX_0F38D8) },
5052     { Bad_Opcode },
5053     { Bad_Opcode },
5054     { "aesimc", { XM, EXx }, PREFIX_DATA },
5055     { PREFIX_TABLE (PREFIX_0F38DC) },
5056     { PREFIX_TABLE (PREFIX_0F38DD) },
5057     { PREFIX_TABLE (PREFIX_0F38DE) },
5058     { PREFIX_TABLE (PREFIX_0F38DF) },
5059     /* e0 */
5060     { Bad_Opcode },
5061     { Bad_Opcode },
5062     { Bad_Opcode },
5063     { Bad_Opcode },
5064     { Bad_Opcode },
5065     { Bad_Opcode },
5066     { Bad_Opcode },
5067     { Bad_Opcode },
5068     /* e8 */
5069     { Bad_Opcode },
5070     { Bad_Opcode },
5071     { Bad_Opcode },
5072     { Bad_Opcode },
5073     { Bad_Opcode },
5074     { Bad_Opcode },
5075     { Bad_Opcode },
5076     { Bad_Opcode },
5077     /* f0 */
5078     { PREFIX_TABLE (PREFIX_0F38F0) },
5079     { PREFIX_TABLE (PREFIX_0F38F1) },
5080     { Bad_Opcode },
5081     { Bad_Opcode },
5082     { Bad_Opcode },
5083     { "wrussK",         { M, Gdq }, PREFIX_DATA },
5084     { PREFIX_TABLE (PREFIX_0F38F6) },
5085     { Bad_Opcode },
5086     /* f8 */
5087     { MOD_TABLE (MOD_0F38F8) },
5088     { "movdiri",        { Mdq, Gdq }, PREFIX_OPCODE },
5089     { PREFIX_TABLE (PREFIX_0F38FA) },
5090     { PREFIX_TABLE (PREFIX_0F38FB) },
5091     { PREFIX_TABLE (PREFIX_0F38FC) },
5092     { Bad_Opcode },
5093     { Bad_Opcode },
5094     { Bad_Opcode },
5095   },
5096   /* THREE_BYTE_0F3A */
5097   {
5098     /* 00 */
5099     { Bad_Opcode },
5100     { Bad_Opcode },
5101     { Bad_Opcode },
5102     { Bad_Opcode },
5103     { Bad_Opcode },
5104     { Bad_Opcode },
5105     { Bad_Opcode },
5106     { Bad_Opcode },
5107     /* 08 */
5108     { "roundps", { XM, EXx, Ib }, PREFIX_DATA },
5109     { "roundpd", { XM, EXx, Ib }, PREFIX_DATA },
5110     { "roundss", { XM, EXd, Ib }, PREFIX_DATA },
5111     { "roundsd", { XM, EXq, Ib }, PREFIX_DATA },
5112     { "blendps", { XM, EXx, Ib }, PREFIX_DATA },
5113     { "blendpd", { XM, EXx, Ib }, PREFIX_DATA },
5114     { "pblendw", { XM, EXx, Ib }, PREFIX_DATA },
5115     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
5116     /* 10 */
5117     { Bad_Opcode },
5118     { Bad_Opcode },
5119     { Bad_Opcode },
5120     { Bad_Opcode },
5121     { "pextrb", { Edb, XM, Ib }, PREFIX_DATA },
5122     { "pextrw", { Edw, XM, Ib }, PREFIX_DATA },
5123     { "pextrK", { Edq, XM, Ib }, PREFIX_DATA },
5124     { "extractps", { Ed, XM, Ib }, PREFIX_DATA },
5125     /* 18 */
5126     { Bad_Opcode },
5127     { Bad_Opcode },
5128     { Bad_Opcode },
5129     { Bad_Opcode },
5130     { Bad_Opcode },
5131     { Bad_Opcode },
5132     { Bad_Opcode },
5133     { Bad_Opcode },
5134     /* 20 */
5135     { "pinsrb", { XM, Edb, Ib }, PREFIX_DATA },
5136     { "insertps", { XM, EXd, Ib }, PREFIX_DATA },
5137     { "pinsrK", { XM, Edq, Ib }, PREFIX_DATA },
5138     { Bad_Opcode },
5139     { Bad_Opcode },
5140     { Bad_Opcode },
5141     { Bad_Opcode },
5142     { Bad_Opcode },
5143     /* 28 */
5144     { Bad_Opcode },
5145     { Bad_Opcode },
5146     { Bad_Opcode },
5147     { Bad_Opcode },
5148     { Bad_Opcode },
5149     { Bad_Opcode },
5150     { Bad_Opcode },
5151     { Bad_Opcode },
5152     /* 30 */
5153     { Bad_Opcode },
5154     { Bad_Opcode },
5155     { Bad_Opcode },
5156     { Bad_Opcode },
5157     { Bad_Opcode },
5158     { Bad_Opcode },
5159     { Bad_Opcode },
5160     { Bad_Opcode },
5161     /* 38 */
5162     { Bad_Opcode },
5163     { Bad_Opcode },
5164     { Bad_Opcode },
5165     { Bad_Opcode },
5166     { Bad_Opcode },
5167     { Bad_Opcode },
5168     { Bad_Opcode },
5169     { Bad_Opcode },
5170     /* 40 */
5171     { "dpps",   { XM, EXx, Ib }, PREFIX_DATA },
5172     { "dppd",   { XM, EXx, Ib }, PREFIX_DATA },
5173     { "mpsadbw", { XM, EXx, Ib }, PREFIX_DATA },
5174     { Bad_Opcode },
5175     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_DATA },
5176     { Bad_Opcode },
5177     { Bad_Opcode },
5178     { Bad_Opcode },
5179     /* 48 */
5180     { Bad_Opcode },
5181     { Bad_Opcode },
5182     { Bad_Opcode },
5183     { Bad_Opcode },
5184     { Bad_Opcode },
5185     { Bad_Opcode },
5186     { Bad_Opcode },
5187     { Bad_Opcode },
5188     /* 50 */
5189     { Bad_Opcode },
5190     { Bad_Opcode },
5191     { Bad_Opcode },
5192     { Bad_Opcode },
5193     { Bad_Opcode },
5194     { Bad_Opcode },
5195     { Bad_Opcode },
5196     { Bad_Opcode },
5197     /* 58 */
5198     { Bad_Opcode },
5199     { Bad_Opcode },
5200     { Bad_Opcode },
5201     { Bad_Opcode },
5202     { Bad_Opcode },
5203     { Bad_Opcode },
5204     { Bad_Opcode },
5205     { Bad_Opcode },
5206     /* 60 */
5207     { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
5208     { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
5209     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
5210     { "pcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
5211     { Bad_Opcode },
5212     { Bad_Opcode },
5213     { Bad_Opcode },
5214     { Bad_Opcode },
5215     /* 68 */
5216     { Bad_Opcode },
5217     { Bad_Opcode },
5218     { Bad_Opcode },
5219     { Bad_Opcode },
5220     { Bad_Opcode },
5221     { Bad_Opcode },
5222     { Bad_Opcode },
5223     { Bad_Opcode },
5224     /* 70 */
5225     { Bad_Opcode },
5226     { Bad_Opcode },
5227     { Bad_Opcode },
5228     { Bad_Opcode },
5229     { Bad_Opcode },
5230     { Bad_Opcode },
5231     { Bad_Opcode },
5232     { Bad_Opcode },
5233     /* 78 */
5234     { Bad_Opcode },
5235     { Bad_Opcode },
5236     { Bad_Opcode },
5237     { Bad_Opcode },
5238     { Bad_Opcode },
5239     { Bad_Opcode },
5240     { Bad_Opcode },
5241     { Bad_Opcode },
5242     /* 80 */
5243     { Bad_Opcode },
5244     { Bad_Opcode },
5245     { Bad_Opcode },
5246     { Bad_Opcode },
5247     { Bad_Opcode },
5248     { Bad_Opcode },
5249     { Bad_Opcode },
5250     { Bad_Opcode },
5251     /* 88 */
5252     { Bad_Opcode },
5253     { Bad_Opcode },
5254     { Bad_Opcode },
5255     { Bad_Opcode },
5256     { Bad_Opcode },
5257     { Bad_Opcode },
5258     { Bad_Opcode },
5259     { Bad_Opcode },
5260     /* 90 */
5261     { Bad_Opcode },
5262     { Bad_Opcode },
5263     { Bad_Opcode },
5264     { Bad_Opcode },
5265     { Bad_Opcode },
5266     { Bad_Opcode },
5267     { Bad_Opcode },
5268     { Bad_Opcode },
5269     /* 98 */
5270     { Bad_Opcode },
5271     { Bad_Opcode },
5272     { Bad_Opcode },
5273     { Bad_Opcode },
5274     { Bad_Opcode },
5275     { Bad_Opcode },
5276     { Bad_Opcode },
5277     { Bad_Opcode },
5278     /* a0 */
5279     { Bad_Opcode },
5280     { Bad_Opcode },
5281     { Bad_Opcode },
5282     { Bad_Opcode },
5283     { Bad_Opcode },
5284     { Bad_Opcode },
5285     { Bad_Opcode },
5286     { Bad_Opcode },
5287     /* a8 */
5288     { Bad_Opcode },
5289     { Bad_Opcode },
5290     { Bad_Opcode },
5291     { Bad_Opcode },
5292     { Bad_Opcode },
5293     { Bad_Opcode },
5294     { Bad_Opcode },
5295     { Bad_Opcode },
5296     /* b0 */
5297     { Bad_Opcode },
5298     { Bad_Opcode },
5299     { Bad_Opcode },
5300     { Bad_Opcode },
5301     { Bad_Opcode },
5302     { Bad_Opcode },
5303     { Bad_Opcode },
5304     { Bad_Opcode },
5305     /* b8 */
5306     { Bad_Opcode },
5307     { Bad_Opcode },
5308     { Bad_Opcode },
5309     { Bad_Opcode },
5310     { Bad_Opcode },
5311     { Bad_Opcode },
5312     { Bad_Opcode },
5313     { Bad_Opcode },
5314     /* c0 */
5315     { Bad_Opcode },
5316     { Bad_Opcode },
5317     { Bad_Opcode },
5318     { Bad_Opcode },
5319     { Bad_Opcode },
5320     { Bad_Opcode },
5321     { Bad_Opcode },
5322     { Bad_Opcode },
5323     /* c8 */
5324     { Bad_Opcode },
5325     { Bad_Opcode },
5326     { Bad_Opcode },
5327     { Bad_Opcode },
5328     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
5329     { Bad_Opcode },
5330     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_DATA },
5331     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_DATA },
5332     /* d0 */
5333     { Bad_Opcode },
5334     { Bad_Opcode },
5335     { Bad_Opcode },
5336     { Bad_Opcode },
5337     { Bad_Opcode },
5338     { Bad_Opcode },
5339     { Bad_Opcode },
5340     { Bad_Opcode },
5341     /* d8 */
5342     { Bad_Opcode },
5343     { Bad_Opcode },
5344     { Bad_Opcode },
5345     { Bad_Opcode },
5346     { Bad_Opcode },
5347     { Bad_Opcode },
5348     { Bad_Opcode },
5349     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
5350     /* e0 */
5351     { Bad_Opcode },
5352     { Bad_Opcode },
5353     { Bad_Opcode },
5354     { Bad_Opcode },
5355     { Bad_Opcode },
5356     { Bad_Opcode },
5357     { Bad_Opcode },
5358     { Bad_Opcode },
5359     /* e8 */
5360     { Bad_Opcode },
5361     { Bad_Opcode },
5362     { Bad_Opcode },
5363     { Bad_Opcode },
5364     { Bad_Opcode },
5365     { Bad_Opcode },
5366     { Bad_Opcode },
5367     { Bad_Opcode },
5368     /* f0 */
5369     { PREFIX_TABLE (PREFIX_0F3A0F) },
5370     { Bad_Opcode },
5371     { Bad_Opcode },
5372     { Bad_Opcode },
5373     { Bad_Opcode },
5374     { Bad_Opcode },
5375     { Bad_Opcode },
5376     { Bad_Opcode },
5377     /* f8 */
5378     { Bad_Opcode },
5379     { Bad_Opcode },
5380     { Bad_Opcode },
5381     { Bad_Opcode },
5382     { Bad_Opcode },
5383     { Bad_Opcode },
5384     { Bad_Opcode },
5385     { Bad_Opcode },
5386   },
5387 };
5388
5389 static const struct dis386 xop_table[][256] = {
5390   /* XOP_08 */
5391   {
5392     /* 00 */
5393     { Bad_Opcode },
5394     { Bad_Opcode },
5395     { Bad_Opcode },
5396     { Bad_Opcode },
5397     { Bad_Opcode },
5398     { Bad_Opcode },
5399     { Bad_Opcode },
5400     { Bad_Opcode },
5401     /* 08 */
5402     { Bad_Opcode },
5403     { Bad_Opcode },
5404     { Bad_Opcode },
5405     { Bad_Opcode },
5406     { Bad_Opcode },
5407     { Bad_Opcode },
5408     { Bad_Opcode },
5409     { Bad_Opcode },
5410     /* 10 */
5411     { Bad_Opcode },
5412     { Bad_Opcode },
5413     { Bad_Opcode },
5414     { Bad_Opcode },
5415     { Bad_Opcode },
5416     { Bad_Opcode },
5417     { Bad_Opcode },
5418     { Bad_Opcode },
5419     /* 18 */
5420     { Bad_Opcode },
5421     { Bad_Opcode },
5422     { Bad_Opcode },
5423     { Bad_Opcode },
5424     { Bad_Opcode },
5425     { Bad_Opcode },
5426     { Bad_Opcode },
5427     { Bad_Opcode },
5428     /* 20 */
5429     { Bad_Opcode },
5430     { Bad_Opcode },
5431     { Bad_Opcode },
5432     { Bad_Opcode },
5433     { Bad_Opcode },
5434     { Bad_Opcode },
5435     { Bad_Opcode },
5436     { Bad_Opcode },
5437     /* 28 */
5438     { Bad_Opcode },
5439     { Bad_Opcode },
5440     { Bad_Opcode },
5441     { Bad_Opcode },
5442     { Bad_Opcode },
5443     { Bad_Opcode },
5444     { Bad_Opcode },
5445     { Bad_Opcode },
5446     /* 30 */
5447     { Bad_Opcode },
5448     { Bad_Opcode },
5449     { Bad_Opcode },
5450     { Bad_Opcode },
5451     { Bad_Opcode },
5452     { Bad_Opcode },
5453     { Bad_Opcode },
5454     { Bad_Opcode },
5455     /* 38 */
5456     { Bad_Opcode },
5457     { Bad_Opcode },
5458     { Bad_Opcode },
5459     { Bad_Opcode },
5460     { Bad_Opcode },
5461     { Bad_Opcode },
5462     { Bad_Opcode },
5463     { Bad_Opcode },
5464     /* 40 */
5465     { Bad_Opcode },
5466     { Bad_Opcode },
5467     { Bad_Opcode },
5468     { Bad_Opcode },
5469     { Bad_Opcode },
5470     { Bad_Opcode },
5471     { Bad_Opcode },
5472     { Bad_Opcode },
5473     /* 48 */
5474     { Bad_Opcode },
5475     { Bad_Opcode },
5476     { Bad_Opcode },
5477     { Bad_Opcode },
5478     { Bad_Opcode },
5479     { Bad_Opcode },
5480     { Bad_Opcode },
5481     { Bad_Opcode },
5482     /* 50 */
5483     { Bad_Opcode },
5484     { Bad_Opcode },
5485     { Bad_Opcode },
5486     { Bad_Opcode },
5487     { Bad_Opcode },
5488     { Bad_Opcode },
5489     { Bad_Opcode },
5490     { Bad_Opcode },
5491     /* 58 */
5492     { Bad_Opcode },
5493     { Bad_Opcode },
5494     { Bad_Opcode },
5495     { Bad_Opcode },
5496     { Bad_Opcode },
5497     { Bad_Opcode },
5498     { Bad_Opcode },
5499     { Bad_Opcode },
5500     /* 60 */
5501     { Bad_Opcode },
5502     { Bad_Opcode },
5503     { Bad_Opcode },
5504     { Bad_Opcode },
5505     { Bad_Opcode },
5506     { Bad_Opcode },
5507     { Bad_Opcode },
5508     { Bad_Opcode },
5509     /* 68 */
5510     { Bad_Opcode },
5511     { Bad_Opcode },
5512     { Bad_Opcode },
5513     { Bad_Opcode },
5514     { Bad_Opcode },
5515     { Bad_Opcode },
5516     { Bad_Opcode },
5517     { Bad_Opcode },
5518     /* 70 */
5519     { Bad_Opcode },
5520     { Bad_Opcode },
5521     { Bad_Opcode },
5522     { Bad_Opcode },
5523     { Bad_Opcode },
5524     { Bad_Opcode },
5525     { Bad_Opcode },
5526     { Bad_Opcode },
5527     /* 78 */
5528     { Bad_Opcode },
5529     { Bad_Opcode },
5530     { Bad_Opcode },
5531     { Bad_Opcode },
5532     { Bad_Opcode },
5533     { Bad_Opcode },
5534     { Bad_Opcode },
5535     { Bad_Opcode },
5536     /* 80 */
5537     { Bad_Opcode },
5538     { Bad_Opcode },
5539     { Bad_Opcode },
5540     { Bad_Opcode },
5541     { Bad_Opcode },
5542     { VEX_LEN_TABLE (VEX_LEN_XOP_08_85) },
5543     { VEX_LEN_TABLE (VEX_LEN_XOP_08_86) },
5544     { VEX_LEN_TABLE (VEX_LEN_XOP_08_87) },
5545     /* 88 */
5546     { Bad_Opcode },
5547     { Bad_Opcode },
5548     { Bad_Opcode },
5549     { Bad_Opcode },
5550     { Bad_Opcode },
5551     { Bad_Opcode },
5552     { VEX_LEN_TABLE (VEX_LEN_XOP_08_8E) },
5553     { VEX_LEN_TABLE (VEX_LEN_XOP_08_8F) },
5554     /* 90 */
5555     { Bad_Opcode },
5556     { Bad_Opcode },
5557     { Bad_Opcode },
5558     { Bad_Opcode },
5559     { Bad_Opcode },
5560     { VEX_LEN_TABLE (VEX_LEN_XOP_08_95) },
5561     { VEX_LEN_TABLE (VEX_LEN_XOP_08_96) },
5562     { VEX_LEN_TABLE (VEX_LEN_XOP_08_97) },
5563     /* 98 */
5564     { Bad_Opcode },
5565     { Bad_Opcode },
5566     { Bad_Opcode },
5567     { Bad_Opcode },
5568     { Bad_Opcode },
5569     { Bad_Opcode },
5570     { VEX_LEN_TABLE (VEX_LEN_XOP_08_9E) },
5571     { VEX_LEN_TABLE (VEX_LEN_XOP_08_9F) },
5572     /* a0 */
5573     { Bad_Opcode },
5574     { Bad_Opcode },
5575     { "vpcmov",         { XM, Vex, EXx, XMVexI4 }, 0 },
5576     { VEX_LEN_TABLE (VEX_LEN_XOP_08_A3) },
5577     { Bad_Opcode },
5578     { Bad_Opcode },
5579     { VEX_LEN_TABLE (VEX_LEN_XOP_08_A6) },
5580     { Bad_Opcode },
5581     /* a8 */
5582     { Bad_Opcode },
5583     { Bad_Opcode },
5584     { Bad_Opcode },
5585     { Bad_Opcode },
5586     { Bad_Opcode },
5587     { Bad_Opcode },
5588     { Bad_Opcode },
5589     { Bad_Opcode },
5590     /* b0 */
5591     { Bad_Opcode },
5592     { Bad_Opcode },
5593     { Bad_Opcode },
5594     { Bad_Opcode },
5595     { Bad_Opcode },
5596     { Bad_Opcode },
5597     { VEX_LEN_TABLE (VEX_LEN_XOP_08_B6) },
5598     { Bad_Opcode },
5599     /* b8 */
5600     { Bad_Opcode },
5601     { Bad_Opcode },
5602     { Bad_Opcode },
5603     { Bad_Opcode },
5604     { Bad_Opcode },
5605     { Bad_Opcode },
5606     { Bad_Opcode },
5607     { Bad_Opcode },
5608     /* c0 */
5609     { VEX_LEN_TABLE (VEX_LEN_XOP_08_C0) },
5610     { VEX_LEN_TABLE (VEX_LEN_XOP_08_C1) },
5611     { VEX_LEN_TABLE (VEX_LEN_XOP_08_C2) },
5612     { VEX_LEN_TABLE (VEX_LEN_XOP_08_C3) },
5613     { Bad_Opcode },
5614     { Bad_Opcode },
5615     { Bad_Opcode },
5616     { Bad_Opcode },
5617     /* c8 */
5618     { Bad_Opcode },
5619     { Bad_Opcode },
5620     { Bad_Opcode },
5621     { Bad_Opcode },
5622     { VEX_LEN_TABLE (VEX_LEN_XOP_08_CC) },
5623     { VEX_LEN_TABLE (VEX_LEN_XOP_08_CD) },
5624     { VEX_LEN_TABLE (VEX_LEN_XOP_08_CE) },
5625     { VEX_LEN_TABLE (VEX_LEN_XOP_08_CF) },
5626     /* d0 */
5627     { Bad_Opcode },
5628     { Bad_Opcode },
5629     { Bad_Opcode },
5630     { Bad_Opcode },
5631     { Bad_Opcode },
5632     { Bad_Opcode },
5633     { Bad_Opcode },
5634     { Bad_Opcode },
5635     /* d8 */
5636     { Bad_Opcode },
5637     { Bad_Opcode },
5638     { Bad_Opcode },
5639     { Bad_Opcode },
5640     { Bad_Opcode },
5641     { Bad_Opcode },
5642     { Bad_Opcode },
5643     { Bad_Opcode },
5644     /* e0 */
5645     { Bad_Opcode },
5646     { Bad_Opcode },
5647     { Bad_Opcode },
5648     { Bad_Opcode },
5649     { Bad_Opcode },
5650     { Bad_Opcode },
5651     { Bad_Opcode },
5652     { Bad_Opcode },
5653     /* e8 */
5654     { Bad_Opcode },
5655     { Bad_Opcode },
5656     { Bad_Opcode },
5657     { Bad_Opcode },
5658     { VEX_LEN_TABLE (VEX_LEN_XOP_08_EC) },
5659     { VEX_LEN_TABLE (VEX_LEN_XOP_08_ED) },
5660     { VEX_LEN_TABLE (VEX_LEN_XOP_08_EE) },
5661     { VEX_LEN_TABLE (VEX_LEN_XOP_08_EF) },
5662     /* f0 */
5663     { Bad_Opcode },
5664     { Bad_Opcode },
5665     { Bad_Opcode },
5666     { Bad_Opcode },
5667     { Bad_Opcode },
5668     { Bad_Opcode },
5669     { Bad_Opcode },
5670     { Bad_Opcode },
5671     /* f8 */
5672     { Bad_Opcode },
5673     { Bad_Opcode },
5674     { Bad_Opcode },
5675     { Bad_Opcode },
5676     { Bad_Opcode },
5677     { Bad_Opcode },
5678     { Bad_Opcode },
5679     { Bad_Opcode },
5680   },
5681   /* XOP_09 */
5682   {
5683     /* 00 */
5684     { Bad_Opcode },
5685     { VEX_LEN_TABLE (VEX_LEN_XOP_09_01) },
5686     { VEX_LEN_TABLE (VEX_LEN_XOP_09_02) },
5687     { Bad_Opcode },
5688     { Bad_Opcode },
5689     { Bad_Opcode },
5690     { Bad_Opcode },
5691     { Bad_Opcode },
5692     /* 08 */
5693     { Bad_Opcode },
5694     { Bad_Opcode },
5695     { Bad_Opcode },
5696     { Bad_Opcode },
5697     { Bad_Opcode },
5698     { Bad_Opcode },
5699     { Bad_Opcode },
5700     { Bad_Opcode },
5701     /* 10 */
5702     { Bad_Opcode },
5703     { Bad_Opcode },
5704     { VEX_LEN_TABLE (VEX_LEN_XOP_09_12) },
5705     { Bad_Opcode },
5706     { Bad_Opcode },
5707     { Bad_Opcode },
5708     { Bad_Opcode },
5709     { Bad_Opcode },
5710     /* 18 */
5711     { Bad_Opcode },
5712     { Bad_Opcode },
5713     { Bad_Opcode },
5714     { Bad_Opcode },
5715     { Bad_Opcode },
5716     { Bad_Opcode },
5717     { Bad_Opcode },
5718     { Bad_Opcode },
5719     /* 20 */
5720     { Bad_Opcode },
5721     { Bad_Opcode },
5722     { Bad_Opcode },
5723     { Bad_Opcode },
5724     { Bad_Opcode },
5725     { Bad_Opcode },
5726     { Bad_Opcode },
5727     { Bad_Opcode },
5728     /* 28 */
5729     { Bad_Opcode },
5730     { Bad_Opcode },
5731     { Bad_Opcode },
5732     { Bad_Opcode },
5733     { Bad_Opcode },
5734     { Bad_Opcode },
5735     { Bad_Opcode },
5736     { Bad_Opcode },
5737     /* 30 */
5738     { Bad_Opcode },
5739     { Bad_Opcode },
5740     { Bad_Opcode },
5741     { Bad_Opcode },
5742     { Bad_Opcode },
5743     { Bad_Opcode },
5744     { Bad_Opcode },
5745     { Bad_Opcode },
5746     /* 38 */
5747     { Bad_Opcode },
5748     { Bad_Opcode },
5749     { Bad_Opcode },
5750     { Bad_Opcode },
5751     { Bad_Opcode },
5752     { Bad_Opcode },
5753     { Bad_Opcode },
5754     { Bad_Opcode },
5755     /* 40 */
5756     { Bad_Opcode },
5757     { Bad_Opcode },
5758     { Bad_Opcode },
5759     { Bad_Opcode },
5760     { Bad_Opcode },
5761     { Bad_Opcode },
5762     { Bad_Opcode },
5763     { Bad_Opcode },
5764     /* 48 */
5765     { Bad_Opcode },
5766     { Bad_Opcode },
5767     { Bad_Opcode },
5768     { Bad_Opcode },
5769     { Bad_Opcode },
5770     { Bad_Opcode },
5771     { Bad_Opcode },
5772     { Bad_Opcode },
5773     /* 50 */
5774     { Bad_Opcode },
5775     { Bad_Opcode },
5776     { Bad_Opcode },
5777     { Bad_Opcode },
5778     { Bad_Opcode },
5779     { Bad_Opcode },
5780     { Bad_Opcode },
5781     { Bad_Opcode },
5782     /* 58 */
5783     { Bad_Opcode },
5784     { Bad_Opcode },
5785     { Bad_Opcode },
5786     { Bad_Opcode },
5787     { Bad_Opcode },
5788     { Bad_Opcode },
5789     { Bad_Opcode },
5790     { Bad_Opcode },
5791     /* 60 */
5792     { Bad_Opcode },
5793     { Bad_Opcode },
5794     { Bad_Opcode },
5795     { Bad_Opcode },
5796     { Bad_Opcode },
5797     { Bad_Opcode },
5798     { Bad_Opcode },
5799     { Bad_Opcode },
5800     /* 68 */
5801     { Bad_Opcode },
5802     { Bad_Opcode },
5803     { Bad_Opcode },
5804     { Bad_Opcode },
5805     { Bad_Opcode },
5806     { Bad_Opcode },
5807     { Bad_Opcode },
5808     { Bad_Opcode },
5809     /* 70 */
5810     { Bad_Opcode },
5811     { Bad_Opcode },
5812     { Bad_Opcode },
5813     { Bad_Opcode },
5814     { Bad_Opcode },
5815     { Bad_Opcode },
5816     { Bad_Opcode },
5817     { Bad_Opcode },
5818     /* 78 */
5819     { Bad_Opcode },
5820     { Bad_Opcode },
5821     { Bad_Opcode },
5822     { Bad_Opcode },
5823     { Bad_Opcode },
5824     { Bad_Opcode },
5825     { Bad_Opcode },
5826     { Bad_Opcode },
5827     /* 80 */
5828     { VEX_W_TABLE (VEX_W_XOP_09_80) },
5829     { VEX_W_TABLE (VEX_W_XOP_09_81) },
5830     { VEX_W_TABLE (VEX_W_XOP_09_82) },
5831     { VEX_W_TABLE (VEX_W_XOP_09_83) },
5832     { Bad_Opcode },
5833     { Bad_Opcode },
5834     { Bad_Opcode },
5835     { Bad_Opcode },
5836     /* 88 */
5837     { Bad_Opcode },
5838     { Bad_Opcode },
5839     { Bad_Opcode },
5840     { Bad_Opcode },
5841     { Bad_Opcode },
5842     { Bad_Opcode },
5843     { Bad_Opcode },
5844     { Bad_Opcode },
5845     /* 90 */
5846     { VEX_LEN_TABLE (VEX_LEN_XOP_09_90) },
5847     { VEX_LEN_TABLE (VEX_LEN_XOP_09_91) },
5848     { VEX_LEN_TABLE (VEX_LEN_XOP_09_92) },
5849     { VEX_LEN_TABLE (VEX_LEN_XOP_09_93) },
5850     { VEX_LEN_TABLE (VEX_LEN_XOP_09_94) },
5851     { VEX_LEN_TABLE (VEX_LEN_XOP_09_95) },
5852     { VEX_LEN_TABLE (VEX_LEN_XOP_09_96) },
5853     { VEX_LEN_TABLE (VEX_LEN_XOP_09_97) },
5854     /* 98 */
5855     { VEX_LEN_TABLE (VEX_LEN_XOP_09_98) },
5856     { VEX_LEN_TABLE (VEX_LEN_XOP_09_99) },
5857     { VEX_LEN_TABLE (VEX_LEN_XOP_09_9A) },
5858     { VEX_LEN_TABLE (VEX_LEN_XOP_09_9B) },
5859     { Bad_Opcode },
5860     { Bad_Opcode },
5861     { Bad_Opcode },
5862     { Bad_Opcode },
5863     /* a0 */
5864     { Bad_Opcode },
5865     { Bad_Opcode },
5866     { Bad_Opcode },
5867     { Bad_Opcode },
5868     { Bad_Opcode },
5869     { Bad_Opcode },
5870     { Bad_Opcode },
5871     { Bad_Opcode },
5872     /* a8 */
5873     { Bad_Opcode },
5874     { Bad_Opcode },
5875     { Bad_Opcode },
5876     { Bad_Opcode },
5877     { Bad_Opcode },
5878     { Bad_Opcode },
5879     { Bad_Opcode },
5880     { Bad_Opcode },
5881     /* b0 */
5882     { Bad_Opcode },
5883     { Bad_Opcode },
5884     { Bad_Opcode },
5885     { Bad_Opcode },
5886     { Bad_Opcode },
5887     { Bad_Opcode },
5888     { Bad_Opcode },
5889     { Bad_Opcode },
5890     /* b8 */
5891     { Bad_Opcode },
5892     { Bad_Opcode },
5893     { Bad_Opcode },
5894     { Bad_Opcode },
5895     { Bad_Opcode },
5896     { Bad_Opcode },
5897     { Bad_Opcode },
5898     { Bad_Opcode },
5899     /* c0 */
5900     { Bad_Opcode },
5901     { VEX_LEN_TABLE (VEX_LEN_XOP_09_C1) },
5902     { VEX_LEN_TABLE (VEX_LEN_XOP_09_C2) },
5903     { VEX_LEN_TABLE (VEX_LEN_XOP_09_C3) },
5904     { Bad_Opcode },
5905     { Bad_Opcode },
5906     { VEX_LEN_TABLE (VEX_LEN_XOP_09_C6) },
5907     { VEX_LEN_TABLE (VEX_LEN_XOP_09_C7) },
5908     /* c8 */
5909     { Bad_Opcode },
5910     { Bad_Opcode },
5911     { Bad_Opcode },
5912     { VEX_LEN_TABLE (VEX_LEN_XOP_09_CB) },
5913     { Bad_Opcode },
5914     { Bad_Opcode },
5915     { Bad_Opcode },
5916     { Bad_Opcode },
5917     /* d0 */
5918     { Bad_Opcode },
5919     { VEX_LEN_TABLE (VEX_LEN_XOP_09_D1) },
5920     { VEX_LEN_TABLE (VEX_LEN_XOP_09_D2) },
5921     { VEX_LEN_TABLE (VEX_LEN_XOP_09_D3) },
5922     { Bad_Opcode },
5923     { Bad_Opcode },
5924     { VEX_LEN_TABLE (VEX_LEN_XOP_09_D6) },
5925     { VEX_LEN_TABLE (VEX_LEN_XOP_09_D7) },
5926     /* d8 */
5927     { Bad_Opcode },
5928     { Bad_Opcode },
5929     { Bad_Opcode },
5930     { VEX_LEN_TABLE (VEX_LEN_XOP_09_DB) },
5931     { Bad_Opcode },
5932     { Bad_Opcode },
5933     { Bad_Opcode },
5934     { Bad_Opcode },
5935     /* e0 */
5936     { Bad_Opcode },
5937     { VEX_LEN_TABLE (VEX_LEN_XOP_09_E1) },
5938     { VEX_LEN_TABLE (VEX_LEN_XOP_09_E2) },
5939     { VEX_LEN_TABLE (VEX_LEN_XOP_09_E3) },
5940     { Bad_Opcode },
5941     { Bad_Opcode },
5942     { Bad_Opcode },
5943     { Bad_Opcode },
5944     /* e8 */
5945     { Bad_Opcode },
5946     { Bad_Opcode },
5947     { Bad_Opcode },
5948     { Bad_Opcode },
5949     { Bad_Opcode },
5950     { Bad_Opcode },
5951     { Bad_Opcode },
5952     { Bad_Opcode },
5953     /* f0 */
5954     { Bad_Opcode },
5955     { Bad_Opcode },
5956     { Bad_Opcode },
5957     { Bad_Opcode },
5958     { Bad_Opcode },
5959     { Bad_Opcode },
5960     { Bad_Opcode },
5961     { Bad_Opcode },
5962     /* f8 */
5963     { Bad_Opcode },
5964     { Bad_Opcode },
5965     { Bad_Opcode },
5966     { Bad_Opcode },
5967     { Bad_Opcode },
5968     { Bad_Opcode },
5969     { Bad_Opcode },
5970     { Bad_Opcode },
5971   },
5972   /* XOP_0A */
5973   {
5974     /* 00 */
5975     { Bad_Opcode },
5976     { Bad_Opcode },
5977     { Bad_Opcode },
5978     { Bad_Opcode },
5979     { Bad_Opcode },
5980     { Bad_Opcode },
5981     { Bad_Opcode },
5982     { Bad_Opcode },
5983     /* 08 */
5984     { Bad_Opcode },
5985     { Bad_Opcode },
5986     { Bad_Opcode },
5987     { Bad_Opcode },
5988     { Bad_Opcode },
5989     { Bad_Opcode },
5990     { Bad_Opcode },
5991     { Bad_Opcode },
5992     /* 10 */
5993     { "bextrS", { Gdq, Edq, Id }, 0 },
5994     { Bad_Opcode },
5995     { VEX_LEN_TABLE (VEX_LEN_XOP_0A_12) },
5996     { Bad_Opcode },
5997     { Bad_Opcode },
5998     { Bad_Opcode },
5999     { Bad_Opcode },
6000     { Bad_Opcode },
6001     /* 18 */
6002     { Bad_Opcode },
6003     { Bad_Opcode },
6004     { Bad_Opcode },
6005     { Bad_Opcode },
6006     { Bad_Opcode },
6007     { Bad_Opcode },
6008     { Bad_Opcode },
6009     { Bad_Opcode },
6010     /* 20 */
6011     { Bad_Opcode },
6012     { Bad_Opcode },
6013     { Bad_Opcode },
6014     { Bad_Opcode },
6015     { Bad_Opcode },
6016     { Bad_Opcode },
6017     { Bad_Opcode },
6018     { Bad_Opcode },
6019     /* 28 */
6020     { Bad_Opcode },
6021     { Bad_Opcode },
6022     { Bad_Opcode },
6023     { Bad_Opcode },
6024     { Bad_Opcode },
6025     { Bad_Opcode },
6026     { Bad_Opcode },
6027     { Bad_Opcode },
6028     /* 30 */
6029     { Bad_Opcode },
6030     { Bad_Opcode },
6031     { Bad_Opcode },
6032     { Bad_Opcode },
6033     { Bad_Opcode },
6034     { Bad_Opcode },
6035     { Bad_Opcode },
6036     { Bad_Opcode },
6037     /* 38 */
6038     { Bad_Opcode },
6039     { Bad_Opcode },
6040     { Bad_Opcode },
6041     { Bad_Opcode },
6042     { Bad_Opcode },
6043     { Bad_Opcode },
6044     { Bad_Opcode },
6045     { Bad_Opcode },
6046     /* 40 */
6047     { Bad_Opcode },
6048     { Bad_Opcode },
6049     { Bad_Opcode },
6050     { Bad_Opcode },
6051     { Bad_Opcode },
6052     { Bad_Opcode },
6053     { Bad_Opcode },
6054     { Bad_Opcode },
6055     /* 48 */
6056     { Bad_Opcode },
6057     { Bad_Opcode },
6058     { Bad_Opcode },
6059     { Bad_Opcode },
6060     { Bad_Opcode },
6061     { Bad_Opcode },
6062     { Bad_Opcode },
6063     { Bad_Opcode },
6064     /* 50 */
6065     { Bad_Opcode },
6066     { Bad_Opcode },
6067     { Bad_Opcode },
6068     { Bad_Opcode },
6069     { Bad_Opcode },
6070     { Bad_Opcode },
6071     { Bad_Opcode },
6072     { Bad_Opcode },
6073     /* 58 */
6074     { Bad_Opcode },
6075     { Bad_Opcode },
6076     { Bad_Opcode },
6077     { Bad_Opcode },
6078     { Bad_Opcode },
6079     { Bad_Opcode },
6080     { Bad_Opcode },
6081     { Bad_Opcode },
6082     /* 60 */
6083     { Bad_Opcode },
6084     { Bad_Opcode },
6085     { Bad_Opcode },
6086     { Bad_Opcode },
6087     { Bad_Opcode },
6088     { Bad_Opcode },
6089     { Bad_Opcode },
6090     { Bad_Opcode },
6091     /* 68 */
6092     { Bad_Opcode },
6093     { Bad_Opcode },
6094     { Bad_Opcode },
6095     { Bad_Opcode },
6096     { Bad_Opcode },
6097     { Bad_Opcode },
6098     { Bad_Opcode },
6099     { Bad_Opcode },
6100     /* 70 */
6101     { Bad_Opcode },
6102     { Bad_Opcode },
6103     { Bad_Opcode },
6104     { Bad_Opcode },
6105     { Bad_Opcode },
6106     { Bad_Opcode },
6107     { Bad_Opcode },
6108     { Bad_Opcode },
6109     /* 78 */
6110     { Bad_Opcode },
6111     { Bad_Opcode },
6112     { Bad_Opcode },
6113     { Bad_Opcode },
6114     { Bad_Opcode },
6115     { Bad_Opcode },
6116     { Bad_Opcode },
6117     { Bad_Opcode },
6118     /* 80 */
6119     { Bad_Opcode },
6120     { Bad_Opcode },
6121     { Bad_Opcode },
6122     { Bad_Opcode },
6123     { Bad_Opcode },
6124     { Bad_Opcode },
6125     { Bad_Opcode },
6126     { Bad_Opcode },
6127     /* 88 */
6128     { Bad_Opcode },
6129     { Bad_Opcode },
6130     { Bad_Opcode },
6131     { Bad_Opcode },
6132     { Bad_Opcode },
6133     { Bad_Opcode },
6134     { Bad_Opcode },
6135     { Bad_Opcode },
6136     /* 90 */
6137     { Bad_Opcode },
6138     { Bad_Opcode },
6139     { Bad_Opcode },
6140     { Bad_Opcode },
6141     { Bad_Opcode },
6142     { Bad_Opcode },
6143     { Bad_Opcode },
6144     { Bad_Opcode },
6145     /* 98 */
6146     { Bad_Opcode },
6147     { Bad_Opcode },
6148     { Bad_Opcode },
6149     { Bad_Opcode },
6150     { Bad_Opcode },
6151     { Bad_Opcode },
6152     { Bad_Opcode },
6153     { Bad_Opcode },
6154     /* a0 */
6155     { Bad_Opcode },
6156     { Bad_Opcode },
6157     { Bad_Opcode },
6158     { Bad_Opcode },
6159     { Bad_Opcode },
6160     { Bad_Opcode },
6161     { Bad_Opcode },
6162     { Bad_Opcode },
6163     /* a8 */
6164     { Bad_Opcode },
6165     { Bad_Opcode },
6166     { Bad_Opcode },
6167     { Bad_Opcode },
6168     { Bad_Opcode },
6169     { Bad_Opcode },
6170     { Bad_Opcode },
6171     { Bad_Opcode },
6172     /* b0 */
6173     { Bad_Opcode },
6174     { Bad_Opcode },
6175     { Bad_Opcode },
6176     { Bad_Opcode },
6177     { Bad_Opcode },
6178     { Bad_Opcode },
6179     { Bad_Opcode },
6180     { Bad_Opcode },
6181     /* b8 */
6182     { Bad_Opcode },
6183     { Bad_Opcode },
6184     { Bad_Opcode },
6185     { Bad_Opcode },
6186     { Bad_Opcode },
6187     { Bad_Opcode },
6188     { Bad_Opcode },
6189     { Bad_Opcode },
6190     /* c0 */
6191     { Bad_Opcode },
6192     { Bad_Opcode },
6193     { Bad_Opcode },
6194     { Bad_Opcode },
6195     { Bad_Opcode },
6196     { Bad_Opcode },
6197     { Bad_Opcode },
6198     { Bad_Opcode },
6199     /* c8 */
6200     { Bad_Opcode },
6201     { Bad_Opcode },
6202     { Bad_Opcode },
6203     { Bad_Opcode },
6204     { Bad_Opcode },
6205     { Bad_Opcode },
6206     { Bad_Opcode },
6207     { Bad_Opcode },
6208     /* d0 */
6209     { Bad_Opcode },
6210     { Bad_Opcode },
6211     { Bad_Opcode },
6212     { Bad_Opcode },
6213     { Bad_Opcode },
6214     { Bad_Opcode },
6215     { Bad_Opcode },
6216     { Bad_Opcode },
6217     /* d8 */
6218     { Bad_Opcode },
6219     { Bad_Opcode },
6220     { Bad_Opcode },
6221     { Bad_Opcode },
6222     { Bad_Opcode },
6223     { Bad_Opcode },
6224     { Bad_Opcode },
6225     { Bad_Opcode },
6226     /* e0 */
6227     { Bad_Opcode },
6228     { Bad_Opcode },
6229     { Bad_Opcode },
6230     { Bad_Opcode },
6231     { Bad_Opcode },
6232     { Bad_Opcode },
6233     { Bad_Opcode },
6234     { Bad_Opcode },
6235     /* e8 */
6236     { Bad_Opcode },
6237     { Bad_Opcode },
6238     { Bad_Opcode },
6239     { Bad_Opcode },
6240     { Bad_Opcode },
6241     { Bad_Opcode },
6242     { Bad_Opcode },
6243     { Bad_Opcode },
6244     /* f0 */
6245     { Bad_Opcode },
6246     { Bad_Opcode },
6247     { Bad_Opcode },
6248     { Bad_Opcode },
6249     { Bad_Opcode },
6250     { Bad_Opcode },
6251     { Bad_Opcode },
6252     { Bad_Opcode },
6253     /* f8 */
6254     { Bad_Opcode },
6255     { Bad_Opcode },
6256     { Bad_Opcode },
6257     { Bad_Opcode },
6258     { Bad_Opcode },
6259     { Bad_Opcode },
6260     { Bad_Opcode },
6261     { Bad_Opcode },
6262   },
6263 };
6264
6265 static const struct dis386 vex_table[][256] = {
6266   /* VEX_0F */
6267   {
6268     /* 00 */
6269     { Bad_Opcode },
6270     { Bad_Opcode },
6271     { Bad_Opcode },
6272     { Bad_Opcode },
6273     { Bad_Opcode },
6274     { Bad_Opcode },
6275     { Bad_Opcode },
6276     { Bad_Opcode },
6277     /* 08 */
6278     { Bad_Opcode },
6279     { Bad_Opcode },
6280     { Bad_Opcode },
6281     { Bad_Opcode },
6282     { Bad_Opcode },
6283     { Bad_Opcode },
6284     { Bad_Opcode },
6285     { Bad_Opcode },
6286     /* 10 */
6287     { PREFIX_TABLE (PREFIX_0F10) },
6288     { PREFIX_TABLE (PREFIX_0F11) },
6289     { PREFIX_TABLE (PREFIX_VEX_0F12) },
6290     { VEX_LEN_TABLE (VEX_LEN_0F13) },
6291     { "vunpcklpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
6292     { "vunpckhpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
6293     { PREFIX_TABLE (PREFIX_VEX_0F16) },
6294     { VEX_LEN_TABLE (VEX_LEN_0F17) },
6295     /* 18 */
6296     { Bad_Opcode },
6297     { Bad_Opcode },
6298     { Bad_Opcode },
6299     { Bad_Opcode },
6300     { Bad_Opcode },
6301     { Bad_Opcode },
6302     { Bad_Opcode },
6303     { Bad_Opcode },
6304     /* 20 */
6305     { Bad_Opcode },
6306     { Bad_Opcode },
6307     { Bad_Opcode },
6308     { Bad_Opcode },
6309     { Bad_Opcode },
6310     { Bad_Opcode },
6311     { Bad_Opcode },
6312     { Bad_Opcode },
6313     /* 28 */
6314     { "vmovapX",        { XM, EXx }, PREFIX_OPCODE },
6315     { "vmovapX",        { EXxS, XM }, PREFIX_OPCODE },
6316     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
6317     { "vmovntpX",       { Mx, XM }, PREFIX_OPCODE },
6318     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
6319     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
6320     { PREFIX_TABLE (PREFIX_0F2E) },
6321     { PREFIX_TABLE (PREFIX_0F2F) },
6322     /* 30 */
6323     { Bad_Opcode },
6324     { Bad_Opcode },
6325     { Bad_Opcode },
6326     { Bad_Opcode },
6327     { Bad_Opcode },
6328     { Bad_Opcode },
6329     { Bad_Opcode },
6330     { Bad_Opcode },
6331     /* 38 */
6332     { Bad_Opcode },
6333     { Bad_Opcode },
6334     { Bad_Opcode },
6335     { Bad_Opcode },
6336     { Bad_Opcode },
6337     { Bad_Opcode },
6338     { Bad_Opcode },
6339     { Bad_Opcode },
6340     /* 40 */
6341     { Bad_Opcode },
6342     { VEX_LEN_TABLE (VEX_LEN_0F41) },
6343     { VEX_LEN_TABLE (VEX_LEN_0F42) },
6344     { Bad_Opcode },
6345     { VEX_LEN_TABLE (VEX_LEN_0F44) },
6346     { VEX_LEN_TABLE (VEX_LEN_0F45) },
6347     { VEX_LEN_TABLE (VEX_LEN_0F46) },
6348     { VEX_LEN_TABLE (VEX_LEN_0F47) },
6349     /* 48 */
6350     { Bad_Opcode },
6351     { Bad_Opcode },
6352     { VEX_LEN_TABLE (VEX_LEN_0F4A) },
6353     { VEX_LEN_TABLE (VEX_LEN_0F4B) },
6354     { Bad_Opcode },
6355     { Bad_Opcode },
6356     { Bad_Opcode },
6357     { Bad_Opcode },
6358     /* 50 */
6359     { "vmovmskpX",      { Gdq, Ux }, PREFIX_OPCODE },
6360     { PREFIX_TABLE (PREFIX_0F51) },
6361     { PREFIX_TABLE (PREFIX_0F52) },
6362     { PREFIX_TABLE (PREFIX_0F53) },
6363     { "vandpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
6364     { "vandnpX",        { XM, Vex, EXx }, PREFIX_OPCODE },
6365     { "vorpX",          { XM, Vex, EXx }, PREFIX_OPCODE },
6366     { "vxorpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
6367     /* 58 */
6368     { PREFIX_TABLE (PREFIX_0F58) },
6369     { PREFIX_TABLE (PREFIX_0F59) },
6370     { PREFIX_TABLE (PREFIX_0F5A) },
6371     { PREFIX_TABLE (PREFIX_0F5B) },
6372     { PREFIX_TABLE (PREFIX_0F5C) },
6373     { PREFIX_TABLE (PREFIX_0F5D) },
6374     { PREFIX_TABLE (PREFIX_0F5E) },
6375     { PREFIX_TABLE (PREFIX_0F5F) },
6376     /* 60 */
6377     { "vpunpcklbw",     { XM, Vex, EXx }, PREFIX_DATA },
6378     { "vpunpcklwd",     { XM, Vex, EXx }, PREFIX_DATA },
6379     { "vpunpckldq",     { XM, Vex, EXx }, PREFIX_DATA },
6380     { "vpacksswb",      { XM, Vex, EXx }, PREFIX_DATA },
6381     { "vpcmpgtb",       { XM, Vex, EXx }, PREFIX_DATA },
6382     { "vpcmpgtw",       { XM, Vex, EXx }, PREFIX_DATA },
6383     { "vpcmpgtd",       { XM, Vex, EXx }, PREFIX_DATA },
6384     { "vpackuswb",      { XM, Vex, EXx }, PREFIX_DATA },
6385     /* 68 */
6386     { "vpunpckhbw",     { XM, Vex, EXx }, PREFIX_DATA },
6387     { "vpunpckhwd",     { XM, Vex, EXx }, PREFIX_DATA },
6388     { "vpunpckhdq",     { XM, Vex, EXx }, PREFIX_DATA },
6389     { "vpackssdw",      { XM, Vex, EXx }, PREFIX_DATA },
6390     { "vpunpcklqdq",    { XM, Vex, EXx }, PREFIX_DATA },
6391     { "vpunpckhqdq",    { XM, Vex, EXx }, PREFIX_DATA },
6392     { VEX_LEN_TABLE (VEX_LEN_0F6E) },
6393     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
6394     /* 70 */
6395     { PREFIX_TABLE (PREFIX_VEX_0F70) },
6396     { REG_TABLE (REG_VEX_0F71) },
6397     { REG_TABLE (REG_VEX_0F72) },
6398     { REG_TABLE (REG_VEX_0F73) },
6399     { "vpcmpeqb",       { XM, Vex, EXx }, PREFIX_DATA },
6400     { "vpcmpeqw",       { XM, Vex, EXx }, PREFIX_DATA },
6401     { "vpcmpeqd",       { XM, Vex, EXx }, PREFIX_DATA },
6402     { VEX_LEN_TABLE (VEX_LEN_0F77) },
6403     /* 78 */
6404     { Bad_Opcode },
6405     { Bad_Opcode },
6406     { Bad_Opcode },
6407     { Bad_Opcode },
6408     { PREFIX_TABLE (PREFIX_0F7C) },
6409     { PREFIX_TABLE (PREFIX_0F7D) },
6410     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
6411     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
6412     /* 80 */
6413     { Bad_Opcode },
6414     { Bad_Opcode },
6415     { Bad_Opcode },
6416     { Bad_Opcode },
6417     { Bad_Opcode },
6418     { Bad_Opcode },
6419     { Bad_Opcode },
6420     { Bad_Opcode },
6421     /* 88 */
6422     { Bad_Opcode },
6423     { Bad_Opcode },
6424     { Bad_Opcode },
6425     { Bad_Opcode },
6426     { Bad_Opcode },
6427     { Bad_Opcode },
6428     { Bad_Opcode },
6429     { Bad_Opcode },
6430     /* 90 */
6431     { VEX_LEN_TABLE (VEX_LEN_0F90) },
6432     { VEX_LEN_TABLE (VEX_LEN_0F91) },
6433     { VEX_LEN_TABLE (VEX_LEN_0F92) },
6434     { VEX_LEN_TABLE (VEX_LEN_0F93) },
6435     { Bad_Opcode },
6436     { Bad_Opcode },
6437     { Bad_Opcode },
6438     { Bad_Opcode },
6439     /* 98 */
6440     { VEX_LEN_TABLE (VEX_LEN_0F98) },
6441     { VEX_LEN_TABLE (VEX_LEN_0F99) },
6442     { Bad_Opcode },
6443     { Bad_Opcode },
6444     { Bad_Opcode },
6445     { Bad_Opcode },
6446     { Bad_Opcode },
6447     { Bad_Opcode },
6448     /* a0 */
6449     { Bad_Opcode },
6450     { Bad_Opcode },
6451     { Bad_Opcode },
6452     { Bad_Opcode },
6453     { Bad_Opcode },
6454     { Bad_Opcode },
6455     { Bad_Opcode },
6456     { Bad_Opcode },
6457     /* a8 */
6458     { Bad_Opcode },
6459     { Bad_Opcode },
6460     { Bad_Opcode },
6461     { Bad_Opcode },
6462     { Bad_Opcode },
6463     { Bad_Opcode },
6464     { REG_TABLE (REG_VEX_0FAE) },
6465     { Bad_Opcode },
6466     /* b0 */
6467     { Bad_Opcode },
6468     { Bad_Opcode },
6469     { Bad_Opcode },
6470     { Bad_Opcode },
6471     { Bad_Opcode },
6472     { Bad_Opcode },
6473     { Bad_Opcode },
6474     { Bad_Opcode },
6475     /* b8 */
6476     { Bad_Opcode },
6477     { Bad_Opcode },
6478     { Bad_Opcode },
6479     { Bad_Opcode },
6480     { Bad_Opcode },
6481     { Bad_Opcode },
6482     { Bad_Opcode },
6483     { Bad_Opcode },
6484     /* c0 */
6485     { Bad_Opcode },
6486     { Bad_Opcode },
6487     { PREFIX_TABLE (PREFIX_0FC2) },
6488     { Bad_Opcode },
6489     { VEX_LEN_TABLE (VEX_LEN_0FC4) },
6490     { "vpextrw",        { Gd, Uxmm, Ib }, PREFIX_DATA },
6491     { "vshufpX",        { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
6492     { Bad_Opcode },
6493     /* c8 */
6494     { Bad_Opcode },
6495     { Bad_Opcode },
6496     { Bad_Opcode },
6497     { Bad_Opcode },
6498     { Bad_Opcode },
6499     { Bad_Opcode },
6500     { Bad_Opcode },
6501     { Bad_Opcode },
6502     /* d0 */
6503     { PREFIX_TABLE (PREFIX_0FD0) },
6504     { "vpsrlw",         { XM, Vex, EXxmm }, PREFIX_DATA },
6505     { "vpsrld",         { XM, Vex, EXxmm }, PREFIX_DATA },
6506     { "vpsrlq",         { XM, Vex, EXxmm }, PREFIX_DATA },
6507     { "vpaddq",         { XM, Vex, EXx }, PREFIX_DATA },
6508     { "vpmullw",        { XM, Vex, EXx }, PREFIX_DATA },
6509     { VEX_LEN_TABLE (VEX_LEN_0FD6) },
6510     { "vpmovmskb",      { Gdq, Ux }, PREFIX_DATA },
6511     /* d8 */
6512     { "vpsubusb",       { XM, Vex, EXx }, PREFIX_DATA },
6513     { "vpsubusw",       { XM, Vex, EXx }, PREFIX_DATA },
6514     { "vpminub",        { XM, Vex, EXx }, PREFIX_DATA },
6515     { "vpand",          { XM, Vex, EXx }, PREFIX_DATA },
6516     { "vpaddusb",       { XM, Vex, EXx }, PREFIX_DATA },
6517     { "vpaddusw",       { XM, Vex, EXx }, PREFIX_DATA },
6518     { "vpmaxub",        { XM, Vex, EXx }, PREFIX_DATA },
6519     { "vpandn",         { XM, Vex, EXx }, PREFIX_DATA },
6520     /* e0 */
6521     { "vpavgb",         { XM, Vex, EXx }, PREFIX_DATA },
6522     { "vpsraw",         { XM, Vex, EXxmm }, PREFIX_DATA },
6523     { "vpsrad",         { XM, Vex, EXxmm }, PREFIX_DATA },
6524     { "vpavgw",         { XM, Vex, EXx }, PREFIX_DATA },
6525     { "vpmulhuw",       { XM, Vex, EXx }, PREFIX_DATA },
6526     { "vpmulhw",        { XM, Vex, EXx }, PREFIX_DATA },
6527     { PREFIX_TABLE (PREFIX_0FE6) },
6528     { "vmovntdq",       { Mx, XM }, PREFIX_DATA },
6529     /* e8 */
6530     { "vpsubsb",        { XM, Vex, EXx }, PREFIX_DATA },
6531     { "vpsubsw",        { XM, Vex, EXx }, PREFIX_DATA },
6532     { "vpminsw",        { XM, Vex, EXx }, PREFIX_DATA },
6533     { "vpor",           { XM, Vex, EXx }, PREFIX_DATA },
6534     { "vpaddsb",        { XM, Vex, EXx }, PREFIX_DATA },
6535     { "vpaddsw",        { XM, Vex, EXx }, PREFIX_DATA },
6536     { "vpmaxsw",        { XM, Vex, EXx }, PREFIX_DATA },
6537     { "vpxor",          { XM, Vex, EXx }, PREFIX_DATA },
6538     /* f0 */
6539     { PREFIX_TABLE (PREFIX_0FF0) },
6540     { "vpsllw",         { XM, Vex, EXxmm }, PREFIX_DATA },
6541     { "vpslld",         { XM, Vex, EXxmm }, PREFIX_DATA },
6542     { "vpsllq",         { XM, Vex, EXxmm }, PREFIX_DATA },
6543     { "vpmuludq",       { XM, Vex, EXx }, PREFIX_DATA },
6544     { "vpmaddwd",       { XM, Vex, EXx }, PREFIX_DATA },
6545     { "vpsadbw",        { XM, Vex, EXx }, PREFIX_DATA },
6546     { "vmaskmovdqu",    { XM, Uxmm }, PREFIX_DATA },
6547     /* f8 */
6548     { "vpsubb",         { XM, Vex, EXx }, PREFIX_DATA },
6549     { "vpsubw",         { XM, Vex, EXx }, PREFIX_DATA },
6550     { "vpsubd",         { XM, Vex, EXx }, PREFIX_DATA },
6551     { "vpsubq",         { XM, Vex, EXx }, PREFIX_DATA },
6552     { "vpaddb",         { XM, Vex, EXx }, PREFIX_DATA },
6553     { "vpaddw",         { XM, Vex, EXx }, PREFIX_DATA },
6554     { "vpaddd",         { XM, Vex, EXx }, PREFIX_DATA },
6555     { Bad_Opcode },
6556   },
6557   /* VEX_0F38 */
6558   {
6559     /* 00 */
6560     { "vpshufb",        { XM, Vex, EXx }, PREFIX_DATA },
6561     { "vphaddw",        { XM, Vex, EXx }, PREFIX_DATA },
6562     { "vphaddd",        { XM, Vex, EXx }, PREFIX_DATA },
6563     { "vphaddsw",       { XM, Vex, EXx }, PREFIX_DATA },
6564     { "vpmaddubsw",     { XM, Vex, EXx }, PREFIX_DATA },
6565     { "vphsubw",        { XM, Vex, EXx }, PREFIX_DATA },
6566     { "vphsubd",        { XM, Vex, EXx }, PREFIX_DATA },
6567     { "vphsubsw",       { XM, Vex, EXx }, PREFIX_DATA },
6568     /* 08 */
6569     { "vpsignb",        { XM, Vex, EXx }, PREFIX_DATA },
6570     { "vpsignw",        { XM, Vex, EXx }, PREFIX_DATA },
6571     { "vpsignd",        { XM, Vex, EXx }, PREFIX_DATA },
6572     { "vpmulhrsw",      { XM, Vex, EXx }, PREFIX_DATA },
6573     { VEX_W_TABLE (VEX_W_0F380C) },
6574     { VEX_W_TABLE (VEX_W_0F380D) },
6575     { VEX_W_TABLE (VEX_W_0F380E) },
6576     { VEX_W_TABLE (VEX_W_0F380F) },
6577     /* 10 */
6578     { Bad_Opcode },
6579     { Bad_Opcode },
6580     { Bad_Opcode },
6581     { VEX_W_TABLE (VEX_W_0F3813) },
6582     { Bad_Opcode },
6583     { Bad_Opcode },
6584     { VEX_LEN_TABLE (VEX_LEN_0F3816) },
6585     { "vptest",         { XM, EXx }, PREFIX_DATA },
6586     /* 18 */
6587     { VEX_W_TABLE (VEX_W_0F3818) },
6588     { VEX_LEN_TABLE (VEX_LEN_0F3819) },
6589     { VEX_LEN_TABLE (VEX_LEN_0F381A) },
6590     { Bad_Opcode },
6591     { "vpabsb",         { XM, EXx }, PREFIX_DATA },
6592     { "vpabsw",         { XM, EXx }, PREFIX_DATA },
6593     { "vpabsd",         { XM, EXx }, PREFIX_DATA },
6594     { Bad_Opcode },
6595     /* 20 */
6596     { "vpmovsxbw",      { XM, EXxmmq }, PREFIX_DATA },
6597     { "vpmovsxbd",      { XM, EXxmmqd }, PREFIX_DATA },
6598     { "vpmovsxbq",      { XM, EXxmmdw }, PREFIX_DATA },
6599     { "vpmovsxwd",      { XM, EXxmmq }, PREFIX_DATA },
6600     { "vpmovsxwq",      { XM, EXxmmqd }, PREFIX_DATA },
6601     { "vpmovsxdq",      { XM, EXxmmq }, PREFIX_DATA },
6602     { Bad_Opcode },
6603     { Bad_Opcode },
6604     /* 28 */
6605     { "vpmuldq",        { XM, Vex, EXx }, PREFIX_DATA },
6606     { "vpcmpeqq",       { XM, Vex, EXx }, PREFIX_DATA },
6607     { "vmovntdqa",      { XM, Mx }, PREFIX_DATA },
6608     { "vpackusdw",      { XM, Vex, EXx }, PREFIX_DATA },
6609     { VEX_W_TABLE (VEX_W_0F382C) },
6610     { VEX_W_TABLE (VEX_W_0F382D) },
6611     { VEX_W_TABLE (VEX_W_0F382E) },
6612     { VEX_W_TABLE (VEX_W_0F382F) },
6613     /* 30 */
6614     { "vpmovzxbw",      { XM, EXxmmq }, PREFIX_DATA },
6615     { "vpmovzxbd",      { XM, EXxmmqd }, PREFIX_DATA },
6616     { "vpmovzxbq",      { XM, EXxmmdw }, PREFIX_DATA },
6617     { "vpmovzxwd",      { XM, EXxmmq }, PREFIX_DATA },
6618     { "vpmovzxwq",      { XM, EXxmmqd }, PREFIX_DATA },
6619     { "vpmovzxdq",      { XM, EXxmmq }, PREFIX_DATA },
6620     { VEX_LEN_TABLE (VEX_LEN_0F3836) },
6621     { "vpcmpgtq",       { XM, Vex, EXx }, PREFIX_DATA },
6622     /* 38 */
6623     { "vpminsb",        { XM, Vex, EXx }, PREFIX_DATA },
6624     { "vpminsd",        { XM, Vex, EXx }, PREFIX_DATA },
6625     { "vpminuw",        { XM, Vex, EXx }, PREFIX_DATA },
6626     { "vpminud",        { XM, Vex, EXx }, PREFIX_DATA },
6627     { "vpmaxsb",        { XM, Vex, EXx }, PREFIX_DATA },
6628     { "vpmaxsd",        { XM, Vex, EXx }, PREFIX_DATA },
6629     { "vpmaxuw",        { XM, Vex, EXx }, PREFIX_DATA },
6630     { "vpmaxud",        { XM, Vex, EXx }, PREFIX_DATA },
6631     /* 40 */
6632     { "vpmulld",        { XM, Vex, EXx }, PREFIX_DATA },
6633     { VEX_LEN_TABLE (VEX_LEN_0F3841) },
6634     { Bad_Opcode },
6635     { Bad_Opcode },
6636     { Bad_Opcode },
6637     { "vpsrlv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6638     { VEX_W_TABLE (VEX_W_0F3846) },
6639     { "vpsllv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6640     /* 48 */
6641     { X86_64_TABLE (X86_64_VEX_0F3848) },
6642     { X86_64_TABLE (X86_64_VEX_0F3849) },
6643     { X86_64_TABLE (X86_64_VEX_0F384A) },
6644     { X86_64_TABLE (X86_64_VEX_0F384B) },
6645     { Bad_Opcode },
6646     { Bad_Opcode },
6647     { Bad_Opcode },
6648     { Bad_Opcode },
6649     /* 50 */
6650     { VEX_W_TABLE (VEX_W_0F3850) },
6651     { VEX_W_TABLE (VEX_W_0F3851) },
6652     { VEX_W_TABLE (VEX_W_0F3852) },
6653     { VEX_W_TABLE (VEX_W_0F3853) },
6654     { Bad_Opcode },
6655     { Bad_Opcode },
6656     { Bad_Opcode },
6657     { Bad_Opcode },
6658     /* 58 */
6659     { VEX_W_TABLE (VEX_W_0F3858) },
6660     { VEX_W_TABLE (VEX_W_0F3859) },
6661     { VEX_LEN_TABLE (VEX_LEN_0F385A) },
6662     { Bad_Opcode },
6663     { X86_64_TABLE (X86_64_VEX_0F385C) },
6664     { Bad_Opcode },
6665     { X86_64_TABLE (X86_64_VEX_0F385E) },
6666     { X86_64_TABLE (X86_64_VEX_0F385F) },
6667     /* 60 */
6668     { Bad_Opcode },
6669     { Bad_Opcode },
6670     { Bad_Opcode },
6671     { Bad_Opcode },
6672     { Bad_Opcode },
6673     { Bad_Opcode },
6674     { Bad_Opcode },
6675     { Bad_Opcode },
6676     /* 68 */
6677     { Bad_Opcode },
6678     { Bad_Opcode },
6679     { Bad_Opcode },
6680     { X86_64_TABLE (X86_64_VEX_0F386B) },
6681     { X86_64_TABLE (X86_64_VEX_0F386C) },
6682     { Bad_Opcode },
6683     { X86_64_TABLE (X86_64_VEX_0F386E) },
6684     { X86_64_TABLE (X86_64_VEX_0F386F) },
6685     /* 70 */
6686     { Bad_Opcode },
6687     { Bad_Opcode },
6688     { PREFIX_TABLE (PREFIX_VEX_0F3872) },
6689     { Bad_Opcode },
6690     { Bad_Opcode },
6691     { Bad_Opcode },
6692     { Bad_Opcode },
6693     { Bad_Opcode },
6694     /* 78 */
6695     { VEX_W_TABLE (VEX_W_0F3878) },
6696     { VEX_W_TABLE (VEX_W_0F3879) },
6697     { Bad_Opcode },
6698     { Bad_Opcode },
6699     { Bad_Opcode },
6700     { Bad_Opcode },
6701     { Bad_Opcode },
6702     { Bad_Opcode },
6703     /* 80 */
6704     { Bad_Opcode },
6705     { Bad_Opcode },
6706     { Bad_Opcode },
6707     { Bad_Opcode },
6708     { Bad_Opcode },
6709     { Bad_Opcode },
6710     { Bad_Opcode },
6711     { Bad_Opcode },
6712     /* 88 */
6713     { Bad_Opcode },
6714     { Bad_Opcode },
6715     { Bad_Opcode },
6716     { Bad_Opcode },
6717     { "vpmaskmov%DQ",   { XM, Vex, Mx }, PREFIX_DATA },
6718     { Bad_Opcode },
6719     { "vpmaskmov%DQ",   { Mx, Vex, XM }, PREFIX_DATA },
6720     { Bad_Opcode },
6721     /* 90 */
6722     { "vpgatherd%DQ", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
6723     { "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6724     { "vgatherdp%XW", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
6725     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6726     { Bad_Opcode },
6727     { Bad_Opcode },
6728     { "vfmaddsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6729     { "vfmsubadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6730     /* 98 */
6731     { "vfmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6732     { "vfmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6733     { "vfmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6734     { "vfmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6735     { "vfnmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6736     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6737     { "vfnmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6738     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6739     /* a0 */
6740     { Bad_Opcode },
6741     { Bad_Opcode },
6742     { Bad_Opcode },
6743     { Bad_Opcode },
6744     { Bad_Opcode },
6745     { Bad_Opcode },
6746     { "vfmaddsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6747     { "vfmsubadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6748     /* a8 */
6749     { "vfmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6750     { "vfmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6751     { "vfmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6752     { "vfmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6753     { "vfnmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6754     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6755     { "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6756     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6757     /* b0 */
6758     { VEX_W_TABLE (VEX_W_0F38B0) },
6759     { VEX_W_TABLE (VEX_W_0F38B1) },
6760     { Bad_Opcode },
6761     { Bad_Opcode },
6762     { VEX_W_TABLE (VEX_W_0F38B4) },
6763     { VEX_W_TABLE (VEX_W_0F38B5) },
6764     { "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6765     { "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6766     /* b8 */
6767     { "vfmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6768     { "vfmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6769     { "vfmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6770     { "vfmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6771     { "vfnmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6772     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6773     { "vfnmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6774     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6775     /* c0 */
6776     { Bad_Opcode },
6777     { Bad_Opcode },
6778     { Bad_Opcode },
6779     { Bad_Opcode },
6780     { Bad_Opcode },
6781     { Bad_Opcode },
6782     { Bad_Opcode },
6783     { Bad_Opcode },
6784     /* c8 */
6785     { Bad_Opcode },
6786     { Bad_Opcode },
6787     { Bad_Opcode },
6788     { PREFIX_TABLE (PREFIX_VEX_0F38CB) },
6789     { PREFIX_TABLE (PREFIX_VEX_0F38CC) },
6790     { PREFIX_TABLE (PREFIX_VEX_0F38CD) },
6791     { Bad_Opcode },
6792     { VEX_W_TABLE (VEX_W_0F38CF) },
6793     /* d0 */
6794     { Bad_Opcode },
6795     { Bad_Opcode },
6796     { VEX_W_TABLE (VEX_W_0F38D2) },
6797     { VEX_W_TABLE (VEX_W_0F38D3) },
6798     { Bad_Opcode },
6799     { Bad_Opcode },
6800     { Bad_Opcode },
6801     { Bad_Opcode },
6802     /* d8 */
6803     { Bad_Opcode },
6804     { Bad_Opcode },
6805     { VEX_W_TABLE (VEX_W_0F38DA) },
6806     { VEX_LEN_TABLE (VEX_LEN_0F38DB) },
6807     { "vaesenc",        { XM, Vex, EXx }, PREFIX_DATA },
6808     { "vaesenclast",    { XM, Vex, EXx }, PREFIX_DATA },
6809     { "vaesdec",        { XM, Vex, EXx }, PREFIX_DATA },
6810     { "vaesdeclast",    { XM, Vex, EXx }, PREFIX_DATA },
6811     /* e0 */
6812     { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6813     { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6814     { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6815     { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6816     { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6817     { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6818     { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6819     { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6820     /* e8 */
6821     { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6822     { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6823     { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6824     { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6825     { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6826     { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6827     { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6828     { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6829     /* f0 */
6830     { Bad_Opcode },
6831     { Bad_Opcode },
6832     { VEX_LEN_TABLE (VEX_LEN_0F38F2) },
6833     { VEX_LEN_TABLE (VEX_LEN_0F38F3) },
6834     { Bad_Opcode },
6835     { VEX_LEN_TABLE (VEX_LEN_0F38F5) },
6836     { VEX_LEN_TABLE (VEX_LEN_0F38F6) },
6837     { VEX_LEN_TABLE (VEX_LEN_0F38F7) },
6838     /* f8 */
6839     { Bad_Opcode },
6840     { Bad_Opcode },
6841     { Bad_Opcode },
6842     { Bad_Opcode },
6843     { Bad_Opcode },
6844     { Bad_Opcode },
6845     { Bad_Opcode },
6846     { Bad_Opcode },
6847   },
6848   /* VEX_0F3A */
6849   {
6850     /* 00 */
6851     { VEX_LEN_TABLE (VEX_LEN_0F3A00) },
6852     { VEX_LEN_TABLE (VEX_LEN_0F3A01) },
6853     { VEX_W_TABLE (VEX_W_0F3A02) },
6854     { Bad_Opcode },
6855     { VEX_W_TABLE (VEX_W_0F3A04) },
6856     { VEX_W_TABLE (VEX_W_0F3A05) },
6857     { VEX_LEN_TABLE (VEX_LEN_0F3A06) },
6858     { Bad_Opcode },
6859     /* 08 */
6860     { "vroundps",       { XM, EXx, Ib }, PREFIX_DATA },
6861     { "vroundpd",       { XM, EXx, Ib }, PREFIX_DATA },
6862     { "vroundss",       { XMScalar, VexScalar, EXd, Ib }, PREFIX_DATA },
6863     { "vroundsd",       { XMScalar, VexScalar, EXq, Ib }, PREFIX_DATA },
6864     { "vblendps",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6865     { "vblendpd",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6866     { "vpblendw",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6867     { "vpalignr",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6868     /* 10 */
6869     { Bad_Opcode },
6870     { Bad_Opcode },
6871     { Bad_Opcode },
6872     { Bad_Opcode },
6873     { VEX_LEN_TABLE (VEX_LEN_0F3A14) },
6874     { VEX_LEN_TABLE (VEX_LEN_0F3A15) },
6875     { VEX_LEN_TABLE (VEX_LEN_0F3A16) },
6876     { VEX_LEN_TABLE (VEX_LEN_0F3A17) },
6877     /* 18 */
6878     { VEX_LEN_TABLE (VEX_LEN_0F3A18) },
6879     { VEX_LEN_TABLE (VEX_LEN_0F3A19) },
6880     { Bad_Opcode },
6881     { Bad_Opcode },
6882     { Bad_Opcode },
6883     { VEX_W_TABLE (VEX_W_0F3A1D) },
6884     { Bad_Opcode },
6885     { Bad_Opcode },
6886     /* 20 */
6887     { VEX_LEN_TABLE (VEX_LEN_0F3A20) },
6888     { VEX_LEN_TABLE (VEX_LEN_0F3A21) },
6889     { VEX_LEN_TABLE (VEX_LEN_0F3A22) },
6890     { Bad_Opcode },
6891     { Bad_Opcode },
6892     { Bad_Opcode },
6893     { Bad_Opcode },
6894     { Bad_Opcode },
6895     /* 28 */
6896     { Bad_Opcode },
6897     { Bad_Opcode },
6898     { Bad_Opcode },
6899     { Bad_Opcode },
6900     { Bad_Opcode },
6901     { Bad_Opcode },
6902     { Bad_Opcode },
6903     { Bad_Opcode },
6904     /* 30 */
6905     { VEX_LEN_TABLE (VEX_LEN_0F3A30) },
6906     { VEX_LEN_TABLE (VEX_LEN_0F3A31) },
6907     { VEX_LEN_TABLE (VEX_LEN_0F3A32) },
6908     { VEX_LEN_TABLE (VEX_LEN_0F3A33) },
6909     { Bad_Opcode },
6910     { Bad_Opcode },
6911     { Bad_Opcode },
6912     { Bad_Opcode },
6913     /* 38 */
6914     { VEX_LEN_TABLE (VEX_LEN_0F3A38) },
6915     { VEX_LEN_TABLE (VEX_LEN_0F3A39) },
6916     { Bad_Opcode },
6917     { Bad_Opcode },
6918     { Bad_Opcode },
6919     { Bad_Opcode },
6920     { Bad_Opcode },
6921     { Bad_Opcode },
6922     /* 40 */
6923     { "vdpps",          { XM, Vex, EXx, Ib }, PREFIX_DATA },
6924     { VEX_LEN_TABLE (VEX_LEN_0F3A41) },
6925     { "vmpsadbw",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6926     { Bad_Opcode },
6927     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, PREFIX_DATA },
6928     { Bad_Opcode },
6929     { VEX_LEN_TABLE (VEX_LEN_0F3A46) },
6930     { Bad_Opcode },
6931     /* 48 */
6932     { "vpermil2ps",     { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6933     { "vpermil2pd",     { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6934     { VEX_W_TABLE (VEX_W_0F3A4A) },
6935     { VEX_W_TABLE (VEX_W_0F3A4B) },
6936     { VEX_W_TABLE (VEX_W_0F3A4C) },
6937     { Bad_Opcode },
6938     { Bad_Opcode },
6939     { Bad_Opcode },
6940     /* 50 */
6941     { Bad_Opcode },
6942     { Bad_Opcode },
6943     { Bad_Opcode },
6944     { Bad_Opcode },
6945     { Bad_Opcode },
6946     { Bad_Opcode },
6947     { Bad_Opcode },
6948     { Bad_Opcode },
6949     /* 58 */
6950     { Bad_Opcode },
6951     { Bad_Opcode },
6952     { Bad_Opcode },
6953     { Bad_Opcode },
6954     { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6955     { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6956     { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6957     { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6958     /* 60 */
6959     { VEX_LEN_TABLE (VEX_LEN_0F3A60) },
6960     { VEX_LEN_TABLE (VEX_LEN_0F3A61) },
6961     { VEX_LEN_TABLE (VEX_LEN_0F3A62) },
6962     { VEX_LEN_TABLE (VEX_LEN_0F3A63) },
6963     { Bad_Opcode },
6964     { Bad_Opcode },
6965     { Bad_Opcode },
6966     { Bad_Opcode },
6967     /* 68 */
6968     { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6969     { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6970     { "vfmaddss",       { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6971     { "vfmaddsd",       { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6972     { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6973     { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6974     { "vfmsubss",       { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6975     { "vfmsubsd",       { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6976     /* 70 */
6977     { Bad_Opcode },
6978     { Bad_Opcode },
6979     { Bad_Opcode },
6980     { Bad_Opcode },
6981     { Bad_Opcode },
6982     { Bad_Opcode },
6983     { Bad_Opcode },
6984     { Bad_Opcode },
6985     /* 78 */
6986     { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6987     { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6988     { "vfnmaddss",      { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6989     { "vfnmaddsd",      { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6990     { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6991     { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6992     { "vfnmsubss",      { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6993     { "vfnmsubsd",      { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6994     /* 80 */
6995     { Bad_Opcode },
6996     { Bad_Opcode },
6997     { Bad_Opcode },
6998     { Bad_Opcode },
6999     { Bad_Opcode },
7000     { Bad_Opcode },
7001     { Bad_Opcode },
7002     { Bad_Opcode },
7003     /* 88 */
7004     { Bad_Opcode },
7005     { Bad_Opcode },
7006     { Bad_Opcode },
7007     { Bad_Opcode },
7008     { Bad_Opcode },
7009     { Bad_Opcode },
7010     { Bad_Opcode },
7011     { Bad_Opcode },
7012     /* 90 */
7013     { Bad_Opcode },
7014     { Bad_Opcode },
7015     { Bad_Opcode },
7016     { Bad_Opcode },
7017     { Bad_Opcode },
7018     { Bad_Opcode },
7019     { Bad_Opcode },
7020     { Bad_Opcode },
7021     /* 98 */
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     { Bad_Opcode },
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     { Bad_Opcode },
7028     { Bad_Opcode },
7029     { Bad_Opcode },
7030     /* a0 */
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     { Bad_Opcode },
7034     { Bad_Opcode },
7035     { Bad_Opcode },
7036     { Bad_Opcode },
7037     { Bad_Opcode },
7038     { Bad_Opcode },
7039     /* a8 */
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     { Bad_Opcode },
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     /* b0 */
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     /* b8 */
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     /* c0 */
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     /* c8 */
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { VEX_W_TABLE (VEX_W_0F3ACE) },
7083     { VEX_W_TABLE (VEX_W_0F3ACF) },
7084     /* d0 */
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     /* d8 */
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { VEX_W_TABLE (VEX_W_0F3ADE) },
7101     { VEX_LEN_TABLE (VEX_LEN_0F3ADF) },
7102     /* e0 */
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     /* e8 */
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     /* f0 */
7121     { VEX_LEN_TABLE (VEX_LEN_0F3AF0) },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     /* f8 */
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138   },
7139 };
7140
7141 #include "i386-dis-evex.h"
7142
7143 static const struct dis386 vex_len_table[][2] = {
7144   /* VEX_LEN_0F12_P_0 */
7145   {
7146     { MOD_TABLE (MOD_0F12_PREFIX_0) },
7147   },
7148
7149   /* VEX_LEN_0F12_P_2 */
7150   {
7151     { "%XEVmovlpYX",    { XM, Vex, Mq }, 0 },
7152   },
7153
7154   /* VEX_LEN_0F13 */
7155   {
7156     { "%XEVmovlpYX",    { Mq, XM }, PREFIX_OPCODE },
7157   },
7158
7159   /* VEX_LEN_0F16_P_0 */
7160   {
7161     { MOD_TABLE (MOD_0F16_PREFIX_0) },
7162   },
7163
7164   /* VEX_LEN_0F16_P_2 */
7165   {
7166     { "%XEVmovhpYX",    { XM, Vex, Mq }, 0 },
7167   },
7168
7169   /* VEX_LEN_0F17 */
7170   {
7171     { "%XEVmovhpYX",    { Mq, XM }, PREFIX_OPCODE },
7172   },
7173
7174   /* VEX_LEN_0F41 */
7175   {
7176     { Bad_Opcode },
7177     { VEX_W_TABLE (VEX_W_0F41_L_1) },
7178   },
7179
7180   /* VEX_LEN_0F42 */
7181   {
7182     { Bad_Opcode },
7183     { VEX_W_TABLE (VEX_W_0F42_L_1) },
7184   },
7185
7186   /* VEX_LEN_0F44 */
7187   {
7188     { VEX_W_TABLE (VEX_W_0F44_L_0) },
7189   },
7190
7191   /* VEX_LEN_0F45 */
7192   {
7193     { Bad_Opcode },
7194     { VEX_W_TABLE (VEX_W_0F45_L_1) },
7195   },
7196
7197   /* VEX_LEN_0F46 */
7198   {
7199     { Bad_Opcode },
7200     { VEX_W_TABLE (VEX_W_0F46_L_1) },
7201   },
7202
7203   /* VEX_LEN_0F47 */
7204   {
7205     { Bad_Opcode },
7206     { VEX_W_TABLE (VEX_W_0F47_L_1) },
7207   },
7208
7209   /* VEX_LEN_0F4A */
7210   {
7211     { Bad_Opcode },
7212     { VEX_W_TABLE (VEX_W_0F4A_L_1) },
7213   },
7214
7215   /* VEX_LEN_0F4B */
7216   {
7217     { Bad_Opcode },
7218     { VEX_W_TABLE (VEX_W_0F4B_L_1) },
7219   },
7220
7221   /* VEX_LEN_0F6E */
7222   {
7223     { "%XEvmovYK",      { XMScalar, Edq }, PREFIX_DATA },
7224   },
7225
7226   /* VEX_LEN_0F77 */
7227   {
7228     { "vzeroupper",     { XX }, 0 },
7229     { "vzeroall",       { XX }, 0 },
7230   },
7231
7232   /* VEX_LEN_0F7E_P_1 */
7233   {
7234     { "%XEvmovqY",      { XMScalar, EXq }, 0 },
7235   },
7236
7237   /* VEX_LEN_0F7E_P_2 */
7238   {
7239     { "%XEvmovK",       { Edq, XMScalar }, 0 },
7240   },
7241
7242   /* VEX_LEN_0F90 */
7243   {
7244     { VEX_W_TABLE (VEX_W_0F90_L_0) },
7245   },
7246
7247   /* VEX_LEN_0F91 */
7248   {
7249     { VEX_W_TABLE (VEX_W_0F91_L_0) },
7250   },
7251
7252   /* VEX_LEN_0F92 */
7253   {
7254     { VEX_W_TABLE (VEX_W_0F92_L_0) },
7255   },
7256
7257   /* VEX_LEN_0F93 */
7258   {
7259     { VEX_W_TABLE (VEX_W_0F93_L_0) },
7260   },
7261
7262   /* VEX_LEN_0F98 */
7263   {
7264     { VEX_W_TABLE (VEX_W_0F98_L_0) },
7265   },
7266
7267   /* VEX_LEN_0F99 */
7268   {
7269     { VEX_W_TABLE (VEX_W_0F99_L_0) },
7270   },
7271
7272   /* VEX_LEN_0FAE_R_2 */
7273   {
7274     { "vldmxcsr",       { Md }, 0 },
7275   },
7276
7277   /* VEX_LEN_0FAE_R_3 */
7278   {
7279     { "vstmxcsr",       { Md }, 0 },
7280   },
7281
7282   /* VEX_LEN_0FC4 */
7283   {
7284     { "%XEvpinsrwY",    { XM, Vex, Edw, Ib }, PREFIX_DATA },
7285   },
7286
7287   /* VEX_LEN_0FD6 */
7288   {
7289     { "%XEvmovqY",      { EXqS, XMScalar }, PREFIX_DATA },
7290   },
7291
7292   /* VEX_LEN_0F3816 */
7293   {
7294     { Bad_Opcode },
7295     { VEX_W_TABLE (VEX_W_0F3816_L_1) },
7296   },
7297
7298   /* VEX_LEN_0F3819 */
7299   {
7300     { Bad_Opcode },
7301     { VEX_W_TABLE (VEX_W_0F3819_L_1) },
7302   },
7303
7304   /* VEX_LEN_0F381A */
7305   {
7306     { Bad_Opcode },
7307     { VEX_W_TABLE (VEX_W_0F381A_L_1) },
7308   },
7309
7310   /* VEX_LEN_0F3836 */
7311   {
7312     { Bad_Opcode },
7313     { VEX_W_TABLE (VEX_W_0F3836) },
7314   },
7315
7316   /* VEX_LEN_0F3841 */
7317   {
7318     { "vphminposuw",    { XM, EXx }, PREFIX_DATA },
7319   },
7320
7321   /* VEX_LEN_0F3848_X86_64 */
7322   {
7323     { VEX_W_TABLE (VEX_W_0F3848_X86_64_L_0) },
7324   },
7325
7326   /* VEX_LEN_0F3849_X86_64 */
7327   {
7328     { VEX_W_TABLE (VEX_W_0F3849_X86_64_L_0) },
7329   },
7330
7331   /* VEX_LEN_0F384A_X86_64_W_0 */
7332   {
7333     { PREFIX_TABLE (PREFIX_VEX_0F384A_X86_64_W_0_L_0) },
7334   },
7335
7336   /* VEX_LEN_0F384B_X86_64 */
7337   {
7338     { VEX_W_TABLE (VEX_W_0F384B_X86_64_L_0) },
7339   },
7340
7341   /* VEX_LEN_0F385A */
7342   {
7343     { Bad_Opcode },
7344     { VEX_W_TABLE (VEX_W_0F385A_L_0) },
7345   },
7346
7347   /* VEX_LEN_0F385C_X86_64 */
7348   {
7349     { VEX_W_TABLE (VEX_W_0F385C_X86_64_L_0) },
7350   },
7351
7352   /* VEX_LEN_0F385E_X86_64 */
7353   {
7354     { VEX_W_TABLE (VEX_W_0F385E_X86_64_L_0) },
7355   },
7356
7357   /* VEX_LEN_0F385F_X86_64 */
7358   {
7359     { VEX_W_TABLE (VEX_W_0F385F_X86_64_L_0) },
7360   },
7361
7362   /* VEX_LEN_0F386B_X86_64 */
7363   {
7364     { VEX_W_TABLE (VEX_W_0F386B_X86_64_L_0) },
7365   },
7366
7367   /* VEX_LEN_0F386C_X86_64 */
7368   {
7369     { VEX_W_TABLE (VEX_W_0F386C_X86_64_L_0) },
7370   },
7371
7372   /* VEX_LEN_0F386E_X86_64 */
7373   {
7374     { VEX_W_TABLE (VEX_W_0F386E_X86_64_L_0) },
7375   },
7376
7377   /* VEX_LEN_0F386F_X86_64 */
7378   {
7379     { VEX_W_TABLE (VEX_W_0F386F_X86_64_L_0) },
7380   },
7381
7382   /* VEX_LEN_0F38CB_P_3_W_0 */
7383   {
7384     { Bad_Opcode },
7385     { "vsha512rnds2", { XM, Vex, Rxmmq }, 0 },
7386   },
7387
7388   /* VEX_LEN_0F38CC_P_3_W_0 */
7389   {
7390     { Bad_Opcode },
7391     { "vsha512msg1", { XM, Rxmmq }, 0 },
7392   },
7393
7394   /* VEX_LEN_0F38CD_P_3_W_0 */
7395   {
7396     { Bad_Opcode },
7397     { "vsha512msg2", { XM, Rymm }, 0 },
7398   },
7399
7400   /* VEX_LEN_0F38DA_W_0_P_0 */
7401   {
7402     { "vsm3msg1", { XM, Vex, EXxmm }, 0 },
7403   },
7404
7405   /* VEX_LEN_0F38DA_W_0_P_2 */
7406   {
7407     { "vsm3msg2", { XM, Vex, EXxmm }, 0 },
7408   },
7409
7410   /* VEX_LEN_0F38DB */
7411   {
7412     { "vaesimc",        { XM, EXx }, PREFIX_DATA },
7413   },
7414
7415   /* VEX_LEN_0F38F2 */
7416   {
7417     { PREFIX_TABLE (PREFIX_VEX_0F38F2_L_0) },
7418   },
7419
7420   /* VEX_LEN_0F38F3 */
7421   {
7422     { PREFIX_TABLE (PREFIX_VEX_0F38F3_L_0) },
7423   },
7424
7425   /* VEX_LEN_0F38F5 */
7426   {
7427     { PREFIX_TABLE(PREFIX_VEX_0F38F5_L_0) },
7428   },
7429
7430   /* VEX_LEN_0F38F6 */
7431   {
7432     { PREFIX_TABLE(PREFIX_VEX_0F38F6_L_0) },
7433   },
7434
7435   /* VEX_LEN_0F38F7 */
7436   {
7437     { PREFIX_TABLE(PREFIX_VEX_0F38F7_L_0) },
7438   },
7439
7440   /* VEX_LEN_0F3A00 */
7441   {
7442     { Bad_Opcode },
7443     { VEX_W_TABLE (VEX_W_0F3A00_L_1) },
7444   },
7445
7446   /* VEX_LEN_0F3A01 */
7447   {
7448     { Bad_Opcode },
7449     { VEX_W_TABLE (VEX_W_0F3A01_L_1) },
7450   },
7451
7452   /* VEX_LEN_0F3A06 */
7453   {
7454     { Bad_Opcode },
7455     { VEX_W_TABLE (VEX_W_0F3A06_L_1) },
7456   },
7457
7458   /* VEX_LEN_0F3A14 */
7459   {
7460     { "%XEvpextrb",     { Edb, XM, Ib }, PREFIX_DATA },
7461   },
7462
7463   /* VEX_LEN_0F3A15 */
7464   {
7465     { "%XEvpextrw",     { Edw, XM, Ib }, PREFIX_DATA },
7466   },
7467
7468   /* VEX_LEN_0F3A16  */
7469   {
7470     { "%XEvpextrK",     { Edq, XM, Ib }, PREFIX_DATA },
7471   },
7472
7473   /* VEX_LEN_0F3A17 */
7474   {
7475     { "%XEvextractps",  { Ed, XM, Ib }, PREFIX_DATA },
7476   },
7477
7478   /* VEX_LEN_0F3A18 */
7479   {
7480     { Bad_Opcode },
7481     { VEX_W_TABLE (VEX_W_0F3A18_L_1) },
7482   },
7483
7484   /* VEX_LEN_0F3A19 */
7485   {
7486     { Bad_Opcode },
7487     { VEX_W_TABLE (VEX_W_0F3A19_L_1) },
7488   },
7489
7490   /* VEX_LEN_0F3A20 */
7491   {
7492     { "%XEvpinsrbY",    { XM, Vex, Edb, Ib }, PREFIX_DATA },
7493   },
7494
7495   /* VEX_LEN_0F3A21 */
7496   {
7497     { "%XEvinsertpsY",  { XM, Vex, EXd, Ib }, PREFIX_DATA },
7498   },
7499
7500   /* VEX_LEN_0F3A22 */
7501   {
7502     { "%XEvpinsrYK",    { XM, Vex, Edq, Ib }, PREFIX_DATA },
7503   },
7504
7505   /* VEX_LEN_0F3A30 */
7506   {
7507     { "kshiftr%BW",     { MaskG, MaskR, Ib }, PREFIX_DATA },
7508   },
7509
7510   /* VEX_LEN_0F3A31 */
7511   {
7512     { "kshiftr%DQ",     { MaskG, MaskR, Ib }, PREFIX_DATA },
7513   },
7514
7515   /* VEX_LEN_0F3A32 */
7516   {
7517     { "kshiftl%BW",     { MaskG, MaskR, Ib }, PREFIX_DATA },
7518   },
7519
7520   /* VEX_LEN_0F3A33 */
7521   {
7522     { "kshiftl%DQ",     { MaskG, MaskR, Ib }, PREFIX_DATA },
7523   },
7524
7525   /* VEX_LEN_0F3A38 */
7526   {
7527     { Bad_Opcode },
7528     { VEX_W_TABLE (VEX_W_0F3A38_L_1) },
7529   },
7530
7531   /* VEX_LEN_0F3A39 */
7532   {
7533     { Bad_Opcode },
7534     { VEX_W_TABLE (VEX_W_0F3A39_L_1) },
7535   },
7536
7537   /* VEX_LEN_0F3A41 */
7538   {
7539     { "vdppd",          { XM, Vex, EXx, Ib }, PREFIX_DATA },
7540   },
7541
7542   /* VEX_LEN_0F3A46 */
7543   {
7544     { Bad_Opcode },
7545     { VEX_W_TABLE (VEX_W_0F3A46_L_1) },
7546   },
7547
7548   /* VEX_LEN_0F3A60 */
7549   {
7550     { "vpcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7551   },
7552
7553   /* VEX_LEN_0F3A61 */
7554   {
7555     { "vpcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7556   },
7557
7558   /* VEX_LEN_0F3A62 */
7559   {
7560     { "vpcmpistrm",     { XM, EXx, Ib }, PREFIX_DATA },
7561   },
7562
7563   /* VEX_LEN_0F3A63 */
7564   {
7565     { "vpcmpistri",     { XM, EXx, Ib }, PREFIX_DATA },
7566   },
7567
7568   /* VEX_LEN_0F3ADE_W_0 */
7569   {
7570     { "vsm3rnds2", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7571   },
7572
7573   /* VEX_LEN_0F3ADF */
7574   {
7575     { "vaeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
7576   },
7577
7578   /* VEX_LEN_0F3AF0 */
7579   {
7580     { PREFIX_TABLE (PREFIX_VEX_0F3AF0_L_0) },
7581   },
7582
7583   /* VEX_LEN_MAP5_F8_X86_64 */
7584   {
7585     { VEX_W_TABLE (VEX_W_MAP5_F8_X86_64_L_0) },
7586   },
7587
7588   /* VEX_LEN_MAP5_F9_X86_64 */
7589   {
7590     { VEX_W_TABLE (VEX_W_MAP5_F9_X86_64_L_0) },
7591   },
7592
7593   /* VEX_LEN_MAP5_FD_X86_64 */
7594   {
7595     { VEX_W_TABLE (VEX_W_MAP5_FD_X86_64_L_0) },
7596   },
7597
7598   /* VEX_LEN_MAP7_F6 */
7599   {
7600     { VEX_W_TABLE (VEX_W_MAP7_F6_L_0) },
7601   },
7602
7603   /* VEX_LEN_MAP7_F8 */
7604   {
7605     { VEX_W_TABLE (VEX_W_MAP7_F8_L_0) },
7606   },
7607
7608   /* VEX_LEN_XOP_08_85 */
7609   {
7610     { VEX_W_TABLE (VEX_W_XOP_08_85_L_0) },
7611   },
7612
7613   /* VEX_LEN_XOP_08_86 */
7614   {
7615     { VEX_W_TABLE (VEX_W_XOP_08_86_L_0) },
7616   },
7617
7618   /* VEX_LEN_XOP_08_87 */
7619   {
7620     { VEX_W_TABLE (VEX_W_XOP_08_87_L_0) },
7621   },
7622
7623   /* VEX_LEN_XOP_08_8E */
7624   {
7625     { VEX_W_TABLE (VEX_W_XOP_08_8E_L_0) },
7626   },
7627
7628   /* VEX_LEN_XOP_08_8F */
7629   {
7630     { VEX_W_TABLE (VEX_W_XOP_08_8F_L_0) },
7631   },
7632
7633   /* VEX_LEN_XOP_08_95 */
7634   {
7635     { VEX_W_TABLE (VEX_W_XOP_08_95_L_0) },
7636   },
7637
7638   /* VEX_LEN_XOP_08_96 */
7639   {
7640     { VEX_W_TABLE (VEX_W_XOP_08_96_L_0) },
7641   },
7642
7643   /* VEX_LEN_XOP_08_97 */
7644   {
7645     { VEX_W_TABLE (VEX_W_XOP_08_97_L_0) },
7646   },
7647
7648   /* VEX_LEN_XOP_08_9E */
7649   {
7650     { VEX_W_TABLE (VEX_W_XOP_08_9E_L_0) },
7651   },
7652
7653   /* VEX_LEN_XOP_08_9F */
7654   {
7655     { VEX_W_TABLE (VEX_W_XOP_08_9F_L_0) },
7656   },
7657
7658   /* VEX_LEN_XOP_08_A3 */
7659   {
7660     { "vpperm",         { XM, Vex, EXx, XMVexI4 }, 0 },
7661   },
7662
7663   /* VEX_LEN_XOP_08_A6 */
7664   {
7665     { VEX_W_TABLE (VEX_W_XOP_08_A6_L_0) },
7666   },
7667
7668   /* VEX_LEN_XOP_08_B6 */
7669   {
7670     { VEX_W_TABLE (VEX_W_XOP_08_B6_L_0) },
7671   },
7672
7673   /* VEX_LEN_XOP_08_C0 */
7674   {
7675     { VEX_W_TABLE (VEX_W_XOP_08_C0_L_0) },
7676   },
7677
7678   /* VEX_LEN_XOP_08_C1 */
7679   {
7680     { VEX_W_TABLE (VEX_W_XOP_08_C1_L_0) },
7681   },
7682
7683   /* VEX_LEN_XOP_08_C2 */
7684   {
7685     { VEX_W_TABLE (VEX_W_XOP_08_C2_L_0) },
7686   },
7687
7688   /* VEX_LEN_XOP_08_C3 */
7689   {
7690     { VEX_W_TABLE (VEX_W_XOP_08_C3_L_0) },
7691   },
7692
7693   /* VEX_LEN_XOP_08_CC */
7694   {
7695     { VEX_W_TABLE (VEX_W_XOP_08_CC_L_0) },
7696   },
7697
7698   /* VEX_LEN_XOP_08_CD */
7699   {
7700     { VEX_W_TABLE (VEX_W_XOP_08_CD_L_0) },
7701   },
7702
7703   /* VEX_LEN_XOP_08_CE */
7704   {
7705     { VEX_W_TABLE (VEX_W_XOP_08_CE_L_0) },
7706   },
7707
7708   /* VEX_LEN_XOP_08_CF */
7709   {
7710     { VEX_W_TABLE (VEX_W_XOP_08_CF_L_0) },
7711   },
7712
7713   /* VEX_LEN_XOP_08_EC */
7714   {
7715     { VEX_W_TABLE (VEX_W_XOP_08_EC_L_0) },
7716   },
7717
7718   /* VEX_LEN_XOP_08_ED */
7719   {
7720     { VEX_W_TABLE (VEX_W_XOP_08_ED_L_0) },
7721   },
7722
7723   /* VEX_LEN_XOP_08_EE */
7724   {
7725     { VEX_W_TABLE (VEX_W_XOP_08_EE_L_0) },
7726   },
7727
7728   /* VEX_LEN_XOP_08_EF */
7729   {
7730     { VEX_W_TABLE (VEX_W_XOP_08_EF_L_0) },
7731   },
7732
7733   /* VEX_LEN_XOP_09_01 */
7734   {
7735     { REG_TABLE (REG_XOP_09_01_L_0) },
7736   },
7737
7738   /* VEX_LEN_XOP_09_02 */
7739   {
7740     { REG_TABLE (REG_XOP_09_02_L_0) },
7741   },
7742
7743   /* VEX_LEN_XOP_09_12 */
7744   {
7745     { REG_TABLE (REG_XOP_09_12_L_0) },
7746   },
7747
7748   /* VEX_LEN_XOP_09_82_W_0 */
7749   {
7750     { "vfrczss",        { XM, EXd }, 0 },
7751   },
7752
7753   /* VEX_LEN_XOP_09_83_W_0 */
7754   {
7755     { "vfrczsd",        { XM, EXq }, 0 },
7756   },
7757
7758   /* VEX_LEN_XOP_09_90 */
7759   {
7760     { "vprotb",         { XM, EXx, VexW }, 0 },
7761   },
7762
7763   /* VEX_LEN_XOP_09_91 */
7764   {
7765     { "vprotw",         { XM, EXx, VexW }, 0 },
7766   },
7767
7768   /* VEX_LEN_XOP_09_92 */
7769   {
7770     { "vprotd",         { XM, EXx, VexW }, 0 },
7771   },
7772
7773   /* VEX_LEN_XOP_09_93 */
7774   {
7775     { "vprotq",         { XM, EXx, VexW }, 0 },
7776   },
7777
7778   /* VEX_LEN_XOP_09_94 */
7779   {
7780     { "vpshlb",         { XM, EXx, VexW }, 0 },
7781   },
7782
7783   /* VEX_LEN_XOP_09_95 */
7784   {
7785     { "vpshlw",         { XM, EXx, VexW }, 0 },
7786   },
7787
7788   /* VEX_LEN_XOP_09_96 */
7789   {
7790     { "vpshld",         { XM, EXx, VexW }, 0 },
7791   },
7792
7793   /* VEX_LEN_XOP_09_97 */
7794   {
7795     { "vpshlq",         { XM, EXx, VexW }, 0 },
7796   },
7797
7798   /* VEX_LEN_XOP_09_98 */
7799   {
7800     { "vpshab",         { XM, EXx, VexW }, 0 },
7801   },
7802
7803   /* VEX_LEN_XOP_09_99 */
7804   {
7805     { "vpshaw",         { XM, EXx, VexW }, 0 },
7806   },
7807
7808   /* VEX_LEN_XOP_09_9A */
7809   {
7810     { "vpshad",         { XM, EXx, VexW }, 0 },
7811   },
7812
7813   /* VEX_LEN_XOP_09_9B */
7814   {
7815     { "vpshaq",         { XM, EXx, VexW }, 0 },
7816   },
7817
7818   /* VEX_LEN_XOP_09_C1 */
7819   {
7820     { VEX_W_TABLE (VEX_W_XOP_09_C1_L_0) },
7821   },
7822
7823   /* VEX_LEN_XOP_09_C2 */
7824   {
7825     { VEX_W_TABLE (VEX_W_XOP_09_C2_L_0) },
7826   },
7827
7828   /* VEX_LEN_XOP_09_C3 */
7829   {
7830     { VEX_W_TABLE (VEX_W_XOP_09_C3_L_0) },
7831   },
7832
7833   /* VEX_LEN_XOP_09_C6 */
7834   {
7835     { VEX_W_TABLE (VEX_W_XOP_09_C6_L_0) },
7836   },
7837
7838   /* VEX_LEN_XOP_09_C7 */
7839   {
7840     { VEX_W_TABLE (VEX_W_XOP_09_C7_L_0) },
7841   },
7842
7843   /* VEX_LEN_XOP_09_CB */
7844   {
7845     { VEX_W_TABLE (VEX_W_XOP_09_CB_L_0) },
7846   },
7847
7848   /* VEX_LEN_XOP_09_D1 */
7849   {
7850     { VEX_W_TABLE (VEX_W_XOP_09_D1_L_0) },
7851   },
7852
7853   /* VEX_LEN_XOP_09_D2 */
7854   {
7855     { VEX_W_TABLE (VEX_W_XOP_09_D2_L_0) },
7856   },
7857
7858   /* VEX_LEN_XOP_09_D3 */
7859   {
7860     { VEX_W_TABLE (VEX_W_XOP_09_D3_L_0) },
7861   },
7862
7863   /* VEX_LEN_XOP_09_D6 */
7864   {
7865     { VEX_W_TABLE (VEX_W_XOP_09_D6_L_0) },
7866   },
7867
7868   /* VEX_LEN_XOP_09_D7 */
7869   {
7870     { VEX_W_TABLE (VEX_W_XOP_09_D7_L_0) },
7871   },
7872
7873   /* VEX_LEN_XOP_09_DB */
7874   {
7875     { VEX_W_TABLE (VEX_W_XOP_09_DB_L_0) },
7876   },
7877
7878   /* VEX_LEN_XOP_09_E1 */
7879   {
7880     { VEX_W_TABLE (VEX_W_XOP_09_E1_L_0) },
7881   },
7882
7883   /* VEX_LEN_XOP_09_E2 */
7884   {
7885     { VEX_W_TABLE (VEX_W_XOP_09_E2_L_0) },
7886   },
7887
7888   /* VEX_LEN_XOP_09_E3 */
7889   {
7890     { VEX_W_TABLE (VEX_W_XOP_09_E3_L_0) },
7891   },
7892
7893   /* VEX_LEN_XOP_0A_12 */
7894   {
7895     { REG_TABLE (REG_XOP_0A_12_L_0) },
7896   },
7897 };
7898
7899 #include "i386-dis-evex-len.h"
7900
7901 static const struct dis386 vex_w_table[][2] = {
7902   {
7903     /* VEX_W_0F41_L_1_M_1 */
7904     { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_W_0) },
7905     { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_W_1) },
7906   },
7907   {
7908     /* VEX_W_0F42_L_1_M_1 */
7909     { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_W_0) },
7910     { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_W_1) },
7911   },
7912   {
7913     /* VEX_W_0F44_L_0_M_1 */
7914     { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_W_0) },
7915     { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_W_1) },
7916   },
7917   {
7918     /* VEX_W_0F45_L_1_M_1 */
7919     { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_W_0) },
7920     { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_W_1) },
7921   },
7922   {
7923     /* VEX_W_0F46_L_1_M_1 */
7924     { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_W_0) },
7925     { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_W_1) },
7926   },
7927   {
7928     /* VEX_W_0F47_L_1_M_1 */
7929     { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_W_0) },
7930     { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_W_1) },
7931   },
7932   {
7933     /* VEX_W_0F4A_L_1_M_1 */
7934     { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_W_0) },
7935     { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_W_1) },
7936   },
7937   {
7938     /* VEX_W_0F4B_L_1_M_1 */
7939     { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_W_0) },
7940     { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_W_1) },
7941   },
7942   {
7943     /* VEX_W_0F90_L_0 */
7944     { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_0) },
7945     { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_1) },
7946   },
7947   {
7948     /* VEX_W_0F91_L_0_M_0 */
7949     { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_W_0) },
7950     { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_W_1) },
7951   },
7952   {
7953     /* VEX_W_0F92_L_0_M_1 */
7954     { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_W_0) },
7955     { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_W_1) },
7956   },
7957   {
7958     /* VEX_W_0F93_L_0_M_1 */
7959     { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_W_0) },
7960     { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_W_1) },
7961   },
7962   {
7963     /* VEX_W_0F98_L_0_M_1 */
7964     { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_W_0) },
7965     { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_W_1) },
7966   },
7967   {
7968     /* VEX_W_0F99_L_0_M_1 */
7969     { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_W_0) },
7970     { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_W_1) },
7971   },
7972   {
7973     /* VEX_W_0F380C  */
7974     { "%XEvpermilps",   { XM, Vex, EXx }, PREFIX_DATA },
7975   },
7976   {
7977     /* VEX_W_0F380D  */
7978     { "vpermilpd",      { XM, Vex, EXx }, PREFIX_DATA },
7979   },
7980   {
7981     /* VEX_W_0F380E  */
7982     { "vtestps",        { XM, EXx }, PREFIX_DATA },
7983   },
7984   {
7985     /* VEX_W_0F380F  */
7986     { "vtestpd",        { XM, EXx }, PREFIX_DATA },
7987   },
7988   {
7989     /* VEX_W_0F3813 */
7990     { "vcvtph2ps", { XM, EXxmmq }, PREFIX_DATA },
7991   },
7992   {
7993     /* VEX_W_0F3816_L_1  */
7994     { "vpermps",        { XM, Vex, EXx }, PREFIX_DATA },
7995   },
7996   {
7997     /* VEX_W_0F3818 */
7998     { "%XEvbroadcastss",        { XM, EXd }, PREFIX_DATA },
7999   },
8000   {
8001     /* VEX_W_0F3819_L_1 */
8002     { "vbroadcastsd",   { XM, EXq }, PREFIX_DATA },
8003   },
8004   {
8005     /* VEX_W_0F381A_L_1 */
8006     { "vbroadcastf128", { XM, Mxmm }, PREFIX_DATA },
8007   },
8008   {
8009     /* VEX_W_0F382C */
8010     { "vmaskmovps",     { XM, Vex, Mx }, PREFIX_DATA },
8011   },
8012   {
8013     /* VEX_W_0F382D */
8014     { "vmaskmovpd",     { XM, Vex, Mx }, PREFIX_DATA },
8015   },
8016   {
8017     /* VEX_W_0F382E */
8018     { "vmaskmovps",     { Mx, Vex, XM }, PREFIX_DATA },
8019   },
8020   {
8021     /* VEX_W_0F382F */
8022     { "vmaskmovpd",     { Mx, Vex, XM }, PREFIX_DATA },
8023   },
8024   {
8025     /* VEX_W_0F3836  */
8026     { "vpermd",         { XM, Vex, EXx }, PREFIX_DATA },
8027   },
8028   {
8029     /* VEX_W_0F3846 */
8030     { "vpsravd",        { XM, Vex, EXx }, PREFIX_DATA },
8031   },
8032   {
8033     /* VEX_W_0F3848_X86_64_L_0 */
8034     { PREFIX_TABLE (PREFIX_VEX_0F3848_X86_64_L_0_W_0) },
8035   },
8036   {
8037     /* VEX_W_0F3849_X86_64_L_0 */
8038     { MOD_TABLE (MOD_VEX_0F3849_X86_64_L_0_W_0) },
8039   },
8040   {
8041     /* VEX_W_0F384A_X86_64 */
8042     { VEX_LEN_TABLE (VEX_LEN_0F384A_X86_64_W_0) },
8043   },
8044   {
8045     /* VEX_W_0F384B_X86_64_L_0 */
8046     { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64_L_0_W_0) },
8047   },
8048   {
8049     /* VEX_W_0F3850 */
8050     { PREFIX_TABLE (PREFIX_VEX_0F3850_W_0) },
8051   },
8052   {
8053     /* VEX_W_0F3851 */
8054     { PREFIX_TABLE (PREFIX_VEX_0F3851_W_0) },
8055   },
8056   {
8057     /* VEX_W_0F3852 */
8058     { "%XVvpdpwssd",    { XM, Vex, EXx }, PREFIX_DATA },
8059   },
8060   {
8061     /* VEX_W_0F3853 */
8062     { "%XVvpdpwssds",   { XM, Vex, EXx }, PREFIX_DATA },
8063   },
8064   {
8065     /* VEX_W_0F3858 */
8066     { "%XEvpbroadcastd", { XM, EXd }, PREFIX_DATA },
8067   },
8068   {
8069     /* VEX_W_0F3859 */
8070     { "vpbroadcastq", { XM, EXq }, PREFIX_DATA },
8071   },
8072   {
8073     /* VEX_W_0F385A_L_0 */
8074     { "vbroadcasti128", { XM, Mxmm }, PREFIX_DATA },
8075   },
8076   {
8077     /* VEX_W_0F385C_X86_64_L_0 */
8078     { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64_L_0_W_0) },
8079   },
8080   {
8081     /* VEX_W_0F385E_X86_64_L_0 */
8082     { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64_L_0_W_0) },
8083   },
8084   {
8085     /* VEX_W_0F385F_X86_64_L_0 */
8086     { PREFIX_TABLE (PREFIX_VEX_0F385F_X86_64_L_0_W_0) },
8087   },
8088   {
8089     /* VEX_W_0F386B_X86_64_L_0 */
8090     { PREFIX_TABLE (PREFIX_VEX_0F386B_X86_64_L_0_W_0) },
8091   },
8092   {
8093     /* VEX_W_0F386C_X86_64_L_0 */
8094     { PREFIX_TABLE (PREFIX_VEX_0F386C_X86_64_L_0_W_0) },
8095   },
8096   {
8097     /* VEX_W_0F386E_X86_64_L_0 */
8098     { PREFIX_TABLE (PREFIX_VEX_0F386E_X86_64_L_0_W_0) },
8099   },
8100   {
8101     /* VEX_W_0F386F_X86_64_L_0 */
8102     { PREFIX_TABLE (PREFIX_VEX_0F386F_X86_64_L_0_W_0) },
8103   },
8104   {
8105     /* VEX_W_0F3872_P_1 */
8106     { "%XVvcvtneps2bf16%XY", { XMM, EXx }, 0 },
8107   },
8108   {
8109     /* VEX_W_0F3878 */
8110     { "%XEvpbroadcastb",        { XM, EXb }, PREFIX_DATA },
8111   },
8112   {
8113     /* VEX_W_0F3879 */
8114     { "%XEvpbroadcastw",        { XM, EXw }, PREFIX_DATA },
8115   },
8116   {
8117     /* VEX_W_0F38B0 */
8118     { PREFIX_TABLE (PREFIX_VEX_0F38B0_W_0) },
8119   },
8120   {
8121     /* VEX_W_0F38B1 */
8122     { PREFIX_TABLE (PREFIX_VEX_0F38B1_W_0) },
8123   },
8124   {
8125     /* VEX_W_0F38B4 */
8126     { Bad_Opcode },
8127     { "%XVvpmadd52luq", { XM, Vex, EXx }, PREFIX_DATA },
8128   },
8129   {
8130     /* VEX_W_0F38B5 */
8131     { Bad_Opcode },
8132     { "%XVvpmadd52huq", { XM, Vex, EXx }, PREFIX_DATA },
8133   },
8134   {
8135     /* VEX_W_0F38CB_P_3 */
8136     { VEX_LEN_TABLE (VEX_LEN_0F38CB_P_3_W_0) },
8137   },
8138   {
8139     /* VEX_W_0F38CC_P_3 */
8140     { VEX_LEN_TABLE (VEX_LEN_0F38CC_P_3_W_0) },
8141   },
8142   {
8143     /* VEX_W_0F38CD_P_3 */
8144     { VEX_LEN_TABLE (VEX_LEN_0F38CD_P_3_W_0) },
8145   },
8146   {
8147     /* VEX_W_0F38CF */
8148     { "%XEvgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
8149   },
8150   {
8151     /* VEX_W_0F38D2 */
8152     { PREFIX_TABLE (PREFIX_VEX_0F38D2_W_0) },
8153   },
8154   {
8155     /* VEX_W_0F38D3 */
8156     { PREFIX_TABLE (PREFIX_VEX_0F38D3_W_0) },
8157   },
8158   {
8159     /* VEX_W_0F38DA */
8160     { PREFIX_TABLE (PREFIX_VEX_0F38DA_W_0) },
8161   },
8162   {
8163     /* VEX_W_0F3A00_L_1 */
8164     { Bad_Opcode },
8165     { "%XEvpermq",              { XM, EXx, Ib }, PREFIX_DATA },
8166   },
8167   {
8168     /* VEX_W_0F3A01_L_1 */
8169     { Bad_Opcode },
8170     { "%XEvpermpd",     { XM, EXx, Ib }, PREFIX_DATA },
8171   },
8172   {
8173     /* VEX_W_0F3A02 */
8174     { "vpblendd",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
8175   },
8176   {
8177     /* VEX_W_0F3A04 */
8178     { "%XEvpermilps",   { XM, EXx, Ib }, PREFIX_DATA },
8179   },
8180   {
8181     /* VEX_W_0F3A05 */
8182     { "vpermilpd",      { XM, EXx, Ib }, PREFIX_DATA },
8183   },
8184   {
8185     /* VEX_W_0F3A06_L_1 */
8186     { "vperm2f128",     { XM, Vex, EXx, Ib }, PREFIX_DATA },
8187   },
8188   {
8189     /* VEX_W_0F3A18_L_1 */
8190     { "vinsertf128",    { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
8191   },
8192   {
8193     /* VEX_W_0F3A19_L_1 */
8194     { "vextractf128",   { EXxmm, XM, Ib }, PREFIX_DATA },
8195   },
8196   {
8197     /* VEX_W_0F3A1D */
8198     { "%XEvcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA },
8199   },
8200   {
8201     /* VEX_W_0F3A38_L_1 */
8202     { "vinserti128",    { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
8203   },
8204   {
8205     /* VEX_W_0F3A39_L_1 */
8206     { "vextracti128",   { EXxmm, XM, Ib }, PREFIX_DATA },
8207   },
8208   {
8209     /* VEX_W_0F3A46_L_1 */
8210     { "vperm2i128",     { XM, Vex, EXx, Ib }, PREFIX_DATA },
8211   },
8212   {
8213     /* VEX_W_0F3A4A */
8214     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
8215   },
8216   {
8217     /* VEX_W_0F3A4B */
8218     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
8219   },
8220   {
8221     /* VEX_W_0F3A4C */
8222     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
8223   },
8224   {
8225     /* VEX_W_0F3ACE */
8226     { Bad_Opcode },
8227     { "%XEvgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
8228   },
8229   {
8230     /* VEX_W_0F3ACF */
8231     { Bad_Opcode },
8232     { "%XEvgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, PREFIX_DATA },
8233   },
8234   {
8235     /* VEX_W_0F3ADE */
8236     { VEX_LEN_TABLE (VEX_LEN_0F3ADE_W_0) },
8237   },
8238   {
8239     /* VEX_W_MAP5_F8_X86_64 */
8240     { PREFIX_TABLE (PREFIX_VEX_MAP5_F8_X86_64_L_0_W_0) },
8241   },
8242   {
8243     /* VEX_W_MAP5_F9_X86_64 */
8244     { PREFIX_TABLE (PREFIX_VEX_MAP5_F9_X86_64_L_0_W_0) },
8245   },
8246   {
8247     /* VEX_W_MAP5_FD_X86_64 */
8248     { PREFIX_TABLE (PREFIX_VEX_MAP5_FD_X86_64_L_0_W_0) },
8249   },
8250   {
8251     /* VEX_W_MAP7_F6_L_0 */
8252     { REG_TABLE (REG_VEX_MAP7_F6_L_0_W_0) },
8253   },
8254   {
8255     /* VEX_W_MAP7_F8_L_0 */
8256     { REG_TABLE (REG_VEX_MAP7_F8_L_0_W_0) },
8257   },
8258   /* VEX_W_XOP_08_85_L_0 */
8259   {
8260     { "vpmacssww",      { XM, Vex, EXx, XMVexI4 }, 0 },
8261   },
8262   /* VEX_W_XOP_08_86_L_0 */
8263   {
8264     { "vpmacsswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
8265   },
8266   /* VEX_W_XOP_08_87_L_0 */
8267   {
8268     { "vpmacssdql",     { XM, Vex, EXx, XMVexI4 }, 0 },
8269   },
8270   /* VEX_W_XOP_08_8E_L_0 */
8271   {
8272     { "vpmacssdd",      { XM, Vex, EXx, XMVexI4 }, 0 },
8273   },
8274   /* VEX_W_XOP_08_8F_L_0 */
8275   {
8276     { "vpmacssdqh",     { XM, Vex, EXx, XMVexI4 }, 0 },
8277   },
8278   /* VEX_W_XOP_08_95_L_0 */
8279   {
8280     { "vpmacsww",       { XM, Vex, EXx, XMVexI4 }, 0 },
8281   },
8282   /* VEX_W_XOP_08_96_L_0 */
8283   {
8284     { "vpmacswd",       { XM, Vex, EXx, XMVexI4 }, 0 },
8285   },
8286   /* VEX_W_XOP_08_97_L_0 */
8287   {
8288     { "vpmacsdql",      { XM, Vex, EXx, XMVexI4 }, 0 },
8289   },
8290   /* VEX_W_XOP_08_9E_L_0 */
8291   {
8292     { "vpmacsdd",       { XM, Vex, EXx, XMVexI4 }, 0 },
8293   },
8294   /* VEX_W_XOP_08_9F_L_0 */
8295   {
8296     { "vpmacsdqh",      { XM, Vex, EXx, XMVexI4 }, 0 },
8297   },
8298   /* VEX_W_XOP_08_A6_L_0 */
8299   {
8300     { "vpmadcsswd",     { XM, Vex, EXx, XMVexI4 }, 0 },
8301   },
8302   /* VEX_W_XOP_08_B6_L_0 */
8303   {
8304     { "vpmadcswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
8305   },
8306   /* VEX_W_XOP_08_C0_L_0 */
8307   {
8308     { "vprotb",         { XM, EXx, Ib }, 0 },
8309   },
8310   /* VEX_W_XOP_08_C1_L_0 */
8311   {
8312     { "vprotw",         { XM, EXx, Ib }, 0 },
8313   },
8314   /* VEX_W_XOP_08_C2_L_0 */
8315   {
8316     { "vprotd",         { XM, EXx, Ib }, 0 },
8317   },
8318   /* VEX_W_XOP_08_C3_L_0 */
8319   {
8320     { "vprotq",         { XM, EXx, Ib }, 0 },
8321   },
8322   /* VEX_W_XOP_08_CC_L_0 */
8323   {
8324      { "vpcomb",        { XM, Vex, EXx, VPCOM }, 0 },
8325   },
8326   /* VEX_W_XOP_08_CD_L_0 */
8327   {
8328      { "vpcomw",        { XM, Vex, EXx, VPCOM }, 0 },
8329   },
8330   /* VEX_W_XOP_08_CE_L_0 */
8331   {
8332      { "vpcomd",        { XM, Vex, EXx, VPCOM }, 0 },
8333   },
8334   /* VEX_W_XOP_08_CF_L_0 */
8335   {
8336      { "vpcomq",        { XM, Vex, EXx, VPCOM }, 0 },
8337   },
8338   /* VEX_W_XOP_08_EC_L_0 */
8339   {
8340      { "vpcomub",       { XM, Vex, EXx, VPCOM }, 0 },
8341   },
8342   /* VEX_W_XOP_08_ED_L_0 */
8343   {
8344      { "vpcomuw",       { XM, Vex, EXx, VPCOM }, 0 },
8345   },
8346   /* VEX_W_XOP_08_EE_L_0 */
8347   {
8348      { "vpcomud",       { XM, Vex, EXx, VPCOM }, 0 },
8349   },
8350   /* VEX_W_XOP_08_EF_L_0 */
8351   {
8352      { "vpcomuq",       { XM, Vex, EXx, VPCOM }, 0 },
8353   },
8354   /* VEX_W_XOP_09_80 */
8355   {
8356     { "vfrczps",        { XM, EXx }, 0 },
8357   },
8358   /* VEX_W_XOP_09_81 */
8359   {
8360     { "vfrczpd",        { XM, EXx }, 0 },
8361   },
8362   /* VEX_W_XOP_09_82 */
8363   {
8364     { VEX_LEN_TABLE (VEX_LEN_XOP_09_82_W_0) },
8365   },
8366   /* VEX_W_XOP_09_83 */
8367   {
8368     { VEX_LEN_TABLE (VEX_LEN_XOP_09_83_W_0) },
8369   },
8370   /* VEX_W_XOP_09_C1_L_0 */
8371   {
8372     { "vphaddbw",       { XM, EXxmm }, 0 },
8373   },
8374   /* VEX_W_XOP_09_C2_L_0 */
8375   {
8376     { "vphaddbd",       { XM, EXxmm }, 0 },
8377   },
8378   /* VEX_W_XOP_09_C3_L_0 */
8379   {
8380     { "vphaddbq",       { XM, EXxmm }, 0 },
8381   },
8382   /* VEX_W_XOP_09_C6_L_0 */
8383   {
8384     { "vphaddwd",       { XM, EXxmm }, 0 },
8385   },
8386   /* VEX_W_XOP_09_C7_L_0 */
8387   {
8388     { "vphaddwq",       { XM, EXxmm }, 0 },
8389   },
8390   /* VEX_W_XOP_09_CB_L_0 */
8391   {
8392     { "vphadddq",       { XM, EXxmm }, 0 },
8393   },
8394   /* VEX_W_XOP_09_D1_L_0 */
8395   {
8396     { "vphaddubw",      { XM, EXxmm }, 0 },
8397   },
8398   /* VEX_W_XOP_09_D2_L_0 */
8399   {
8400     { "vphaddubd",      { XM, EXxmm }, 0 },
8401   },
8402   /* VEX_W_XOP_09_D3_L_0 */
8403   {
8404     { "vphaddubq",      { XM, EXxmm }, 0 },
8405   },
8406   /* VEX_W_XOP_09_D6_L_0 */
8407   {
8408     { "vphadduwd",      { XM, EXxmm }, 0 },
8409   },
8410   /* VEX_W_XOP_09_D7_L_0 */
8411   {
8412     { "vphadduwq",      { XM, EXxmm }, 0 },
8413   },
8414   /* VEX_W_XOP_09_DB_L_0 */
8415   {
8416     { "vphaddudq",      { XM, EXxmm }, 0 },
8417   },
8418   /* VEX_W_XOP_09_E1_L_0 */
8419   {
8420     { "vphsubbw",       { XM, EXxmm }, 0 },
8421   },
8422   /* VEX_W_XOP_09_E2_L_0 */
8423   {
8424     { "vphsubwd",       { XM, EXxmm }, 0 },
8425   },
8426   /* VEX_W_XOP_09_E3_L_0 */
8427   {
8428     { "vphsubdq",       { XM, EXxmm }, 0 },
8429   },
8430
8431 #include "i386-dis-evex-w.h"
8432 };
8433
8434 static const struct dis386 mod_table[][2] = {
8435   {
8436     /* MOD_62_32BIT */
8437     { "bound{S|}",      { Gv, Ma }, 0 },
8438     { EVEX_TABLE () },
8439   },
8440   {
8441     /* MOD_C4_32BIT */
8442     { "lesS",           { Gv, Mp }, 0 },
8443     { VEX_C4_TABLE () },
8444   },
8445   {
8446     /* MOD_C5_32BIT */
8447     { "ldsS",           { Gv, Mp }, 0 },
8448     { VEX_C5_TABLE () },
8449   },
8450   {
8451     /* MOD_0F01_REG_0 */
8452     { X86_64_TABLE (X86_64_0F01_REG_0) },
8453     { RM_TABLE (RM_0F01_REG_0) },
8454   },
8455   {
8456     /* MOD_0F01_REG_1 */
8457     { X86_64_TABLE (X86_64_0F01_REG_1) },
8458     { RM_TABLE (RM_0F01_REG_1) },
8459   },
8460   {
8461     /* MOD_0F01_REG_2 */
8462     { X86_64_TABLE (X86_64_0F01_REG_2) },
8463     { RM_TABLE (RM_0F01_REG_2) },
8464   },
8465   {
8466     /* MOD_0F01_REG_3 */
8467     { X86_64_TABLE (X86_64_0F01_REG_3) },
8468     { RM_TABLE (RM_0F01_REG_3) },
8469   },
8470   {
8471     /* MOD_0F01_REG_5 */
8472     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
8473     { RM_TABLE (RM_0F01_REG_5_MOD_3) },
8474   },
8475   {
8476     /* MOD_0F01_REG_7 */
8477     { "invlpg",         { Mb }, 0 },
8478     { RM_TABLE (RM_0F01_REG_7_MOD_3) },
8479   },
8480   {
8481     /* MOD_0F12_PREFIX_0 */
8482     { "%XEVmovlpYX",    { XM, Vex, EXq }, 0 },
8483     { "%XEVmovhlpY%XS", { XM, Vex, EXq }, 0 },
8484   },
8485   {
8486     /* MOD_0F16_PREFIX_0 */
8487     { "%XEVmovhpYX",    { XM, Vex, EXq }, 0 },
8488     { "%XEVmovlhpY%XS", { XM, Vex, EXq }, 0 },
8489   },
8490   {
8491     /* MOD_0F18_REG_0 */
8492     { "prefetchnta",    { Mb }, 0 },
8493     { "nopQ",           { Ev }, 0 },
8494   },
8495   {
8496     /* MOD_0F18_REG_1 */
8497     { "prefetcht0",     { Mb }, 0 },
8498     { "nopQ",           { Ev }, 0 },
8499   },
8500   {
8501     /* MOD_0F18_REG_2 */
8502     { "prefetcht1",     { Mb }, 0 },
8503     { "nopQ",           { Ev }, 0 },
8504   },
8505   {
8506     /* MOD_0F18_REG_3 */
8507     { "prefetcht2",     { Mb }, 0 },
8508     { "nopQ",           { Ev }, 0 },
8509   },
8510   {
8511     /* MOD_0F18_REG_4 */
8512     { "prefetchrst2",   { Mb }, 0 },
8513     { "nopQ",           { Ev }, 0 },
8514   },
8515   {
8516     /* MOD_0F18_REG_6 */
8517     { X86_64_TABLE (X86_64_0F18_REG_6_MOD_0) },
8518     { "nopQ",           { Ev }, 0 },
8519   },
8520   {
8521     /* MOD_0F18_REG_7 */
8522     { X86_64_TABLE (X86_64_0F18_REG_7_MOD_0) },
8523     { "nopQ",           { Ev }, 0 },
8524   },
8525   {
8526     /* MOD_0F1A_PREFIX_0 */
8527     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
8528     { "nopQ",           { Ev }, 0 },
8529   },
8530   {
8531     /* MOD_0F1B_PREFIX_0 */
8532     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
8533     { "nopQ",           { Ev }, 0 },
8534   },
8535   {
8536     /* MOD_0F1B_PREFIX_1 */
8537     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
8538     { "nopQ",           { Ev }, PREFIX_IGNORED },
8539   },
8540   {
8541     /* MOD_0F1C_PREFIX_0 */
8542     { REG_TABLE (REG_0F1C_P_0_MOD_0) },
8543     { "nopQ",           { Ev }, 0 },
8544   },
8545   {
8546     /* MOD_0F1E_PREFIX_1 */
8547     { "nopQ",           { Ev }, PREFIX_IGNORED },
8548     { REG_TABLE (REG_0F1E_P_1_MOD_3) },
8549   },
8550   {
8551     /* MOD_0FAE_REG_0 */
8552     { "fxsave",         { FXSAVE }, 0 },
8553     { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
8554   },
8555   {
8556     /* MOD_0FAE_REG_1 */
8557     { "fxrstor",        { FXSAVE }, 0 },
8558     { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
8559   },
8560   {
8561     /* MOD_0FAE_REG_2 */
8562     { "ldmxcsr",        { Md }, 0 },
8563     { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
8564   },
8565   {
8566     /* MOD_0FAE_REG_3 */
8567     { "stmxcsr",        { Md }, 0 },
8568     { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
8569   },
8570   {
8571     /* MOD_0FAE_REG_4 */
8572     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
8573     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
8574   },
8575   {
8576     /* MOD_0FAE_REG_5 */
8577     { "xrstor",         { FXSAVE }, PREFIX_OPCODE | PREFIX_REX2_ILLEGAL },
8578     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
8579   },
8580   {
8581     /* MOD_0FAE_REG_6 */
8582     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
8583     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
8584   },
8585   {
8586     /* MOD_0FAE_REG_7 */
8587     { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
8588     { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
8589   },
8590   {
8591     /* MOD_0FC7_REG_6 */
8592     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
8593     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
8594   },
8595   {
8596     /* MOD_0FC7_REG_7 */
8597     { "vmptrst",        { Mq }, 0 },
8598     { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
8599   },
8600   {
8601     /* MOD_0F38DC_PREFIX_1 */
8602     { "aesenc128kl",    { XM, M }, 0 },
8603     { "loadiwkey",      { XM, EXx }, 0 },
8604   },
8605   /* MOD_0F38F8 */
8606   {
8607     { PREFIX_TABLE (PREFIX_0F38F8_M_0) },
8608     { X86_64_TABLE (X86_64_0F38F8_M_1) },
8609   },
8610   {
8611     /* MOD_VEX_0F3849_X86_64_L_0_W_0 */
8612     { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0) },
8613     { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1) },
8614   },
8615
8616 #include "i386-dis-evex-mod.h"
8617 };
8618
8619 static const struct dis386 rm_table[][8] = {
8620   {
8621     /* RM_C6_REG_7 */
8622     { "xabort",         { Skip_MODRM, Ib }, 0 },
8623   },
8624   {
8625     /* RM_C7_REG_7 */
8626     { "xbeginT",        { Skip_MODRM, Jdqw }, 0 },
8627   },
8628   {
8629     /* RM_0F01_REG_0 */
8630     { "enclv",          { Skip_MODRM }, 0 },
8631     { "vmcall",         { Skip_MODRM }, 0 },
8632     { "vmlaunch",       { Skip_MODRM }, 0 },
8633     { "vmresume",       { Skip_MODRM }, 0 },
8634     { "vmxoff",         { Skip_MODRM }, 0 },
8635     { "pconfig",        { Skip_MODRM }, 0 },
8636     { PREFIX_TABLE (PREFIX_0F01_REG_0_MOD_3_RM_6) },
8637     { PREFIX_TABLE (PREFIX_0F01_REG_0_MOD_3_RM_7) },
8638   },
8639   {
8640     /* RM_0F01_REG_1 */
8641     { "monitor",        { { OP_Monitor, 0 } }, 0 },
8642     { "mwait",          { { OP_Mwait, 0 } }, 0 },
8643     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_2) },
8644     { "stac",           { Skip_MODRM }, 0 },
8645     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_4) },
8646     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_5) },
8647     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_6) },
8648     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_7) },
8649   },
8650   {
8651     /* RM_0F01_REG_2 */
8652     { "xgetbv",         { Skip_MODRM }, 0 },
8653     { "xsetbv",         { Skip_MODRM }, 0 },
8654     { Bad_Opcode },
8655     { Bad_Opcode },
8656     { "vmfunc",         { Skip_MODRM }, 0 },
8657     { "xend",           { Skip_MODRM }, 0 },
8658     { "xtest",          { Skip_MODRM }, 0 },
8659     { "enclu",          { Skip_MODRM }, 0 },
8660   },
8661   {
8662     /* RM_0F01_REG_3 */
8663     { "vmrun",          { Skip_MODRM }, 0 },
8664     { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
8665     { "vmload",         { Skip_MODRM }, 0 },
8666     { "vmsave",         { Skip_MODRM }, 0 },
8667     { "stgi",           { Skip_MODRM }, 0 },
8668     { "clgi",           { Skip_MODRM }, 0 },
8669     { "skinit",         { Skip_MODRM }, 0 },
8670     { "invlpga",        { Skip_MODRM }, 0 },
8671   },
8672   {
8673     /* RM_0F01_REG_5_MOD_3 */
8674     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
8675     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
8676     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
8677     { Bad_Opcode },
8678     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_4) },
8679     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_5) },
8680     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_6) },
8681     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_7) },
8682   },
8683   {
8684     /* RM_0F01_REG_7_MOD_3 */
8685     { "swapgs",         { Skip_MODRM }, 0  },
8686     { "rdtscp",         { Skip_MODRM }, 0  },
8687     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
8688     { "mwaitx",         { { OP_Mwait, eBX_reg } }, PREFIX_OPCODE },
8689     { "clzero",         { Skip_MODRM }, 0  },
8690     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_5) },
8691     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_6) },
8692     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_7) },
8693   },
8694   {
8695     /* RM_0F1E_P_1_MOD_3_REG_7 */
8696     { "nopQ",           { Ev }, PREFIX_IGNORED },
8697     { "nopQ",           { Ev }, PREFIX_IGNORED },
8698     { "endbr64",        { Skip_MODRM }, 0 },
8699     { "endbr32",        { Skip_MODRM }, 0 },
8700     { "nopQ",           { Ev }, PREFIX_IGNORED },
8701     { "nopQ",           { Ev }, PREFIX_IGNORED },
8702     { "nopQ",           { Ev }, PREFIX_IGNORED },
8703     { "nopQ",           { Ev }, PREFIX_IGNORED },
8704   },
8705   {
8706     /* RM_0FAE_REG_6_MOD_3 */
8707     { "mfence",         { Skip_MODRM }, 0 },
8708   },
8709   {
8710     /* RM_0FAE_REG_7_MOD_3 */
8711     { "sfence",         { Skip_MODRM }, 0 },
8712   },
8713   {
8714     /* RM_0F3A0F_P_1_R_0 */
8715     { "hreset",         { Skip_MODRM, Ib }, 0 },
8716   },
8717   {
8718     /* RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0 */
8719     { "tilerelease",    { Skip_MODRM }, 0 },
8720   },
8721   {
8722     /* RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3 */
8723     { "tilezero",       { TMM, Skip_MODRM }, 0 },
8724   },
8725 };
8726
8727 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
8728
8729 /* The values used here must be non-zero, fit in 'unsigned char', and not be
8730    in conflict with actual prefix opcodes.  */
8731 #define REP_PREFIX      0x01
8732 #define XACQUIRE_PREFIX 0x02
8733 #define XRELEASE_PREFIX 0x03
8734 #define BND_PREFIX      0x04
8735 #define NOTRACK_PREFIX  0x05
8736
8737 static enum {
8738   ckp_okay,
8739   ckp_bogus,
8740   ckp_fetch_error,
8741 }
8742 ckprefix (instr_info *ins)
8743 {
8744   int i, length;
8745   uint8_t newrex;
8746
8747   i = 0;
8748   length = 0;
8749   /* The maximum instruction length is 15bytes.  */
8750   while (length < MAX_CODE_LENGTH - 1)
8751     {
8752       if (!fetch_code (ins->info, ins->codep + 1))
8753         return ckp_fetch_error;
8754       newrex = 0;
8755       switch (*ins->codep)
8756         {
8757         /* REX prefixes family.  */
8758         case 0x40:
8759         case 0x41:
8760         case 0x42:
8761         case 0x43:
8762         case 0x44:
8763         case 0x45:
8764         case 0x46:
8765         case 0x47:
8766         case 0x48:
8767         case 0x49:
8768         case 0x4a:
8769         case 0x4b:
8770         case 0x4c:
8771         case 0x4d:
8772         case 0x4e:
8773         case 0x4f:
8774           if (ins->address_mode == mode_64bit)
8775             newrex = *ins->codep;
8776           else
8777             return ckp_okay;
8778           ins->last_rex_prefix = i;
8779           break;
8780         /* REX2 must be the last prefix. */
8781         case REX2_OPCODE:
8782           if (ins->address_mode == mode_64bit)
8783             {
8784               if (ins->last_rex_prefix >= 0)
8785                 return ckp_bogus;
8786
8787               ins->codep++;
8788               if (!fetch_code (ins->info, ins->codep + 1))
8789                 return ckp_fetch_error;
8790               ins->rex2_payload = *ins->codep;
8791               ins->rex2 = ins->rex2_payload >> 4;
8792               ins->rex = (ins->rex2_payload & 0xf) | REX_OPCODE;
8793               ins->codep++;
8794               ins->last_rex2_prefix = i;
8795               ins->all_prefixes[i] = REX2_OPCODE;
8796             }
8797           return ckp_okay;
8798         case 0xf3:
8799           ins->prefixes |= PREFIX_REPZ;
8800           ins->last_repz_prefix = i;
8801           break;
8802         case 0xf2:
8803           ins->prefixes |= PREFIX_REPNZ;
8804           ins->last_repnz_prefix = i;
8805           break;
8806         case 0xf0:
8807           ins->prefixes |= PREFIX_LOCK;
8808           ins->last_lock_prefix = i;
8809           break;
8810         case 0x2e:
8811           ins->prefixes |= PREFIX_CS;
8812           ins->last_seg_prefix = i;
8813           if (ins->address_mode != mode_64bit)
8814             ins->active_seg_prefix = PREFIX_CS;
8815           break;
8816         case 0x36:
8817           ins->prefixes |= PREFIX_SS;
8818           ins->last_seg_prefix = i;
8819           if (ins->address_mode != mode_64bit)
8820             ins->active_seg_prefix = PREFIX_SS;
8821           break;
8822         case 0x3e:
8823           ins->prefixes |= PREFIX_DS;
8824           ins->last_seg_prefix = i;
8825           if (ins->address_mode != mode_64bit)
8826             ins->active_seg_prefix = PREFIX_DS;
8827           break;
8828         case 0x26:
8829           ins->prefixes |= PREFIX_ES;
8830           ins->last_seg_prefix = i;
8831           if (ins->address_mode != mode_64bit)
8832             ins->active_seg_prefix = PREFIX_ES;
8833           break;
8834         case 0x64:
8835           ins->prefixes |= PREFIX_FS;
8836           ins->last_seg_prefix = i;
8837           ins->active_seg_prefix = PREFIX_FS;
8838           break;
8839         case 0x65:
8840           ins->prefixes |= PREFIX_GS;
8841           ins->last_seg_prefix = i;
8842           ins->active_seg_prefix = PREFIX_GS;
8843           break;
8844         case 0x66:
8845           ins->prefixes |= PREFIX_DATA;
8846           ins->last_data_prefix = i;
8847           break;
8848         case 0x67:
8849           ins->prefixes |= PREFIX_ADDR;
8850           ins->last_addr_prefix = i;
8851           break;
8852         case FWAIT_OPCODE:
8853           /* fwait is really an instruction.  If there are prefixes
8854              before the fwait, they belong to the fwait, *not* to the
8855              following instruction.  */
8856           ins->fwait_prefix = i;
8857           if (ins->prefixes || ins->rex)
8858             {
8859               ins->prefixes |= PREFIX_FWAIT;
8860               ins->codep++;
8861               /* This ensures that the previous REX prefixes are noticed
8862                  as unused prefixes, as in the return case below.  */
8863               return ins->rex ? ckp_bogus : ckp_okay;
8864             }
8865           ins->prefixes = PREFIX_FWAIT;
8866           break;
8867         default:
8868           return ckp_okay;
8869         }
8870       /* Rex is ignored when followed by another prefix.  */
8871       if (ins->rex)
8872         return ckp_bogus;
8873       if (*ins->codep != FWAIT_OPCODE)
8874         ins->all_prefixes[i++] = *ins->codep;
8875       ins->rex = newrex;
8876       ins->codep++;
8877       length++;
8878     }
8879   return ckp_bogus;
8880 }
8881
8882 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
8883    prefix byte.  */
8884
8885 static const char *
8886 prefix_name (enum address_mode mode, uint8_t pref, int sizeflag)
8887 {
8888   static const char *rexes [16] =
8889     {
8890       "rex",            /* 0x40 */
8891       "rex.B",          /* 0x41 */
8892       "rex.X",          /* 0x42 */
8893       "rex.XB",         /* 0x43 */
8894       "rex.R",          /* 0x44 */
8895       "rex.RB",         /* 0x45 */
8896       "rex.RX",         /* 0x46 */
8897       "rex.RXB",        /* 0x47 */
8898       "rex.W",          /* 0x48 */
8899       "rex.WB",         /* 0x49 */
8900       "rex.WX",         /* 0x4a */
8901       "rex.WXB",        /* 0x4b */
8902       "rex.WR",         /* 0x4c */
8903       "rex.WRB",        /* 0x4d */
8904       "rex.WRX",        /* 0x4e */
8905       "rex.WRXB",       /* 0x4f */
8906     };
8907
8908   switch (pref)
8909     {
8910     /* REX prefixes family.  */
8911     case 0x40:
8912     case 0x41:
8913     case 0x42:
8914     case 0x43:
8915     case 0x44:
8916     case 0x45:
8917     case 0x46:
8918     case 0x47:
8919     case 0x48:
8920     case 0x49:
8921     case 0x4a:
8922     case 0x4b:
8923     case 0x4c:
8924     case 0x4d:
8925     case 0x4e:
8926     case 0x4f:
8927       return rexes [pref - 0x40];
8928     case 0xf3:
8929       return "repz";
8930     case 0xf2:
8931       return "repnz";
8932     case 0xf0:
8933       return "lock";
8934     case 0x2e:
8935       return "cs";
8936     case 0x36:
8937       return "ss";
8938     case 0x3e:
8939       return "ds";
8940     case 0x26:
8941       return "es";
8942     case 0x64:
8943       return "fs";
8944     case 0x65:
8945       return "gs";
8946     case 0x66:
8947       return (sizeflag & DFLAG) ? "data16" : "data32";
8948     case 0x67:
8949       if (mode == mode_64bit)
8950         return (sizeflag & AFLAG) ? "addr32" : "addr64";
8951       else
8952         return (sizeflag & AFLAG) ? "addr16" : "addr32";
8953     case FWAIT_OPCODE:
8954       return "fwait";
8955     case REP_PREFIX:
8956       return "rep";
8957     case XACQUIRE_PREFIX:
8958       return "xacquire";
8959     case XRELEASE_PREFIX:
8960       return "xrelease";
8961     case BND_PREFIX:
8962       return "bnd";
8963     case NOTRACK_PREFIX:
8964       return "notrack";
8965     case REX2_OPCODE:
8966       return "rex2";
8967     default:
8968       return NULL;
8969     }
8970 }
8971
8972 void
8973 print_i386_disassembler_options (FILE *stream)
8974 {
8975   fprintf (stream, _("\n\
8976 The following i386/x86-64 specific disassembler options are supported for use\n\
8977 with the -M switch (multiple options should be separated by commas):\n"));
8978
8979   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
8980   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
8981   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
8982   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
8983   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
8984   fprintf (stream, _("  att-mnemonic  (AT&T syntax only)\n"
8985                      "              Display instruction with AT&T mnemonic\n"));
8986   fprintf (stream, _("  intel-mnemonic  (AT&T syntax only)\n"
8987                      "              Display instruction with Intel mnemonic\n"));
8988   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
8989   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
8990   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
8991   fprintf (stream, _("  data32      Assume 32bit data size\n"));
8992   fprintf (stream, _("  data16      Assume 16bit data size\n"));
8993   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
8994   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
8995   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
8996 }
8997
8998 /* Bad opcode.  */
8999 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
9000
9001 /* Fetch error indicator.  */
9002 static const struct dis386 err_opcode = { NULL, { XX }, 0 };
9003
9004 static const struct dis386 map5_f8_opcode = { X86_64_TABLE (X86_64_VEX_MAP5_F8) };
9005 static const struct dis386 map5_f9_opcode = { X86_64_TABLE (X86_64_VEX_MAP5_F9) };
9006 static const struct dis386 map5_fd_opcode = { X86_64_TABLE (X86_64_VEX_MAP5_FD) };
9007 static const struct dis386 map7_f6_opcode = { VEX_LEN_TABLE (VEX_LEN_MAP7_F6) };
9008 static const struct dis386 map7_f8_opcode = { VEX_LEN_TABLE (VEX_LEN_MAP7_F8) };
9009
9010 /* Get a pointer to struct dis386 with a valid name.  */
9011
9012 static const struct dis386 *
9013 get_valid_dis386 (const struct dis386 *dp, instr_info *ins)
9014 {
9015   int vindex, vex_table_index;
9016
9017   if (dp->name != NULL)
9018     return dp;
9019
9020   switch (dp->op[0].bytemode)
9021     {
9022     case USE_REG_TABLE:
9023       dp = &reg_table[dp->op[1].bytemode][ins->modrm.reg];
9024       break;
9025
9026     case USE_MOD_TABLE:
9027       vindex = ins->modrm.mod == 0x3 ? 1 : 0;
9028       dp = &mod_table[dp->op[1].bytemode][vindex];
9029       break;
9030
9031     case USE_RM_TABLE:
9032       dp = &rm_table[dp->op[1].bytemode][ins->modrm.rm];
9033       break;
9034
9035     case USE_PREFIX_TABLE:
9036     use_prefix_table:
9037       if (ins->need_vex)
9038         {
9039           /* The prefix in VEX is implicit.  */
9040           switch (ins->vex.prefix)
9041             {
9042             case 0:
9043               vindex = 0;
9044               break;
9045             case REPE_PREFIX_OPCODE:
9046               vindex = 1;
9047               break;
9048             case DATA_PREFIX_OPCODE:
9049               vindex = 2;
9050               break;
9051             case REPNE_PREFIX_OPCODE:
9052               vindex = 3;
9053               break;
9054             default:
9055               abort ();
9056               break;
9057             }
9058         }
9059       else
9060         {
9061           int last_prefix = -1;
9062           int prefix = 0;
9063           vindex = 0;
9064           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
9065              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
9066              last one wins.  */
9067           if ((ins->prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
9068             {
9069               if (ins->last_repz_prefix > ins->last_repnz_prefix)
9070                 {
9071                   vindex = 1;
9072                   prefix = PREFIX_REPZ;
9073                   last_prefix = ins->last_repz_prefix;
9074                 }
9075               else
9076                 {
9077                   vindex = 3;
9078                   prefix = PREFIX_REPNZ;
9079                   last_prefix = ins->last_repnz_prefix;
9080                 }
9081
9082               /* Check if prefix should be ignored.  */
9083               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
9084                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
9085                    & prefix) != 0
9086                   && !prefix_table[dp->op[1].bytemode][vindex].name)
9087                 vindex = 0;
9088             }
9089
9090           if (vindex == 0 && (ins->prefixes & PREFIX_DATA) != 0)
9091             {
9092               vindex = 2;
9093               prefix = PREFIX_DATA;
9094               last_prefix = ins->last_data_prefix;
9095             }
9096
9097           if (vindex != 0)
9098             {
9099               ins->used_prefixes |= prefix;
9100               ins->all_prefixes[last_prefix] = 0;
9101             }
9102         }
9103       dp = &prefix_table[dp->op[1].bytemode][vindex];
9104       break;
9105
9106     case USE_X86_64_EVEX_FROM_VEX_TABLE:
9107     case USE_X86_64_EVEX_PFX_TABLE:
9108     case USE_X86_64_EVEX_W_TABLE:
9109     case USE_X86_64_EVEX_MEM_W_TABLE:
9110       ins->evex_type = evex_from_vex;
9111       /* EVEX from VEX instructions are 64-bit only and require that EVEX.z,
9112          EVEX.L'L, EVEX.b, and the lower 2 bits of EVEX.aaa must be 0.  */
9113       if (ins->address_mode != mode_64bit
9114           || (ins->vex.mask_register_specifier & 0x3) != 0
9115           || ins->vex.ll != 0
9116           || ins->vex.zeroing != 0
9117           || ins->vex.b)
9118         return &bad_opcode;
9119
9120       if (dp->op[0].bytemode == USE_X86_64_EVEX_PFX_TABLE)
9121         goto use_prefix_table;
9122       if (dp->op[0].bytemode == USE_X86_64_EVEX_W_TABLE)
9123         goto use_vex_w_table;
9124       if (dp->op[0].bytemode == USE_X86_64_EVEX_MEM_W_TABLE)
9125         {
9126           if (ins->modrm.mod == 3)
9127             return &bad_opcode;
9128           goto use_vex_w_table;
9129         }
9130
9131       /* Fall through.  */
9132     case USE_X86_64_TABLE:
9133       vindex = ins->address_mode == mode_64bit ? 1 : 0;
9134       dp = &x86_64_table[dp->op[1].bytemode][vindex];
9135       break;
9136
9137     case USE_3BYTE_TABLE:
9138       if (ins->last_rex2_prefix >= 0)
9139         return &err_opcode;
9140       if (!fetch_code (ins->info, ins->codep + 2))
9141         return &err_opcode;
9142       vindex = *ins->codep++;
9143       dp = &three_byte_table[dp->op[1].bytemode][vindex];
9144       ins->end_codep = ins->codep;
9145       if (!fetch_modrm (ins))
9146         return &err_opcode;
9147       break;
9148
9149     case USE_VEX_LEN_TABLE:
9150       if (!ins->need_vex)
9151         abort ();
9152
9153       switch (ins->vex.length)
9154         {
9155         case 128:
9156           vindex = 0;
9157           break;
9158         case 512:
9159           /* This allows re-using in particular table entries where only
9160              128-bit operand size (VEX.L=0 / EVEX.L'L=0) are valid.  */
9161           if (ins->vex.evex)
9162             {
9163         case 256:
9164               vindex = 1;
9165               break;
9166             }
9167         /* Fall through.  */
9168         default:
9169           abort ();
9170           break;
9171         }
9172
9173       dp = &vex_len_table[dp->op[1].bytemode][vindex];
9174       break;
9175
9176     case USE_EVEX_LEN_TABLE:
9177       if (!ins->vex.evex)
9178         abort ();
9179
9180       switch (ins->vex.length)
9181         {
9182         case 128:
9183           vindex = 0;
9184           break;
9185         case 256:
9186           vindex = 1;
9187           break;
9188         case 512:
9189           vindex = 2;
9190           break;
9191         default:
9192           abort ();
9193           break;
9194         }
9195
9196       dp = &evex_len_table[dp->op[1].bytemode][vindex];
9197       break;
9198
9199     case USE_XOP_8F_TABLE:
9200       if (!fetch_code (ins->info, ins->codep + 3))
9201         return &err_opcode;
9202       ins->rex = ~(*ins->codep >> 5) & 0x7;
9203
9204       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
9205       switch ((*ins->codep & 0x1f))
9206         {
9207         default:
9208           dp = &bad_opcode;
9209           return dp;
9210         case 0x8:
9211           vex_table_index = XOP_08;
9212           break;
9213         case 0x9:
9214           vex_table_index = XOP_09;
9215           break;
9216         case 0xa:
9217           vex_table_index = XOP_0A;
9218           break;
9219         }
9220       ins->codep++;
9221       ins->vex.w = *ins->codep & 0x80;
9222       if (ins->vex.w && ins->address_mode == mode_64bit)
9223         ins->rex |= REX_W;
9224
9225       ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9226       if (ins->address_mode != mode_64bit)
9227         {
9228           /* In 16/32-bit mode REX_B is silently ignored.  */
9229           ins->rex &= ~REX_B;
9230         }
9231
9232       ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
9233       switch ((*ins->codep & 0x3))
9234         {
9235         case 0:
9236           break;
9237         case 1:
9238           ins->vex.prefix = DATA_PREFIX_OPCODE;
9239           break;
9240         case 2:
9241           ins->vex.prefix = REPE_PREFIX_OPCODE;
9242           break;
9243         case 3:
9244           ins->vex.prefix = REPNE_PREFIX_OPCODE;
9245           break;
9246         }
9247       ins->need_vex = 3;
9248       ins->codep++;
9249       vindex = *ins->codep++;
9250       dp = &xop_table[vex_table_index][vindex];
9251
9252       ins->end_codep = ins->codep;
9253       if (!fetch_modrm (ins))
9254         return &err_opcode;
9255
9256       /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
9257          having to decode the bits for every otherwise valid encoding.  */
9258       if (ins->vex.prefix)
9259         return &bad_opcode;
9260       break;
9261
9262     case USE_VEX_C4_TABLE:
9263       /* VEX prefix.  */
9264       if (!fetch_code (ins->info, ins->codep + 3))
9265         return &err_opcode;
9266       ins->rex = ~(*ins->codep >> 5) & 0x7;
9267       switch ((*ins->codep & 0x1f))
9268         {
9269         default:
9270           dp = &bad_opcode;
9271           return dp;
9272         case 0x1:
9273           vex_table_index = VEX_0F;
9274           break;
9275         case 0x2:
9276           vex_table_index = VEX_0F38;
9277           break;
9278         case 0x3:
9279           vex_table_index = VEX_0F3A;
9280           break;
9281         case 0x5:
9282           vex_table_index = VEX_MAP5;
9283           break;
9284         case 0x7:
9285           vex_table_index = VEX_MAP7;
9286           break;
9287         }
9288       ins->codep++;
9289       ins->vex.w = *ins->codep & 0x80;
9290       if (ins->address_mode == mode_64bit)
9291         {
9292           if (ins->vex.w)
9293             ins->rex |= REX_W;
9294         }
9295       else
9296         {
9297           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
9298              is ignored, other REX bits are 0 and the highest bit in
9299              VEX.vvvv is also ignored (but we mustn't clear it here).  */
9300           ins->rex = 0;
9301         }
9302       ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9303       ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
9304       switch ((*ins->codep & 0x3))
9305         {
9306         case 0:
9307           break;
9308         case 1:
9309           ins->vex.prefix = DATA_PREFIX_OPCODE;
9310           break;
9311         case 2:
9312           ins->vex.prefix = REPE_PREFIX_OPCODE;
9313           break;
9314         case 3:
9315           ins->vex.prefix = REPNE_PREFIX_OPCODE;
9316           break;
9317         }
9318       ins->need_vex = 3;
9319       ins->codep++;
9320       vindex = *ins->codep++;
9321       ins->condition_code = vindex & 0xf;
9322       if (vex_table_index != VEX_MAP7 && vex_table_index != VEX_MAP5)
9323         dp = &vex_table[vex_table_index][vindex];
9324       else if (vindex == 0xf6)
9325         dp = &map7_f6_opcode;
9326       else if (vindex == 0xf8)
9327         {
9328           if (vex_table_index == VEX_MAP5)
9329             dp = &map5_f8_opcode;
9330           else
9331             dp = &map7_f8_opcode;
9332         }
9333       else if (vindex == 0xf9)
9334         dp = &map5_f9_opcode;
9335       else if (vindex == 0xfd)
9336         dp = &map5_fd_opcode;
9337       else
9338         dp = &bad_opcode;
9339       ins->end_codep = ins->codep;
9340       /* There is no MODRM byte for VEX0F 77.  */
9341       if ((vex_table_index != VEX_0F || vindex != 0x77)
9342           && !fetch_modrm (ins))
9343         return &err_opcode;
9344       break;
9345
9346     case USE_VEX_C5_TABLE:
9347       /* VEX prefix.  */
9348       if (!fetch_code (ins->info, ins->codep + 2))
9349         return &err_opcode;
9350       ins->rex = (*ins->codep & 0x80) ? 0 : REX_R;
9351
9352       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
9353          VEX.vvvv is 1.  */
9354       ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9355       ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
9356       switch ((*ins->codep & 0x3))
9357         {
9358         case 0:
9359           break;
9360         case 1:
9361           ins->vex.prefix = DATA_PREFIX_OPCODE;
9362           break;
9363         case 2:
9364           ins->vex.prefix = REPE_PREFIX_OPCODE;
9365           break;
9366         case 3:
9367           ins->vex.prefix = REPNE_PREFIX_OPCODE;
9368           break;
9369         }
9370       ins->need_vex = 2;
9371       ins->codep++;
9372       vindex = *ins->codep++;
9373       dp = &vex_table[VEX_0F][vindex];
9374       ins->end_codep = ins->codep;
9375       /* There is no MODRM byte for VEX 77.  */
9376       if (vindex != 0x77 && !fetch_modrm (ins))
9377         return &err_opcode;
9378       break;
9379
9380     case USE_VEX_W_TABLE:
9381     use_vex_w_table:
9382       if (!ins->need_vex)
9383         abort ();
9384
9385       dp = &vex_w_table[dp->op[1].bytemode][ins->vex.w];
9386       break;
9387
9388     case USE_EVEX_TABLE:
9389       ins->two_source_ops = false;
9390       /* EVEX prefix.  */
9391       ins->vex.evex = true;
9392       if (!fetch_code (ins->info, ins->codep + 4))
9393         return &err_opcode;
9394       /* The first byte after 0x62.  */
9395       if (*ins->codep & 0x8)
9396         ins->rex2 |= REX_B;
9397       if (!(*ins->codep & 0x10))
9398         ins->rex2 |= REX_R;
9399
9400       ins->rex = ~(*ins->codep >> 5) & 0x7;
9401       switch (*ins->codep & 0x7)
9402         {
9403         default:
9404           return &bad_opcode;
9405         case 0x1:
9406           vex_table_index = EVEX_0F;
9407           break;
9408         case 0x2:
9409           vex_table_index = EVEX_0F38;
9410           break;
9411         case 0x3:
9412           vex_table_index = EVEX_0F3A;
9413           break;
9414         case 0x4:
9415           vex_table_index = EVEX_MAP4;
9416           ins->evex_type = evex_from_legacy;
9417           if (ins->address_mode != mode_64bit)
9418             return &bad_opcode;
9419           ins->rex |= REX_OPCODE;
9420           break;
9421         case 0x5:
9422           vex_table_index = EVEX_MAP5;
9423           break;
9424         case 0x6:
9425           vex_table_index = EVEX_MAP6;
9426           break;
9427         case 0x7:
9428           vex_table_index = EVEX_MAP7;
9429           break;
9430         }
9431
9432       /* The second byte after 0x62.  */
9433       ins->codep++;
9434       ins->vex.w = *ins->codep & 0x80;
9435       if (ins->vex.w && ins->address_mode == mode_64bit)
9436         ins->rex |= REX_W;
9437
9438       ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9439
9440       if (!(*ins->codep & 0x4))
9441         ins->rex2 |= REX_X;
9442
9443       ins->vex.u = *ins->codep & 0x4;
9444
9445       switch ((*ins->codep & 0x3))
9446         {
9447         case 0:
9448           break;
9449         case 1:
9450           ins->vex.prefix = DATA_PREFIX_OPCODE;
9451           break;
9452         case 2:
9453           ins->vex.prefix = REPE_PREFIX_OPCODE;
9454           break;
9455         case 3:
9456           ins->vex.prefix = REPNE_PREFIX_OPCODE;
9457           break;
9458         }
9459
9460       /* The third byte after 0x62.  */
9461       ins->codep++;
9462
9463       /* Remember the static rounding bits.  */
9464       ins->vex.ll = (*ins->codep >> 5) & 3;
9465       ins->vex.b = *ins->codep & 0x10;
9466
9467       ins->vex.v = *ins->codep & 0x8;
9468       ins->vex.mask_register_specifier = *ins->codep & 0x7;
9469       ins->vex.scc = *ins->codep & 0xf;
9470       ins->vex.zeroing = *ins->codep & 0x80;
9471       /* Set the NF bit for EVEX-Promoted instructions, this bit will be cleared
9472          when it's an evex_default one.  */
9473       ins->vex.nf = *ins->codep & 0x4;
9474
9475       if (ins->address_mode != mode_64bit)
9476         {
9477           /* Report bad for !evex_default and when two fixed values of evex
9478              change.  */
9479           if (ins->evex_type != evex_default || (ins->rex2 & REX_B)
9480               || ((ins->rex2 & REX_X) && (ins->modrm.mod != 3)))
9481             return &bad_opcode;
9482           /* In 16/32-bit mode silently ignore following bits.  */
9483           ins->rex &= ~REX_B;
9484           ins->rex2 &= ~REX_R;
9485         }
9486
9487       ins->need_vex = 4;
9488
9489       ins->codep++;
9490       vindex = *ins->codep++;
9491       ins->condition_code = vindex & 0xf;
9492       if (vex_table_index != EVEX_MAP7)
9493         dp = &evex_table[vex_table_index][vindex];
9494       else if (vindex == 0xf8)
9495         dp = &map7_f8_opcode;
9496       else if (vindex == 0xf6)
9497         dp = &map7_f6_opcode;
9498       else
9499         dp = &bad_opcode;
9500       ins->end_codep = ins->codep;
9501       if (!fetch_modrm (ins))
9502         return &err_opcode;
9503
9504       /* When modrm.mod != 3, the U bit is used by APX for bit X4.
9505          When modrm.mod == 3, the U bit is used by AVX10.  The U bit and
9506          the b bit should not be zero at the same time.  */
9507       if (ins->modrm.mod == 3 && !ins->vex.u && !ins->vex.b)
9508         return &bad_opcode;
9509
9510       /* Set vector length. For EVEX-promoted instructions, evex.ll == 0b00,
9511          which has the same encoding as vex.length == 128 and they can share
9512          the same processing with vex.length in OP_VEX.  */
9513       if (ins->modrm.mod == 3 && ins->vex.b && ins->evex_type != evex_from_legacy)
9514         {
9515           if (ins->vex.u)
9516             ins->vex.length = 512;
9517           else
9518             ins->vex.length = 256;
9519         }
9520       else
9521         {
9522           switch (ins->vex.ll)
9523             {
9524             case 0x0:
9525               ins->vex.length = 128;
9526               break;
9527             case 0x1:
9528               ins->vex.length = 256;
9529               break;
9530             case 0x2:
9531               ins->vex.length = 512;
9532               break;
9533             default:
9534               return &bad_opcode;
9535             }
9536         }
9537       break;
9538
9539     case 0:
9540       dp = &bad_opcode;
9541       break;
9542
9543     default:
9544       abort ();
9545     }
9546
9547   if (dp->name != NULL)
9548     return dp;
9549   else
9550     return get_valid_dis386 (dp, ins);
9551 }
9552
9553 static bool
9554 get_sib (instr_info *ins, int sizeflag)
9555 {
9556   /* If modrm.mod == 3, operand must be register.  */
9557   if (ins->need_modrm
9558       && ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
9559       && ins->modrm.mod != 3
9560       && ins->modrm.rm == 4)
9561     {
9562       if (!fetch_code (ins->info, ins->codep + 2))
9563         return false;
9564       ins->sib.index = (ins->codep[1] >> 3) & 7;
9565       ins->sib.scale = (ins->codep[1] >> 6) & 3;
9566       ins->sib.base = ins->codep[1] & 7;
9567       ins->has_sib = true;
9568     }
9569   else
9570     ins->has_sib = false;
9571
9572   return true;
9573 }
9574
9575 /* Like oappend_with_style (below) but always with text style.  */
9576
9577 static void
9578 oappend (instr_info *ins, const char *s)
9579 {
9580   oappend_with_style (ins, s, dis_style_text);
9581 }
9582
9583 /* Like oappend (above), but S is a string starting with '%'.  In
9584    Intel syntax, the '%' is elided.  */
9585
9586 static void
9587 oappend_register (instr_info *ins, const char *s)
9588 {
9589   oappend_with_style (ins, s + ins->intel_syntax, dis_style_register);
9590 }
9591
9592 /* Wrap around a call to INS->info->fprintf_styled_func, printing FMT.
9593    STYLE is the default style to use in the fprintf_styled_func calls,
9594    however, FMT might include embedded style markers (see oappend_style),
9595    these embedded markers are not printed, but instead change the style
9596    used in the next fprintf_styled_func call.  */
9597
9598 static void ATTRIBUTE_PRINTF_3
9599 i386_dis_printf (const disassemble_info *info, enum disassembler_style style,
9600                  const char *fmt, ...)
9601 {
9602   va_list ap;
9603   enum disassembler_style curr_style = style;
9604   const char *start, *curr;
9605   char staging_area[50];
9606
9607   va_start (ap, fmt);
9608   /* In particular print_insn()'s processing of op_txt[] can hand rather long
9609      strings here.  Bypass vsnprintf() in such cases to avoid capacity issues
9610      with the staging area.  */
9611   if (strcmp (fmt, "%s"))
9612     {
9613       int res = vsnprintf (staging_area, sizeof (staging_area), fmt, ap);
9614
9615       va_end (ap);
9616
9617       if (res < 0)
9618         return;
9619
9620       if ((size_t) res >= sizeof (staging_area))
9621         abort ();
9622
9623       start = curr = staging_area;
9624     }
9625   else
9626     {
9627       start = curr = va_arg (ap, const char *);
9628       va_end (ap);
9629     }
9630
9631   do
9632     {
9633       if (*curr == '\0'
9634           || (*curr == STYLE_MARKER_CHAR
9635               && ISXDIGIT (*(curr + 1))
9636               && *(curr + 2) == STYLE_MARKER_CHAR))
9637         {
9638           /* Output content between our START position and CURR.  */
9639           int len = curr - start;
9640           int n = (*info->fprintf_styled_func) (info->stream, curr_style,
9641                                                 "%.*s", len, start);
9642           if (n < 0)
9643             break;
9644
9645           if (*curr == '\0')
9646             break;
9647
9648           /* Skip over the initial STYLE_MARKER_CHAR.  */
9649           ++curr;
9650
9651           /* Update the CURR_STYLE.  As there are less than 16 styles, it
9652              is possible, that if the input is corrupted in some way, that
9653              we might set CURR_STYLE to an invalid value.  Don't worry
9654              though, we check for this situation.  */
9655           if (*curr >= '0' && *curr <= '9')
9656             curr_style = (enum disassembler_style) (*curr - '0');
9657           else if (*curr >= 'a' && *curr <= 'f')
9658             curr_style = (enum disassembler_style) (*curr - 'a' + 10);
9659           else
9660             curr_style = dis_style_text;
9661
9662           /* Check for an invalid style having been selected.  This should
9663              never happen, but it doesn't hurt to be a little paranoid.  */
9664           if (curr_style > dis_style_comment_start)
9665             curr_style = dis_style_text;
9666
9667           /* Skip the hex character, and the closing STYLE_MARKER_CHAR.  */
9668           curr += 2;
9669
9670           /* Reset the START to after the style marker.  */
9671           start = curr;
9672         }
9673       else
9674         ++curr;
9675     }
9676   while (true);
9677 }
9678
9679 static int
9680 print_insn (bfd_vma pc, disassemble_info *info, int intel_syntax)
9681 {
9682   const struct dis386 *dp;
9683   int i;
9684   int ret;
9685   char *op_txt[MAX_OPERANDS];
9686   int needcomma;
9687   bool intel_swap_2_3;
9688   int sizeflag, orig_sizeflag;
9689   const char *p;
9690   struct dis_private priv;
9691   int prefix_length;
9692   int op_count;
9693   instr_info ins = {
9694     .info = info,
9695     .intel_syntax = intel_syntax >= 0
9696                     ? intel_syntax
9697                     : (info->mach & bfd_mach_i386_intel_syntax) != 0,
9698     .intel_mnemonic = !SYSV386_COMPAT,
9699     .op_index[0 ... MAX_OPERANDS - 1] = -1,
9700     .start_pc = pc,
9701     .start_codep = priv.the_buffer,
9702     .codep = priv.the_buffer,
9703     .obufp = ins.obuf,
9704     .last_lock_prefix = -1,
9705     .last_repz_prefix = -1,
9706     .last_repnz_prefix = -1,
9707     .last_data_prefix = -1,
9708     .last_addr_prefix = -1,
9709     .last_rex_prefix = -1,
9710     .last_rex2_prefix = -1,
9711     .last_seg_prefix = -1,
9712     .fwait_prefix = -1,
9713   };
9714   char op_out[MAX_OPERANDS][MAX_OPERAND_BUFFER_SIZE];
9715
9716   priv.orig_sizeflag = AFLAG | DFLAG;
9717   if ((info->mach & bfd_mach_i386_i386) != 0)
9718     ins.address_mode = mode_32bit;
9719   else if (info->mach == bfd_mach_i386_i8086)
9720     {
9721       ins.address_mode = mode_16bit;
9722       priv.orig_sizeflag = 0;
9723     }
9724   else
9725     ins.address_mode = mode_64bit;
9726
9727   for (p = info->disassembler_options; p != NULL;)
9728     {
9729       if (startswith (p, "amd64"))
9730         ins.isa64 = amd64;
9731       else if (startswith (p, "intel64"))
9732         ins.isa64 = intel64;
9733       else if (startswith (p, "x86-64"))
9734         {
9735           ins.address_mode = mode_64bit;
9736           priv.orig_sizeflag |= AFLAG | DFLAG;
9737         }
9738       else if (startswith (p, "i386"))
9739         {
9740           ins.address_mode = mode_32bit;
9741           priv.orig_sizeflag |= AFLAG | DFLAG;
9742         }
9743       else if (startswith (p, "i8086"))
9744         {
9745           ins.address_mode = mode_16bit;
9746           priv.orig_sizeflag &= ~(AFLAG | DFLAG);
9747         }
9748       else if (startswith (p, "intel"))
9749         {
9750           if (startswith (p + 5, "-mnemonic"))
9751             ins.intel_mnemonic = true;
9752           else
9753             ins.intel_syntax = 1;
9754         }
9755       else if (startswith (p, "att"))
9756         {
9757           ins.intel_syntax = 0;
9758           if (startswith (p + 3, "-mnemonic"))
9759             ins.intel_mnemonic = false;
9760         }
9761       else if (startswith (p, "addr"))
9762         {
9763           if (ins.address_mode == mode_64bit)
9764             {
9765               if (p[4] == '3' && p[5] == '2')
9766                 priv.orig_sizeflag &= ~AFLAG;
9767               else if (p[4] == '6' && p[5] == '4')
9768                 priv.orig_sizeflag |= AFLAG;
9769             }
9770           else
9771             {
9772               if (p[4] == '1' && p[5] == '6')
9773                 priv.orig_sizeflag &= ~AFLAG;
9774               else if (p[4] == '3' && p[5] == '2')
9775                 priv.orig_sizeflag |= AFLAG;
9776             }
9777         }
9778       else if (startswith (p, "data"))
9779         {
9780           if (p[4] == '1' && p[5] == '6')
9781             priv.orig_sizeflag &= ~DFLAG;
9782           else if (p[4] == '3' && p[5] == '2')
9783             priv.orig_sizeflag |= DFLAG;
9784         }
9785       else if (startswith (p, "suffix"))
9786         priv.orig_sizeflag |= SUFFIX_ALWAYS;
9787
9788       p = strchr (p, ',');
9789       if (p != NULL)
9790         p++;
9791     }
9792
9793   if (ins.address_mode == mode_64bit && sizeof (bfd_vma) < 8)
9794     {
9795       i386_dis_printf (info, dis_style_text, _("64-bit address is disabled"));
9796       return -1;
9797     }
9798
9799   if (ins.intel_syntax)
9800     {
9801       ins.open_char = '[';
9802       ins.close_char = ']';
9803       ins.separator_char = '+';
9804       ins.scale_char = '*';
9805     }
9806   else
9807     {
9808       ins.open_char = '(';
9809       ins.close_char =  ')';
9810       ins.separator_char = ',';
9811       ins.scale_char = ',';
9812     }
9813
9814   /* The output looks better if we put 7 bytes on a line, since that
9815      puts most long word instructions on a single line.  */
9816   info->bytes_per_line = 7;
9817
9818   info->private_data = &priv;
9819   priv.fetched = 0;
9820   priv.insn_start = pc;
9821
9822   for (i = 0; i < MAX_OPERANDS; ++i)
9823     {
9824       op_out[i][0] = 0;
9825       ins.op_out[i] = op_out[i];
9826     }
9827
9828   sizeflag = priv.orig_sizeflag;
9829
9830   switch (ckprefix (&ins))
9831     {
9832     case ckp_okay:
9833       break;
9834
9835     case ckp_bogus:
9836       /* Too many prefixes or unused REX prefixes.  */
9837       for (i = 0;
9838            i < (int) ARRAY_SIZE (ins.all_prefixes) && ins.all_prefixes[i];
9839            i++)
9840         i386_dis_printf (info, dis_style_mnemonic, "%s%s",
9841                          (i == 0 ? "" : " "),
9842                          prefix_name (ins.address_mode, ins.all_prefixes[i],
9843                                       sizeflag));
9844       ret = i;
9845       goto out;
9846
9847     case ckp_fetch_error:
9848       goto fetch_error_out;
9849     }
9850
9851   ins.nr_prefixes = ins.codep - ins.start_codep;
9852
9853   if (!fetch_code (info, ins.codep + 1))
9854     {
9855     fetch_error_out:
9856       ret = fetch_error (&ins);
9857       goto out;
9858     }
9859
9860   ins.two_source_ops = (*ins.codep == 0x62 || *ins.codep == 0xc8);
9861
9862   if ((ins.prefixes & PREFIX_FWAIT)
9863       && (*ins.codep < 0xd8 || *ins.codep > 0xdf))
9864     {
9865       /* Handle ins.prefixes before fwait.  */
9866       for (i = 0; i < ins.fwait_prefix && ins.all_prefixes[i];
9867            i++)
9868         i386_dis_printf (info, dis_style_mnemonic, "%s ",
9869                          prefix_name (ins.address_mode, ins.all_prefixes[i],
9870                                       sizeflag));
9871       i386_dis_printf (info, dis_style_mnemonic, "fwait");
9872       ret = i + 1;
9873       goto out;
9874     }
9875
9876   /* REX2.M in rex2 prefix represents map0 or map1.  */
9877   if (ins.last_rex2_prefix < 0 ? *ins.codep == 0x0f : (ins.rex2 & REX2_M))
9878     {
9879       if (!ins.rex2)
9880         {
9881           ins.codep++;
9882           if (!fetch_code (info, ins.codep + 1))
9883             goto fetch_error_out;
9884         }
9885
9886       dp = &dis386_twobyte[*ins.codep];
9887       ins.need_modrm = twobyte_has_modrm[*ins.codep];
9888     }
9889   else
9890     {
9891       dp = &dis386[*ins.codep];
9892       ins.need_modrm = onebyte_has_modrm[*ins.codep];
9893     }
9894   ins.condition_code = *ins.codep & 0xf;
9895   ins.codep++;
9896
9897   /* Save sizeflag for printing the extra ins.prefixes later before updating
9898      it for mnemonic and operand processing.  The prefix names depend
9899      only on the address mode.  */
9900   orig_sizeflag = sizeflag;
9901   if (ins.prefixes & PREFIX_ADDR)
9902     sizeflag ^= AFLAG;
9903   if ((ins.prefixes & PREFIX_DATA))
9904     sizeflag ^= DFLAG;
9905
9906   ins.end_codep = ins.codep;
9907   if (ins.need_modrm && !fetch_modrm (&ins))
9908     goto fetch_error_out;
9909
9910   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
9911     {
9912       if (!get_sib (&ins, sizeflag)
9913           || !dofloat (&ins, sizeflag))
9914         goto fetch_error_out;
9915     }
9916   else
9917     {
9918       dp = get_valid_dis386 (dp, &ins);
9919       if (dp == &err_opcode)
9920         goto fetch_error_out;
9921
9922       /* For APX instructions promoted from legacy maps 0/1, embedded prefix
9923          is interpreted as the operand size override.  */
9924       if (ins.evex_type == evex_from_legacy
9925           && ins.vex.prefix == DATA_PREFIX_OPCODE)
9926         sizeflag ^= DFLAG;
9927
9928       if(ins.evex_type == evex_default)
9929         ins.vex.nf = false;
9930       else
9931         /* For EVEX-promoted formats, we need to clear EVEX.NF (ccmp and ctest
9932            are cleared separately.) in mask_register_specifier and keep the low
9933            2 bits of mask_register_specifier to report errors for invalid cases
9934            .  */
9935         ins.vex.mask_register_specifier &= 0x3;
9936
9937       if (dp != NULL && putop (&ins, dp->name, sizeflag) == 0)
9938         {
9939           if (!get_sib (&ins, sizeflag))
9940             goto fetch_error_out;
9941           for (i = 0; i < MAX_OPERANDS; ++i)
9942             {
9943               ins.obufp = ins.op_out[i];
9944               ins.op_ad = MAX_OPERANDS - 1 - i;
9945               if (dp->op[i].rtn
9946                   && !dp->op[i].rtn (&ins, dp->op[i].bytemode, sizeflag))
9947                 goto fetch_error_out;
9948               /* For EVEX instruction after the last operand masking
9949                  should be printed.  */
9950               if (i == 0 && ins.vex.evex)
9951                 {
9952                   /* Don't print {%k0}.  */
9953                   if (ins.vex.mask_register_specifier)
9954                     {
9955                       const char *reg_name
9956                         = att_names_mask[ins.vex.mask_register_specifier];
9957
9958                       oappend (&ins, "{");
9959                       oappend_register (&ins, reg_name);
9960                       oappend (&ins, "}");
9961
9962                       if (ins.vex.zeroing)
9963                         oappend (&ins, "{z}");
9964                     }
9965                   else if (ins.vex.zeroing)
9966                     {
9967                       oappend (&ins, "{bad}");
9968                       continue;
9969                     }
9970
9971                   /* Instructions with a mask register destination allow for
9972                      zeroing-masking only (if any masking at all), which is
9973                      _not_ expressed by EVEX.z.  */
9974                   if (ins.vex.zeroing && dp->op[0].bytemode == mask_mode)
9975                     ins.illegal_masking = true;
9976
9977                   /* S/G insns require a mask and don't allow
9978                      zeroing-masking.  */
9979                   if ((dp->op[0].bytemode == vex_vsib_d_w_dq_mode
9980                        || dp->op[0].bytemode == vex_vsib_q_w_dq_mode)
9981                       && (ins.vex.mask_register_specifier == 0
9982                           || ins.vex.zeroing))
9983                     ins.illegal_masking = true;
9984
9985                   if (ins.illegal_masking)
9986                     oappend (&ins, "/(bad)");
9987                 }
9988             }
9989           /* vex.nf is cleared after being consumed.  */
9990           if (ins.vex.nf)
9991             oappend (&ins, "{bad-nf}");
9992
9993           /* Check whether rounding control was enabled for an insn not
9994              supporting it, when evex.b is not treated as evex.nd.  */
9995           if (ins.modrm.mod == 3 && ins.vex.b && ins.evex_type == evex_default
9996               && !(ins.evex_used & EVEX_b_used))
9997             {
9998               for (i = 0; i < MAX_OPERANDS; ++i)
9999                 {
10000                   ins.obufp = ins.op_out[i];
10001                   if (*ins.obufp)
10002                     continue;
10003                   oappend (&ins, names_rounding[ins.vex.ll]);
10004                   oappend (&ins, "bad}");
10005                   break;
10006                 }
10007             }
10008         }
10009     }
10010
10011   /* Clear instruction information.  */
10012   info->insn_info_valid = 0;
10013   info->branch_delay_insns = 0;
10014   info->data_size = 0;
10015   info->insn_type = dis_noninsn;
10016   info->target = 0;
10017   info->target2 = 0;
10018
10019   /* Reset jump operation indicator.  */
10020   ins.op_is_jump = false;
10021   {
10022     int jump_detection = 0;
10023
10024     /* Extract flags.  */
10025     for (i = 0; i < MAX_OPERANDS; ++i)
10026       {
10027         if ((dp->op[i].rtn == OP_J)
10028             || (dp->op[i].rtn == OP_indirE))
10029           jump_detection |= 1;
10030         else if ((dp->op[i].rtn == BND_Fixup)
10031                  || (!dp->op[i].rtn && !dp->op[i].bytemode))
10032           jump_detection |= 2;
10033         else if ((dp->op[i].bytemode == cond_jump_mode)
10034                  || (dp->op[i].bytemode == loop_jcxz_mode))
10035           jump_detection |= 4;
10036       }
10037
10038     /* Determine if this is a jump or branch.  */
10039     if ((jump_detection & 0x3) == 0x3)
10040       {
10041         ins.op_is_jump = true;
10042         if (jump_detection & 0x4)
10043           info->insn_type = dis_condbranch;
10044         else
10045           info->insn_type = (dp->name && !strncmp (dp->name, "call", 4))
10046             ? dis_jsr : dis_branch;
10047       }
10048   }
10049   /* The purpose of placing the check here is to wait for the EVEX prefix for
10050      conditional CMP and TEST to be consumed and cleared, and then make a
10051      unified judgment. Because they are both in map4, we can not distinguish
10052      EVEX prefix for conditional CMP and TEST from others during the
10053      EVEX prefix stage of parsing.  */
10054   if (ins.evex_type == evex_from_legacy)
10055     {
10056       /* EVEX from legacy instructions, when the EVEX.ND bit is 0,
10057          all bits of EVEX.vvvv and EVEX.V' must be 1.  */
10058       if (!ins.vex.nd && (ins.vex.register_specifier || !ins.vex.v))
10059         {
10060           i386_dis_printf (info, dis_style_text, "(bad)");
10061           ret = ins.end_codep - priv.the_buffer;
10062           goto out;
10063         }
10064
10065       /* EVEX from legacy instructions require that EVEX.z, EVEX.L’L and the
10066          lower 2 bits of EVEX.aaa must be 0.  */
10067       if ((ins.vex.mask_register_specifier & 0x3) != 0
10068           || ins.vex.ll != 0 || ins.vex.zeroing != 0)
10069         {
10070           i386_dis_printf (info, dis_style_text, "(bad)");
10071           ret = ins.end_codep - priv.the_buffer;
10072           goto out;
10073         }
10074     }
10075   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
10076      are all 0s in inverted form.  */
10077   if (ins.need_vex && ins.vex.register_specifier != 0)
10078     {
10079       i386_dis_printf (info, dis_style_text, "(bad)");
10080       ret = ins.end_codep - priv.the_buffer;
10081       goto out;
10082     }
10083
10084   if ((dp->prefix_requirement & PREFIX_REX2_ILLEGAL)
10085       && ins.last_rex2_prefix >= 0 && (ins.rex2 & REX2_SPECIAL) == 0)
10086     {
10087       i386_dis_printf (info, dis_style_text, "(bad)");
10088       ret = ins.end_codep - priv.the_buffer;
10089       goto out;
10090     }
10091
10092   switch (dp->prefix_requirement & ~PREFIX_REX2_ILLEGAL)
10093     {
10094     case PREFIX_DATA:
10095       /* If only the data prefix is marked as mandatory, its absence renders
10096          the encoding invalid.  Most other PREFIX_OPCODE rules still apply.  */
10097       if (ins.need_vex ? !ins.vex.prefix : !(ins.prefixes & PREFIX_DATA))
10098         {
10099           i386_dis_printf (info, dis_style_text, "(bad)");
10100           ret = ins.end_codep - priv.the_buffer;
10101           goto out;
10102         }
10103       ins.used_prefixes |= PREFIX_DATA;
10104       /* Fall through.  */
10105     case PREFIX_OPCODE:
10106       /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
10107          unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
10108          used by putop and MMX/SSE operand and may be overridden by the
10109          PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
10110          separately.  */
10111       if (((ins.need_vex
10112             ? ins.vex.prefix == REPE_PREFIX_OPCODE
10113               || ins.vex.prefix == REPNE_PREFIX_OPCODE
10114             : (ins.prefixes
10115                & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
10116            && (ins.used_prefixes
10117                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
10118           || (((ins.need_vex
10119                 ? ins.vex.prefix == DATA_PREFIX_OPCODE
10120                 : ((ins.prefixes
10121                     & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
10122                    == PREFIX_DATA))
10123                && (ins.used_prefixes & PREFIX_DATA) == 0))
10124           || (ins.vex.evex && dp->prefix_requirement != PREFIX_DATA
10125               && !ins.vex.w != !(ins.used_prefixes & PREFIX_DATA)))
10126         {
10127           i386_dis_printf (info, dis_style_text, "(bad)");
10128           ret = ins.end_codep - priv.the_buffer;
10129           goto out;
10130         }
10131       break;
10132
10133     case PREFIX_IGNORED:
10134       /* Zap data size and rep prefixes from used_prefixes and reinstate their
10135          origins in all_prefixes.  */
10136       ins.used_prefixes &= ~PREFIX_OPCODE;
10137       if (ins.last_data_prefix >= 0)
10138         ins.all_prefixes[ins.last_data_prefix] = 0x66;
10139       if (ins.last_repz_prefix >= 0)
10140         ins.all_prefixes[ins.last_repz_prefix] = 0xf3;
10141       if (ins.last_repnz_prefix >= 0)
10142         ins.all_prefixes[ins.last_repnz_prefix] = 0xf2;
10143       break;
10144
10145     case PREFIX_NP_OR_DATA:
10146       if (ins.vex.prefix == REPE_PREFIX_OPCODE
10147           || ins.vex.prefix == REPNE_PREFIX_OPCODE)
10148         {
10149           i386_dis_printf (info, dis_style_text, "(bad)");
10150           ret = ins.end_codep - priv.the_buffer;
10151           goto out;
10152         }
10153       break;
10154
10155     case NO_PREFIX:
10156       if (ins.vex.prefix)
10157         {
10158           i386_dis_printf (info, dis_style_text, "(bad)");
10159           ret = ins.end_codep - priv.the_buffer;
10160           goto out;
10161         }
10162       break;
10163     }
10164
10165   /* Check if the REX prefix is used.  */
10166   if ((ins.rex ^ ins.rex_used) == 0
10167       && !ins.need_vex && ins.last_rex_prefix >= 0)
10168     ins.all_prefixes[ins.last_rex_prefix] = 0;
10169
10170   /* Check if the REX2 prefix is used.  */
10171   if (ins.last_rex2_prefix >= 0
10172       && ((ins.rex2 & REX2_SPECIAL)
10173           || (((ins.rex2 & 7) ^ (ins.rex2_used & 7)) == 0
10174               && (ins.rex ^ ins.rex_used) == 0
10175               && (ins.rex2 & 7))))
10176     ins.all_prefixes[ins.last_rex2_prefix] = 0;
10177
10178   /* Check if the SEG prefix is used.  */
10179   if ((ins.prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
10180                        | PREFIX_FS | PREFIX_GS)) != 0
10181       && (ins.used_prefixes & ins.active_seg_prefix) != 0)
10182     ins.all_prefixes[ins.last_seg_prefix] = 0;
10183
10184   /* Check if the ADDR prefix is used.  */
10185   if ((ins.prefixes & PREFIX_ADDR) != 0
10186       && (ins.used_prefixes & PREFIX_ADDR) != 0)
10187     ins.all_prefixes[ins.last_addr_prefix] = 0;
10188
10189   /* Check if the DATA prefix is used.  */
10190   if ((ins.prefixes & PREFIX_DATA) != 0
10191       && (ins.used_prefixes & PREFIX_DATA) != 0
10192       && !ins.need_vex)
10193     ins.all_prefixes[ins.last_data_prefix] = 0;
10194
10195   /* Print the extra ins.prefixes.  */
10196   prefix_length = 0;
10197   for (i = 0; i < (int) ARRAY_SIZE (ins.all_prefixes); i++)
10198     if (ins.all_prefixes[i])
10199       {
10200         const char *name = prefix_name (ins.address_mode, ins.all_prefixes[i],
10201                                         orig_sizeflag);
10202
10203         if (name == NULL)
10204           abort ();
10205         prefix_length += strlen (name) + 1;
10206         if (ins.all_prefixes[i] == REX2_OPCODE)
10207           i386_dis_printf (info, dis_style_mnemonic, "{%s 0x%x} ", name,
10208                            (unsigned int) ins.rex2_payload);
10209         else
10210           i386_dis_printf (info, dis_style_mnemonic, "%s ", name);
10211       }
10212
10213   /* Check maximum code length.  */
10214   if ((ins.codep - ins.start_codep) > MAX_CODE_LENGTH)
10215     {
10216       i386_dis_printf (info, dis_style_text, "(bad)");
10217       ret = MAX_CODE_LENGTH;
10218       goto out;
10219     }
10220
10221   /* Calculate the number of operands this instruction has.  */
10222   op_count = 0;
10223   for (i = 0; i < MAX_OPERANDS; ++i)
10224     if (*ins.op_out[i] != '\0')
10225       ++op_count;
10226
10227   /* Calculate the number of spaces to print after the mnemonic.  */
10228   ins.obufp = ins.mnemonicendp;
10229   if (op_count > 0)
10230     {
10231       i = strlen (ins.obuf) + prefix_length;
10232       if (i < 7)
10233         i = 7 - i;
10234       else
10235         i = 1;
10236     }
10237   else
10238     i = 0;
10239
10240   /* Print the instruction mnemonic along with any trailing whitespace.  */
10241   i386_dis_printf (info, dis_style_mnemonic, "%s%*s", ins.obuf, i, "");
10242
10243   /* The enter and bound instructions are printed with operands in the same
10244      order as the intel book; everything else is printed in reverse order.  */
10245   intel_swap_2_3 = false;
10246   if (ins.intel_syntax || ins.two_source_ops)
10247     {
10248       for (i = 0; i < MAX_OPERANDS; ++i)
10249         op_txt[i] = ins.op_out[i];
10250
10251       if (ins.intel_syntax && dp && dp->op[2].rtn == OP_Rounding
10252           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
10253         {
10254           op_txt[2] = ins.op_out[3];
10255           op_txt[3] = ins.op_out[2];
10256           intel_swap_2_3 = true;
10257         }
10258
10259       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
10260         {
10261           bool riprel;
10262
10263           ins.op_ad = ins.op_index[i];
10264           ins.op_index[i] = ins.op_index[MAX_OPERANDS - 1 - i];
10265           ins.op_index[MAX_OPERANDS - 1 - i] = ins.op_ad;
10266           riprel = ins.op_riprel[i];
10267           ins.op_riprel[i] = ins.op_riprel[MAX_OPERANDS - 1 - i];
10268           ins.op_riprel[MAX_OPERANDS - 1 - i] = riprel;
10269         }
10270     }
10271   else
10272     {
10273       for (i = 0; i < MAX_OPERANDS; ++i)
10274         op_txt[MAX_OPERANDS - 1 - i] = ins.op_out[i];
10275     }
10276
10277   needcomma = 0;
10278   for (i = 0; i < MAX_OPERANDS; ++i)
10279     if (*op_txt[i])
10280       {
10281         /* In Intel syntax embedded rounding / SAE are not separate operands.
10282            Instead they're attached to the prior register operand.  Simply
10283            suppress emission of the comma to achieve that effect.  */
10284         switch (i & -(ins.intel_syntax && dp))
10285           {
10286           case 2:
10287             if (dp->op[2].rtn == OP_Rounding && !intel_swap_2_3)
10288               needcomma = 0;
10289             break;
10290           case 3:
10291             if (dp->op[3].rtn == OP_Rounding || intel_swap_2_3)
10292               needcomma = 0;
10293             break;
10294           }
10295         if (needcomma)
10296           i386_dis_printf (info, dis_style_text, ",");
10297         if (ins.op_index[i] != -1 && !ins.op_riprel[i])
10298           {
10299             bfd_vma target = (bfd_vma) ins.op_address[ins.op_index[i]];
10300
10301             if (ins.op_is_jump)
10302               {
10303                 info->insn_info_valid = 1;
10304                 info->branch_delay_insns = 0;
10305                 info->data_size = 0;
10306                 info->target = target;
10307                 info->target2 = 0;
10308               }
10309             (*info->print_address_func) (target, info);
10310           }
10311         else
10312           i386_dis_printf (info, dis_style_text, "%s", op_txt[i]);
10313         needcomma = 1;
10314       }
10315
10316   for (i = 0; i < MAX_OPERANDS; i++)
10317     if (ins.op_index[i] != -1 && ins.op_riprel[i])
10318       {
10319         i386_dis_printf (info, dis_style_comment_start, "        # ");
10320         (*info->print_address_func)
10321           ((bfd_vma)(ins.start_pc + (ins.codep - ins.start_codep)
10322                      + ins.op_address[ins.op_index[i]]),
10323           info);
10324         break;
10325       }
10326   ret = ins.codep - priv.the_buffer;
10327  out:
10328   info->private_data = NULL;
10329   return ret;
10330 }
10331
10332 /* Here for backwards compatibility.  When gdb stops using
10333    print_insn_i386_att and print_insn_i386_intel these functions can
10334    disappear, and print_insn_i386 be merged into print_insn.  */
10335 int
10336 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
10337 {
10338   return print_insn (pc, info, 0);
10339 }
10340
10341 int
10342 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
10343 {
10344   return print_insn (pc, info, 1);
10345 }
10346
10347 int
10348 print_insn_i386 (bfd_vma pc, disassemble_info *info)
10349 {
10350   return print_insn (pc, info, -1);
10351 }
10352
10353 static const char *float_mem[] = {
10354   /* d8 */
10355   "fadd{s|}",
10356   "fmul{s|}",
10357   "fcom{s|}",
10358   "fcomp{s|}",
10359   "fsub{s|}",
10360   "fsubr{s|}",
10361   "fdiv{s|}",
10362   "fdivr{s|}",
10363   /* d9 */
10364   "fld{s|}",
10365   "(bad)",
10366   "fst{s|}",
10367   "fstp{s|}",
10368   "fldenv{C|C}",
10369   "fldcw",
10370   "fNstenv{C|C}",
10371   "fNstcw",
10372   /* da */
10373   "fiadd{l|}",
10374   "fimul{l|}",
10375   "ficom{l|}",
10376   "ficomp{l|}",
10377   "fisub{l|}",
10378   "fisubr{l|}",
10379   "fidiv{l|}",
10380   "fidivr{l|}",
10381   /* db */
10382   "fild{l|}",
10383   "fisttp{l|}",
10384   "fist{l|}",
10385   "fistp{l|}",
10386   "(bad)",
10387   "fld{t|}",
10388   "(bad)",
10389   "fstp{t|}",
10390   /* dc */
10391   "fadd{l|}",
10392   "fmul{l|}",
10393   "fcom{l|}",
10394   "fcomp{l|}",
10395   "fsub{l|}",
10396   "fsubr{l|}",
10397   "fdiv{l|}",
10398   "fdivr{l|}",
10399   /* dd */
10400   "fld{l|}",
10401   "fisttp{ll|}",
10402   "fst{l||}",
10403   "fstp{l|}",
10404   "frstor{C|C}",
10405   "(bad)",
10406   "fNsave{C|C}",
10407   "fNstsw",
10408   /* de */
10409   "fiadd{s|}",
10410   "fimul{s|}",
10411   "ficom{s|}",
10412   "ficomp{s|}",
10413   "fisub{s|}",
10414   "fisubr{s|}",
10415   "fidiv{s|}",
10416   "fidivr{s|}",
10417   /* df */
10418   "fild{s|}",
10419   "fisttp{s|}",
10420   "fist{s|}",
10421   "fistp{s|}",
10422   "fbld",
10423   "fild{ll|}",
10424   "fbstp",
10425   "fistp{ll|}",
10426 };
10427
10428 static const unsigned char float_mem_mode[] = {
10429   /* d8 */
10430   d_mode,
10431   d_mode,
10432   d_mode,
10433   d_mode,
10434   d_mode,
10435   d_mode,
10436   d_mode,
10437   d_mode,
10438   /* d9 */
10439   d_mode,
10440   0,
10441   d_mode,
10442   d_mode,
10443   0,
10444   w_mode,
10445   0,
10446   w_mode,
10447   /* da */
10448   d_mode,
10449   d_mode,
10450   d_mode,
10451   d_mode,
10452   d_mode,
10453   d_mode,
10454   d_mode,
10455   d_mode,
10456   /* db */
10457   d_mode,
10458   d_mode,
10459   d_mode,
10460   d_mode,
10461   0,
10462   t_mode,
10463   0,
10464   t_mode,
10465   /* dc */
10466   q_mode,
10467   q_mode,
10468   q_mode,
10469   q_mode,
10470   q_mode,
10471   q_mode,
10472   q_mode,
10473   q_mode,
10474   /* dd */
10475   q_mode,
10476   q_mode,
10477   q_mode,
10478   q_mode,
10479   0,
10480   0,
10481   0,
10482   w_mode,
10483   /* de */
10484   w_mode,
10485   w_mode,
10486   w_mode,
10487   w_mode,
10488   w_mode,
10489   w_mode,
10490   w_mode,
10491   w_mode,
10492   /* df */
10493   w_mode,
10494   w_mode,
10495   w_mode,
10496   w_mode,
10497   t_mode,
10498   q_mode,
10499   t_mode,
10500   q_mode
10501 };
10502
10503 #define ST { OP_ST, 0 }
10504 #define STi { OP_STi, 0 }
10505
10506 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
10507 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
10508 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
10509 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
10510 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
10511 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
10512 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
10513 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
10514 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
10515
10516 static const struct dis386 float_reg[][8] = {
10517   /* d8 */
10518   {
10519     { "fadd",   { ST, STi }, 0 },
10520     { "fmul",   { ST, STi }, 0 },
10521     { "fcom",   { STi }, 0 },
10522     { "fcomp",  { STi }, 0 },
10523     { "fsub",   { ST, STi }, 0 },
10524     { "fsubr",  { ST, STi }, 0 },
10525     { "fdiv",   { ST, STi }, 0 },
10526     { "fdivr",  { ST, STi }, 0 },
10527   },
10528   /* d9 */
10529   {
10530     { "fld",    { STi }, 0 },
10531     { "fxch",   { STi }, 0 },
10532     { FGRPd9_2 },
10533     { Bad_Opcode },
10534     { FGRPd9_4 },
10535     { FGRPd9_5 },
10536     { FGRPd9_6 },
10537     { FGRPd9_7 },
10538   },
10539   /* da */
10540   {
10541     { "fcmovb", { ST, STi }, 0 },
10542     { "fcmove", { ST, STi }, 0 },
10543     { "fcmovbe",{ ST, STi }, 0 },
10544     { "fcmovu", { ST, STi }, 0 },
10545     { Bad_Opcode },
10546     { FGRPda_5 },
10547     { Bad_Opcode },
10548     { Bad_Opcode },
10549   },
10550   /* db */
10551   {
10552     { "fcmovnb",{ ST, STi }, 0 },
10553     { "fcmovne",{ ST, STi }, 0 },
10554     { "fcmovnbe",{ ST, STi }, 0 },
10555     { "fcmovnu",{ ST, STi }, 0 },
10556     { FGRPdb_4 },
10557     { "fucomi", { ST, STi }, 0 },
10558     { "fcomi",  { ST, STi }, 0 },
10559     { Bad_Opcode },
10560   },
10561   /* dc */
10562   {
10563     { "fadd",   { STi, ST }, 0 },
10564     { "fmul",   { STi, ST }, 0 },
10565     { Bad_Opcode },
10566     { Bad_Opcode },
10567     { "fsub{!M|r}",     { STi, ST }, 0 },
10568     { "fsub{M|}",       { STi, ST }, 0 },
10569     { "fdiv{!M|r}",     { STi, ST }, 0 },
10570     { "fdiv{M|}",       { STi, ST }, 0 },
10571   },
10572   /* dd */
10573   {
10574     { "ffree",  { STi }, 0 },
10575     { Bad_Opcode },
10576     { "fst",    { STi }, 0 },
10577     { "fstp",   { STi }, 0 },
10578     { "fucom",  { STi }, 0 },
10579     { "fucomp", { STi }, 0 },
10580     { Bad_Opcode },
10581     { Bad_Opcode },
10582   },
10583   /* de */
10584   {
10585     { "faddp",  { STi, ST }, 0 },
10586     { "fmulp",  { STi, ST }, 0 },
10587     { Bad_Opcode },
10588     { FGRPde_3 },
10589     { "fsub{!M|r}p",    { STi, ST }, 0 },
10590     { "fsub{M|}p",      { STi, ST }, 0 },
10591     { "fdiv{!M|r}p",    { STi, ST }, 0 },
10592     { "fdiv{M|}p",      { STi, ST }, 0 },
10593   },
10594   /* df */
10595   {
10596     { "ffreep", { STi }, 0 },
10597     { Bad_Opcode },
10598     { Bad_Opcode },
10599     { Bad_Opcode },
10600     { FGRPdf_4 },
10601     { "fucomip", { ST, STi }, 0 },
10602     { "fcomip", { ST, STi }, 0 },
10603     { Bad_Opcode },
10604   },
10605 };
10606
10607 static const char *const fgrps[][8] = {
10608   /* Bad opcode 0 */
10609   {
10610     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10611   },
10612
10613   /* d9_2  1 */
10614   {
10615     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10616   },
10617
10618   /* d9_4  2 */
10619   {
10620     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10621   },
10622
10623   /* d9_5  3 */
10624   {
10625     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10626   },
10627
10628   /* d9_6  4 */
10629   {
10630     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10631   },
10632
10633   /* d9_7  5 */
10634   {
10635     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10636   },
10637
10638   /* da_5  6 */
10639   {
10640     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10641   },
10642
10643   /* db_4  7 */
10644   {
10645     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10646     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10647   },
10648
10649   /* de_3  8 */
10650   {
10651     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10652   },
10653
10654   /* df_4  9 */
10655   {
10656     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10657   },
10658 };
10659
10660 static const char *const oszc_flags[16] = {
10661   " {dfv=}", " {dfv=cf}", " {dfv=zf}", " {dfv=zf, cf}", " {dfv=sf}",
10662   " {dfv=sf, cf}", " {dfv=sf, zf}", " {dfv=sf, zf, cf}", " {dfv=of}",
10663   " {dfv=of, cf}", " {dfv=of, zf}", " {dfv=of, zf, cf}", " {dfv=of, sf}",
10664   " {dfv=of, sf, cf}", " {dfv=of, sf, zf}", " {dfv=of, sf, zf, cf}"
10665 };
10666
10667 static const char *const scc_suffix[16] = {
10668   "o", "no", "b", "ae", "e", "ne", "be", "a", "s", "ns", "t", "f",
10669   "l", "ge", "le", "g"
10670 };
10671
10672 static void
10673 swap_operand (instr_info *ins)
10674 {
10675   char *p = ins->mnemonicendp;
10676
10677   if (p[-1] == '}')
10678     {
10679       while (*--p != '{')
10680         {
10681           if (p <= ins->obuf + 2)
10682             abort ();
10683         }
10684       if (p[-1] == ' ')
10685         --p;
10686     }
10687   memmove (p + 2, p, ins->mnemonicendp - p + 1);
10688   p[0] = '.';
10689   p[1] = 's';
10690   ins->mnemonicendp += 2;
10691 }
10692
10693 static bool
10694 dofloat (instr_info *ins, int sizeflag)
10695 {
10696   const struct dis386 *dp;
10697   unsigned char floatop = ins->codep[-1];
10698
10699   if (ins->modrm.mod != 3)
10700     {
10701       int fp_indx = (floatop - 0xd8) * 8 + ins->modrm.reg;
10702
10703       putop (ins, float_mem[fp_indx], sizeflag);
10704       ins->obufp = ins->op_out[0];
10705       ins->op_ad = 2;
10706       return OP_E (ins, float_mem_mode[fp_indx], sizeflag);
10707     }
10708   /* Skip mod/rm byte.  */
10709   MODRM_CHECK;
10710   ins->codep++;
10711
10712   dp = &float_reg[floatop - 0xd8][ins->modrm.reg];
10713   if (dp->name == NULL)
10714     {
10715       putop (ins, fgrps[dp->op[0].bytemode][ins->modrm.rm], sizeflag);
10716
10717       /* Instruction fnstsw is only one with strange arg.  */
10718       if (floatop == 0xdf && ins->codep[-1] == 0xe0)
10719         strcpy (ins->op_out[0], att_names16[0] + ins->intel_syntax);
10720     }
10721   else
10722     {
10723       putop (ins, dp->name, sizeflag);
10724
10725       ins->obufp = ins->op_out[0];
10726       ins->op_ad = 2;
10727       if (dp->op[0].rtn
10728           && !dp->op[0].rtn (ins, dp->op[0].bytemode, sizeflag))
10729         return false;
10730
10731       ins->obufp = ins->op_out[1];
10732       ins->op_ad = 1;
10733       if (dp->op[1].rtn
10734           && !dp->op[1].rtn (ins, dp->op[1].bytemode, sizeflag))
10735         return false;
10736     }
10737   return true;
10738 }
10739
10740 static bool
10741 OP_ST (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10742        int sizeflag ATTRIBUTE_UNUSED)
10743 {
10744   oappend_register (ins, "%st");
10745   return true;
10746 }
10747
10748 static bool
10749 OP_STi (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10750         int sizeflag ATTRIBUTE_UNUSED)
10751 {
10752   char scratch[8];
10753   int res = snprintf (scratch, ARRAY_SIZE (scratch), "%%st(%d)", ins->modrm.rm);
10754
10755   if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
10756     abort ();
10757   oappend_register (ins, scratch);
10758   return true;
10759 }
10760
10761 /* Capital letters in template are macros.  */
10762 static int
10763 putop (instr_info *ins, const char *in_template, int sizeflag)
10764 {
10765   const char *p;
10766   int alt = 0;
10767   int cond = 1;
10768   unsigned int l = 0, len = 0;
10769   char last[4];
10770   bool evex_printed = false;
10771
10772   /* We don't want to add any prefix or suffix to (bad), so return early.  */
10773   if (!strncmp (in_template, "(bad)", 5))
10774     {
10775       oappend (ins, "(bad)");
10776       *ins->obufp = 0;
10777       ins->mnemonicendp = ins->obufp;
10778       return 0;
10779     }
10780
10781   for (p = in_template; *p; p++)
10782     {
10783       if (len > l)
10784         {
10785           if (l >= sizeof (last) || !ISUPPER (*p))
10786             abort ();
10787           last[l++] = *p;
10788           continue;
10789         }
10790       switch (*p)
10791         {
10792         default:
10793           if (ins->evex_type == evex_from_legacy && !ins->vex.nd
10794               && !(ins->rex2 & 7) && !evex_printed)
10795             {
10796               oappend (ins, "{evex} ");
10797               evex_printed = true;
10798             }
10799           *ins->obufp++ = *p;
10800           break;
10801         case '%':
10802           len++;
10803           break;
10804         case '!':
10805           cond = 0;
10806           break;
10807         case '{':
10808           if (ins->intel_syntax)
10809             {
10810               while (*++p != '|')
10811                 if (*p == '}' || *p == '\0')
10812                   abort ();
10813               alt = 1;
10814             }
10815           break;
10816         case '|':
10817           while (*++p != '}')
10818             {
10819               if (*p == '\0')
10820                 abort ();
10821             }
10822           break;
10823         case '}':
10824           alt = 0;
10825           break;
10826         case 'A':
10827           if (ins->intel_syntax)
10828             break;
10829           if ((ins->need_modrm && ins->modrm.mod != 3 && !ins->vex.nd)
10830               || (sizeflag & SUFFIX_ALWAYS))
10831             *ins->obufp++ = 'b';
10832           break;
10833         case 'B':
10834           if (l == 0)
10835             {
10836             case_B:
10837               if (ins->intel_syntax)
10838                 break;
10839               if (sizeflag & SUFFIX_ALWAYS)
10840                 *ins->obufp++ = 'b';
10841             }
10842           else if (l == 1 && last[0] == 'L')
10843             {
10844               if (ins->address_mode == mode_64bit
10845                   && !(ins->prefixes & PREFIX_ADDR))
10846                 {
10847                   *ins->obufp++ = 'a';
10848                   *ins->obufp++ = 'b';
10849                   *ins->obufp++ = 's';
10850                 }
10851
10852               goto case_B;
10853             }
10854           else if (l && last[0] == 'X')
10855             {
10856               if (!ins->vex.w)
10857                 oappend (ins, "bf16");
10858               else
10859                 oappend (ins, "{bad}");
10860             }
10861           else
10862             abort ();
10863           break;
10864         case 'C':
10865           if (l == 1 && last[0] == 'C')
10866             {
10867               /* Condition code (taken from the map-0 Jcc entries).  */
10868               for (const char *q = dis386[0x70 | ins->condition_code].name + 1;
10869                    ISLOWER(*q); ++q)
10870                 *ins->obufp++ = *q;
10871               break;
10872             }
10873           else if (l == 1 && last[0] == 'S')
10874             {
10875               /* Add scc suffix.  */
10876               oappend (ins, scc_suffix[ins->vex.scc]);
10877
10878               /* For SCC insns, the ND bit is required to be set to 0.  */
10879               if (ins->vex.nd)
10880                 oappend (ins, "(bad)");
10881
10882               /* These bits have been consumed and should be cleared or restored
10883                  to default values.  */
10884               ins->vex.v = 1;
10885               ins->vex.nf = false;
10886               ins->vex.mask_register_specifier = 0;
10887               break;
10888             }
10889
10890           if (l)
10891             abort ();
10892           if (ins->intel_syntax && !alt)
10893             break;
10894           if ((ins->prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10895             {
10896               if (sizeflag & DFLAG)
10897                 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10898               else
10899                 *ins->obufp++ = ins->intel_syntax ? 'w' : 's';
10900               ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10901             }
10902           break;
10903         case 'D':
10904           if (l == 1)
10905             {
10906               switch (last[0])
10907               {
10908               case 'X':
10909                 if (!ins->vex.evex || ins->vex.w)
10910                   *ins->obufp++ = 'd';
10911                 else
10912                   oappend (ins, "{bad}");
10913                 break;
10914               default:
10915                 abort ();
10916               }
10917               break;
10918             }
10919           if (l)
10920             abort ();
10921           if (ins->intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10922             break;
10923           USED_REX (REX_W);
10924           if (ins->modrm.mod == 3)
10925             {
10926               if (ins->rex & REX_W)
10927                 *ins->obufp++ = 'q';
10928               else
10929                 {
10930                   if (sizeflag & DFLAG)
10931                     *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10932                   else
10933                     *ins->obufp++ = 'w';
10934                   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10935                 }
10936             }
10937           else
10938             *ins->obufp++ = 'w';
10939           break;
10940         case 'E':
10941           if (l == 1)
10942             {
10943               switch (last[0])
10944                 {
10945                 case 'M':
10946                   if (ins->modrm.mod != 3)
10947                     break;
10948                 /* Fall through.  */
10949                 case 'X':
10950                   if (!ins->vex.evex || ins->vex.b || ins->vex.ll >= 2
10951                       || (ins->rex2 & 7)
10952                       || (ins->modrm.mod == 3 && (ins->rex & REX_X))
10953                       || !ins->vex.v || ins->vex.mask_register_specifier)
10954                     break;
10955                   /* AVX512 extends a number of V*D insns to also have V*Q variants,
10956                      merely distinguished by EVEX.W.  Look for a use of the
10957                      respective macro.  */
10958                   if (ins->vex.w)
10959                     {
10960                       const char *pct = strchr (p + 1, '%');
10961
10962                       if (pct != NULL && pct[1] == 'D' && pct[2] == 'Q')
10963                         break;
10964                     }
10965                   *ins->obufp++ = '{';
10966                   *ins->obufp++ = 'e';
10967                   *ins->obufp++ = 'v';
10968                   *ins->obufp++ = 'e';
10969                   *ins->obufp++ = 'x';
10970                   *ins->obufp++ = '}';
10971                   *ins->obufp++ = ' ';
10972                   break;
10973                 case 'N':
10974                   /* Skip printing {evex} for some special instructions in MAP4.  */
10975                   evex_printed = true;
10976                   break;
10977                 default:
10978                   abort ();
10979                 }
10980                 break;
10981             }
10982           /* For jcxz/jecxz */
10983           if (ins->address_mode == mode_64bit)
10984             {
10985               if (sizeflag & AFLAG)
10986                 *ins->obufp++ = 'r';
10987               else
10988                 *ins->obufp++ = 'e';
10989             }
10990           else
10991             if (sizeflag & AFLAG)
10992               *ins->obufp++ = 'e';
10993           ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
10994           break;
10995         case 'F':
10996           if (l == 0)
10997             {
10998               if (ins->intel_syntax)
10999                 break;
11000               if ((ins->prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
11001                 {
11002                   if (sizeflag & AFLAG)
11003                     *ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l';
11004                   else
11005                     *ins->obufp++ = ins->address_mode == mode_64bit ? 'l' : 'w';
11006                   ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
11007                 }
11008             }
11009           else if (l == 1 && last[0] == 'C')
11010             {
11011               if (ins->vex.nd && !ins->vex.nf)
11012                 break;
11013               *ins->obufp++ = 'c';
11014               *ins->obufp++ = 'f';
11015               /* Skip printing {evex} */
11016               evex_printed = true;
11017             }
11018           else if (l == 1 && last[0] == 'N')
11019             {
11020               if (ins->vex.nf)
11021                 {
11022                   oappend (ins, "{nf} ");
11023                   /* This bit needs to be cleared after it is consumed.  */
11024                   ins->vex.nf = false;
11025                   evex_printed = true;
11026                 }
11027               else if (ins->evex_type == evex_from_vex && !(ins->rex2 & 7)
11028                        && ins->vex.v)
11029                 {
11030                   oappend (ins, "{evex} ");
11031                   evex_printed = true;
11032                 }
11033             }
11034           else if (l == 1 && last[0] == 'D')
11035             {
11036               /* Get oszc flags value from register_specifier.  */
11037               int oszc_value = ~ins->vex.register_specifier & 0xf;
11038
11039               /* Add {dfv=of, sf, zf, cf} flags.  */
11040               oappend (ins, oszc_flags[oszc_value]);
11041
11042               /* These bits have been consumed and should be cleared.  */
11043               ins->vex.register_specifier = 0;
11044             }
11045           else
11046             abort ();
11047           break;
11048         case 'G':
11049           if (ins->intel_syntax || (ins->obufp[-1] != 's'
11050                                     && !(sizeflag & SUFFIX_ALWAYS)))
11051             break;
11052           if ((ins->rex & REX_W) || (sizeflag & DFLAG))
11053             *ins->obufp++ = 'l';
11054           else
11055             *ins->obufp++ = 'w';
11056           if (!(ins->rex & REX_W))
11057             ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11058           break;
11059         case 'H':
11060           if (l == 0)
11061             {
11062               if (ins->intel_syntax)
11063                 break;
11064               if ((ins->prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
11065                   || (ins->prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
11066                 {
11067                   ins->used_prefixes |= ins->prefixes & (PREFIX_CS | PREFIX_DS);
11068                   *ins->obufp++ = ',';
11069                   *ins->obufp++ = 'p';
11070
11071                   /* Set active_seg_prefix even if not set in 64-bit mode
11072                      because here it is a valid branch hint. */
11073                   if (ins->prefixes & PREFIX_DS)
11074                     {
11075                       ins->active_seg_prefix = PREFIX_DS;
11076                       *ins->obufp++ = 't';
11077                     }
11078                   else
11079                     {
11080                       ins->active_seg_prefix = PREFIX_CS;
11081                       *ins->obufp++ = 'n';
11082                     }
11083                 }
11084             }
11085           else if (l == 1 && last[0] == 'X')
11086             {
11087               if (!ins->vex.w)
11088                 *ins->obufp++ = 'h';
11089               else
11090                 oappend (ins, "{bad}");
11091             }
11092           else
11093             abort ();
11094           break;
11095         case 'K':
11096           USED_REX (REX_W);
11097           if (ins->rex & REX_W)
11098             *ins->obufp++ = 'q';
11099           else
11100             *ins->obufp++ = 'd';
11101           break;
11102         case 'L':
11103           if (ins->intel_syntax)
11104             break;
11105           if (sizeflag & SUFFIX_ALWAYS)
11106             {
11107               if (ins->rex & REX_W)
11108                 *ins->obufp++ = 'q';
11109               else
11110                 *ins->obufp++ = 'l';
11111             }
11112           break;
11113         case 'M':
11114           if (ins->intel_mnemonic != cond)
11115             *ins->obufp++ = 'r';
11116           break;
11117         case 'N':
11118           if ((ins->prefixes & PREFIX_FWAIT) == 0)
11119             *ins->obufp++ = 'n';
11120           else
11121             ins->used_prefixes |= PREFIX_FWAIT;
11122           break;
11123         case 'O':
11124           USED_REX (REX_W);
11125           if (ins->rex & REX_W)
11126             *ins->obufp++ = 'o';
11127           else if (ins->intel_syntax && (sizeflag & DFLAG))
11128             *ins->obufp++ = 'q';
11129           else
11130             *ins->obufp++ = 'd';
11131           if (!(ins->rex & REX_W))
11132             ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11133           break;
11134         case '@':
11135           if (ins->address_mode == mode_64bit
11136               && (ins->isa64 == intel64 || (ins->rex & REX_W)
11137                   || !(ins->prefixes & PREFIX_DATA)))
11138             {
11139               if (sizeflag & SUFFIX_ALWAYS)
11140                 *ins->obufp++ = 'q';
11141               break;
11142             }
11143           /* Fall through.  */
11144         case 'P':
11145           if (l == 0)
11146             {
11147               if (!cond && ins->last_rex2_prefix >= 0 && (ins->rex & REX_W))
11148                 {
11149                   /* For pushp and popp, p is printed and do not print {rex2}
11150                      for them.  */
11151                   *ins->obufp++ = 'p';
11152                   ins->rex2 |= REX2_SPECIAL;
11153                   break;
11154                 }
11155
11156               /* For "!P" print nothing else in Intel syntax.  */
11157               if (!cond && ins->intel_syntax)
11158                 break;
11159
11160               if ((ins->modrm.mod == 3 || !cond)
11161                   && !(sizeflag & SUFFIX_ALWAYS))
11162                 break;
11163           /* Fall through.  */
11164         case 'T':
11165               if ((!(ins->rex & REX_W) && (ins->prefixes & PREFIX_DATA))
11166                   || ((sizeflag & SUFFIX_ALWAYS)
11167                       && ins->address_mode != mode_64bit))
11168                 {
11169                   *ins->obufp++ = (sizeflag & DFLAG)
11170                                   ? ins->intel_syntax ? 'd' : 'l' : 'w';
11171                   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11172                 }
11173               else if (sizeflag & SUFFIX_ALWAYS)
11174                 *ins->obufp++ = 'q';
11175             }
11176           else if (l == 1 && last[0] == 'L')
11177             {
11178               if ((ins->prefixes & PREFIX_DATA)
11179                   || (ins->rex & REX_W)
11180                   || (sizeflag & SUFFIX_ALWAYS))
11181                 {
11182                   USED_REX (REX_W);
11183                   if (ins->rex & REX_W)
11184                     *ins->obufp++ = 'q';
11185                   else
11186                     {
11187                       if (sizeflag & DFLAG)
11188                         *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
11189                       else
11190                         *ins->obufp++ = 'w';
11191                       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11192                     }
11193                 }
11194             }
11195           else
11196             abort ();
11197           break;
11198         case 'Q':
11199           if (l == 0)
11200             {
11201               if (ins->intel_syntax && !alt)
11202                 break;
11203               USED_REX (REX_W);
11204               if ((ins->need_modrm && ins->modrm.mod != 3 && !ins->vex.nd)
11205                   || (sizeflag & SUFFIX_ALWAYS))
11206                 {
11207                   if (ins->rex & REX_W)
11208                     *ins->obufp++ = 'q';
11209                   else
11210                     {
11211                       if (sizeflag & DFLAG)
11212                         *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
11213                       else
11214                         *ins->obufp++ = 'w';
11215                       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11216                     }
11217                 }
11218             }
11219           else if (l == 1 && last[0] == 'D')
11220             *ins->obufp++ = ins->vex.w ? 'q' : 'd';
11221           else if (l == 1 && last[0] == 'L')
11222             {
11223               if (cond ? ins->modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)
11224                        : ins->address_mode != mode_64bit)
11225                 break;
11226               if ((ins->rex & REX_W))
11227                 {
11228                   USED_REX (REX_W);
11229                   *ins->obufp++ = 'q';
11230                 }
11231               else if ((ins->address_mode == mode_64bit && cond)
11232                       || (sizeflag & SUFFIX_ALWAYS))
11233                 *ins->obufp++ = ins->intel_syntax? 'd' : 'l';
11234             }
11235           else
11236             abort ();
11237           break;
11238         case 'R':
11239           USED_REX (REX_W);
11240           if (ins->rex & REX_W)
11241             *ins->obufp++ = 'q';
11242           else if (sizeflag & DFLAG)
11243             {
11244               if (ins->intel_syntax)
11245                   *ins->obufp++ = 'd';
11246               else
11247                   *ins->obufp++ = 'l';
11248             }
11249           else
11250             *ins->obufp++ = 'w';
11251           if (ins->intel_syntax && !p[1]
11252               && ((ins->rex & REX_W) || (sizeflag & DFLAG)))
11253             *ins->obufp++ = 'e';
11254           if (!(ins->rex & REX_W))
11255             ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11256           break;
11257         case 'S':
11258           if (l == 0)
11259             {
11260             case_S:
11261               if (ins->intel_syntax)
11262                 break;
11263               if (sizeflag & SUFFIX_ALWAYS)
11264                 {
11265                   if (ins->rex & REX_W)
11266                     *ins->obufp++ = 'q';
11267                   else
11268                     {
11269                       if (sizeflag & DFLAG)
11270                         *ins->obufp++ = 'l';
11271                       else
11272                         *ins->obufp++ = 'w';
11273                       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11274                     }
11275                 }
11276               break;
11277             }
11278           if (l != 1)
11279             abort ();
11280           switch (last[0])
11281             {
11282             case 'L':
11283               if (ins->address_mode == mode_64bit
11284                   && !(ins->prefixes & PREFIX_ADDR))
11285                 {
11286                   *ins->obufp++ = 'a';
11287                   *ins->obufp++ = 'b';
11288                   *ins->obufp++ = 's';
11289                 }
11290
11291               goto case_S;
11292             case 'X':
11293               if (!ins->vex.evex || !ins->vex.w)
11294                 *ins->obufp++ = 's';
11295               else
11296                 oappend (ins, "{bad}");
11297               break;
11298             default:
11299               abort ();
11300             }
11301           break;
11302         case 'U':
11303           if (l == 1 && (last[0] == 'Z'))
11304             {
11305               /* Although IMUL/SETcc does not support NDD, the EVEX.ND bit is
11306                  used to control whether its destination register has its upper
11307                  bits zeroed.  */
11308               if (ins->vex.nd)
11309                 oappend (ins, "zu");
11310             }
11311           else
11312             abort ();
11313           break;
11314         case 'V':
11315           if (l == 0)
11316             {
11317               if (ins->need_vex)
11318                 *ins->obufp++ = 'v';
11319             }
11320           else if (l == 1)
11321             {
11322               switch (last[0])
11323                 {
11324                 case 'X':
11325                   if (ins->vex.evex)
11326                     break;
11327                   *ins->obufp++ = '{';
11328                   *ins->obufp++ = 'v';
11329                   *ins->obufp++ = 'e';
11330                   *ins->obufp++ = 'x';
11331                   *ins->obufp++ = '}';
11332                   *ins->obufp++ = ' ';
11333                   break;
11334                 case 'L':
11335                   if (ins->rex & REX_W)
11336                     {
11337                       *ins->obufp++ = 'a';
11338                       *ins->obufp++ = 'b';
11339                       *ins->obufp++ = 's';
11340                     }
11341                   goto case_S;
11342                 default:
11343                   abort ();
11344                 }
11345             }
11346           else
11347             abort ();
11348           break;
11349         case 'W':
11350           if (l == 0)
11351             {
11352               /* operand size flag for cwtl, cbtw */
11353               USED_REX (REX_W);
11354               if (ins->rex & REX_W)
11355                 {
11356                   if (ins->intel_syntax)
11357                     *ins->obufp++ = 'd';
11358                   else
11359                     *ins->obufp++ = 'l';
11360                 }
11361               else if (sizeflag & DFLAG)
11362                 *ins->obufp++ = 'w';
11363               else
11364                 *ins->obufp++ = 'b';
11365               if (!(ins->rex & REX_W))
11366                 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11367             }
11368           else if (l == 1)
11369             {
11370               if (!ins->need_vex)
11371                 abort ();
11372               if (last[0] == 'X')
11373                 *ins->obufp++ = ins->vex.w ? 'd': 's';
11374               else if (last[0] == 'B')
11375                 *ins->obufp++ = ins->vex.w ? 'w': 'b';
11376               else
11377                 abort ();
11378             }
11379           else
11380             abort ();
11381           break;
11382         case 'X':
11383           if (l != 0)
11384             abort ();
11385           if (ins->need_vex
11386               ? ins->vex.prefix == DATA_PREFIX_OPCODE
11387               : ins->prefixes & PREFIX_DATA)
11388             {
11389               *ins->obufp++ = 'd';
11390               ins->used_prefixes |= PREFIX_DATA;
11391             }
11392           else
11393             *ins->obufp++ = 's';
11394           break;
11395         case 'Y':
11396           if (l == 0)
11397             {
11398               if (ins->vex.mask_register_specifier)
11399                 ins->illegal_masking = true;
11400             }
11401           else if (l == 1 && last[0] == 'X')
11402             {
11403               if (!ins->need_vex)
11404                 break;
11405               if (ins->intel_syntax
11406                   || ((ins->modrm.mod == 3 || ins->vex.b)
11407                       && !(sizeflag & SUFFIX_ALWAYS)))
11408                 break;
11409               switch (ins->vex.length)
11410                 {
11411                 case 128:
11412                   *ins->obufp++ = 'x';
11413                   break;
11414                 case 256:
11415                   *ins->obufp++ = 'y';
11416                   break;
11417                 case 512:
11418                   if (!ins->vex.evex)
11419                 default:
11420                     abort ();
11421                 }
11422             }
11423           else
11424             abort ();
11425           break;
11426         case 'Z':
11427           if (l == 0)
11428             {
11429               /* These insns ignore ModR/M.mod: Force it to 3 for OP_E().  */
11430               ins->modrm.mod = 3;
11431               if (!ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
11432                 *ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l';
11433             }
11434           else if (l == 1 && last[0] == 'X')
11435             {
11436               if (!ins->vex.evex)
11437                 abort ();
11438               if (ins->intel_syntax
11439                   || ((ins->modrm.mod == 3 || ins->vex.b)
11440                       && !(sizeflag & SUFFIX_ALWAYS)))
11441                 break;
11442               switch (ins->vex.length)
11443                 {
11444                 case 128:
11445                   *ins->obufp++ = 'x';
11446                   break;
11447                 case 256:
11448                   *ins->obufp++ = 'y';
11449                   break;
11450                 case 512:
11451                   *ins->obufp++ = 'z';
11452                   break;
11453                 default:
11454                   abort ();
11455                 }
11456             }
11457           else
11458             abort ();
11459           break;
11460         case '^':
11461           if (ins->intel_syntax)
11462             break;
11463           if (ins->isa64 == intel64 && (ins->rex & REX_W))
11464             {
11465               USED_REX (REX_W);
11466               *ins->obufp++ = 'q';
11467               break;
11468             }
11469           if ((ins->prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
11470             {
11471               if (sizeflag & DFLAG)
11472                 *ins->obufp++ = 'l';
11473               else
11474                 *ins->obufp++ = 'w';
11475               ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11476             }
11477           break;
11478         }
11479
11480       if (len == l)
11481         len = l = 0;
11482     }
11483   *ins->obufp = 0;
11484   ins->mnemonicendp = ins->obufp;
11485   return 0;
11486 }
11487
11488 /* Add a style marker to *INS->obufp that encodes STYLE.  This assumes that
11489    the buffer pointed to by INS->obufp has space.  A style marker is made
11490    from the STYLE_MARKER_CHAR followed by STYLE converted to a single hex
11491    digit, followed by another STYLE_MARKER_CHAR.  This function assumes
11492    that the number of styles is not greater than 16.  */
11493
11494 static void
11495 oappend_insert_style (instr_info *ins, enum disassembler_style style)
11496 {
11497   unsigned num = (unsigned) style;
11498
11499   /* We currently assume that STYLE can be encoded as a single hex
11500      character.  If more styles are added then this might start to fail,
11501      and we'll need to expand this code.  */
11502   if (num > 0xf)
11503     abort ();
11504
11505   *ins->obufp++ = STYLE_MARKER_CHAR;
11506   *ins->obufp++ = (num < 10 ? ('0' + num)
11507                    : ((num < 16) ? ('a' + (num - 10)) : '0'));
11508   *ins->obufp++ = STYLE_MARKER_CHAR;
11509
11510   /* This final null character is not strictly necessary, after inserting a
11511      style marker we should always be inserting some additional content.
11512      However, having the buffer null terminated doesn't cost much, and make
11513      it easier to debug what's going on.  Also, if we do ever forget to add
11514      any additional content after this style marker, then the buffer will
11515      still be well formed.  */
11516   *ins->obufp = '\0';
11517 }
11518
11519 static void
11520 oappend_with_style (instr_info *ins, const char *s,
11521                     enum disassembler_style style)
11522 {
11523   oappend_insert_style (ins, style);
11524   ins->obufp = stpcpy (ins->obufp, s);
11525 }
11526
11527 /* Add a single character C to the buffer pointer to by INS->obufp, marking
11528    the style for the character as STYLE.  */
11529
11530 static void
11531 oappend_char_with_style (instr_info *ins, const char c,
11532                          enum disassembler_style style)
11533 {
11534   oappend_insert_style (ins, style);
11535   *ins->obufp++ = c;
11536   *ins->obufp = '\0';
11537 }
11538
11539 /* Like oappend_char_with_style, but always uses dis_style_text.  */
11540
11541 static void
11542 oappend_char (instr_info *ins, const char c)
11543 {
11544   oappend_char_with_style (ins, c, dis_style_text);
11545 }
11546
11547 static void
11548 append_seg (instr_info *ins)
11549 {
11550   /* Only print the active segment register.  */
11551   if (!ins->active_seg_prefix)
11552     return;
11553
11554   ins->used_prefixes |= ins->active_seg_prefix;
11555   switch (ins->active_seg_prefix)
11556     {
11557     case PREFIX_CS:
11558       oappend_register (ins, att_names_seg[1]);
11559       break;
11560     case PREFIX_DS:
11561       oappend_register (ins, att_names_seg[3]);
11562       break;
11563     case PREFIX_SS:
11564       oappend_register (ins, att_names_seg[2]);
11565       break;
11566     case PREFIX_ES:
11567       oappend_register (ins, att_names_seg[0]);
11568       break;
11569     case PREFIX_FS:
11570       oappend_register (ins, att_names_seg[4]);
11571       break;
11572     case PREFIX_GS:
11573       oappend_register (ins, att_names_seg[5]);
11574       break;
11575     default:
11576       break;
11577     }
11578   oappend_char (ins, ':');
11579 }
11580
11581 static void
11582 print_operand_value (instr_info *ins, bfd_vma disp,
11583                      enum disassembler_style style)
11584 {
11585   char tmp[30];
11586
11587   if (ins->address_mode != mode_64bit)
11588     disp &= 0xffffffff;
11589   sprintf (tmp, "0x%" PRIx64, (uint64_t) disp);
11590   oappend_with_style (ins, tmp, style);
11591 }
11592
11593 /* Like oappend, but called for immediate operands.  */
11594
11595 static void
11596 oappend_immediate (instr_info *ins, bfd_vma imm)
11597 {
11598   if (!ins->intel_syntax)
11599     oappend_char_with_style (ins, '$', dis_style_immediate);
11600   print_operand_value (ins, imm, dis_style_immediate);
11601 }
11602
11603 /* Put DISP in BUF as signed hex number.  */
11604
11605 static void
11606 print_displacement (instr_info *ins, bfd_signed_vma val)
11607 {
11608   char tmp[30];
11609
11610   if (val < 0)
11611     {
11612       oappend_char_with_style (ins, '-', dis_style_address_offset);
11613       val = (bfd_vma) 0 - val;
11614
11615       /* Check for possible overflow.  */
11616       if (val < 0)
11617         {
11618           switch (ins->address_mode)
11619             {
11620             case mode_64bit:
11621               oappend_with_style (ins, "0x8000000000000000",
11622                                   dis_style_address_offset);
11623               break;
11624             case mode_32bit:
11625               oappend_with_style (ins, "0x80000000",
11626                                   dis_style_address_offset);
11627               break;
11628             case mode_16bit:
11629               oappend_with_style (ins, "0x8000",
11630                                   dis_style_address_offset);
11631               break;
11632             }
11633           return;
11634         }
11635     }
11636
11637   sprintf (tmp, "0x%" PRIx64, (int64_t) val);
11638   oappend_with_style (ins, tmp, dis_style_address_offset);
11639 }
11640
11641 static void
11642 intel_operand_size (instr_info *ins, int bytemode, int sizeflag)
11643 {
11644   /* Check if there is a broadcast, when evex.b is not treated as evex.nd.  */
11645   if (ins->vex.b && ins->evex_type == evex_default)
11646     {
11647       if (!ins->vex.no_broadcast)
11648         switch (bytemode)
11649           {
11650           case x_mode:
11651           case evex_half_bcst_xmmq_mode:
11652             if (ins->vex.w)
11653               oappend (ins, "QWORD BCST ");
11654             else
11655               oappend (ins, "DWORD BCST ");
11656             break;
11657           case xh_mode:
11658           case evex_half_bcst_xmmqh_mode:
11659           case evex_half_bcst_xmmqdh_mode:
11660             oappend (ins, "WORD BCST ");
11661             break;
11662           default:
11663             ins->vex.no_broadcast = true;
11664             break;
11665           }
11666       return;
11667     }
11668   switch (bytemode)
11669     {
11670     case b_mode:
11671     case b_swap_mode:
11672     case db_mode:
11673       oappend (ins, "BYTE PTR ");
11674       break;
11675     case w_mode:
11676     case w_swap_mode:
11677     case dw_mode:
11678       oappend (ins, "WORD PTR ");
11679       break;
11680     case indir_v_mode:
11681       if (ins->address_mode == mode_64bit && ins->isa64 == intel64)
11682         {
11683           oappend (ins, "QWORD PTR ");
11684           break;
11685         }
11686       /* Fall through.  */
11687     case stack_v_mode:
11688       if (ins->address_mode == mode_64bit && ((sizeflag & DFLAG)
11689                                               || (ins->rex & REX_W)))
11690         {
11691           oappend (ins, "QWORD PTR ");
11692           break;
11693         }
11694       /* Fall through.  */
11695     case v_mode:
11696     case v_swap_mode:
11697     case dq_mode:
11698       USED_REX (REX_W);
11699       if (ins->rex & REX_W)
11700         oappend (ins, "QWORD PTR ");
11701       else if (bytemode == dq_mode)
11702         oappend (ins, "DWORD PTR ");
11703       else
11704         {
11705           if (sizeflag & DFLAG)
11706             oappend (ins, "DWORD PTR ");
11707           else
11708             oappend (ins, "WORD PTR ");
11709           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11710         }
11711       break;
11712     case z_mode:
11713       if ((ins->rex & REX_W) || (sizeflag & DFLAG))
11714         *ins->obufp++ = 'D';
11715       oappend (ins, "WORD PTR ");
11716       if (!(ins->rex & REX_W))
11717         ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11718       break;
11719     case a_mode:
11720       if (sizeflag & DFLAG)
11721         oappend (ins, "QWORD PTR ");
11722       else
11723         oappend (ins, "DWORD PTR ");
11724       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11725       break;
11726     case movsxd_mode:
11727       if (!(sizeflag & DFLAG) && ins->isa64 == intel64)
11728         oappend (ins, "WORD PTR ");
11729       else
11730         oappend (ins, "DWORD PTR ");
11731       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11732       break;
11733     case d_mode:
11734     case d_swap_mode:
11735       oappend (ins, "DWORD PTR ");
11736       break;
11737     case q_mode:
11738     case q_swap_mode:
11739       oappend (ins, "QWORD PTR ");
11740       break;
11741     case m_mode:
11742       if (ins->address_mode == mode_64bit)
11743         oappend (ins, "QWORD PTR ");
11744       else
11745         oappend (ins, "DWORD PTR ");
11746       break;
11747     case f_mode:
11748       if (sizeflag & DFLAG)
11749         oappend (ins, "FWORD PTR ");
11750       else
11751         oappend (ins, "DWORD PTR ");
11752       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11753       break;
11754     case t_mode:
11755       oappend (ins, "TBYTE PTR ");
11756       break;
11757     case x_mode:
11758     case xh_mode:
11759     case x_swap_mode:
11760     case evex_x_gscat_mode:
11761     case evex_x_nobcst_mode:
11762     case bw_unit_mode:
11763       if (ins->need_vex)
11764         {
11765           switch (ins->vex.length)
11766             {
11767             case 128:
11768               oappend (ins, "XMMWORD PTR ");
11769               break;
11770             case 256:
11771               oappend (ins, "YMMWORD PTR ");
11772               break;
11773             case 512:
11774               oappend (ins, "ZMMWORD PTR ");
11775               break;
11776             default:
11777               abort ();
11778             }
11779         }
11780       else
11781         oappend (ins, "XMMWORD PTR ");
11782       break;
11783     case xmm_mode:
11784       oappend (ins, "XMMWORD PTR ");
11785       break;
11786     case ymm_mode:
11787       oappend (ins, "YMMWORD PTR ");
11788       break;
11789     case xmmq_mode:
11790     case evex_half_bcst_xmmqh_mode:
11791     case evex_half_bcst_xmmq_mode:
11792       switch (ins->vex.length)
11793         {
11794         case 0:
11795         case 128:
11796           oappend (ins, "QWORD PTR ");
11797           break;
11798         case 256:
11799           oappend (ins, "XMMWORD PTR ");
11800           break;
11801         case 512:
11802           oappend (ins, "YMMWORD PTR ");
11803           break;
11804         default:
11805           abort ();
11806         }
11807       break;
11808     case xmmdw_mode:
11809       if (!ins->need_vex)
11810         abort ();
11811
11812       switch (ins->vex.length)
11813         {
11814         case 128:
11815           oappend (ins, "WORD PTR ");
11816           break;
11817         case 256:
11818           oappend (ins, "DWORD PTR ");
11819           break;
11820         case 512:
11821           oappend (ins, "QWORD PTR ");
11822           break;
11823         default:
11824           abort ();
11825         }
11826       break;
11827     case xmmqd_mode:
11828     case evex_half_bcst_xmmqdh_mode:
11829       if (!ins->need_vex)
11830         abort ();
11831
11832       switch (ins->vex.length)
11833         {
11834         case 128:
11835           oappend (ins, "DWORD PTR ");
11836           break;
11837         case 256:
11838           oappend (ins, "QWORD PTR ");
11839           break;
11840         case 512:
11841           oappend (ins, "XMMWORD PTR ");
11842           break;
11843         default:
11844           abort ();
11845         }
11846       break;
11847     case ymmq_mode:
11848       if (!ins->need_vex)
11849         abort ();
11850
11851       switch (ins->vex.length)
11852         {
11853         case 128:
11854           oappend (ins, "QWORD PTR ");
11855           break;
11856         case 256:
11857           oappend (ins, "YMMWORD PTR ");
11858           break;
11859         case 512:
11860           oappend (ins, "ZMMWORD PTR ");
11861           break;
11862         default:
11863           abort ();
11864         }
11865       break;
11866     case o_mode:
11867       oappend (ins, "OWORD PTR ");
11868       break;
11869     case vex_vsib_d_w_dq_mode:
11870     case vex_vsib_q_w_dq_mode:
11871       if (!ins->need_vex)
11872         abort ();
11873       if (ins->vex.w)
11874         oappend (ins, "QWORD PTR ");
11875       else
11876         oappend (ins, "DWORD PTR ");
11877       break;
11878     case mask_bd_mode:
11879       if (!ins->need_vex || ins->vex.length != 128)
11880         abort ();
11881       if (ins->vex.w)
11882         oappend (ins, "DWORD PTR ");
11883       else
11884         oappend (ins, "BYTE PTR ");
11885       break;
11886     case mask_mode:
11887       if (!ins->need_vex)
11888         abort ();
11889       if (ins->vex.w)
11890         oappend (ins, "QWORD PTR ");
11891       else
11892         oappend (ins, "WORD PTR ");
11893       break;
11894     case v_bnd_mode:
11895     case v_bndmk_mode:
11896     default:
11897       break;
11898     }
11899 }
11900
11901 static void
11902 print_register (instr_info *ins, unsigned int reg, unsigned int rexmask,
11903                 int bytemode, int sizeflag)
11904 {
11905   const char (*names)[8];
11906
11907   /* Masking is invalid for insns with GPR destination. Set the flag uniformly,
11908      as the consumer will inspect it only for the destination operand.  */
11909   if (bytemode != mask_mode && ins->vex.mask_register_specifier)
11910     ins->illegal_masking = true;
11911
11912   USED_REX (rexmask);
11913   if (ins->rex & rexmask)
11914     reg += 8;
11915   if (ins->rex2 & rexmask)
11916     reg += 16;
11917
11918   switch (bytemode)
11919     {
11920     case b_mode:
11921     case b_swap_mode:
11922       if (reg & 4)
11923         USED_REX (0);
11924       if (ins->rex || ins->rex2)
11925         names = att_names8rex;
11926       else
11927         names = att_names8;
11928       break;
11929     case w_mode:
11930       names = att_names16;
11931       break;
11932     case d_mode:
11933     case dw_mode:
11934     case db_mode:
11935       names = att_names32;
11936       break;
11937     case q_mode:
11938       names = att_names64;
11939       break;
11940     case m_mode:
11941     case v_bnd_mode:
11942       names = ins->address_mode == mode_64bit ? att_names64 : att_names32;
11943       break;
11944     case bnd_mode:
11945     case bnd_swap_mode:
11946       if (reg > 0x3)
11947         {
11948           oappend (ins, "(bad)");
11949           return;
11950         }
11951       names = att_names_bnd;
11952       break;
11953     case indir_v_mode:
11954       if (ins->address_mode == mode_64bit && ins->isa64 == intel64)
11955         {
11956           names = att_names64;
11957           break;
11958         }
11959       /* Fall through.  */
11960     case stack_v_mode:
11961       if (ins->address_mode == mode_64bit && ((sizeflag & DFLAG)
11962                                               || (ins->rex & REX_W)))
11963         {
11964           names = att_names64;
11965           break;
11966         }
11967       bytemode = v_mode;
11968       /* Fall through.  */
11969     case v_mode:
11970     case v_swap_mode:
11971     case dq_mode:
11972       USED_REX (REX_W);
11973       if (ins->rex & REX_W)
11974         names = att_names64;
11975       else if (bytemode != v_mode && bytemode != v_swap_mode)
11976         names = att_names32;
11977       else
11978         {
11979           if (sizeflag & DFLAG)
11980             names = att_names32;
11981           else
11982             names = att_names16;
11983           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11984         }
11985       break;
11986     case movsxd_mode:
11987       if (!(sizeflag & DFLAG) && ins->isa64 == intel64)
11988         names = att_names16;
11989       else
11990         names = att_names32;
11991       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11992       break;
11993     case va_mode:
11994       names = (ins->address_mode == mode_64bit
11995                ? att_names64 : att_names32);
11996       if (!(ins->prefixes & PREFIX_ADDR))
11997         names = (ins->address_mode == mode_16bit
11998                      ? att_names16 : names);
11999       else
12000         {
12001           /* Remove "addr16/addr32".  */
12002           ins->all_prefixes[ins->last_addr_prefix] = 0;
12003           names = (ins->address_mode != mode_32bit
12004                        ? att_names32 : att_names16);
12005           ins->used_prefixes |= PREFIX_ADDR;
12006         }
12007       break;
12008     case mask_bd_mode:
12009     case mask_mode:
12010       if (reg > 0x7)
12011         {
12012           oappend (ins, "(bad)");
12013           return;
12014         }
12015       names = att_names_mask;
12016       break;
12017     case 0:
12018       return;
12019     default:
12020       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12021       return;
12022     }
12023   oappend_register (ins, names[reg]);
12024 }
12025
12026 static bool
12027 get8s (instr_info *ins, bfd_vma *res)
12028 {
12029   if (!fetch_code (ins->info, ins->codep + 1))
12030     return false;
12031   *res = ((bfd_vma) *ins->codep++ ^ 0x80) - 0x80;
12032   return true;
12033 }
12034
12035 static bool
12036 get16 (instr_info *ins, bfd_vma *res)
12037 {
12038   if (!fetch_code (ins->info, ins->codep + 2))
12039     return false;
12040   *res = *ins->codep++;
12041   *res |= (bfd_vma) *ins->codep++ << 8;
12042   return true;
12043 }
12044
12045 static bool
12046 get16s (instr_info *ins, bfd_vma *res)
12047 {
12048   if (!get16 (ins, res))
12049     return false;
12050   *res = (*res ^ 0x8000) - 0x8000;
12051   return true;
12052 }
12053
12054 static bool
12055 get32 (instr_info *ins, bfd_vma *res)
12056 {
12057   if (!fetch_code (ins->info, ins->codep + 4))
12058     return false;
12059   *res = *ins->codep++;
12060   *res |= (bfd_vma) *ins->codep++ << 8;
12061   *res |= (bfd_vma) *ins->codep++ << 16;
12062   *res |= (bfd_vma) *ins->codep++ << 24;
12063   return true;
12064 }
12065
12066 static bool
12067 get32s (instr_info *ins, bfd_vma *res)
12068 {
12069   if (!get32 (ins, res))
12070     return false;
12071
12072   *res = (*res ^ ((bfd_vma) 1 << 31)) - ((bfd_vma) 1 << 31);
12073
12074   return true;
12075 }
12076
12077 static bool
12078 get64 (instr_info *ins, uint64_t *res)
12079 {
12080   unsigned int a;
12081   unsigned int b;
12082
12083   if (!fetch_code (ins->info, ins->codep + 8))
12084     return false;
12085   a = *ins->codep++;
12086   a |= (unsigned int) *ins->codep++ << 8;
12087   a |= (unsigned int) *ins->codep++ << 16;
12088   a |= (unsigned int) *ins->codep++ << 24;
12089   b = *ins->codep++;
12090   b |= (unsigned int) *ins->codep++ << 8;
12091   b |= (unsigned int) *ins->codep++ << 16;
12092   b |= (unsigned int) *ins->codep++ << 24;
12093   *res = a + ((uint64_t) b << 32);
12094   return true;
12095 }
12096
12097 static void
12098 set_op (instr_info *ins, bfd_vma op, bool riprel)
12099 {
12100   ins->op_index[ins->op_ad] = ins->op_ad;
12101   if (ins->address_mode == mode_64bit)
12102     ins->op_address[ins->op_ad] = op;
12103   else /* Mask to get a 32-bit address.  */
12104     ins->op_address[ins->op_ad] = op & 0xffffffff;
12105   ins->op_riprel[ins->op_ad] = riprel;
12106 }
12107
12108 static bool
12109 BadOp (instr_info *ins)
12110 {
12111   /* Throw away prefixes and 1st. opcode byte.  */
12112   struct dis_private *priv = ins->info->private_data;
12113
12114   ins->codep = priv->the_buffer + ins->nr_prefixes + ins->need_vex + 1;
12115   ins->obufp = stpcpy (ins->obufp, "(bad)");
12116   return true;
12117 }
12118
12119 static bool
12120 OP_Skip_MODRM (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
12121                int sizeflag ATTRIBUTE_UNUSED)
12122 {
12123   if (ins->modrm.mod != 3)
12124     return BadOp (ins);
12125
12126   /* Skip mod/rm byte.  */
12127   MODRM_CHECK;
12128   ins->codep++;
12129   ins->has_skipped_modrm = true;
12130   return true;
12131 }
12132
12133 static bool
12134 OP_E_memory (instr_info *ins, int bytemode, int sizeflag)
12135 {
12136   int add = (ins->rex & REX_B) ? 8 : 0;
12137   int riprel = 0;
12138   int shift;
12139
12140   add += (ins->rex2 & REX_B) ? 16 : 0;
12141
12142   /* Handles EVEX other than APX EVEX-promoted instructions.  */
12143   if (ins->vex.evex && ins->evex_type == evex_default)
12144     {
12145
12146       /* Zeroing-masking is invalid for memory destinations. Set the flag
12147          uniformly, as the consumer will inspect it only for the destination
12148          operand.  */
12149       if (ins->vex.zeroing)
12150         ins->illegal_masking = true;
12151
12152       switch (bytemode)
12153         {
12154         case dw_mode:
12155         case w_mode:
12156         case w_swap_mode:
12157           shift = 1;
12158           break;
12159         case db_mode:
12160         case b_mode:
12161           shift = 0;
12162           break;
12163         case dq_mode:
12164           if (ins->address_mode != mode_64bit)
12165             {
12166         case d_mode:
12167         case d_swap_mode:
12168               shift = 2;
12169               break;
12170             }
12171             /* fall through */
12172         case vex_vsib_d_w_dq_mode:
12173         case vex_vsib_q_w_dq_mode:
12174         case evex_x_gscat_mode:
12175           shift = ins->vex.w ? 3 : 2;
12176           break;
12177         case xh_mode:
12178         case evex_half_bcst_xmmqh_mode:
12179         case evex_half_bcst_xmmqdh_mode:
12180           if (ins->vex.b)
12181             {
12182               shift = ins->vex.w ? 2 : 1;
12183               break;
12184             }
12185           /* Fall through.  */
12186         case x_mode:
12187         case evex_half_bcst_xmmq_mode:
12188           if (ins->vex.b)
12189             {
12190               shift = ins->vex.w ? 3 : 2;
12191               break;
12192             }
12193           /* Fall through.  */
12194         case xmmqd_mode:
12195         case xmmdw_mode:
12196         case xmmq_mode:
12197         case ymmq_mode:
12198         case evex_x_nobcst_mode:
12199         case x_swap_mode:
12200           switch (ins->vex.length)
12201             {
12202             case 128:
12203               shift = 4;
12204               break;
12205             case 256:
12206               shift = 5;
12207               break;
12208             case 512:
12209               shift = 6;
12210               break;
12211             default:
12212               abort ();
12213             }
12214           /* Make necessary corrections to shift for modes that need it.  */
12215           if (bytemode == xmmq_mode
12216               || bytemode == evex_half_bcst_xmmqh_mode
12217               || bytemode == evex_half_bcst_xmmq_mode
12218               || (bytemode == ymmq_mode && ins->vex.length == 128))
12219             shift -= 1;
12220           else if (bytemode == xmmqd_mode
12221                    || bytemode == evex_half_bcst_xmmqdh_mode)
12222             shift -= 2;
12223           else if (bytemode == xmmdw_mode)
12224             shift -= 3;
12225           break;
12226         case ymm_mode:
12227           shift = 5;
12228           break;
12229         case xmm_mode:
12230           shift = 4;
12231           break;
12232         case q_mode:
12233         case q_swap_mode:
12234           shift = 3;
12235           break;
12236         case bw_unit_mode:
12237           shift = ins->vex.w ? 1 : 0;
12238           break;
12239         default:
12240           abort ();
12241         }
12242     }
12243   else
12244     shift = 0;
12245
12246   USED_REX (REX_B);
12247   if (ins->intel_syntax)
12248     intel_operand_size (ins, bytemode, sizeflag);
12249   append_seg (ins);
12250
12251   if ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
12252     {
12253       /* 32/64 bit address mode */
12254       bfd_vma disp = 0;
12255       int havedisp;
12256       int havebase;
12257       int needindex;
12258       int needaddr32;
12259       int base, rbase;
12260       int vindex = 0;
12261       int scale = 0;
12262       int addr32flag = !((sizeflag & AFLAG)
12263                          || bytemode == v_bnd_mode
12264                          || bytemode == v_bndmk_mode
12265                          || bytemode == bnd_mode
12266                          || bytemode == bnd_swap_mode);
12267       bool check_gather = false;
12268       const char (*indexes)[8] = NULL;
12269
12270       havebase = 1;
12271       base = ins->modrm.rm;
12272
12273       if (base == 4)
12274         {
12275           vindex = ins->sib.index;
12276           USED_REX (REX_X);
12277           if (ins->rex & REX_X)
12278             vindex += 8;
12279           switch (bytemode)
12280             {
12281             case vex_vsib_d_w_dq_mode:
12282             case vex_vsib_q_w_dq_mode:
12283               if (!ins->need_vex)
12284                 abort ();
12285               if (ins->vex.evex)
12286                 {
12287                   /* S/G EVEX insns require EVEX.X4 not to be set.  */
12288                   if (ins->rex2 & REX_X)
12289                     {
12290                       oappend (ins, "(bad)");
12291                       return true;
12292                     }
12293
12294                   if (!ins->vex.v)
12295                     vindex += 16;
12296                   check_gather = ins->obufp == ins->op_out[1];
12297                 }
12298
12299               switch (ins->vex.length)
12300                 {
12301                 case 128:
12302                   indexes = att_names_xmm;
12303                   break;
12304                 case 256:
12305                   if (!ins->vex.w
12306                       || bytemode == vex_vsib_q_w_dq_mode)
12307                     indexes = att_names_ymm;
12308                   else
12309                     indexes = att_names_xmm;
12310                   break;
12311                 case 512:
12312                   if (!ins->vex.w
12313                       || bytemode == vex_vsib_q_w_dq_mode)
12314                     indexes = att_names_zmm;
12315                   else
12316                     indexes = att_names_ymm;
12317                   break;
12318                 default:
12319                   abort ();
12320                 }
12321               break;
12322             default:
12323               if (ins->rex2 & REX_X)
12324                 vindex += 16;
12325
12326               if (vindex != 4)
12327                 indexes = ins->address_mode == mode_64bit && !addr32flag
12328                           ? att_names64 : att_names32;
12329               break;
12330             }
12331           scale = ins->sib.scale;
12332           base = ins->sib.base;
12333           ins->codep++;
12334         }
12335       else
12336         {
12337           /* Check for mandatory SIB.  */
12338           if (bytemode == vex_vsib_d_w_dq_mode
12339               || bytemode == vex_vsib_q_w_dq_mode
12340               || bytemode == vex_sibmem_mode)
12341             {
12342               oappend (ins, "(bad)");
12343               return true;
12344             }
12345         }
12346       rbase = base + add;
12347
12348       switch (ins->modrm.mod)
12349         {
12350         case 0:
12351           if (base == 5)
12352             {
12353               havebase = 0;
12354               if (ins->address_mode == mode_64bit && !ins->has_sib)
12355                 riprel = 1;
12356               if (!get32s (ins, &disp))
12357                 return false;
12358               if (riprel && bytemode == v_bndmk_mode)
12359                 {
12360                   oappend (ins, "(bad)");
12361                   return true;
12362                 }
12363             }
12364           break;
12365         case 1:
12366           if (!get8s (ins, &disp))
12367             return false;
12368           if (ins->vex.evex && shift > 0)
12369             disp <<= shift;
12370           break;
12371         case 2:
12372           if (!get32s (ins, &disp))
12373             return false;
12374           break;
12375         }
12376
12377       needindex = 0;
12378       needaddr32 = 0;
12379       if (ins->has_sib
12380           && !havebase
12381           && !indexes
12382           && ins->address_mode != mode_16bit)
12383         {
12384           if (ins->address_mode == mode_64bit)
12385             {
12386               if (addr32flag)
12387                 {
12388                   /* Without base nor index registers, zero-extend the
12389                      lower 32-bit displacement to 64 bits.  */
12390                   disp &= 0xffffffff;
12391                   needindex = 1;
12392                 }
12393               needaddr32 = 1;
12394             }
12395           else
12396             {
12397               /* In 32-bit mode, we need index register to tell [offset]
12398                  from [eiz*1 + offset].  */
12399               needindex = 1;
12400             }
12401         }
12402
12403       havedisp = (havebase
12404                   || needindex
12405                   || (ins->has_sib && (indexes || scale != 0)));
12406
12407       if (!ins->intel_syntax)
12408         if (ins->modrm.mod != 0 || base == 5)
12409           {
12410             if (havedisp || riprel)
12411               print_displacement (ins, disp);
12412             else
12413               print_operand_value (ins, disp, dis_style_address_offset);
12414             if (riprel)
12415               {
12416                 set_op (ins, disp, true);
12417                 oappend_char (ins, '(');
12418                 oappend_with_style (ins, !addr32flag ? "%rip" : "%eip",
12419                                     dis_style_register);
12420                 oappend_char (ins, ')');
12421               }
12422           }
12423
12424       if ((havebase || indexes || needindex || needaddr32 || riprel)
12425           && (ins->address_mode != mode_64bit
12426               || ((bytemode != v_bnd_mode)
12427                   && (bytemode != v_bndmk_mode)
12428                   && (bytemode != bnd_mode)
12429                   && (bytemode != bnd_swap_mode))))
12430         ins->used_prefixes |= PREFIX_ADDR;
12431
12432       if (havedisp || (ins->intel_syntax && riprel))
12433         {
12434           oappend_char (ins, ins->open_char);
12435           if (ins->intel_syntax && riprel)
12436             {
12437               set_op (ins, disp, true);
12438               oappend_with_style (ins, !addr32flag ? "rip" : "eip",
12439                                   dis_style_register);
12440             }
12441           if (havebase)
12442             oappend_register
12443               (ins,
12444                (ins->address_mode == mode_64bit && !addr32flag
12445                 ? att_names64 : att_names32)[rbase]);
12446           if (ins->has_sib)
12447             {
12448               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
12449                  print index to tell base + index from base.  */
12450               if (scale != 0
12451                   || needindex
12452                   || indexes
12453                   || (havebase && base != ESP_REG_NUM))
12454                 {
12455                   if (!ins->intel_syntax || havebase)
12456                     oappend_char (ins, ins->separator_char);
12457                   if (indexes)
12458                     {
12459                       if (ins->address_mode == mode_64bit || vindex < 16)
12460                         oappend_register (ins, indexes[vindex]);
12461                       else
12462                         oappend (ins, "(bad)");
12463                     }
12464                   else
12465                     oappend_register (ins,
12466                                       ins->address_mode == mode_64bit
12467                                       && !addr32flag
12468                                       ? att_index64
12469                                       : att_index32);
12470
12471                   oappend_char (ins, ins->scale_char);
12472                   oappend_char_with_style (ins, '0' + (1 << scale),
12473                                            dis_style_immediate);
12474                 }
12475             }
12476           if (ins->intel_syntax
12477               && (disp || ins->modrm.mod != 0 || base == 5))
12478             {
12479               if (!havedisp || (bfd_signed_vma) disp >= 0)
12480                   oappend_char (ins, '+');
12481               if (havedisp)
12482                 print_displacement (ins, disp);
12483               else
12484                 print_operand_value (ins, disp, dis_style_address_offset);
12485             }
12486
12487           oappend_char (ins, ins->close_char);
12488
12489           if (check_gather)
12490             {
12491               /* Both XMM/YMM/ZMM registers must be distinct.  */
12492               int modrm_reg = ins->modrm.reg;
12493
12494               if (ins->rex & REX_R)
12495                 modrm_reg += 8;
12496               if (ins->rex2 & REX_R)
12497                 modrm_reg += 16;
12498               if (vindex == modrm_reg)
12499                 oappend (ins, "/(bad)");
12500             }
12501         }
12502       else if (ins->intel_syntax)
12503         {
12504           if (ins->modrm.mod != 0 || base == 5)
12505             {
12506               if (!ins->active_seg_prefix)
12507                 {
12508                   oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12509                   oappend (ins, ":");
12510                 }
12511               print_operand_value (ins, disp, dis_style_text);
12512             }
12513         }
12514     }
12515   else if (bytemode == v_bnd_mode
12516            || bytemode == v_bndmk_mode
12517            || bytemode == bnd_mode
12518            || bytemode == bnd_swap_mode
12519            || bytemode == vex_vsib_d_w_dq_mode
12520            || bytemode == vex_vsib_q_w_dq_mode)
12521     {
12522       oappend (ins, "(bad)");
12523       return true;
12524     }
12525   else
12526     {
12527       /* 16 bit address mode */
12528       bfd_vma disp = 0;
12529
12530       ins->used_prefixes |= ins->prefixes & PREFIX_ADDR;
12531       switch (ins->modrm.mod)
12532         {
12533         case 0:
12534           if (ins->modrm.rm == 6)
12535             {
12536         case 2:
12537               if (!get16s (ins, &disp))
12538                 return false;
12539             }
12540           break;
12541         case 1:
12542           if (!get8s (ins, &disp))
12543             return false;
12544           if (ins->vex.evex && shift > 0)
12545             disp <<= shift;
12546           break;
12547         }
12548
12549       if (!ins->intel_syntax)
12550         if (ins->modrm.mod != 0 || ins->modrm.rm == 6)
12551           print_displacement (ins, disp);
12552
12553       if (ins->modrm.mod != 0 || ins->modrm.rm != 6)
12554         {
12555           oappend_char (ins, ins->open_char);
12556           oappend (ins, ins->intel_syntax ? intel_index16[ins->modrm.rm]
12557                                           : att_index16[ins->modrm.rm]);
12558           if (ins->intel_syntax
12559               && (disp || ins->modrm.mod != 0 || ins->modrm.rm == 6))
12560             {
12561               if ((bfd_signed_vma) disp >= 0)
12562                 oappend_char (ins, '+');
12563               print_displacement (ins, disp);
12564             }
12565
12566           oappend_char (ins, ins->close_char);
12567         }
12568       else if (ins->intel_syntax)
12569         {
12570           if (!ins->active_seg_prefix)
12571             {
12572               oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12573               oappend (ins, ":");
12574             }
12575           print_operand_value (ins, disp & 0xffff, dis_style_text);
12576         }
12577     }
12578   if (ins->vex.b && ins->evex_type == evex_default)
12579     {
12580       ins->evex_used |= EVEX_b_used;
12581
12582       /* Broadcast can only ever be valid for memory sources.  */
12583       if (ins->obufp == ins->op_out[0])
12584         ins->vex.no_broadcast = true;
12585
12586       if (!ins->vex.no_broadcast
12587           && (!ins->intel_syntax || !(ins->evex_used & EVEX_len_used)))
12588         {
12589           if (bytemode == xh_mode)
12590             {
12591               switch (ins->vex.length)
12592                 {
12593                 case 128:
12594                   oappend (ins, "{1to8}");
12595                   break;
12596                 case 256:
12597                   oappend (ins, "{1to16}");
12598                   break;
12599                 case 512:
12600                   oappend (ins, "{1to32}");
12601                   break;
12602                 default:
12603                   abort ();
12604                 }
12605             }
12606           else if (bytemode == q_mode
12607                    || bytemode == ymmq_mode)
12608             ins->vex.no_broadcast = true;
12609           else if (ins->vex.w
12610                    || bytemode == evex_half_bcst_xmmqdh_mode
12611                    || bytemode == evex_half_bcst_xmmq_mode)
12612             {
12613               switch (ins->vex.length)
12614                 {
12615                 case 128:
12616                   oappend (ins, "{1to2}");
12617                   break;
12618                 case 256:
12619                   oappend (ins, "{1to4}");
12620                   break;
12621                 case 512:
12622                   oappend (ins, "{1to8}");
12623                   break;
12624                 default:
12625                   abort ();
12626                 }
12627             }
12628           else if (bytemode == x_mode
12629                    || bytemode == evex_half_bcst_xmmqh_mode)
12630             {
12631               switch (ins->vex.length)
12632                 {
12633                 case 128:
12634                   oappend (ins, "{1to4}");
12635                   break;
12636                 case 256:
12637                   oappend (ins, "{1to8}");
12638                   break;
12639                 case 512:
12640                   oappend (ins, "{1to16}");
12641                   break;
12642                 default:
12643                   abort ();
12644                 }
12645             }
12646           else
12647             ins->vex.no_broadcast = true;
12648         }
12649       if (ins->vex.no_broadcast)
12650         oappend (ins, "{bad}");
12651     }
12652
12653   return true;
12654 }
12655
12656 static bool
12657 OP_E (instr_info *ins, int bytemode, int sizeflag)
12658 {
12659   /* Skip mod/rm byte.  */
12660   MODRM_CHECK;
12661   if (!ins->has_skipped_modrm)
12662     {
12663       ins->codep++;
12664       ins->has_skipped_modrm = true;
12665     }
12666
12667   if (ins->modrm.mod == 3)
12668     {
12669       if ((sizeflag & SUFFIX_ALWAYS)
12670           && (bytemode == b_swap_mode
12671               || bytemode == bnd_swap_mode
12672               || bytemode == v_swap_mode))
12673         swap_operand (ins);
12674
12675       print_register (ins, ins->modrm.rm, REX_B, bytemode, sizeflag);
12676       return true;
12677     }
12678
12679   /* Masking is invalid for insns with GPR-like memory destination. Set the
12680      flag uniformly, as the consumer will inspect it only for the destination
12681      operand.  */
12682   if (ins->vex.mask_register_specifier)
12683     ins->illegal_masking = true;
12684
12685   return OP_E_memory (ins, bytemode, sizeflag);
12686 }
12687
12688 static bool
12689 OP_indirE (instr_info *ins, int bytemode, int sizeflag)
12690 {
12691   if (ins->modrm.mod == 3 && bytemode == f_mode)
12692     /* bad lcall/ljmp */
12693     return BadOp (ins);
12694   if (!ins->intel_syntax)
12695     oappend (ins, "*");
12696   return OP_E (ins, bytemode, sizeflag);
12697 }
12698
12699 static bool
12700 OP_G (instr_info *ins, int bytemode, int sizeflag)
12701 {
12702   print_register (ins, ins->modrm.reg, REX_R, bytemode, sizeflag);
12703   return true;
12704 }
12705
12706 static bool
12707 OP_REG (instr_info *ins, int code, int sizeflag)
12708 {
12709   const char *s;
12710   int add = 0;
12711
12712   switch (code)
12713     {
12714     case es_reg: case ss_reg: case cs_reg:
12715     case ds_reg: case fs_reg: case gs_reg:
12716       oappend_register (ins, att_names_seg[code - es_reg]);
12717       return true;
12718     }
12719
12720   USED_REX (REX_B);
12721   if (ins->rex & REX_B)
12722     add = 8;
12723   if (ins->rex2 & REX_B)
12724     add += 16;
12725
12726   switch (code)
12727     {
12728     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12729     case sp_reg: case bp_reg: case si_reg: case di_reg:
12730       s = att_names16[code - ax_reg + add];
12731       break;
12732     case ah_reg: case ch_reg: case dh_reg: case bh_reg:
12733       USED_REX (0);
12734       /* Fall through.  */
12735     case al_reg: case cl_reg: case dl_reg: case bl_reg:
12736       if (ins->rex)
12737         s = att_names8rex[code - al_reg + add];
12738       else
12739         s = att_names8[code - al_reg];
12740       break;
12741     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
12742     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
12743       if (ins->address_mode == mode_64bit
12744           && ((sizeflag & DFLAG) || (ins->rex & REX_W)))
12745         {
12746           s = att_names64[code - rAX_reg + add];
12747           break;
12748         }
12749       code += eAX_reg - rAX_reg;
12750       /* Fall through.  */
12751     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12752     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12753       USED_REX (REX_W);
12754       if (ins->rex & REX_W)
12755         s = att_names64[code - eAX_reg + add];
12756       else
12757         {
12758           if (sizeflag & DFLAG)
12759             s = att_names32[code - eAX_reg + add];
12760           else
12761             s = att_names16[code - eAX_reg + add];
12762           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12763         }
12764       break;
12765     default:
12766       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12767       return true;
12768     }
12769   oappend_register (ins, s);
12770   return true;
12771 }
12772
12773 static bool
12774 OP_IMREG (instr_info *ins, int code, int sizeflag)
12775 {
12776   const char *s;
12777
12778   switch (code)
12779     {
12780     case indir_dx_reg:
12781       if (!ins->intel_syntax)
12782         {
12783           oappend (ins, "(%dx)");
12784           return true;
12785         }
12786       s = att_names16[dx_reg - ax_reg];
12787       break;
12788     case al_reg: case cl_reg:
12789       s = att_names8[code - al_reg];
12790       break;
12791     case eAX_reg:
12792       USED_REX (REX_W);
12793       if (ins->rex & REX_W)
12794         {
12795           s = *att_names64;
12796           break;
12797         }
12798       /* Fall through.  */
12799     case z_mode_ax_reg:
12800       if ((ins->rex & REX_W) || (sizeflag & DFLAG))
12801         s = *att_names32;
12802       else
12803         s = *att_names16;
12804       if (!(ins->rex & REX_W))
12805         ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12806       break;
12807     default:
12808       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12809       return true;
12810     }
12811   oappend_register (ins, s);
12812   return true;
12813 }
12814
12815 static bool
12816 OP_I (instr_info *ins, int bytemode, int sizeflag)
12817 {
12818   bfd_vma op;
12819
12820   switch (bytemode)
12821     {
12822     case b_mode:
12823       if (!fetch_code (ins->info, ins->codep + 1))
12824         return false;
12825       op = *ins->codep++;
12826       break;
12827     case v_mode:
12828       USED_REX (REX_W);
12829       if (ins->rex & REX_W)
12830         {
12831           if (!get32s (ins, &op))
12832             return false;
12833         }
12834       else
12835         {
12836           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12837           if (sizeflag & DFLAG)
12838             {
12839     case d_mode:
12840               if (!get32 (ins, &op))
12841                 return false;
12842             }
12843           else
12844             {
12845               /* Fall through.  */
12846     case w_mode:
12847               if (!get16 (ins, &op))
12848                 return false;
12849             }
12850         }
12851       break;
12852     case const_1_mode:
12853       if (ins->intel_syntax)
12854         oappend_with_style (ins, "1", dis_style_immediate);
12855       else
12856         oappend_with_style (ins, "$1", dis_style_immediate);
12857       return true;
12858     default:
12859       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12860       return true;
12861     }
12862
12863   oappend_immediate (ins, op);
12864   return true;
12865 }
12866
12867 static bool
12868 OP_I64 (instr_info *ins, int bytemode, int sizeflag)
12869 {
12870   uint64_t op;
12871
12872   if (bytemode != v_mode || ins->address_mode != mode_64bit
12873       || !(ins->rex & REX_W))
12874     return OP_I (ins, bytemode, sizeflag);
12875
12876   USED_REX (REX_W);
12877
12878   if (!get64 (ins, &op))
12879     return false;
12880
12881   oappend_immediate (ins, op);
12882   return true;
12883 }
12884
12885 static bool
12886 OP_sI (instr_info *ins, int bytemode, int sizeflag)
12887 {
12888   bfd_vma op;
12889
12890   switch (bytemode)
12891     {
12892     case b_mode:
12893     case b_T_mode:
12894       if (!get8s (ins, &op))
12895         return false;
12896       if (bytemode == b_T_mode)
12897         {
12898           if (ins->address_mode != mode_64bit
12899               || !((sizeflag & DFLAG) || (ins->rex & REX_W)))
12900             {
12901               /* The operand-size prefix is overridden by a REX prefix.  */
12902               if ((sizeflag & DFLAG) || (ins->rex & REX_W))
12903                 op &= 0xffffffff;
12904               else
12905                 op &= 0xffff;
12906           }
12907         }
12908       else
12909         {
12910           if (!(ins->rex & REX_W))
12911             {
12912               if (sizeflag & DFLAG)
12913                 op &= 0xffffffff;
12914               else
12915                 op &= 0xffff;
12916             }
12917         }
12918       break;
12919     case v_mode:
12920       /* The operand-size prefix is overridden by a REX prefix.  */
12921       if (!(sizeflag & DFLAG) && !(ins->rex & REX_W))
12922         {
12923           if (!get16 (ins, &op))
12924             return false;
12925         }
12926       else if (!get32s (ins, &op))
12927         return false;
12928       break;
12929     default:
12930       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12931       return true;
12932     }
12933
12934   oappend_immediate (ins, op);
12935   return true;
12936 }
12937
12938 static bool
12939 OP_J (instr_info *ins, int bytemode, int sizeflag)
12940 {
12941   bfd_vma disp;
12942   bfd_vma mask = -1;
12943   bfd_vma segment = 0;
12944
12945   switch (bytemode)
12946     {
12947     case b_mode:
12948       if (!get8s (ins, &disp))
12949         return false;
12950       break;
12951     case v_mode:
12952     case dqw_mode:
12953       if ((sizeflag & DFLAG)
12954           || (ins->address_mode == mode_64bit
12955               && ((ins->isa64 == intel64 && bytemode != dqw_mode)
12956                   || (ins->rex & REX_W))))
12957         {
12958           if (!get32s (ins, &disp))
12959             return false;
12960         }
12961       else
12962         {
12963           if (!get16s (ins, &disp))
12964             return false;
12965           /* In 16bit mode, address is wrapped around at 64k within
12966              the same segment.  Otherwise, a data16 prefix on a jump
12967              instruction means that the pc is masked to 16 bits after
12968              the displacement is added!  */
12969           mask = 0xffff;
12970           if ((ins->prefixes & PREFIX_DATA) == 0)
12971             segment = ((ins->start_pc + (ins->codep - ins->start_codep))
12972                        & ~((bfd_vma) 0xffff));
12973         }
12974       if (ins->address_mode != mode_64bit
12975           || (ins->isa64 != intel64 && !(ins->rex & REX_W)))
12976         ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12977       break;
12978     default:
12979       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12980       return true;
12981     }
12982   disp = ((ins->start_pc + (ins->codep - ins->start_codep) + disp) & mask)
12983          | segment;
12984   set_op (ins, disp, false);
12985   print_operand_value (ins, disp, dis_style_text);
12986   return true;
12987 }
12988
12989 static bool
12990 OP_SEG (instr_info *ins, int bytemode, int sizeflag)
12991 {
12992   if (bytemode == w_mode)
12993     {
12994       oappend_register (ins, att_names_seg[ins->modrm.reg]);
12995       return true;
12996     }
12997   return OP_E (ins, ins->modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12998 }
12999
13000 static bool
13001 OP_DIR (instr_info *ins, int dummy ATTRIBUTE_UNUSED, int sizeflag)
13002 {
13003   bfd_vma seg, offset;
13004   int res;
13005   char scratch[24];
13006
13007   if (sizeflag & DFLAG)
13008     {
13009       if (!get32 (ins, &offset))
13010         return false;;
13011     }
13012   else if (!get16 (ins, &offset))
13013     return false;
13014   if (!get16 (ins, &seg))
13015     return false;;
13016   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13017
13018   res = snprintf (scratch, ARRAY_SIZE (scratch),
13019                   ins->intel_syntax ? "0x%x:0x%x" : "$0x%x,$0x%x",
13020                   (unsigned) seg, (unsigned) offset);
13021   if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
13022     abort ();
13023   oappend (ins, scratch);
13024   return true;
13025 }
13026
13027 static bool
13028 OP_OFF (instr_info *ins, int bytemode, int sizeflag)
13029 {
13030   bfd_vma off;
13031
13032   if (ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
13033     intel_operand_size (ins, bytemode, sizeflag);
13034   append_seg (ins);
13035
13036   if ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
13037     {
13038       if (!get32 (ins, &off))
13039         return false;
13040     }
13041   else
13042     {
13043       if (!get16 (ins, &off))
13044         return false;
13045     }
13046
13047   if (ins->intel_syntax)
13048     {
13049       if (!ins->active_seg_prefix)
13050         {
13051           oappend_register (ins, att_names_seg[ds_reg - es_reg]);
13052           oappend (ins, ":");
13053         }
13054     }
13055   print_operand_value (ins, off, dis_style_address_offset);
13056   return true;
13057 }
13058
13059 static bool
13060 OP_OFF64 (instr_info *ins, int bytemode, int sizeflag)
13061 {
13062   uint64_t off;
13063
13064   if (ins->address_mode != mode_64bit
13065       || (ins->prefixes & PREFIX_ADDR))
13066     return OP_OFF (ins, bytemode, sizeflag);
13067
13068   if (ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
13069     intel_operand_size (ins, bytemode, sizeflag);
13070   append_seg (ins);
13071
13072   if (!get64 (ins, &off))
13073     return false;
13074
13075   if (ins->intel_syntax)
13076     {
13077       if (!ins->active_seg_prefix)
13078         {
13079           oappend_register (ins, att_names_seg[ds_reg - es_reg]);
13080           oappend (ins, ":");
13081         }
13082     }
13083   print_operand_value (ins, off, dis_style_address_offset);
13084   return true;
13085 }
13086
13087 static void
13088 ptr_reg (instr_info *ins, int code, int sizeflag)
13089 {
13090   const char *s;
13091
13092   *ins->obufp++ = ins->open_char;
13093   ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
13094   if (ins->address_mode == mode_64bit)
13095     {
13096       if (!(sizeflag & AFLAG))
13097         s = att_names32[code - eAX_reg];
13098       else
13099         s = att_names64[code - eAX_reg];
13100     }
13101   else if (sizeflag & AFLAG)
13102     s = att_names32[code - eAX_reg];
13103   else
13104     s = att_names16[code - eAX_reg];
13105   oappend_register (ins, s);
13106   oappend_char (ins, ins->close_char);
13107 }
13108
13109 static bool
13110 OP_ESreg (instr_info *ins, int code, int sizeflag)
13111 {
13112   if (ins->intel_syntax)
13113     {
13114       switch (ins->codep[-1])
13115         {
13116         case 0x6d:      /* insw/insl */
13117           intel_operand_size (ins, z_mode, sizeflag);
13118           break;
13119         case 0xa5:      /* movsw/movsl/movsq */
13120         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
13121         case 0xab:      /* stosw/stosl */
13122         case 0xaf:      /* scasw/scasl */
13123           intel_operand_size (ins, v_mode, sizeflag);
13124           break;
13125         default:
13126           intel_operand_size (ins, b_mode, sizeflag);
13127         }
13128     }
13129   oappend_register (ins, att_names_seg[0]);
13130   oappend_char (ins, ':');
13131   ptr_reg (ins, code, sizeflag);
13132   return true;
13133 }
13134
13135 static bool
13136 OP_DSreg (instr_info *ins, int code, int sizeflag)
13137 {
13138   if (ins->intel_syntax)
13139     {
13140       switch (ins->codep[-1])
13141         {
13142         case 0x6f:      /* outsw/outsl */
13143           intel_operand_size (ins, z_mode, sizeflag);
13144           break;
13145         case 0xa5:      /* movsw/movsl/movsq */
13146         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
13147         case 0xad:      /* lodsw/lodsl/lodsq */
13148           intel_operand_size (ins, v_mode, sizeflag);
13149           break;
13150         default:
13151           intel_operand_size (ins, b_mode, sizeflag);
13152         }
13153     }
13154   /* Set ins->active_seg_prefix to PREFIX_DS if it is unset so that the
13155      default segment register DS is printed.  */
13156   if (!ins->active_seg_prefix)
13157     ins->active_seg_prefix = PREFIX_DS;
13158   append_seg (ins);
13159   ptr_reg (ins, code, sizeflag);
13160   return true;
13161 }
13162
13163 static bool
13164 OP_C (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
13165       int sizeflag ATTRIBUTE_UNUSED)
13166 {
13167   int add, res;
13168   char scratch[8];
13169
13170   if (ins->rex & REX_R)
13171     {
13172       USED_REX (REX_R);
13173       add = 8;
13174     }
13175   else if (ins->address_mode != mode_64bit && (ins->prefixes & PREFIX_LOCK))
13176     {
13177       ins->all_prefixes[ins->last_lock_prefix] = 0;
13178       ins->used_prefixes |= PREFIX_LOCK;
13179       add = 8;
13180     }
13181   else
13182     add = 0;
13183   res = snprintf (scratch, ARRAY_SIZE (scratch), "%%cr%d",
13184                   ins->modrm.reg + add);
13185   if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
13186     abort ();
13187   oappend_register (ins, scratch);
13188   return true;
13189 }
13190
13191 static bool
13192 OP_D (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
13193       int sizeflag ATTRIBUTE_UNUSED)
13194 {
13195   int add, res;
13196   char scratch[8];
13197
13198   USED_REX (REX_R);
13199   if (ins->rex & REX_R)
13200     add = 8;
13201   else
13202     add = 0;
13203   res = snprintf (scratch, ARRAY_SIZE (scratch),
13204                   ins->intel_syntax ? "dr%d" : "%%db%d",
13205                   ins->modrm.reg + add);
13206   if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
13207     abort ();
13208   oappend (ins, scratch);
13209   return true;
13210 }
13211
13212 static bool
13213 OP_T (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
13214       int sizeflag ATTRIBUTE_UNUSED)
13215 {
13216   int res;
13217   char scratch[8];
13218
13219   res = snprintf (scratch, ARRAY_SIZE (scratch), "%%tr%d", ins->modrm.reg);
13220   if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
13221     abort ();
13222   oappend_register (ins, scratch);
13223   return true;
13224 }
13225
13226 static bool
13227 OP_MMX (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13228         int sizeflag ATTRIBUTE_UNUSED)
13229 {
13230   int reg = ins->modrm.reg;
13231   const char (*names)[8];
13232
13233   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13234   if (ins->prefixes & PREFIX_DATA)
13235     {
13236       names = att_names_xmm;
13237       USED_REX (REX_R);
13238       if (ins->rex & REX_R)
13239         reg += 8;
13240     }
13241   else
13242     names = att_names_mm;
13243   oappend_register (ins, names[reg]);
13244   return true;
13245 }
13246
13247 static void
13248 print_vector_reg (instr_info *ins, unsigned int reg, int bytemode)
13249 {
13250   const char (*names)[8];
13251
13252   if (bytemode == xmmq_mode
13253       || bytemode == evex_half_bcst_xmmqh_mode
13254       || bytemode == evex_half_bcst_xmmq_mode)
13255     {
13256       switch (ins->vex.length)
13257         {
13258         case 0:
13259         case 128:
13260         case 256:
13261           names = att_names_xmm;
13262           break;
13263         case 512:
13264           names = att_names_ymm;
13265           ins->evex_used |= EVEX_len_used;
13266           break;
13267         default:
13268           abort ();
13269         }
13270     }
13271   else if (bytemode == ymm_mode)
13272     names = att_names_ymm;
13273   else if (bytemode == tmm_mode)
13274     {
13275       if (reg >= 8)
13276         {
13277           oappend (ins, "(bad)");
13278           return;
13279         }
13280       names = att_names_tmm;
13281     }
13282   else if (ins->need_vex
13283            && bytemode != xmm_mode
13284            && bytemode != scalar_mode
13285            && bytemode != xmmdw_mode
13286            && bytemode != xmmqd_mode
13287            && bytemode != evex_half_bcst_xmmqdh_mode
13288            && bytemode != w_swap_mode
13289            && bytemode != b_mode
13290            && bytemode != w_mode
13291            && bytemode != d_mode
13292            && bytemode != q_mode)
13293     {
13294       ins->evex_used |= EVEX_len_used;
13295       switch (ins->vex.length)
13296         {
13297         case 128:
13298           names = att_names_xmm;
13299           break;
13300         case 256:
13301           if (ins->vex.w
13302               || bytemode != vex_vsib_q_w_dq_mode)
13303             names = att_names_ymm;
13304           else
13305             names = att_names_xmm;
13306           break;
13307         case 512:
13308           if (ins->vex.w
13309               || bytemode != vex_vsib_q_w_dq_mode)
13310             names = att_names_zmm;
13311           else
13312             names = att_names_ymm;
13313           break;
13314         default:
13315           abort ();
13316         }
13317     }
13318   else
13319     names = att_names_xmm;
13320   oappend_register (ins, names[reg]);
13321 }
13322
13323 static bool
13324 OP_XMM (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13325 {
13326   unsigned int reg = ins->modrm.reg;
13327
13328   USED_REX (REX_R);
13329   if (ins->rex & REX_R)
13330     reg += 8;
13331   if (ins->vex.evex)
13332     {
13333       if (ins->rex2 & REX_R)
13334         reg += 16;
13335     }
13336
13337   if (bytemode == tmm_mode)
13338     ins->modrm.reg = reg;
13339   else if (bytemode == scalar_mode)
13340     ins->vex.no_broadcast = true;
13341
13342   print_vector_reg (ins, reg, bytemode);
13343   return true;
13344 }
13345
13346 static bool
13347 OP_EM (instr_info *ins, int bytemode, int sizeflag)
13348 {
13349   int reg;
13350   const char (*names)[8];
13351
13352   if (ins->modrm.mod != 3)
13353     {
13354       if (ins->intel_syntax
13355           && (bytemode == v_mode || bytemode == v_swap_mode))
13356         {
13357           bytemode = (ins->prefixes & PREFIX_DATA) ? x_mode : q_mode;
13358           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13359         }
13360       return OP_E (ins, bytemode, sizeflag);
13361     }
13362
13363   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
13364     swap_operand (ins);
13365
13366   /* Skip mod/rm byte.  */
13367   MODRM_CHECK;
13368   ins->codep++;
13369   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13370   reg = ins->modrm.rm;
13371   if (ins->prefixes & PREFIX_DATA)
13372     {
13373       names = att_names_xmm;
13374       USED_REX (REX_B);
13375       if (ins->rex & REX_B)
13376         reg += 8;
13377     }
13378   else
13379     names = att_names_mm;
13380   oappend_register (ins, names[reg]);
13381   return true;
13382 }
13383
13384 /* cvt* are the only instructions in sse2 which have
13385    both SSE and MMX operands and also have 0x66 prefix
13386    in their opcode. 0x66 was originally used to differentiate
13387    between SSE and MMX instruction(operands). So we have to handle the
13388    cvt* separately using OP_EMC and OP_MXC */
13389 static bool
13390 OP_EMC (instr_info *ins, int bytemode, int sizeflag)
13391 {
13392   if (ins->modrm.mod != 3)
13393     {
13394       if (ins->intel_syntax && bytemode == v_mode)
13395         {
13396           bytemode = (ins->prefixes & PREFIX_DATA) ? x_mode : q_mode;
13397           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13398         }
13399       return OP_E (ins, bytemode, sizeflag);
13400     }
13401
13402   /* Skip mod/rm byte.  */
13403   MODRM_CHECK;
13404   ins->codep++;
13405   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13406   oappend_register (ins, att_names_mm[ins->modrm.rm]);
13407   return true;
13408 }
13409
13410 static bool
13411 OP_MXC (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13412         int sizeflag ATTRIBUTE_UNUSED)
13413 {
13414   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13415   oappend_register (ins, att_names_mm[ins->modrm.reg]);
13416   return true;
13417 }
13418
13419 static bool
13420 OP_EX (instr_info *ins, int bytemode, int sizeflag)
13421 {
13422   int reg;
13423
13424   /* Skip mod/rm byte.  */
13425   MODRM_CHECK;
13426   ins->codep++;
13427
13428   if (bytemode == dq_mode)
13429     bytemode = ins->vex.w ? q_mode : d_mode;
13430
13431   if (ins->modrm.mod != 3)
13432     return OP_E_memory (ins, bytemode, sizeflag);
13433
13434   reg = ins->modrm.rm;
13435   USED_REX (REX_B);
13436   if (ins->rex & REX_B)
13437     reg += 8;
13438   if (ins->vex.evex)
13439     {
13440       USED_REX (REX_X);
13441       if ((ins->rex & REX_X))
13442         reg += 16;
13443       ins->rex2_used &= ~REX_B;
13444     }
13445   else if (ins->rex2 & REX_B)
13446     reg += 16;
13447
13448   if ((sizeflag & SUFFIX_ALWAYS)
13449       && (bytemode == x_swap_mode
13450           || bytemode == w_swap_mode
13451           || bytemode == d_swap_mode
13452           || bytemode == q_swap_mode))
13453     swap_operand (ins);
13454
13455   if (bytemode == tmm_mode)
13456     ins->modrm.rm = reg;
13457
13458   print_vector_reg (ins, reg, bytemode);
13459   return true;
13460 }
13461
13462 static bool
13463 OP_R (instr_info *ins, int bytemode, int sizeflag)
13464 {
13465   if (ins->modrm.mod != 3)
13466     return BadOp (ins);
13467
13468   switch (bytemode)
13469     {
13470     case d_mode:
13471     case dq_mode:
13472     case q_mode:
13473     case mask_mode:
13474       return OP_E (ins, bytemode, sizeflag);
13475     case q_mm_mode:
13476       return OP_EM (ins, x_mode, sizeflag);
13477     case xmm_mode:
13478       if (ins->vex.length <= 128)
13479         break;
13480       return BadOp (ins);
13481     }
13482
13483   return OP_EX (ins, bytemode, sizeflag);
13484 }
13485
13486 static bool
13487 OP_M (instr_info *ins, int bytemode, int sizeflag)
13488 {
13489   /* Skip mod/rm byte.  */
13490   MODRM_CHECK;
13491   ins->codep++;
13492
13493   if (ins->modrm.mod == 3)
13494     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
13495     return BadOp (ins);
13496
13497   if (bytemode == x_mode)
13498     ins->vex.no_broadcast = true;
13499
13500   return OP_E_memory (ins, bytemode, sizeflag);
13501 }
13502
13503 static bool
13504 OP_0f07 (instr_info *ins, int bytemode, int sizeflag)
13505 {
13506   if (ins->modrm.mod != 3 || ins->modrm.rm != 0)
13507     return BadOp (ins);
13508   return OP_E (ins, bytemode, sizeflag);
13509 }
13510
13511 /* montmul instruction need display repz and skip modrm */
13512
13513 static bool
13514 MONTMUL_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13515 {
13516   if (ins->modrm.mod != 3 || ins->modrm.rm != 0)
13517     return BadOp (ins);
13518
13519   /* The 0xf3 prefix should be displayed as "repz" for montmul. */
13520   if (ins->prefixes & PREFIX_REPZ)
13521     ins->all_prefixes[ins->last_repz_prefix] = 0xf3;
13522
13523   /* Skip mod/rm byte.  */
13524   MODRM_CHECK;
13525   ins->codep++;
13526   return true;
13527 }
13528
13529 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
13530    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
13531
13532 static bool
13533 NOP_Fixup (instr_info *ins, int opnd, int sizeflag)
13534 {
13535   if ((ins->prefixes & PREFIX_DATA) == 0 && (ins->rex & REX_B) == 0)
13536     {
13537       ins->mnemonicendp = stpcpy (ins->obuf, "nop");
13538       return true;
13539     }
13540   if (opnd == 0)
13541     return OP_REG (ins, eAX_reg, sizeflag);
13542   return OP_IMREG (ins, eAX_reg, sizeflag);
13543 }
13544
13545 static const char *const Suffix3DNow[] = {
13546 /* 00 */        NULL,           NULL,           NULL,           NULL,
13547 /* 04 */        NULL,           NULL,           NULL,           NULL,
13548 /* 08 */        NULL,           NULL,           NULL,           NULL,
13549 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
13550 /* 10 */        NULL,           NULL,           NULL,           NULL,
13551 /* 14 */        NULL,           NULL,           NULL,           NULL,
13552 /* 18 */        NULL,           NULL,           NULL,           NULL,
13553 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
13554 /* 20 */        NULL,           NULL,           NULL,           NULL,
13555 /* 24 */        NULL,           NULL,           NULL,           NULL,
13556 /* 28 */        NULL,           NULL,           NULL,           NULL,
13557 /* 2C */        NULL,           NULL,           NULL,           NULL,
13558 /* 30 */        NULL,           NULL,           NULL,           NULL,
13559 /* 34 */        NULL,           NULL,           NULL,           NULL,
13560 /* 38 */        NULL,           NULL,           NULL,           NULL,
13561 /* 3C */        NULL,           NULL,           NULL,           NULL,
13562 /* 40 */        NULL,           NULL,           NULL,           NULL,
13563 /* 44 */        NULL,           NULL,           NULL,           NULL,
13564 /* 48 */        NULL,           NULL,           NULL,           NULL,
13565 /* 4C */        NULL,           NULL,           NULL,           NULL,
13566 /* 50 */        NULL,           NULL,           NULL,           NULL,
13567 /* 54 */        NULL,           NULL,           NULL,           NULL,
13568 /* 58 */        NULL,           NULL,           NULL,           NULL,
13569 /* 5C */        NULL,           NULL,           NULL,           NULL,
13570 /* 60 */        NULL,           NULL,           NULL,           NULL,
13571 /* 64 */        NULL,           NULL,           NULL,           NULL,
13572 /* 68 */        NULL,           NULL,           NULL,           NULL,
13573 /* 6C */        NULL,           NULL,           NULL,           NULL,
13574 /* 70 */        NULL,           NULL,           NULL,           NULL,
13575 /* 74 */        NULL,           NULL,           NULL,           NULL,
13576 /* 78 */        NULL,           NULL,           NULL,           NULL,
13577 /* 7C */        NULL,           NULL,           NULL,           NULL,
13578 /* 80 */        NULL,           NULL,           NULL,           NULL,
13579 /* 84 */        NULL,           NULL,           NULL,           NULL,
13580 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
13581 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
13582 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
13583 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
13584 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
13585 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
13586 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
13587 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
13588 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
13589 /* AC */        NULL,           NULL,           "pfacc",        NULL,
13590 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
13591 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
13592 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
13593 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
13594 /* C0 */        NULL,           NULL,           NULL,           NULL,
13595 /* C4 */        NULL,           NULL,           NULL,           NULL,
13596 /* C8 */        NULL,           NULL,           NULL,           NULL,
13597 /* CC */        NULL,           NULL,           NULL,           NULL,
13598 /* D0 */        NULL,           NULL,           NULL,           NULL,
13599 /* D4 */        NULL,           NULL,           NULL,           NULL,
13600 /* D8 */        NULL,           NULL,           NULL,           NULL,
13601 /* DC */        NULL,           NULL,           NULL,           NULL,
13602 /* E0 */        NULL,           NULL,           NULL,           NULL,
13603 /* E4 */        NULL,           NULL,           NULL,           NULL,
13604 /* E8 */        NULL,           NULL,           NULL,           NULL,
13605 /* EC */        NULL,           NULL,           NULL,           NULL,
13606 /* F0 */        NULL,           NULL,           NULL,           NULL,
13607 /* F4 */        NULL,           NULL,           NULL,           NULL,
13608 /* F8 */        NULL,           NULL,           NULL,           NULL,
13609 /* FC */        NULL,           NULL,           NULL,           NULL,
13610 };
13611
13612 static bool
13613 OP_3DNowSuffix (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13614                 int sizeflag ATTRIBUTE_UNUSED)
13615 {
13616   const char *mnemonic;
13617
13618   if (!fetch_code (ins->info, ins->codep + 1))
13619     return false;
13620   /* AMD 3DNow! instructions are specified by an opcode suffix in the
13621      place where an 8-bit immediate would normally go.  ie. the last
13622      byte of the instruction.  */
13623   ins->obufp = ins->mnemonicendp;
13624   mnemonic = Suffix3DNow[*ins->codep++];
13625   if (mnemonic)
13626     ins->obufp = stpcpy (ins->obufp, mnemonic);
13627   else
13628     {
13629       /* Since a variable sized ins->modrm/ins->sib chunk is between the start
13630          of the opcode (0x0f0f) and the opcode suffix, we need to do
13631          all the ins->modrm processing first, and don't know until now that
13632          we have a bad opcode.  This necessitates some cleaning up.  */
13633       ins->op_out[0][0] = '\0';
13634       ins->op_out[1][0] = '\0';
13635       BadOp (ins);
13636     }
13637   ins->mnemonicendp = ins->obufp;
13638   return true;
13639 }
13640
13641 static const struct op simd_cmp_op[] =
13642 {
13643   { STRING_COMMA_LEN ("eq") },
13644   { STRING_COMMA_LEN ("lt") },
13645   { STRING_COMMA_LEN ("le") },
13646   { STRING_COMMA_LEN ("unord") },
13647   { STRING_COMMA_LEN ("neq") },
13648   { STRING_COMMA_LEN ("nlt") },
13649   { STRING_COMMA_LEN ("nle") },
13650   { STRING_COMMA_LEN ("ord") }
13651 };
13652
13653 static const struct op vex_cmp_op[] =
13654 {
13655   { STRING_COMMA_LEN ("eq_uq") },
13656   { STRING_COMMA_LEN ("nge") },
13657   { STRING_COMMA_LEN ("ngt") },
13658   { STRING_COMMA_LEN ("false") },
13659   { STRING_COMMA_LEN ("neq_oq") },
13660   { STRING_COMMA_LEN ("ge") },
13661   { STRING_COMMA_LEN ("gt") },
13662   { STRING_COMMA_LEN ("true") },
13663   { STRING_COMMA_LEN ("eq_os") },
13664   { STRING_COMMA_LEN ("lt_oq") },
13665   { STRING_COMMA_LEN ("le_oq") },
13666   { STRING_COMMA_LEN ("unord_s") },
13667   { STRING_COMMA_LEN ("neq_us") },
13668   { STRING_COMMA_LEN ("nlt_uq") },
13669   { STRING_COMMA_LEN ("nle_uq") },
13670   { STRING_COMMA_LEN ("ord_s") },
13671   { STRING_COMMA_LEN ("eq_us") },
13672   { STRING_COMMA_LEN ("nge_uq") },
13673   { STRING_COMMA_LEN ("ngt_uq") },
13674   { STRING_COMMA_LEN ("false_os") },
13675   { STRING_COMMA_LEN ("neq_os") },
13676   { STRING_COMMA_LEN ("ge_oq") },
13677   { STRING_COMMA_LEN ("gt_oq") },
13678   { STRING_COMMA_LEN ("true_us") },
13679 };
13680
13681 static bool
13682 CMP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13683            int sizeflag ATTRIBUTE_UNUSED)
13684 {
13685   unsigned int cmp_type;
13686
13687   if (!fetch_code (ins->info, ins->codep + 1))
13688     return false;
13689   cmp_type = *ins->codep++;
13690   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
13691     {
13692       char suffix[3];
13693       char *p = ins->mnemonicendp - 2;
13694       suffix[0] = p[0];
13695       suffix[1] = p[1];
13696       suffix[2] = '\0';
13697       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13698       ins->mnemonicendp += simd_cmp_op[cmp_type].len;
13699     }
13700   else if (ins->need_vex
13701            && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op))
13702     {
13703       char suffix[3];
13704       char *p = ins->mnemonicendp - 2;
13705       suffix[0] = p[0];
13706       suffix[1] = p[1];
13707       suffix[2] = '\0';
13708       cmp_type -= ARRAY_SIZE (simd_cmp_op);
13709       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
13710       ins->mnemonicendp += vex_cmp_op[cmp_type].len;
13711     }
13712   else
13713     {
13714       /* We have a reserved extension byte.  Output it directly.  */
13715       oappend_immediate (ins, cmp_type);
13716     }
13717   return true;
13718 }
13719
13720 static bool
13721 OP_Mwait (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13722 {
13723   /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx  */
13724   if (!ins->intel_syntax)
13725     {
13726       strcpy (ins->op_out[0], att_names32[0] + ins->intel_syntax);
13727       strcpy (ins->op_out[1], att_names32[1] + ins->intel_syntax);
13728       if (bytemode == eBX_reg)
13729         strcpy (ins->op_out[2], att_names32[3] + ins->intel_syntax);
13730       ins->two_source_ops = true;
13731     }
13732   /* Skip mod/rm byte.  */
13733   MODRM_CHECK;
13734   ins->codep++;
13735   return true;
13736 }
13737
13738 static bool
13739 OP_Monitor (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13740             int sizeflag ATTRIBUTE_UNUSED)
13741 {
13742   /* monitor %{e,r,}ax,%ecx,%edx"  */
13743   if (!ins->intel_syntax)
13744     {
13745       const char (*names)[8] = (ins->address_mode == mode_64bit
13746                                 ? att_names64 : att_names32);
13747
13748       if (ins->prefixes & PREFIX_ADDR)
13749         {
13750           /* Remove "addr16/addr32".  */
13751           ins->all_prefixes[ins->last_addr_prefix] = 0;
13752           names = (ins->address_mode != mode_32bit
13753                    ? att_names32 : att_names16);
13754           ins->used_prefixes |= PREFIX_ADDR;
13755         }
13756       else if (ins->address_mode == mode_16bit)
13757         names = att_names16;
13758       strcpy (ins->op_out[0], names[0] + ins->intel_syntax);
13759       strcpy (ins->op_out[1], att_names32[1] + ins->intel_syntax);
13760       strcpy (ins->op_out[2], att_names32[2] + ins->intel_syntax);
13761       ins->two_source_ops = true;
13762     }
13763   /* Skip mod/rm byte.  */
13764   MODRM_CHECK;
13765   ins->codep++;
13766   return true;
13767 }
13768
13769 static bool
13770 REP_Fixup (instr_info *ins, int bytemode, int sizeflag)
13771 {
13772   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13773      lods and stos.  */
13774   if (ins->prefixes & PREFIX_REPZ)
13775     ins->all_prefixes[ins->last_repz_prefix] = REP_PREFIX;
13776
13777   switch (bytemode)
13778     {
13779     case al_reg:
13780     case eAX_reg:
13781     case indir_dx_reg:
13782       return OP_IMREG (ins, bytemode, sizeflag);
13783     case eDI_reg:
13784       return OP_ESreg (ins, bytemode, sizeflag);
13785     case eSI_reg:
13786       return OP_DSreg (ins, bytemode, sizeflag);
13787     default:
13788       abort ();
13789       break;
13790     }
13791   return true;
13792 }
13793
13794 static bool
13795 SEP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13796            int sizeflag ATTRIBUTE_UNUSED)
13797 {
13798   if (ins->isa64 != amd64)
13799     return true;
13800
13801   ins->obufp = ins->obuf;
13802   BadOp (ins);
13803   ins->mnemonicendp = ins->obufp;
13804   ++ins->codep;
13805   return true;
13806 }
13807
13808 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
13809    "bnd".  */
13810
13811 static bool
13812 BND_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13813            int sizeflag ATTRIBUTE_UNUSED)
13814 {
13815   if (ins->prefixes & PREFIX_REPNZ)
13816     ins->all_prefixes[ins->last_repnz_prefix] = BND_PREFIX;
13817   return true;
13818 }
13819
13820 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
13821    "notrack".  */
13822
13823 static bool
13824 NOTRACK_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13825                int sizeflag ATTRIBUTE_UNUSED)
13826 {
13827   /* Since active_seg_prefix is not set in 64-bit mode, check whether
13828      we've seen a PREFIX_DS.  */
13829   if ((ins->prefixes & PREFIX_DS) != 0
13830       && (ins->address_mode != mode_64bit || ins->last_data_prefix < 0))
13831     {
13832       /* NOTRACK prefix is only valid on indirect branch instructions.
13833          NB: DATA prefix is unsupported for Intel64.  */
13834       ins->active_seg_prefix = 0;
13835       ins->all_prefixes[ins->last_seg_prefix] = NOTRACK_PREFIX;
13836     }
13837   return true;
13838 }
13839
13840 /* Similar to OP_E.  But the 0xf2/0xf3 ins->prefixes should be displayed as
13841    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
13842  */
13843
13844 static bool
13845 HLE_Fixup1 (instr_info *ins, int bytemode, int sizeflag)
13846 {
13847   if (ins->modrm.mod != 3
13848       && (ins->prefixes & PREFIX_LOCK) != 0)
13849     {
13850       if (ins->prefixes & PREFIX_REPZ)
13851         ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13852       if (ins->prefixes & PREFIX_REPNZ)
13853         ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13854     }
13855
13856   return OP_E (ins, bytemode, sizeflag);
13857 }
13858
13859 /* Similar to OP_E.  But the 0xf2/0xf3 ins->prefixes should be displayed as
13860    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
13861  */
13862
13863 static bool
13864 HLE_Fixup2 (instr_info *ins, int bytemode, int sizeflag)
13865 {
13866   if (ins->modrm.mod != 3)
13867     {
13868       if (ins->prefixes & PREFIX_REPZ)
13869         ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13870       if (ins->prefixes & PREFIX_REPNZ)
13871         ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13872     }
13873
13874   return OP_E (ins, bytemode, sizeflag);
13875 }
13876
13877 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
13878    "xrelease" for memory operand.  No check for LOCK prefix.   */
13879
13880 static bool
13881 HLE_Fixup3 (instr_info *ins, int bytemode, int sizeflag)
13882 {
13883   if (ins->modrm.mod != 3
13884       && ins->last_repz_prefix > ins->last_repnz_prefix
13885       && (ins->prefixes & PREFIX_REPZ) != 0)
13886     ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13887
13888   return OP_E (ins, bytemode, sizeflag);
13889 }
13890
13891 static bool
13892 CMPXCHG8B_Fixup (instr_info *ins, int bytemode, int sizeflag)
13893 {
13894   USED_REX (REX_W);
13895   if (ins->rex & REX_W)
13896     {
13897       /* Change cmpxchg8b to cmpxchg16b.  */
13898       char *p = ins->mnemonicendp - 2;
13899       ins->mnemonicendp = stpcpy (p, "16b");
13900       bytemode = o_mode;
13901     }
13902   else if ((ins->prefixes & PREFIX_LOCK) != 0)
13903     {
13904       if (ins->prefixes & PREFIX_REPZ)
13905         ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13906       if (ins->prefixes & PREFIX_REPNZ)
13907         ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13908     }
13909
13910   return OP_M (ins, bytemode, sizeflag);
13911 }
13912
13913 static bool
13914 XMM_Fixup (instr_info *ins, int reg, int sizeflag ATTRIBUTE_UNUSED)
13915 {
13916   const char (*names)[8] = att_names_xmm;
13917
13918   if (ins->need_vex)
13919     {
13920       switch (ins->vex.length)
13921         {
13922         case 128:
13923           break;
13924         case 256:
13925           names = att_names_ymm;
13926           break;
13927         default:
13928           abort ();
13929         }
13930     }
13931   oappend_register (ins, names[reg]);
13932   return true;
13933 }
13934
13935 static bool
13936 FXSAVE_Fixup (instr_info *ins, int bytemode, int sizeflag)
13937 {
13938   /* Add proper suffix to "fxsave" and "fxrstor".  */
13939   USED_REX (REX_W);
13940   if (ins->rex & REX_W)
13941     {
13942       char *p = ins->mnemonicendp;
13943       *p++ = '6';
13944       *p++ = '4';
13945       *p = '\0';
13946       ins->mnemonicendp = p;
13947     }
13948   return OP_M (ins, bytemode, sizeflag);
13949 }
13950
13951 /* Display the destination register operand for instructions with
13952    VEX. */
13953
13954 static bool
13955 OP_VEX (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13956 {
13957   int reg, modrm_reg, sib_index = -1;
13958   const char (*names)[8];
13959
13960   if (!ins->need_vex)
13961     return true;
13962
13963   if (ins->evex_type == evex_from_legacy)
13964     {
13965       ins->evex_used |= EVEX_b_used;
13966       if (!ins->vex.nd)
13967         return true;
13968     }
13969
13970   reg = ins->vex.register_specifier;
13971   ins->vex.register_specifier = 0;
13972   if (ins->address_mode != mode_64bit)
13973     {
13974       if (ins->vex.evex && !ins->vex.v)
13975         {
13976           oappend (ins, "(bad)");
13977           return true;
13978         }
13979
13980       reg &= 7;
13981     }
13982   else if (ins->vex.evex && !ins->vex.v)
13983     reg += 16;
13984
13985   switch (bytemode)
13986     {
13987     case scalar_mode:
13988       oappend_register (ins, att_names_xmm[reg]);
13989       return true;
13990
13991     case vex_vsib_d_w_dq_mode:
13992     case vex_vsib_q_w_dq_mode:
13993       /* This must be the 3rd operand.  */
13994       if (ins->obufp != ins->op_out[2])
13995         abort ();
13996       if (ins->vex.length == 128
13997           || (bytemode != vex_vsib_d_w_dq_mode
13998               && !ins->vex.w))
13999         oappend_register (ins, att_names_xmm[reg]);
14000       else
14001         oappend_register (ins, att_names_ymm[reg]);
14002
14003       /* All 3 XMM/YMM registers must be distinct.  */
14004       modrm_reg = ins->modrm.reg;
14005       if (ins->rex & REX_R)
14006         modrm_reg += 8;
14007
14008       if (ins->has_sib && ins->modrm.rm == 4)
14009         {
14010           sib_index = ins->sib.index;
14011           if (ins->rex & REX_X)
14012             sib_index += 8;
14013         }
14014
14015       if (reg == modrm_reg || reg == sib_index)
14016         strcpy (ins->obufp, "/(bad)");
14017       if (modrm_reg == sib_index || modrm_reg == reg)
14018         strcat (ins->op_out[0], "/(bad)");
14019       if (sib_index == modrm_reg || sib_index == reg)
14020         strcat (ins->op_out[1], "/(bad)");
14021
14022       return true;
14023
14024     case tmm_mode:
14025       /* All 3 TMM registers must be distinct.  */
14026       if (reg >= 8)
14027         oappend (ins, "(bad)");
14028       else
14029         {
14030           /* This must be the 3rd operand.  */
14031           if (ins->obufp != ins->op_out[2])
14032             abort ();
14033           oappend_register (ins, att_names_tmm[reg]);
14034           if (reg == ins->modrm.reg || reg == ins->modrm.rm)
14035             strcpy (ins->obufp, "/(bad)");
14036         }
14037
14038       if (ins->modrm.reg == ins->modrm.rm || ins->modrm.reg == reg
14039           || ins->modrm.rm == reg)
14040         {
14041           if (ins->modrm.reg <= 8
14042               && (ins->modrm.reg == ins->modrm.rm || ins->modrm.reg == reg))
14043             strcat (ins->op_out[0], "/(bad)");
14044           if (ins->modrm.rm <= 8
14045               && (ins->modrm.rm == ins->modrm.reg || ins->modrm.rm == reg))
14046             strcat (ins->op_out[1], "/(bad)");
14047         }
14048
14049       return true;
14050
14051     case v_mode:
14052     case dq_mode:
14053       if (ins->rex & REX_W)
14054         oappend_register (ins, att_names64[reg]);
14055       else if (bytemode == v_mode
14056                && !(sizeflag & DFLAG))
14057         oappend_register (ins, att_names16[reg]);
14058       else
14059         oappend_register (ins, att_names32[reg]);
14060       return true;
14061
14062     case b_mode:
14063       oappend_register (ins, att_names8rex[reg]);
14064       return true;
14065
14066     case q_mode:
14067       oappend_register (ins, att_names64[reg]);
14068       return true;
14069     }
14070
14071   switch (ins->vex.length)
14072     {
14073     case 128:
14074       switch (bytemode)
14075         {
14076         case x_mode:
14077           names = att_names_xmm;
14078           ins->evex_used |= EVEX_len_used;
14079           break;
14080         case mask_bd_mode:
14081         case mask_mode:
14082           if (reg > 0x7)
14083             {
14084               oappend (ins, "(bad)");
14085               return true;
14086             }
14087           names = att_names_mask;
14088           break;
14089         default:
14090           abort ();
14091           return true;
14092         }
14093       break;
14094     case 256:
14095       switch (bytemode)
14096         {
14097         case x_mode:
14098           names = att_names_ymm;
14099           ins->evex_used |= EVEX_len_used;
14100           break;
14101         case mask_bd_mode:
14102         case mask_mode:
14103           if (reg <= 0x7)
14104             {
14105               names = att_names_mask;
14106               break;
14107             }
14108           /* Fall through.  */
14109         default:
14110           /* See PR binutils/20893 for a reproducer.  */
14111           oappend (ins, "(bad)");
14112           return true;
14113         }
14114       break;
14115     case 512:
14116       names = att_names_zmm;
14117       ins->evex_used |= EVEX_len_used;
14118       break;
14119     default:
14120       abort ();
14121       break;
14122     }
14123   oappend_register (ins, names[reg]);
14124   return true;
14125 }
14126
14127 static bool
14128 OP_VexR (instr_info *ins, int bytemode, int sizeflag)
14129 {
14130   if (ins->modrm.mod == 3)
14131     return OP_VEX (ins, bytemode, sizeflag);
14132   return true;
14133 }
14134
14135 static bool
14136 OP_VexW (instr_info *ins, int bytemode, int sizeflag)
14137 {
14138   OP_VEX (ins, bytemode, sizeflag);
14139
14140   if (ins->vex.w)
14141     {
14142       /* Swap 2nd and 3rd operands.  */
14143       char *tmp = ins->op_out[2];
14144
14145       ins->op_out[2] = ins->op_out[1];
14146       ins->op_out[1] = tmp;
14147     }
14148   return true;
14149 }
14150
14151 static bool
14152 OP_REG_VexI4 (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14153 {
14154   int reg;
14155   const char (*names)[8] = att_names_xmm;
14156
14157   if (!fetch_code (ins->info, ins->codep + 1))
14158     return false;
14159   reg = *ins->codep++;
14160
14161   if (bytemode != x_mode && bytemode != scalar_mode)
14162     abort ();
14163
14164   reg >>= 4;
14165   if (ins->address_mode != mode_64bit)
14166     reg &= 7;
14167
14168   if (bytemode == x_mode && ins->vex.length == 256)
14169     names = att_names_ymm;
14170
14171   oappend_register (ins, names[reg]);
14172
14173   if (ins->vex.w)
14174     {
14175       /* Swap 3rd and 4th operands.  */
14176       char *tmp = ins->op_out[3];
14177
14178       ins->op_out[3] = ins->op_out[2];
14179       ins->op_out[2] = tmp;
14180     }
14181   return true;
14182 }
14183
14184 static bool
14185 OP_VexI4 (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
14186           int sizeflag ATTRIBUTE_UNUSED)
14187 {
14188   oappend_immediate (ins, ins->codep[-1] & 0xf);
14189   return true;
14190 }
14191
14192 static bool
14193 VPCMP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
14194              int sizeflag ATTRIBUTE_UNUSED)
14195 {
14196   unsigned int cmp_type;
14197
14198   if (!ins->vex.evex)
14199     abort ();
14200
14201   if (!fetch_code (ins->info, ins->codep + 1))
14202     return false;
14203   cmp_type = *ins->codep++;
14204   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
14205      If it's the case, print suffix, otherwise - print the immediate.  */
14206   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
14207       && cmp_type != 3
14208       && cmp_type != 7)
14209     {
14210       char suffix[3];
14211       char *p = ins->mnemonicendp - 2;
14212
14213       /* vpcmp* can have both one- and two-lettered suffix.  */
14214       if (p[0] == 'p')
14215         {
14216           p++;
14217           suffix[0] = p[0];
14218           suffix[1] = '\0';
14219         }
14220       else
14221         {
14222           suffix[0] = p[0];
14223           suffix[1] = p[1];
14224           suffix[2] = '\0';
14225         }
14226
14227       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
14228       ins->mnemonicendp += simd_cmp_op[cmp_type].len;
14229     }
14230   else
14231     {
14232       /* We have a reserved extension byte.  Output it directly.  */
14233       oappend_immediate (ins, cmp_type);
14234     }
14235   return true;
14236 }
14237
14238 static const struct op xop_cmp_op[] =
14239 {
14240   { STRING_COMMA_LEN ("lt") },
14241   { STRING_COMMA_LEN ("le") },
14242   { STRING_COMMA_LEN ("gt") },
14243   { STRING_COMMA_LEN ("ge") },
14244   { STRING_COMMA_LEN ("eq") },
14245   { STRING_COMMA_LEN ("neq") },
14246   { STRING_COMMA_LEN ("false") },
14247   { STRING_COMMA_LEN ("true") }
14248 };
14249
14250 static bool
14251 VPCOM_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
14252              int sizeflag ATTRIBUTE_UNUSED)
14253 {
14254   unsigned int cmp_type;
14255
14256   if (!fetch_code (ins->info, ins->codep + 1))
14257     return false;
14258   cmp_type = *ins->codep++;
14259   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
14260     {
14261       char suffix[3];
14262       char *p = ins->mnemonicendp - 2;
14263
14264       /* vpcom* can have both one- and two-lettered suffix.  */
14265       if (p[0] == 'm')
14266         {
14267           p++;
14268           suffix[0] = p[0];
14269           suffix[1] = '\0';
14270         }
14271       else
14272         {
14273           suffix[0] = p[0];
14274           suffix[1] = p[1];
14275           suffix[2] = '\0';
14276         }
14277
14278       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
14279       ins->mnemonicendp += xop_cmp_op[cmp_type].len;
14280     }
14281   else
14282     {
14283       /* We have a reserved extension byte.  Output it directly.  */
14284       oappend_immediate (ins, cmp_type);
14285     }
14286   return true;
14287 }
14288
14289 static const struct op pclmul_op[] =
14290 {
14291   { STRING_COMMA_LEN ("lql") },
14292   { STRING_COMMA_LEN ("hql") },
14293   { STRING_COMMA_LEN ("lqh") },
14294   { STRING_COMMA_LEN ("hqh") }
14295 };
14296
14297 static bool
14298 PCLMUL_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
14299               int sizeflag ATTRIBUTE_UNUSED)
14300 {
14301   unsigned int pclmul_type;
14302
14303   if (!fetch_code (ins->info, ins->codep + 1))
14304     return false;
14305   pclmul_type = *ins->codep++;
14306   switch (pclmul_type)
14307     {
14308     case 0x10:
14309       pclmul_type = 2;
14310       break;
14311     case 0x11:
14312       pclmul_type = 3;
14313       break;
14314     default:
14315       break;
14316     }
14317   if (pclmul_type < ARRAY_SIZE (pclmul_op))
14318     {
14319       char suffix[4];
14320       char *p = ins->mnemonicendp - 3;
14321       suffix[0] = p[0];
14322       suffix[1] = p[1];
14323       suffix[2] = p[2];
14324       suffix[3] = '\0';
14325       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
14326       ins->mnemonicendp += pclmul_op[pclmul_type].len;
14327     }
14328   else
14329     {
14330       /* We have a reserved extension byte.  Output it directly.  */
14331       oappend_immediate (ins, pclmul_type);
14332     }
14333   return true;
14334 }
14335
14336 static bool
14337 MOVSXD_Fixup (instr_info *ins, int bytemode, int sizeflag)
14338 {
14339   /* Add proper suffix to "movsxd".  */
14340   char *p = ins->mnemonicendp;
14341
14342   switch (bytemode)
14343     {
14344     case movsxd_mode:
14345       if (!ins->intel_syntax)
14346         {
14347           USED_REX (REX_W);
14348           if (ins->rex & REX_W)
14349             {
14350               *p++ = 'l';
14351               *p++ = 'q';
14352               break;
14353             }
14354         }
14355
14356       *p++ = 'x';
14357       *p++ = 'd';
14358       break;
14359     default:
14360       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
14361       break;
14362     }
14363
14364   ins->mnemonicendp = p;
14365   *p = '\0';
14366   return OP_E (ins, bytemode, sizeflag);
14367 }
14368
14369 static bool
14370 DistinctDest_Fixup (instr_info *ins, int bytemode, int sizeflag)
14371 {
14372   unsigned int reg = ins->vex.register_specifier;
14373   unsigned int modrm_reg = ins->modrm.reg;
14374   unsigned int modrm_rm = ins->modrm.rm;
14375
14376   /* Calc destination register number.  */
14377   if (ins->rex & REX_R)
14378     modrm_reg += 8;
14379   if (ins->rex2 & REX_R)
14380     modrm_reg += 16;
14381
14382   /* Calc src1 register number.  */
14383   if (ins->address_mode != mode_64bit)
14384     reg &= 7;
14385   else if (ins->vex.evex && !ins->vex.v)
14386     reg += 16;
14387
14388   /* Calc src2 register number.  */
14389   if (ins->modrm.mod == 3)
14390     {
14391       if (ins->rex & REX_B)
14392         modrm_rm += 8;
14393       if (ins->rex & REX_X)
14394         modrm_rm += 16;
14395     }
14396
14397   /* Destination and source registers must be distinct, output bad if
14398      dest == src1 or dest == src2.  */
14399   if (modrm_reg == reg
14400       || (ins->modrm.mod == 3
14401           && modrm_reg == modrm_rm))
14402     {
14403       oappend (ins, "(bad)");
14404       return true;
14405     }
14406   return OP_XMM (ins, bytemode, sizeflag);
14407 }
14408
14409 static bool
14410 OP_Rounding (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14411 {
14412   if (ins->modrm.mod != 3 || !ins->vex.b)
14413     return true;
14414
14415   ins->evex_used |= EVEX_b_used;
14416   switch (bytemode)
14417     {
14418     case evex_rounding_64_mode:
14419       if (ins->address_mode != mode_64bit || !ins->vex.w)
14420         return true;
14421       /* Fall through.  */
14422     case evex_rounding_mode:
14423       oappend (ins, names_rounding[ins->vex.ll]);
14424       break;
14425     case evex_sae_mode:
14426       oappend (ins, "{");
14427       break;
14428     default:
14429       abort ();
14430     }
14431   oappend (ins, "sae}");
14432   return true;
14433 }
14434
14435 static bool
14436 PREFETCHI_Fixup (instr_info *ins, int bytemode, int sizeflag)
14437 {
14438   if (ins->modrm.mod != 0 || ins->modrm.rm != 5)
14439     {
14440       if (ins->intel_syntax)
14441         {
14442           ins->mnemonicendp = stpcpy (ins->obuf, "nop   ");
14443         }
14444       else
14445         {
14446           USED_REX (REX_W);
14447           if (ins->rex & REX_W)
14448             ins->mnemonicendp = stpcpy (ins->obuf, "nopq  ");
14449           else
14450             {
14451               if (sizeflag & DFLAG)
14452                 ins->mnemonicendp = stpcpy (ins->obuf, "nopl  ");
14453               else
14454                 ins->mnemonicendp = stpcpy (ins->obuf, "nopw  ");
14455               ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
14456             }
14457         }
14458       bytemode = v_mode;
14459     }
14460
14461   return OP_M (ins, bytemode, sizeflag);
14462 }
14463
14464 static bool
14465 PUSH2_POP2_Fixup (instr_info *ins, int bytemode, int sizeflag)
14466 {
14467   if (ins->modrm.mod != 3)
14468     return true;
14469
14470   unsigned int vvvv_reg = ins->vex.register_specifier
14471     | (!ins->vex.v << 4);
14472   unsigned int rm_reg = ins->modrm.rm + (ins->rex & REX_B ? 8 : 0)
14473     + (ins->rex2 & REX_B ? 16 : 0);
14474
14475   /* Push2/Pop2 cannot use RSP and Pop2 cannot pop two same registers.  */
14476   if (!ins->vex.nd || vvvv_reg == 0x4 || rm_reg == 0x4
14477       || (!ins->modrm.reg
14478           && vvvv_reg == rm_reg))
14479     {
14480       oappend (ins, "(bad)");
14481       return true;
14482     }
14483
14484   return OP_VEX (ins, bytemode, sizeflag);
14485 }
14486
14487 static bool
14488 JMPABS_Fixup (instr_info *ins, int bytemode, int sizeflag)
14489 {
14490   if (ins->last_rex2_prefix >= 0)
14491     {
14492       uint64_t op;
14493
14494       if ((ins->prefixes & (PREFIX_OPCODE | PREFIX_ADDR | PREFIX_LOCK)) != 0x0
14495           || (ins->rex & REX_W) != 0x0)
14496         {
14497           oappend (ins, "(bad)");
14498           return true;
14499         }
14500
14501       if (bytemode == eAX_reg)
14502         return true;
14503
14504       if (!get64 (ins, &op))
14505         return false;
14506
14507       ins->mnemonicendp = stpcpy (ins->obuf, "jmpabs");
14508       ins->rex2 |= REX2_SPECIAL;
14509       oappend_immediate (ins, op);
14510
14511       return true;
14512     }
14513
14514   if (bytemode == eAX_reg)
14515     return OP_IMREG (ins, bytemode, sizeflag);
14516   return OP_OFF64 (ins, bytemode, sizeflag);
14517 }
14518
14519 static bool
14520 CFCMOV_Fixup (instr_info *ins, int opnd, int sizeflag)
14521 {
14522   /* EVEX.NF is used as a direction bit in the 2-operand case to reverse the
14523      source and destination operands.  */
14524   bool dstmem = !ins->vex.nd && ins->vex.nf;
14525
14526   if (opnd == 0)
14527     {
14528       if (dstmem)
14529         return OP_E (ins, v_swap_mode, sizeflag);
14530       return OP_G (ins, v_mode, sizeflag);
14531     }
14532
14533   /* These bits have been consumed and should be cleared.  */
14534   ins->vex.nf = false;
14535   ins->vex.mask_register_specifier = 0;
14536
14537   if (dstmem)
14538     return OP_G (ins, v_mode, sizeflag);
14539   return OP_E (ins, v_mode, sizeflag);
14540 }