opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright (C) 2007-2024 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GAS; see the file COPYING.  If not, write to the Free
  18    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  19    02110-1301, USA.  */
  20
  21 #include "opcode/i386.h"
  22 #include <limits.h>
  23 #ifndef CHAR_BIT
  24 #define CHAR_BIT 8
  25 #endif
  26
  27 /* Position of cpu flags bitfiled.  */
  28
  29 enum i386_cpu
  30 {
  31   /* i186 or better required */
  32   Cpu186 = 0,
  33   /* i286 or better required */
  34   Cpu286,
  35   /* i386 or better required */
  36   Cpu386,
  37   /* i486 or better required */
  38   Cpu486,
  39   /* i585 or better required */
  40   Cpu586,
  41   /* i686 or better required */
  42   Cpu686,
  43   /* CMOV Instruction support required */
  44   CpuCMOV,
  45   /* FXSR Instruction support required */
  46   CpuFXSR,
  47   /* CLFLUSH Instruction support required */
  48   CpuClflush,
  49   /* NOP Instruction support required */
  50   CpuNop,
  51   /* SYSCALL Instructions support required */
  52   CpuSYSCALL,
  53   /* Floating point support required */
  54   Cpu8087,
  55   /* i686 and floating point support required */
  56   Cpu687,
  57   /* SSE3 and floating point support required */
  58   CpuFISTTP,
  59   /* MMX support required */
  60   CpuMMX,
  61   /* SSE support required */
  62   CpuSSE,
  63   /* SSE2 support required */
  64   CpuSSE2,
  65   /* SSE3 support required */
  66   CpuSSE3,
  67   /* VIA PadLock required */
  68   CpuPadLock,
  69   /* ZHAOXIN GMI required */
  70   CpuGMI,
  71   /* AMD Secure Virtual Machine Ext-s required */
  72   CpuSVME,
  73   /* VMX Instructions required */
  74   CpuVMX,
  75   /* SMX Instructions required */
  76   CpuSMX,
  77   /* SSSE3 support required */
  78   CpuSSSE3,
  79   /* SSE4a support required */
  80   CpuSSE4a,
  81   /* LZCNT support required */
  82   CpuLZCNT,
  83   /* POPCNT support required */
  84   CpuPOPCNT,
  85   /* MONITOR support required */
  86   CpuMONITOR,
  87   /* SSE4.1 support required */
  88   CpuSSE4_1,
  89   /* SSE4.2 support required */
  90   CpuSSE4_2,
  91   /* AVX2 support required */
  92   CpuAVX2,
  93   /* Intel AVX-512 Conflict Detection Instructions support required */
  94   CpuAVX512CD,
  95   /* Intel AVX-512 Exponential and Reciprocal Instructions support
  96      required */
  97   CpuAVX512ER,
  98   /* Intel AVX-512 Prefetch Instructions support required */
  99   CpuAVX512PF,
 100   /* Intel AVX-512 DQ Instructions support required.  */
 101   CpuAVX512DQ,
 102   /* Intel AVX-512 BW Instructions support required.  */
 103   CpuAVX512BW,
 104   /* Intel IAMCU support required */
 105   CpuIAMCU,
 106   /* Xsave/xrstor New Instructions support required */
 107   CpuXsave,
 108   /* Xsaveopt New Instructions support required */
 109   CpuXsaveopt,
 110   /* AES support required */
 111   CpuAES,
 112   /* PCLMULQDQ support required */
 113   CpuPCLMULQDQ,
 114   /* FMA support required */
 115   CpuFMA,
 116   /* FMA4 support required */
 117   CpuFMA4,
 118   /* XOP support required */
 119   CpuXOP,
 120   /* LWP support required */
 121   CpuLWP,
 122   /* BMI support required */
 123   CpuBMI,
 124   /* TBM support required */
 125   CpuTBM,
 126   /* MOVBE Instruction support required */
 127   CpuMovbe,
 128   /* CMPXCHG16B instruction support required.  */
 129   CpuCX16,
 130   /* LAHF/SAHF instruction support required (in 64-bit mode).  */
 131   CpuLAHF_SAHF,
 132   /* EPT Instructions required */
 133   CpuEPT,
 134   /* RDTSCP Instruction support required */
 135   CpuRdtscp,
 136   /* FSGSBASE Instructions required */
 137   CpuFSGSBase,
 138   /* RDRND Instructions required */
 139   CpuRdRnd,
 140   /* F16C Instructions required */
 141   CpuF16C,
 142   /* Intel BMI2 support required */
 143   CpuBMI2,
 144   /* RTM support required */
 145   CpuRTM,
 146   /* INVPCID Instructions required */
 147   CpuINVPCID,
 148   /* VMFUNC Instruction required */
 149   CpuVMFUNC,
 150   /* Intel MPX Instructions required  */
 151   CpuMPX,
 152   /* RDRSEED instruction required.  */
 153   CpuRDSEED,
 154   /* Multi-presisionn add-carry instructions are required.  */
 155   CpuADX,
 156   /* Supports prefetchw and prefetch instructions.  */
 157   CpuPRFCHW,
 158   /* SMAP instructions required.  */
 159   CpuSMAP,
 160   /* SHA instructions required.  */
 161   CpuSHA,
 162   /* SHA512 instructions required.  */
 163   CpuSHA512,
 164   /* SM3 instructions required.  */
 165   CpuSM3,
 166   /* SM4 instructions required.  */
 167   CpuSM4,
 168   /* CLFLUSHOPT instruction required */
 169   CpuClflushOpt,
 170   /* XSAVES/XRSTORS instruction required */
 171   CpuXSAVES,
 172   /* XSAVEC instruction required */
 173   CpuXSAVEC,
 174   /* PREFETCHWT1 instruction required */
 175   CpuPREFETCHWT1,
 176   /* SE1 instruction required */
 177   CpuSE1,
 178   /* CLWB instruction required */
 179   CpuCLWB,
 180   /* Intel AVX-512 IFMA Instructions support required.  */
 181   CpuAVX512IFMA,
 182   /* Intel AVX-512 VBMI Instructions support required.  */
 183   CpuAVX512VBMI,
 184   /* Intel AVX-512 4FMAPS Instructions support required.  */
 185   CpuAVX512_4FMAPS,
 186   /* Intel AVX-512 4VNNIW Instructions support required.  */
 187   CpuAVX512_4VNNIW,
 188   /* Intel AVX-512 VPOPCNTDQ Instructions support required.  */
 189   CpuAVX512_VPOPCNTDQ,
 190   /* Intel AVX-512 VBMI2 Instructions support required.  */
 191   CpuAVX512_VBMI2,
 192   /* Intel AVX-512 VNNI Instructions support required.  */
 193   CpuAVX512_VNNI,
 194   /* Intel AVX-512 BITALG Instructions support required.  */
 195   CpuAVX512_BITALG,
 196   /* Intel AVX-512 BF16 Instructions support required.  */
 197   CpuAVX512_BF16,
 198   /* Intel AVX-512 VP2INTERSECT Instructions support required.  */
 199   CpuAVX512_VP2INTERSECT,
 200   /* TDX Instructions support required.  */
 201   CpuTDX,
 202   /* Intel AVX VNNI Instructions support required.  */
 203   CpuAVX_VNNI,
 204   /* Intel AVX-512 FP16 Instructions support required.  */
 205   CpuAVX512_FP16,
 206   /* PREFETCHI instruction required */
 207   CpuPREFETCHI,
 208   /* Intel AVX IFMA Instructions support required.  */
 209   CpuAVX_IFMA,
 210   /* Intel AVX VNNI-INT8 Instructions support required.  */
 211   CpuAVX_VNNI_INT8,
 212   /* Intel AVX VNNI-INT16 Instructions support required.  */
 213   CpuAVX_VNNI_INT16,
 214   /* Intel CMPccXADD instructions support required.  */
 215   CpuCMPCCXADD,
 216   /* Intel WRMSRNS Instructions support required */
 217   CpuWRMSRNS,
 218   /* Intel MSRLIST Instructions support required.  */
 219   CpuMSRLIST,
 220   /* Intel AVX NE CONVERT Instructions support required.  */
 221   CpuAVX_NE_CONVERT,
 222   /* Intel RAO INT Instructions support required.  */
 223   CpuRAO_INT,
 224   /* fred instruction required */
 225   CpuFRED,
 226   /* lkgs instruction required */
 227   CpuLKGS,
 228   /* Intel USER_MSR Instruction support required.  */
 229   CpuUSER_MSR,
 230   /* Intel MSR_IMM Instructions support required.  */
 231   CpuMSR_IMM,
 232   /* Intel AVX10.2 Instructions support required.  */
 233   CpuAVX10_2,
 234   /* mwaitx instruction required */
 235   CpuMWAITX,
 236   /* Clzero instruction required */
 237   CpuCLZERO,
 238   /* OSPKE instruction required */
 239   CpuOSPKE,
 240   /* RDPID instruction required */
 241   CpuRDPID,
 242   /* PTWRITE instruction required */
 243   CpuPTWRITE,
 244   /* CET instructions support required */
 245   CpuIBT,
 246   CpuSHSTK,
 247   /* AMX-INT8 instructions required */
 248   CpuAMX_INT8,
 249   /* AMX-BF16 instructions required */
 250   CpuAMX_BF16,
 251   /* AMX-FP16 instructions required */
 252   CpuAMX_FP16,
 253   /* AMX-COMPLEX instructions required.  */
 254   CpuAMX_COMPLEX,
 255   /* AMX-TILE instructions required */
 256   CpuAMX_TILE,
 257   /* GFNI instructions required */
 258   CpuGFNI,
 259   /* VAES instructions required */
 260   CpuVAES,
 261   /* VPCLMULQDQ instructions required */
 262   CpuVPCLMULQDQ,
 263   /* WBNOINVD instructions required */
 264   CpuWBNOINVD,
 265   /* PCONFIG instructions required */
 266   CpuPCONFIG,
 267   /* PBNDKB instructions required.  */
 268   CpuPBNDKB,
 269   /* WAITPKG instructions required */
 270   CpuWAITPKG,
 271   /* UINTR instructions required */
 272   CpuUINTR,
 273   /* CLDEMOTE instruction required */
 274   CpuCLDEMOTE,
 275   /* MOVDIRI instruction support required */
 276   CpuMOVDIRI,
 277   /* MOVDIRR64B instruction required */
 278   CpuMOVDIR64B,
 279   /* ENQCMD instruction required */
 280   CpuENQCMD,
 281   /* SERIALIZE instruction required */
 282   CpuSERIALIZE,
 283   /* RDPRU instruction required */
 284   CpuRDPRU,
 285   /* MCOMMIT instruction required */
 286   CpuMCOMMIT,
 287   /* SEV-ES instruction(s) required */
 288   CpuSEV_ES,
 289   /* TSXLDTRK instruction required */
 290   CpuTSXLDTRK,
 291   /* KL instruction support required */
 292   CpuKL,
 293   /* WideKL instruction support required */
 294   CpuWideKL,
 295   /* HRESET instruction required */
 296   CpuHRESET,
 297   /* INVLPGB instructions required */
 298   CpuINVLPGB,
 299   /* TLBSYNC instructions required */
 300   CpuTLBSYNC,
 301   /* SNP instructions required */
 302   CpuSNP,
 303   /* RMPQUERY instruction required */
 304   CpuRMPQUERY,
 305
 306   /* NOTE: These items, which can be combined with other ISA flags above, need
 307      to remain second to last and in sync with CPU_FLAGS_COMMON. */
 308
 309   /* i287 support required */
 310   Cpu287,
 311   CpuAttrEnums = Cpu287,
 312   /* i387 support required */
 313   Cpu387,
 314   /* 3dnow! support required */
 315   Cpu3dnow,
 316   /* 3dnow! Extensions support required */
 317   Cpu3dnowA,
 318   /* 64bit support required  */
 319   Cpu64,
 320   /* AVX support required */
 321   CpuAVX,
 322   /* HLE support required */
 323   CpuHLE,
 324   /* Intel AVX-512 Foundation Instructions support required */
 325   CpuAVX512F,
 326   /* Intel AVX-512 VL Instructions support required.  */
 327   CpuAVX512VL,
 328   /* Intel APX_F Instructions support required.  */
 329   CpuAPX_F,
 330   /* Not supported in the 64bit mode  */
 331   CpuNo64,
 332
 333   /* NOTE: This item needs to remain last. */
 334
 335   /* The last bitfield in i386_cpu_flags.  */
 336   CpuMax = CpuNo64
 337 };
 338
 339 #define CpuNumOfUints \
 340   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 341 #define CpuNumOfBits \
 342   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 343
 344 #define CpuIsaBits 8
 345 #define CpuAttrNumOfUints \
 346   ((CpuIsaBits + CpuMax - CpuAttrEnums) / sizeof (unsigned int) / CHAR_BIT + 1)
 347 #define CpuAttrNumOfBits \
 348   (CpuAttrNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 349
 350 /* If you get a compiler error for zero width of an unused field,
 351    comment the respective one out.  */
 352 #define CpuUnused       (CpuMax + 1)
 353 #define CpuAttrUnused   (CpuIsaBits + CpuMax + 1 - CpuAttrEnums)
 354
 355 #define CPU_FLAGS_COMMON \
 356       unsigned int cpu287:1, \
 357                    cpu387:1, \
 358                    cpu3dnow:1, \
 359                    cpu3dnowa:1, \
 360                    cpu64:1, \
 361                    cpuavx:1, \
 362                    cpuhle:1, \
 363                    cpuavx512f:1, \
 364                    cpuavx512vl:1, \
 365                    cpuapx_f:1, \
 366       /* NOTE: This field needs to remain last. */ \
 367                    cpuno64:1
 368
 369 typedef union i386_cpu_attr
 370 {
 371   struct
 372     {
 373       unsigned int isa:CpuIsaBits;
 374       CPU_FLAGS_COMMON;
 375 #ifdef CpuAttrUnused
 376       unsigned int unused:(CpuAttrNumOfBits - CpuAttrUnused);
 377 #endif
 378     } bitfield;
 379   unsigned int array[CpuAttrNumOfUints];
 380 } i386_cpu_attr;
 381
 382 /* We can check if an instruction is available with array instead
 383    of bitfield. */
 384 typedef union i386_cpu_flags
 385 {
 386   struct
 387     {
 388       unsigned int cpui186:1;
 389       unsigned int cpui286:1;
 390       unsigned int cpui386:1;
 391       unsigned int cpui486:1;
 392       unsigned int cpui586:1;
 393       unsigned int cpui686:1;
 394       unsigned int cpucmov:1;
 395       unsigned int cpufxsr:1;
 396       unsigned int cpuclflush:1;
 397       unsigned int cpunop:1;
 398       unsigned int cpusyscall:1;
 399       unsigned int cpu8087:1;
 400       unsigned int cpu687:1;
 401       unsigned int cpufisttp:1;
 402       unsigned int cpummx:1;
 403       unsigned int cpusse:1;
 404       unsigned int cpusse2:1;
 405       unsigned int cpusse3:1;
 406       unsigned int cpupadlock:1;
 407       unsigned int cpugmi:1;
 408       unsigned int cpusvme:1;
 409       unsigned int cpuvmx:1;
 410       unsigned int cpusmx:1;
 411       unsigned int cpussse3:1;
 412       unsigned int cpusse4a:1;
 413       unsigned int cpulzcnt:1;
 414       unsigned int cpupopcnt:1;
 415       unsigned int cpumonitor:1;
 416       unsigned int cpusse4_1:1;
 417       unsigned int cpusse4_2:1;
 418       unsigned int cpuavx2:1;
 419       unsigned int cpuavx512cd:1;
 420       unsigned int cpuavx512er:1;
 421       unsigned int cpuavx512pf:1;
 422       unsigned int cpuavx512dq:1;
 423       unsigned int cpuavx512bw:1;
 424       unsigned int cpuiamcu:1;
 425       unsigned int cpuxsave:1;
 426       unsigned int cpuxsaveopt:1;
 427       unsigned int cpuaes:1;
 428       unsigned int cpupclmulqdq:1;
 429       unsigned int cpufma:1;
 430       unsigned int cpufma4:1;
 431       unsigned int cpuxop:1;
 432       unsigned int cpulwp:1;
 433       unsigned int cpubmi:1;
 434       unsigned int cputbm:1;
 435       unsigned int cpumovbe:1;
 436       unsigned int cpucx16:1;
 437       unsigned int cpulahf_sahf:1;
 438       unsigned int cpuept:1;
 439       unsigned int cpurdtscp:1;
 440       unsigned int cpufsgsbase:1;
 441       unsigned int cpurdrnd:1;
 442       unsigned int cpuf16c:1;
 443       unsigned int cpubmi2:1;
 444       unsigned int cpurtm:1;
 445       unsigned int cpuinvpcid:1;
 446       unsigned int cpuvmfunc:1;
 447       unsigned int cpumpx:1;
 448       unsigned int cpurdseed:1;
 449       unsigned int cpuadx:1;
 450       unsigned int cpuprfchw:1;
 451       unsigned int cpusmap:1;
 452       unsigned int cpusha:1;
 453       unsigned int cpusha512:1;
 454       unsigned int cpusm3:1;
 455       unsigned int cpusm4:1;
 456       unsigned int cpuclflushopt:1;
 457       unsigned int cpuxsaves:1;
 458       unsigned int cpuxsavec:1;
 459       unsigned int cpuprefetchwt1:1;
 460       unsigned int cpuse1:1;
 461       unsigned int cpuclwb:1;
 462       unsigned int cpuavx512ifma:1;
 463       unsigned int cpuavx512vbmi:1;
 464       unsigned int cpuavx512_4fmaps:1;
 465       unsigned int cpuavx512_4vnniw:1;
 466       unsigned int cpuavx512_vpopcntdq:1;
 467       unsigned int cpuavx512_vbmi2:1;
 468       unsigned int cpuavx512_vnni:1;
 469       unsigned int cpuavx512_bitalg:1;
 470       unsigned int cpuavx512_bf16:1;
 471       unsigned int cpuavx512_vp2intersect:1;
 472       unsigned int cputdx:1;
 473       unsigned int cpuavx_vnni:1;
 474       unsigned int cpuavx512_fp16:1;
 475       unsigned int cpuprefetchi:1;
 476       unsigned int cpuavx_ifma:1;
 477       unsigned int cpuavx_vnni_int8:1;
 478       unsigned int cpuavx_vnni_int16:1;
 479       unsigned int cpucmpccxadd:1;
 480       unsigned int cpuwrmsrns:1;
 481       unsigned int cpumsrlist:1;
 482       unsigned int cpuavx_ne_convert:1;
 483       unsigned int cpurao_int:1;
 484       unsigned int cpufred:1;
 485       unsigned int cpulkgs:1;
 486       unsigned int cpuuser_msr:1;
 487       unsigned int cpumsr_imm:1;
 488       unsigned int cpuavx10_2:1;
 489       unsigned int cpumwaitx:1;
 490       unsigned int cpuclzero:1;
 491       unsigned int cpuospke:1;
 492       unsigned int cpurdpid:1;
 493       unsigned int cpuptwrite:1;
 494       unsigned int cpuibt:1;
 495       unsigned int cpushstk:1;
 496       unsigned int cpuamx_int8:1;
 497       unsigned int cpuamx_bf16:1;
 498       unsigned int cpuamx_fp16:1;
 499       unsigned int cpuamx_complex:1;
 500       unsigned int cpuamx_tile:1;
 501       unsigned int cpugfni:1;
 502       unsigned int cpuvaes:1;
 503       unsigned int cpuvpclmulqdq:1;
 504       unsigned int cpuwbnoinvd:1;
 505       unsigned int cpupconfig:1;
 506       unsigned int cpupbndkb:1;
 507       unsigned int cpuwaitpkg:1;
 508       unsigned int cpuuintr:1;
 509       unsigned int cpucldemote:1;
 510       unsigned int cpumovdiri:1;
 511       unsigned int cpumovdir64b:1;
 512       unsigned int cpuenqcmd:1;
 513       unsigned int cpuserialize:1;
 514       unsigned int cpurdpru:1;
 515       unsigned int cpumcommit:1;
 516       unsigned int cpusev_es:1;
 517       unsigned int cputsxldtrk:1;
 518       unsigned int cpukl:1;
 519       unsigned int cpuwidekl:1;
 520       unsigned int cpuhreset:1;
 521       unsigned int cpuinvlpgb:1;
 522       unsigned int cputlbsync:1;
 523       unsigned int cpusnp:1;
 524       unsigned int cpurmpquery:1;
 525       CPU_FLAGS_COMMON;
 526 #ifdef CpuUnused
 527       unsigned int unused:(CpuNumOfBits - CpuUnused);
 528 #endif
 529     } bitfield;
 530   unsigned int array[CpuNumOfUints];
 531 } i386_cpu_flags;
 532
 533 /* Position of opcode_modifier bits.  */
 534
 535 enum
 536 {
 537   /* has direction bit. */
 538   D = 0,
 539   /* set if operands can be both bytes and words/dwords/qwords, encoded the
 540      canonical way; the base_opcode field should hold the encoding for byte
 541      operands  */
 542   W,
 543   /* load form instruction. Must be placed before store form.  */
 544   Load,
 545   /* insn has a modrm byte. */
 546   Modrm,
 547   /* special case for jump insns; value has to be 1 */
 548 #define JUMP 1
 549   /* call and jump */
 550 #define JUMP_DWORD 2
 551   /* loop and jecxz */
 552 #define JUMP_BYTE 3
 553   /* special case for intersegment leaps/calls */
 554 #define JUMP_INTERSEGMENT 4
 555   /* absolute address for jump */
 556 #define JUMP_ABSOLUTE 5
 557   Jump,
 558   /* FP insn memory format bit, sized by 0x4 */
 559   FloatMF,
 560   /* needs size prefix if in 32-bit mode */
 561 #define SIZE16 1
 562   /* needs size prefix if in 16-bit mode */
 563 #define SIZE32 2
 564   /* needs size prefix if in 64-bit mode */
 565 #define SIZE64 3
 566   Size,
 567   /* Check that operand sizes match.  */
 568   CheckOperandSize,
 569   /* any memory size */
 570 #define ANY_SIZE 1
 571   /* fake an extra reg operand for clr, imul and special register
 572      processing for some instructions.  */
 573 #define REG_KLUDGE 2
 574   /* deprecated fp insn, gets a warning */
 575 #define UGH 3
 576   /* An implicit xmm0 as the first operand */
 577 #define IMPLICIT_1ST_XMM0 4
 578   /* One of the operands denotes a sequence of registers, with insn-dependent
 579      constraint on the first register number.  It implicitly denotes e.g. the
 580      register group of {x,y,z}mmN - {x,y,z}mm(N + 3), in which case N ought to
 581      be a multiple of 4.
 582    */
 583 #define IMPLICIT_GROUP 5
 584   /* Default mask isn't allowed.  */
 585 #define NO_DEFAULT_MASK 6
 586   /* Address prefix changes register operand */
 587 #define ADDR_PREFIX_OP_REG 7
 588   /* Instrucion requires that destination must be distinct from source
 589      registers.  */
 590 #define DISTINCT_DEST 8
 591   /* Instruction updates stack pointer implicitly.  */
 592 #define IMPLICIT_STACK_OP 9
 593   /* Instruction zeroes upper part of register.  */
 594 #define ZERO_UPPER 10
 595   /* Instruction support SCC.  */
 596 #define SCC 11
 597   /* Instruction requires EVEX.NF to be 1.  */
 598 #define EVEX_NF 12
 599   OperandConstraint,
 600   /* instruction ignores operand size prefix and in Intel mode ignores
 601      mnemonic size suffix check.  */
 602 #define IGNORESIZE      1
 603   /* default insn size depends on mode */
 604 #define DEFAULTSIZE     2
 605   MnemonicSize,
 606   /* b suffix on instruction illegal */
 607   No_bSuf,
 608   /* w suffix on instruction illegal */
 609   No_wSuf,
 610   /* l suffix on instruction illegal */
 611   No_lSuf,
 612   /* s suffix on instruction illegal */
 613   No_sSuf,
 614   /* q suffix on instruction illegal */
 615   No_qSuf,
 616   /* instruction needs FWAIT */
 617   FWait,
 618   /* IsString provides for a quick test for string instructions, and
 619      its actual value also indicates which of the operands (if any)
 620      requires use of the %es segment.  */
 621 #define IS_STRING_ES_OP0 2
 622 #define IS_STRING_ES_OP1 3
 623   IsString,
 624   /* RegMem is for instructions with a modrm byte where the register
 625      destination operand should be encoded in the mod and regmem fields.
 626      Normally, it will be encoded in the reg field. We add a RegMem
 627      flag to indicate that it should be encoded in the regmem field.  */
 628   RegMem,
 629   /* quick test if branch instruction is MPX supported */
 630   BNDPrefixOk,
 631 #define PrefixNone              0
 632 #define PrefixRep               1
 633 #define PrefixHLERelease        2 /* Okay with an XRELEASE (0xf3) prefix. */
 634 #define PrefixNoTrack           3
 635   /* Prefixes implying "LOCK okay" must come after Lock. All others have
 636      to come before.  */
 637 #define PrefixLock              4
 638 #define PrefixHLELock           5 /* Okay with a LOCK prefix.  */
 639 #define PrefixHLEAny            6 /* Okay with or without a LOCK prefix.  */
 640   PrefixOk,
 641   /* opcode is a prefix */
 642   IsPrefix,
 643   /* instruction has extension in 8 bit imm */
 644   ImmExt,
 645   /* instruction don't need Rex64 prefix.  */
 646   NoRex64,
 647   /* insn has VEX prefix:
 648         1: 128bit VEX prefix (or operand dependent).
 649         2: 256bit VEX prefix.
 650         3: Scalar VEX prefix.
 651    */
 652 #define VEX128          1
 653 #define VEX256          2
 654 #define VEXScalar       3
 655   Vex,
 656   /* How to encode VEX.vvvv:
 657      1: VEX.vvvv encodes the src1 register operand.
 658      2: VEX.vvvv encodes the src2 register operand.
 659      3: VEX.vvvv encodes the dest register operand.
 660    */
 661 #define VexVVVV_SRC1   1
 662 #define VexVVVV_SRC2   2
 663 #define VexVVVV_DST    3
 664
 665   VexVVVV,
 666   /* How the VEX.W bit is used:
 667      0: Set by the REX.W bit.
 668      1: VEX.W0.  Should always be 0.
 669      2: VEX.W1.  Should always be 1.
 670      3: VEX.WIG. The VEX.W bit is ignored.
 671    */
 672 #define VEXW0   1
 673 #define VEXW1   2
 674 #define VEXWIG  3
 675   VexW,
 676   /* Opcode prefix (values chosen to be usable directly in
 677      VEX/XOP/EVEX pp fields):
 678      0: None
 679      1: Add 0x66 opcode prefix.
 680      2: Add 0xf3 opcode prefix.
 681      3: Add 0xf2 opcode prefix.
 682    */
 683 #define PREFIX_NONE     0
 684 #define PREFIX_0X66     1
 685 #define PREFIX_0XF3     2
 686 #define PREFIX_0XF2     3
 687   OpcodePrefix,
 688   /* Instruction with a mandatory SIB byte:
 689         1: 128bit vector register.
 690         2: 256bit vector register.
 691         3: 512bit vector register.
 692    */
 693 #define VECSIB128       1
 694 #define VECSIB256       2
 695 #define VECSIB512       3
 696 #define SIBMEM          4
 697   SIB,
 698
 699   /* SSE to AVX support required */
 700   SSE2AVX,
 701
 702   /* insn has EVEX prefix:
 703         1: 512bit EVEX prefix.
 704         2: 128bit EVEX prefix.
 705         3: 256bit EVEX prefix.
 706         4: Length-ignored (LIG) EVEX prefix.
 707         5: Length determined from actual operands.
 708         6: L'L = 3 (reserved, .insn only)
 709    */
 710 #define EVEX512                1
 711 #define EVEX128                2
 712 #define EVEX256                3
 713 #define EVEXLIG                4
 714 #define EVEXDYN                5
 715 #define EVEX_L3                6
 716   EVex,
 717
 718   /* AVX512 masking support */
 719   Masking,
 720
 721   /* AVX512 broadcast support.  The number of bytes to broadcast is
 722      1 << (Broadcast - 1):
 723         1: Byte broadcast.
 724         2: Word broadcast.
 725         3: Dword broadcast.
 726         4: Qword broadcast.
 727    */
 728 #define BYTE_BROADCAST  1
 729 #define WORD_BROADCAST  2
 730 #define DWORD_BROADCAST 3
 731 #define QWORD_BROADCAST 4
 732   Broadcast,
 733
 734   /* Static rounding control is supported.  */
 735   StaticRounding,
 736
 737   /* Supress All Exceptions is supported.  */
 738   SAE,
 739
 740   /* Compressed Disp8*N attribute.  */
 741 #define DISP8_SHIFT_VL 7
 742   Disp8MemShift,
 743
 744   /* Support encoding optimization.  */
 745   Optimize,
 746
 747   /* Language dialect.  NOTE: Order matters!  */
 748 #define INTEL_SYNTAX 1
 749 #define ATT_SYNTAX   2
 750 #define ATT_MNEMONIC 3
 751   Dialect,
 752
 753   /* Mnemonic suffix permitted in Intel syntax.  */
 754   IntelSuffix,
 755
 756   /* ISA64: Don't change the order without other code adjustments.
 757         0: Common to AMD64 and Intel64.
 758         1: AMD64.
 759         2: Intel64.
 760         3: Only in Intel64.
 761    */
 762 #define AMD64           1
 763 #define INTEL64         2
 764 #define INTEL64ONLY     3
 765   ISA64,
 766
 767   /* egprs (r16-r31) on instruction illegal. We also use it to judge
 768      whether the instruction supports pseudo-prefix {rex2}.  */
 769   NoEgpr,
 770
 771   /* No CSPAZO flags update indication.  */
 772   NF,
 773
 774   /* Instrucion requires REX2 prefix.  */
 775   Rex2,
 776
 777   /* The last bitfield in i386_opcode_modifier.  */
 778   Opcode_Modifier_Num
 779 };
 780
 781 typedef struct i386_opcode_modifier
 782 {
 783   unsigned int d:1;
 784   unsigned int w:1;
 785   unsigned int load:1;
 786   unsigned int modrm:1;
 787   unsigned int jump:3;
 788   unsigned int floatmf:1;
 789   unsigned int size:2;
 790   unsigned int checkoperandsize:1;
 791   unsigned int operandconstraint:4;
 792   unsigned int mnemonicsize:2;
 793   unsigned int no_bsuf:1;
 794   unsigned int no_wsuf:1;
 795   unsigned int no_lsuf:1;
 796   unsigned int no_ssuf:1;
 797   unsigned int no_qsuf:1;
 798   unsigned int fwait:1;
 799   unsigned int isstring:2;
 800   unsigned int regmem:1;
 801   unsigned int bndprefixok:1;
 802   unsigned int prefixok:3;
 803   unsigned int isprefix:1;
 804   unsigned int immext:1;
 805   unsigned int norex64:1;
 806   unsigned int vex:2;
 807   unsigned int vexvvvv:2;
 808   unsigned int vexw:2;
 809   unsigned int opcodeprefix:2;
 810   unsigned int sib:3;
 811   unsigned int sse2avx:1;
 812   unsigned int evex:3;
 813   unsigned int masking:1;
 814   unsigned int broadcast:3;
 815   unsigned int staticrounding:1;
 816   unsigned int sae:1;
 817   unsigned int disp8memshift:3;
 818   unsigned int optimize:1;
 819   unsigned int dialect:2;
 820   unsigned int intelsuffix:1;
 821   unsigned int isa64:2;
 822   unsigned int noegpr:1;
 823   unsigned int nf:1;
 824   unsigned int rex2:1;
 825 } i386_opcode_modifier;
 826
 827 /* Operand classes.  */
 828
 829 #define CLASS_WIDTH 4
 830 enum operand_class
 831 {
 832   ClassNone,
 833   Reg, /* GPRs and FP regs, distinguished by operand size */
 834   SReg, /* Segment register */
 835   RegCR, /* Control register */
 836   RegDR, /* Debug register */
 837   RegTR, /* Test register */
 838   RegMMX, /* MMX register */
 839   RegSIMD, /* XMM/YMM/ZMM registers, distinguished by operand size */
 840   RegMask, /* Vector Mask register */
 841   RegBND, /* Bound register */
 842 };
 843
 844 /* Special operand instances.  */
 845
 846 #define INSTANCE_WIDTH 3
 847 enum operand_instance
 848 {
 849   InstanceNone,
 850   Accum, /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */
 851   RegC,  /* %cl / %cx / %ecx / %rcx, e.g. register to hold shift count */
 852   RegD,  /* %dl / %dx / %edx / %rdx, e.g. register to hold I/O port addr */
 853   RegB,  /* %bl / %bx / %ebx / %rbx */
 854 };
 855
 856 /* Position of operand_type bits.  */
 857
 858 enum
 859 {
 860   /* Class and Instance */
 861   ClassInstance = CLASS_WIDTH + INSTANCE_WIDTH - 1,
 862   /* 1 bit immediate */
 863   Imm1,
 864   /* 8 bit immediate */
 865   Imm8,
 866   /* 8 bit immediate sign extended */
 867   Imm8S,
 868   /* 16 bit immediate */
 869   Imm16,
 870   /* 32 bit immediate */
 871   Imm32,
 872   /* 32 bit immediate sign extended */
 873   Imm32S,
 874   /* 64 bit immediate */
 875   Imm64,
 876   /* 8bit/16bit/32bit displacements are used in different ways,
 877      depending on the instruction.  For jumps, they specify the
 878      size of the PC relative displacement, for instructions with
 879      memory operand, they specify the size of the offset relative
 880      to the base register, and for instructions with memory offset
 881      such as `mov 1234,%al' they specify the size of the offset
 882      relative to the segment base.  */
 883   /* 8 bit displacement */
 884   Disp8,
 885   /* 16 bit displacement */
 886   Disp16,
 887   /* 32 bit displacement (64-bit: sign-extended) */
 888   Disp32,
 889   /* 64 bit displacement */
 890   Disp64,
 891   /* Register which can be used for base or index in memory operand.  */
 892   BaseIndex,
 893   /* BYTE size. */
 894   Byte,
 895   /* WORD size. 2 byte */
 896   Word,
 897   /* DWORD size. 4 byte */
 898   Dword,
 899   /* FWORD size. 6 byte */
 900   Fword,
 901   /* QWORD size. 8 byte */
 902   Qword,
 903   /* TBYTE size. 10 byte */
 904   Tbyte,
 905   /* XMMWORD size. */
 906   Xmmword,
 907   /* YMMWORD size. */
 908   Ymmword,
 909   /* ZMMWORD size.  */
 910   Zmmword,
 911   /* TMMWORD size.  */
 912   Tmmword,
 913   /* Unspecified memory size.  */
 914   Unspecified,
 915
 916   /* The number of bits in i386_operand_type.  */
 917   OTNum
 918 };
 919
 920 #define OTNumOfUints \
 921   ((OTNum - 1) / sizeof (unsigned int) / CHAR_BIT + 1)
 922 #define OTNumOfBits \
 923   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 924
 925 /* If you get a compiler error for zero width of the unused field,
 926    comment it out.  */
 927 #define OTUnused                OTNum
 928
 929 typedef union i386_operand_type
 930 {
 931   struct
 932     {
 933       unsigned int class:CLASS_WIDTH;
 934       unsigned int instance:INSTANCE_WIDTH;
 935       unsigned int imm1:1;
 936       unsigned int imm8:1;
 937       unsigned int imm8s:1;
 938       unsigned int imm16:1;
 939       unsigned int imm32:1;
 940       unsigned int imm32s:1;
 941       unsigned int imm64:1;
 942       unsigned int disp8:1;
 943       unsigned int disp16:1;
 944       unsigned int disp32:1;
 945       unsigned int disp64:1;
 946       unsigned int baseindex:1;
 947       unsigned int byte:1;
 948       unsigned int word:1;
 949       unsigned int dword:1;
 950       unsigned int fword:1;
 951       unsigned int qword:1;
 952       unsigned int tbyte:1;
 953       unsigned int xmmword:1;
 954       unsigned int ymmword:1;
 955       unsigned int zmmword:1;
 956       unsigned int tmmword:1;
 957       unsigned int unspecified:1;
 958 #ifdef OTUnused
 959       unsigned int unused:(OTNumOfBits - OTUnused);
 960 #endif
 961     } bitfield;
 962   unsigned int array[OTNumOfUints];
 963 } i386_operand_type;
 964
 965 typedef struct insn_template
 966 {
 967   /* instruction name sans width suffix ("mov" for movl insns) */
 968   unsigned int mnem_off;
 969
 970   /* Bitfield arrangement is such that individual fields can be easily
 971      extracted (in native builds at least) - either by at most a masking
 972      operation (base_opcode, operands), or by just a (signed) right shift
 973      (extension_opcode).  Please try to maintain this property.  */
 974
 975   /* base_opcode is the fundamental opcode byte without optional
 976      prefix(es).  */
 977   unsigned int base_opcode:16;
 978 #define Opcode_D        0x2 /* Direction bit:
 979                                set if Reg --> Regmem;
 980                                unset if Regmem --> Reg. */
 981 #define Opcode_FloatR   0x8 /* ModR/M bit to swap src/dest for float insns. */
 982 #define Opcode_FloatD   0x4 /* Direction bit for float insns. */
 983 #define Opcode_ExtD     0x1 /* Direction bit for extended opcode space insns. */
 984 #define Opcode_SIMD_IntD 0x10 /* Direction bit for SIMD int insns. */
 985 /* The next value is arbitrary, as long as it's non-zero and distinct
 986    from all other values above.  */
 987 #define Opcode_VexW     0xf /* Operand order controlled by VEX.W. */
 988
 989   /* how many operands */
 990   unsigned int operands:3;
 991
 992   /* opcode space */
 993   unsigned int opcode_space:4;
 994   /* Opcode encoding space (values chosen to be usable directly in
 995      VEX/XOP mmmmm and EVEX mmm fields):
 996      0: Base opcode space.
 997      1: 0F opcode prefix / space.
 998      2: 0F38 opcode prefix / space.
 999      3: 0F3A opcode prefix / space.
1000      4: MAP4 opcode prefix / space.
1001      5: MAP5 opcode prefix / space.
1002      6: MAP6 opcode prefix / space.
1003      7: MAP7 opcode prefix / space.
1004      8: XOP 08 opcode space.
1005      9: XOP 09 opcode space.
1006      A: XOP 0A opcode space.
1007    */
1008 #define SPACE_BASE      0
1009 #define SPACE_0F        1
1010 #define SPACE_0F38      2
1011 #define SPACE_0F3A      3
1012 #define SPACE_MAP4      4
1013 #define SPACE_MAP5      5
1014 #define SPACE_MAP6      6
1015 #define SPACE_MAP7      7
1016 #define SPACE_XOP08     8
1017 #define SPACE_XOP09     9
1018 #define SPACE_XOP0A     0xA
1019
1020 /* (Fake) base opcode value for pseudo prefixes.  */
1021 #define PSEUDO_PREFIX 0
1022
1023   /* extension_opcode is the 3 bit extension for group <n> insns.
1024      This field is also used to store the 8-bit opcode suffix for the
1025      AMD 3DNow! instructions.
1026      If this template has no extension opcode (the usual case) use None
1027      Instructions */
1028   signed int extension_opcode:9;
1029 #define None (-1)               /* If no extension_opcode is possible.  */
1030
1031 /* Pseudo prefixes.  */
1032 #define Prefix_Disp8            0       /* {disp8} */
1033 #define Prefix_Disp16           1       /* {disp16} */
1034 #define Prefix_Disp32           2       /* {disp32} */
1035 #define Prefix_Load             3       /* {load} */
1036 #define Prefix_Store            4       /* {store} */
1037 #define Prefix_VEX              5       /* {vex} */
1038 #define Prefix_VEX3             6       /* {vex3} */
1039 #define Prefix_EVEX             7       /* {evex} */
1040 #define Prefix_REX              8       /* {rex} */
1041 #define Prefix_REX2             9       /* {rex2} */
1042 #define Prefix_NoOptimize       10      /* {nooptimize} */
1043 #define Prefix_NF               11      /* {nf} */
1044
1045   /* the bits in opcode_modifier are used to generate the final opcode from
1046      the base_opcode.  These bits also are used to detect alternate forms of
1047      the same instruction */
1048   i386_opcode_modifier opcode_modifier;
1049
1050   /* cpu feature attributes */
1051   i386_cpu_attr cpu, cpu_any;
1052
1053   /* operand_types[i] describes the type of operand i.  This is made
1054      by OR'ing together all of the possible type masks.  (e.g.
1055      'operand_types[i] = Reg|Imm' specifies that operand i can be
1056      either a register or an immediate operand.  */
1057   i386_operand_type operand_types[MAX_OPERANDS];
1058 }
1059 insn_template;
1060
1061 /* these are for register name --> number & type hash lookup */
1062 typedef struct
1063 {
1064   char reg_name[8];
1065   i386_operand_type reg_type;
1066   unsigned char reg_flags;
1067 #define RegRex      0x1  /* Extended register.  */
1068 #define RegRex64    0x2  /* Extended 8 bit register.  */
1069 #define RegVRex     0x4  /* Extended vector register.  */
1070 #define RegRex2     0x8  /* Extended GPRs R16–R31 register.  */
1071   unsigned char reg_num;
1072 #define RegIP   ((unsigned char ) ~0)
1073 /* EIZ and RIZ are fake index registers.  */
1074 #define RegIZ   (RegIP - 1)
1075 /* FLAT is a fake segment register (Intel mode).  */
1076 #define RegFlat     ((unsigned char) ~0)
1077   unsigned char dw2_regnum[2];
1078 #define Dw2Inval 0xff
1079 }
1080 reg_entry;