opcodes/rl78-decode.opc

   1 /* -*- c -*- */
   2 /* Copyright (C) 2012-2024 Free Software Foundation, Inc.
   3    Contributed by Red Hat.
   4    Written by DJ Delorie.
   5
   6    This file is part of the GNU opcodes library.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3, or (at your option)
  11    any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23 #include "sysdep.h"
  24 #include <stdio.h>
  25 #include <stdlib.h>
  26 #include <string.h>
  27 #include "bfd.h"
  28 #include "opintl.h"
  29 #include "opcode/rl78.h"
  30
  31 static int trace = 0;
  32
  33 typedef struct
  34 {
  35   RL78_Opcode_Decoded * rl78;
  36   int (* getbyte)(void *);
  37   void * ptr;
  38   unsigned char * op;
  39 } LocalData;
  40
  41 #define ID(x) rl78->id = RLO_##x, rl78->lineno = __LINE__
  42 #define OP(n,t,r,a) (rl78->op[n].type = t, \
  43                      rl78->op[n].reg = r,            \
  44                      rl78->op[n].addend = a )
  45 #define OPX(n,t,r1,r2,a) \
  46         (rl78->op[n].type = t, \
  47         rl78->op[n].reg = r1, \
  48         rl78->op[n].reg2 = r2, \
  49         rl78->op[n].addend = a )
  50
  51 #define W() rl78->size = RL78_Word
  52
  53 #define AU ATTRIBUTE_UNUSED
  54
  55 #define OP_BUF_LEN 20
  56 #define GETBYTE() (ld->rl78->n_bytes < (OP_BUF_LEN - 1) ? ld->op [ld->rl78->n_bytes++] = ld->getbyte (ld->ptr): 0)
  57 #define B ((unsigned long) GETBYTE())
  58
  59 #define SYNTAX(x) rl78->syntax = x
  60
  61 #define UNSUPPORTED() \
  62   rl78->syntax = "*unknown*"
  63
  64 #define RB(x) ((x)+RL78_Reg_X)
  65 #define RW(x) ((x)+RL78_Reg_AX)
  66
  67 #define Fz      rl78->flags = RL78_PSW_Z
  68 #define Fza     rl78->flags = RL78_PSW_Z | RL78_PSW_AC
  69 #define Fzc     rl78->flags = RL78_PSW_Z | RL78_PSW_CY
  70 #define Fzac    rl78->flags = RL78_PSW_Z | RL78_PSW_AC | RL78_PSW_CY
  71 #define Fa      rl78->flags = RL78_PSW_AC
  72 #define Fc      rl78->flags = RL78_PSW_CY
  73 #define Fac     rl78->flags = RL78_PSW_AC | RL78_PSW_CY
  74
  75 #define IMMU(bytes)   immediate (bytes, 0, ld)
  76 #define IMMS(bytes)   immediate (bytes, 1, ld)
  77
  78 static int
  79 immediate (int bytes, int sign_extend, LocalData * ld)
  80 {
  81   unsigned long i = 0;
  82
  83   switch (bytes)
  84     {
  85     case 1:
  86       i |= B;
  87       if (sign_extend && (i & 0x80))
  88         i -= 0x100;
  89       break;
  90     case 2:
  91       i |= B;
  92       i |= B << 8;
  93       if (sign_extend && (i & 0x8000))
  94         i -= 0x10000;
  95       break;
  96     case 3:
  97       i |= B;
  98       i |= B << 8;
  99       i |= B << 16;
 100       if (sign_extend && (i & 0x800000))
 101         i -= 0x1000000;
 102       break;
 103     default:
 104       opcodes_error_handler
 105         /* xgettext:c-format */
 106         (_("internal error: immediate() called with invalid byte count %d"),
 107            bytes);
 108       abort();
 109     }
 110   return i;
 111 }
 112
 113 #define DC(c)           OP (0, RL78_Operand_Immediate, 0, c)
 114 #define DR(r)           OP (0, RL78_Operand_Register, RL78_Reg_##r, 0)
 115 #define DRB(r)          OP (0, RL78_Operand_Register, RB(r), 0)
 116 #define DRW(r)          OP (0, RL78_Operand_Register, RW(r), 0)
 117 #define DM(r,a)         OP (0, RL78_Operand_Indirect, RL78_Reg_##r, a)
 118 #define DM2(r1,r2,a)    OPX (0, RL78_Operand_Indirect, RL78_Reg_##r1, RL78_Reg_##r2, a)
 119 #define DE()            rl78->op[0].use_es = 1
 120 #define DB(b)           set_bit (rl78->op, b)
 121 #define DCY()           DR(PSW); DB(0)
 122 #define DPUSH()         OP (0, RL78_Operand_PreDec, RL78_Reg_SP, 0);
 123
 124 #define SC(c)           OP (1, RL78_Operand_Immediate, 0, c)
 125 #define SR(r)           OP (1, RL78_Operand_Register, RL78_Reg_##r, 0)
 126 #define SRB(r)          OP (1, RL78_Operand_Register, RB(r), 0)
 127 #define SRW(r)          OP (1, RL78_Operand_Register, RW(r), 0)
 128 #define SM(r,a)         OP (1, RL78_Operand_Indirect, RL78_Reg_##r, a)
 129 #define SM2(r1,r2,a)    OPX (1, RL78_Operand_Indirect, RL78_Reg_##r1, RL78_Reg_##r2, a)
 130 #define SE()            rl78->op[1].use_es = 1
 131 #define SB(b)           set_bit (rl78->op+1, b)
 132 #define SCY()           SR(PSW); SB(0)
 133 #define COND(c)         rl78->op[1].condition = RL78_Condition_##c
 134 #define SPOP()          OP (1, RL78_Operand_PostInc, RL78_Reg_SP, 0);
 135
 136 static void
 137 set_bit (RL78_Opcode_Operand *op, int bit)
 138 {
 139   op->bit_number = bit;
 140   switch (op->type) {
 141   case RL78_Operand_Register:
 142     op->type = RL78_Operand_Bit;
 143     break;
 144   case RL78_Operand_Indirect:
 145     op->type = RL78_Operand_BitIndirect;
 146     break;
 147   default:
 148     break;
 149   }
 150 }
 151
 152 static int
 153 saddr (int x)
 154 {
 155   if (x < 0x20)
 156     return 0xfff00 + x;
 157   return 0xffe00 + x;
 158 }
 159
 160 static int
 161 sfr (int x)
 162 {
 163   return 0xfff00 + x;
 164 }
 165
 166 #define SADDR saddr (IMMU (1))
 167 #define SFR sfr (IMMU (1))
 168
 169 int
 170 rl78_decode_opcode (unsigned long pc AU,
 171                   RL78_Opcode_Decoded * rl78,
 172                   int (* getbyte)(void *),
 173                   void * ptr,
 174                   RL78_Dis_Isa isa)
 175 {
 176   LocalData lds, * ld = &lds;
 177   unsigned char op_buf[OP_BUF_LEN] = {0};
 178   unsigned char *op = op_buf;
 179   int op0, op1;
 180
 181   lds.rl78 = rl78;
 182   lds.getbyte = getbyte;
 183   lds.ptr = ptr;
 184   lds.op = op;
 185
 186   memset (rl78, 0, sizeof (*rl78));
 187
 188  start_again:
 189
 190 /* Byte registers, not including A.  */
 191 /** VARY rba 000 010 011 100 101 110 111 */
 192 /* Word registers, not including AX.  */
 193 /** VARY ra 01 10 11 */
 194
 195 /*----------------------------------------------------------------------*/
 196 /* ES: prefix                                                           */
 197
 198 /** 0001 0001                   es:                                     */
 199   DE(); SE();
 200   op ++;
 201   pc ++;
 202   goto start_again;
 203
 204 /*----------------------------------------------------------------------*/
 205
 206 /** 0000 1111                   add     %0, %e!1                        */
 207   ID(add); DR(A); SM(None, IMMU(2)); Fzac;
 208
 209 /** 0000 1101                   add     %0, %e1                         */
 210   ID(add); DR(A); SM(HL, 0); Fzac;
 211
 212 /** 0110 0001 1000 000          add     %0, %e1                         */
 213   ID(add); DR(A); SM2(HL, B, 0); Fzac;
 214
 215 /** 0000 1110                   add     %0, %ea1                        */
 216   ID(add); DR(A); SM(HL, IMMU(1)); Fzac;
 217
 218 /** 0110 0001 1000 0010         add     %0, %e1                         */
 219   ID(add); DR(A); SM2(HL, C, 0); Fzac;
 220
 221 /** 0000 1100                   add     %0, #%1                         */
 222   ID(add); DR(A); SC(IMMU(1)); Fzac;
 223
 224 /** 0110 0001 0000 1rba         add     %0, %1                          */
 225   ID(add); DR(A); SRB(rba); Fzac;
 226
 227 /** 0000 1011                   add     %0, %1                          */
 228   ID(add); DR(A); SM(None, SADDR); Fzac;
 229
 230 /** 0110 0001 0000 0reg         add     %0, %1                          */
 231   ID(add); DRB(reg); SR(A); Fzac;
 232
 233 /** 0000 1010                   add     %0, #%1                         */
 234   ID(add); DM(None, SADDR); SC(IMMU(1)); Fzac;
 235
 236 /*----------------------------------------------------------------------*/
 237
 238 /** 0001 1111                   addc    %0, %e!1                        */
 239   ID(addc); DR(A); SM(None, IMMU(2)); Fzac;
 240
 241 /** 0001 1101                   addc    %0, %e1                         */
 242   ID(addc); DR(A); SM(HL, 0); Fzac;
 243
 244 /** 0110 0001 1001 0000         addc    %0, %e1                         */
 245   ID(addc); DR(A); SM2(HL, B, 0); Fzac;
 246
 247 /** 0110 0001 1001 0010         addc    %0, %e1                         */
 248   ID(addc); DR(A); SM2(HL, C, 0); Fzac;
 249
 250 /** 0001 1110                   addc    %0, %ea1                        */
 251   ID(addc); DR(A); SM(HL, IMMU(1)); Fzac;
 252
 253 /** 0001 1100                   addc    %0, #%1                         */
 254   ID(addc); DR(A); SC(IMMU(1)); Fzac;
 255
 256 /** 0110 0001 0001 1rba         addc    %0, %1                          */
 257   ID(addc); DR(A); SRB(rba); Fzac;
 258
 259 /** 0110 0001 0001 0reg         addc    %0, %1                          */
 260   ID(addc); DRB(reg); SR(A); Fzac;
 261
 262 /** 0001 1011                   addc    %0, %1                          */
 263   ID(addc); DR(A); SM(None, SADDR); Fzac;
 264
 265 /** 0001 1010                   addc    %0, #%1                         */
 266   ID(addc); DM(None, SADDR); SC(IMMU(1)); Fzac;
 267
 268 /*----------------------------------------------------------------------*/
 269
 270 /** 0000 0010                   addw    %0, %e!1                        */
 271   ID(add); W(); DR(AX); SM(None, IMMU(2)); Fzac;
 272
 273 /** 0110 0001 0000 1001         addw    %0, %ea1                        */
 274   ID(add); W(); DR(AX); SM(HL, IMMU(1)); Fzac;
 275
 276 /** 0000 0100                   addw    %0, #%1                         */
 277   ID(add); W(); DR(AX); SC(IMMU(2)); Fzac;
 278
 279 /** 0000 0rw1                   addw    %0, %1                          */
 280   ID(add); W(); DR(AX); SRW(rw); Fzac;
 281
 282 /** 0000 0110                   addw    %0, %1                          */
 283   ID(add); W(); DR(AX); SM(None, SADDR); Fzac;
 284
 285 /** 0001 0000                   addw    %0, #%1                         */
 286   ID(add); W(); DR(SP); SC(IMMU(1)); Fzac;
 287
 288 /*----------------------------------------------------------------------*/
 289
 290 /** 0101 1111                   and     %0, %e!1                        */
 291   ID(and); DR(A); SM(None, IMMU(2)); Fz;
 292
 293 /** 0101 1101                   and     %0, %e1                 */
 294   ID(and); DR(A); SM(HL, 0); Fz;
 295
 296 /** 0110 0001 1101 0000         and     %0, %e1                 */
 297   ID(and); DR(A); SM2(HL, B, 0); Fz;
 298
 299 /** 0101 1110                   and     %0, %ea1                        */
 300   ID(and); DR(A); SM(HL, IMMU(1)); Fz;
 301
 302 /** 0110 0001 1101 0010         and     %0, %e1                 */
 303   ID(and); DR(A); SM2(HL, C, 0); Fz;
 304
 305 /** 0101 1100                   and     %0, #%1                         */
 306   ID(and); DR(A); SC(IMMU(1)); Fz;
 307
 308 /** 0110 0001 0101 1rba         and     %0, %1                          */
 309   ID(and); DR(A); SRB(rba); Fz;
 310
 311 /** 0110 0001 0101 0reg         and     %0, %1                          */
 312   ID(and); DRB(reg); SR(A); Fz;
 313
 314 /** 0101 1011                   and     %0, %1                          */
 315   ID(and); DR(A); SM(None, SADDR); Fz;
 316
 317 /** 0101 1010                   and     %0, #%1                         */
 318   ID(and); DM(None, SADDR); SC(IMMU(1)); Fz;
 319
 320 /*----------------------------------------------------------------------*/
 321
 322 /** 0111 0001 1bit 0101         and1    cy, %e1                 */
 323   ID(and); DCY(); SM(HL, 0); SB(bit);
 324
 325 /** 0111 0001 1bit 1101         and1    cy, %1                          */
 326   ID(and); DCY(); SR(A); SB(bit);
 327
 328 /** 0111 0001 0bit 1101         and1    cy, %s1                         */
 329   ID(and); DCY(); SM(None, SFR); SB(bit);
 330
 331 /** 0111 0001 0bit 0101         and1    cy, %s1                         */
 332   ID(and); DCY(); SM(None, SADDR); SB(bit);
 333
 334 /*----------------------------------------------------------------------*/
 335
 336 /* Note that the branch insns need to be listed before the shift
 337    ones, as "shift count of zero" means "branch insn" */
 338
 339 /** 1101 1100                   bc      $%a0                            */
 340   ID(branch_cond); DC(pc+IMMS(1)+2); SR(None); COND(C);
 341
 342 /** 1101 1110                   bnc     $%a0                            */
 343   ID(branch_cond); DC(pc+IMMS(1)+2); SR(None); COND(NC);
 344
 345 /** 0110 0001 1100 0011         bh      $%a0                            */
 346   ID(branch_cond); DC(pc+IMMS(1)+3); SR(None); COND(H);
 347
 348 /** 0110 0001 1101 0011         bnh     $%a0                            */
 349   ID(branch_cond); DC(pc+IMMS(1)+3); SR(None); COND(NH);
 350
 351 /** 1101 1101                   bz      $%a0                            */
 352   ID(branch_cond); DC(pc+IMMS(1)+2); SR(None); COND(Z);
 353
 354 /** 1101 1111                   bnz     $%a0                            */
 355   ID(branch_cond); DC(pc+IMMS(1)+2); SR(None); COND(NZ);
 356
 357 /*----------------------------------------------------------------------*/
 358
 359 /** 0011 0001 1bit 0101         bf      %e1, $%a0                       */
 360   ID(branch_cond); DC(pc+IMMS(1)+3); SM(HL,0); SB(bit); COND(F);
 361
 362 /** 0011 0001 0bit 0101         bf      %1, $%a0                        */
 363   ID(branch_cond); DC(pc+IMMS(1)+3); SR(A); SB(bit); COND(F);
 364
 365 /** 0011 0001 1bit 0100         bf      %s1, $%a0                       */
 366   ID(branch_cond); SM(None, SFR); SB(bit); DC(pc+IMMS(1)+4); COND(F);
 367
 368 /** 0011 0001 0bit 0100         bf      %s1, $%a0                       */
 369   ID(branch_cond); SM(None, SADDR); SB(bit); DC(pc+IMMS(1)+4); COND(F);
 370
 371 /*----------------------------------------------------------------------*/
 372
 373 /** 1110 1100                   br      !%!a0                           */
 374   ID(branch); DC(IMMU(3));
 375
 376 /** 1110 1101                   br      %!a0                            */
 377   ID(branch); DC(IMMU(2));
 378
 379 /** 1110 1110                   br      $%!a0                           */
 380   ID(branch); DC(pc+IMMS(2)+3);
 381
 382 /** 1110 1111                   br      $%a0                            */
 383   ID(branch); DC(pc+IMMS(1)+2);
 384
 385 /** 0110 0001 1100 1011         br      ax                              */
 386   ID(branch); DR(AX);
 387
 388 /*----------------------------------------------------------------------*/
 389
 390 /** 1111 1111                   brk1                                    */
 391   ID(break);
 392
 393 /** 0110 0001 1100 1100         brk                                     */
 394   ID(break);
 395
 396 /*----------------------------------------------------------------------*/
 397
 398 /** 0011 0001 1bit 0011         bt      %e1, $%a0                       */
 399   ID(branch_cond); DC(pc+IMMS(1)+3); SM(HL,0); SB(bit); COND(T);
 400
 401 /** 0011 0001 0bit 0011         bt      %1, $%a0                        */
 402   ID(branch_cond); DC(pc+IMMS(1)+3); SR(A); SB(bit); COND(T);
 403
 404 /** 0011 0001 1bit 0010         bt      %s1, $%a0                       */
 405   ID(branch_cond); SM(None, SFR); SB(bit); DC(pc+IMMS(1)+4); COND(T);
 406
 407 /** 0011 0001 0bit 0010         bt      %s1, $%a0                       */
 408   ID(branch_cond); SM(None, SADDR); SB(bit); DC(pc+IMMS(1)+4); COND(T);
 409
 410 /*----------------------------------------------------------------------*/
 411
 412 /** 0011 0001 1bit 0001         btclr   %e1, $%a0                       */
 413   ID(branch_cond_clear); DC(pc+IMMS(1)+3); SM(HL,0); SB(bit); COND(T);
 414
 415 /** 0011 0001 0bit 0001         btclr   %1, $%a0                        */
 416   ID(branch_cond_clear); DC(pc+IMMS(1)+3); SR(A); SB(bit); COND(T);
 417
 418 /** 0011 0001 1bit 0000         btclr   %s1, $%a0                       */
 419   ID(branch_cond_clear); SM(None, SFR); SB(bit); DC(pc+IMMS(1)+4); COND(T);
 420
 421 /** 0011 0001 0bit 0000         btclr   %s1, $%a0                       */
 422   ID(branch_cond_clear); SM(None, SADDR); SB(bit); DC(pc+IMMS(1)+4); COND(T);
 423
 424 /*----------------------------------------------------------------------*/
 425
 426 /** 1111 1100                   call    !%!a0                           */
 427   ID(call); DC(IMMU(3));
 428
 429 /** 1111 1101                   call    %!a0                            */
 430   ID(call); DC(IMMU(2));
 431
 432 /** 1111 1110                   call    $%!a0                           */
 433   ID(call); DC(pc+IMMS(2)+3);
 434
 435 /** 0110 0001 11rg 1010         call    %0                              */
 436   ID(call); DRW(rg);
 437
 438 /** 0110 0001 1nnn 01mm         callt   [%x0]                           */
 439   ID(call); DM(None, 0x80 + mm*16 + nnn*2);
 440
 441 /*----------------------------------------------------------------------*/
 442
 443 /** 0111 0001 0bit 1000         clr1    %e!0                            */
 444   ID(mov); DM(None, IMMU(2)); DB(bit); SC(0);
 445
 446 /** 0111 0001 1bit 0011         clr1    %e0                             */
 447   ID(mov); DM(HL, 0); DB(bit); SC(0);
 448
 449 /** 0111 0001 1bit 1011         clr1    %0                              */
 450   ID(mov); DR(A); DB(bit); SC(0);
 451
 452 /** 0111 0001 1000 1000         clr1    cy                              */
 453   ID(mov); DCY(); SC(0);
 454
 455 /** 0111 0001 0bit 1011         clr1    %s0                             */
 456   op0 = SFR;
 457   ID(mov); DM(None, op0); DB(bit); SC(0);
 458   if (op0 == RL78_SFR_PSW && bit == 7)
 459     rl78->syntax = "di";
 460
 461 /** 0111 0001 0bit 0011         clr1    %0                              */
 462   ID(mov); DM(None, SADDR); DB(bit); SC(0);
 463
 464 /*----------------------------------------------------------------------*/
 465
 466 /** 1111 0101                   clrb    %e!0                            */
 467   ID(mov); DM(None, IMMU(2)); SC(0);
 468
 469 /** 1111 00rg                   clrb    %0                              */
 470   ID(mov); DRB(rg); SC(0);
 471
 472 /** 1111 0100                   clrb    %0                              */
 473   ID(mov); DM(None, SADDR); SC(0);
 474
 475 /*----------------------------------------------------------------------*/
 476
 477 /** 1111 0110                   clrw    %0                              */
 478   ID(mov); DR(AX); SC(0);
 479
 480 /** 1111 0111                   clrw    %0                              */
 481   ID(mov); DR(BC); SC(0);
 482
 483 /*----------------------------------------------------------------------*/
 484
 485 /** 0100 0000                   cmp     %e!0, #%1                       */
 486   ID(cmp); DM(None, IMMU(2)); SC(IMMU(1)); Fzac;
 487
 488 /** 0100 1010                   cmp     %0, #%1                         */
 489   ID(cmp); DM(None, SADDR); SC(IMMU(1)); Fzac;
 490
 491 /** 0100 1111                   cmp     %0, %e!1                        */
 492   ID(cmp); DR(A); SM(None, IMMU(2)); Fzac;
 493
 494 /** 0100 1101                   cmp     %0, %e1                         */
 495   ID(cmp); DR(A); SM(HL, 0); Fzac;
 496
 497 /** 0110 0001 1100 0000         cmp     %0, %e1                         */
 498   ID(cmp); DR(A); SM2(HL, B, 0); Fzac;
 499
 500 /** 0110 0001 1100 0010         cmp     %0, %e1                         */
 501   ID(cmp); DR(A); SM2(HL, C, 0); Fzac;
 502
 503 /** 0100 1110                   cmp     %0, %ea1                        */
 504   ID(cmp); DR(A); SM(HL, IMMU(1)); Fzac;
 505
 506 /** 0100 1100                   cmp     %0, #%1                         */
 507   ID(cmp); DR(A); SC(IMMU(1)); Fzac;
 508
 509 /** 0110 0001 0100 1rba         cmp     %0, %1                          */
 510   ID(cmp); DR(A); SRB(rba); Fzac;
 511
 512 /** 0110 0001 0100 0reg         cmp     %0, %1                          */
 513   ID(cmp); DRB(reg); SR(A); Fzac;
 514
 515 /** 0100 1011                   cmp     %0, %1                          */
 516   ID(cmp); DR(A); SM(None, SADDR); Fzac;
 517
 518 /*----------------------------------------------------------------------*/
 519
 520 /** 1101 0101                   cmp0    %e!0                            */
 521   ID(cmp); DM(None, IMMU(2)); SC(0); Fzac;
 522
 523 /** 1101 00rg                   cmp0    %0                              */
 524   ID(cmp); DRB(rg); SC(0); Fzac;
 525
 526 /** 1101 0100                   cmp0    %0                              */
 527   ID(cmp); DM(None, SADDR); SC(0); Fzac;
 528
 529 /*----------------------------------------------------------------------*/
 530
 531 /** 0110 0001 1101 1110         cmps    %0, %ea1                        */
 532   ID(cmp); DR(X); SM(HL, IMMU(1)); Fzac;
 533
 534 /*----------------------------------------------------------------------*/
 535
 536 /** 0100 0010                   cmpw    %0, %e!1                        */
 537   ID(cmp); W(); DR(AX); SM(None, IMMU(2)); Fzac;
 538
 539 /** 0110 0001 0100 1001         cmpw    %0, %ea1                        */
 540   ID(cmp); W(); DR(AX); SM(HL, IMMU(1)); Fzac;
 541
 542 /** 0100 0100                   cmpw    %0, #%1                         */
 543   ID(cmp); W(); DR(AX); SC(IMMU(2)); Fzac;
 544
 545 /** 0100 0ra1                   cmpw    %0, %1                          */
 546   ID(cmp); W(); DR(AX); SRW(ra); Fzac;
 547
 548 /** 0100 0110                   cmpw    %0, %1                          */
 549   ID(cmp); W(); DR(AX); SM(None, SADDR); Fzac;
 550
 551 /*----------------------------------------------------------------------*/
 552
 553 /** 1011 0000                   dec     %e!0                            */
 554   ID(sub); DM(None, IMMU(2)); SC(1); Fza;
 555
 556 /** 0110 0001 0110 1001         dec     %ea0                            */
 557   ID(sub); DM(HL, IMMU(1)); SC(1); Fza;
 558
 559 /** 1001 0reg                   dec     %0                              */
 560   ID(sub); DRB(reg); SC(1); Fza;
 561
 562 /** 1011 0100                   dec     %0                              */
 563   ID(sub); DM(None, SADDR); SC(1); Fza;
 564
 565 /*----------------------------------------------------------------------*/
 566
 567 /** 1011 0010                   decw    %e!0                            */
 568   ID(sub); W(); DM(None, IMMU(2)); SC(1);
 569
 570 /** 0110 0001 1000 1001         decw    %ea0                            */
 571   ID(sub); W(); DM(HL, IMMU(1)); SC(1);
 572
 573 /** 1011 0rg1                   decw    %0                              */
 574   ID(sub); W(); DRW(rg); SC(1);
 575
 576 /** 1011 0110                   decw    %0                              */
 577   ID(sub); W(); DM(None, SADDR); SC(1);
 578
 579 /*----------------------------------------------------------------------*/
 580
 581 /** 0110 0001 1110 1101         halt                                    */
 582   ID(halt);
 583
 584 /*----------------------------------------------------------------------*/
 585
 586 /** 1010 0000                   inc     %e!0                            */
 587   ID(add); DM(None, IMMU(2)); SC(1); Fza;
 588
 589 /** 0110 0001 0101 1001         inc     %ea0                            */
 590   ID(add); DM(HL, IMMU(1)); SC(1); Fza;
 591
 592 /** 1000 0reg                   inc     %0                              */
 593   ID(add); DRB(reg); SC(1); Fza;
 594
 595 /** 1010 0100                   inc     %0                              */
 596   ID(add); DM(None, SADDR); SC(1); Fza;
 597
 598 /*----------------------------------------------------------------------*/
 599
 600 /** 1010 0010                   incw    %e!0                            */
 601   ID(add); W(); DM(None, IMMU(2)); SC(1);
 602
 603 /** 0110 0001 0111 1001         incw    %ea0                            */
 604   ID(add); W(); DM(HL, IMMU(1)); SC(1);
 605
 606 /** 1010 0rg1                   incw    %0                              */
 607   ID(add); W(); DRW(rg); SC(1);
 608
 609 /** 1010 0110                   incw    %0                              */
 610   ID(add); W(); DM(None, SADDR); SC(1);
 611
 612 /*----------------------------------------------------------------------*/
 613
 614 /** 1100 1111                   mov     %e!0, #%1                       */
 615   ID(mov); DM(None, IMMU(2)); SC(IMMU(1));
 616
 617 /** 1001 1111                   mov     %e!0, %1                        */
 618   ID(mov); DM(None, IMMU(2)); SR(A);
 619
 620 /** 1001 1001                   mov     %e0, %1                         */
 621   ID(mov); DM(DE, 0); SR(A);
 622
 623 /** 1100 1010                   mov     %ea0, #%1                       */
 624   ID(mov); DM(DE, IMMU(1)); SC(IMMU(1));
 625
 626 /** 1001 1010                   mov     %ea0, %1                                */
 627   ID(mov); DM(DE, IMMU(1)); SR(A);
 628
 629 /** 1001 1011                   mov     %e0, %1                         */
 630   ID(mov); DM(HL, 0); SR(A);
 631
 632 /** 0110 0001 1101 1001         mov     %e0, %1                         */
 633   ID(mov); DM2(HL, B, 0); SR(A);
 634
 635 /** 1100 1100                   mov     %ea0, #%1                       */
 636   ID(mov); DM(HL, IMMU(1)); SC(IMMU(1));
 637
 638 /** 1001 1100                   mov     %ea0, %1                        */
 639   ID(mov); DM(HL, IMMU(1)); SR(A);
 640
 641 /** 0110 0001 1111 1001         mov     %e0, %1                         */
 642   ID(mov); DM2(HL, C, 0); SR(A);
 643
 644 /** 1100 1000                   mov     %a0, #%1                        */
 645   ID(mov); DM(SP, IMMU(1)); SC(IMMU(1));
 646
 647 /** 1001 1000                   mov     %a0, %1                         */
 648   ID(mov); DM(SP, IMMU(1)); SR(A);
 649
 650 /** 1000 1111                   mov     %0, %e!1                        */
 651   ID(mov); DR(A); SM(None, IMMU(2));
 652
 653 /** 1000 1001                   mov     %0, %e1                         */
 654   ID(mov); DR(A); SM(DE, 0);
 655
 656 /** 1000 1010                   mov     %0, %ea1                        */
 657   ID(mov); DR(A); SM(DE, IMMU(1));
 658
 659 /** 1000 1011                   mov     %0, %e1                         */
 660   ID(mov); DR(A); SM(HL, 0);
 661
 662 /** 1000 1100                   mov     %0, %ea1                        */
 663   ID(mov); DR(A); SM(HL, IMMU(1));
 664
 665 /** 0110 0001 1100 1001         mov     %0, %e1                         */
 666   ID(mov); DR(A); SM2(HL, B, 0);
 667
 668 /** 0110 0001 1110 1001         mov     %0, %e1                         */
 669   ID(mov); DR(A); SM2(HL, C, 0);
 670
 671 /** 1000 1000                   mov     %0, %ea1                        */
 672   ID(mov); DR(A); SM(SP, IMMU(1));
 673
 674 /** 0101 0reg                   mov     %0, #%1                         */
 675   ID(mov); DRB(reg); SC(IMMU(1));
 676
 677 /** 0110 0rba                   mov     %0, %1                          */
 678   ID(mov); DR(A); SRB(rba);
 679
 680 /** 1000 1110 1111 1101         mov     %0, %1                          */
 681   ID(mov); DR(A); SR(ES);
 682
 683 /** 0000 1001                   mov     %0, %e1                         */
 684   ID(mov); DR(A); SM(B, IMMU(2));
 685
 686 /** 0100 1001                   mov     %0, %e1                         */
 687   ID(mov); DR(A); SM(BC, IMMU(2));
 688
 689 /** 0010 1001                   mov     %0, %e1                         */
 690   ID(mov); DR(A); SM(C, IMMU(2));
 691
 692 /** 1000 1110                   mov     %0, %s1                         */
 693   ID(mov); DR(A); SM(None, SFR);
 694
 695 /** 1000 1101                   mov     %0, %1                          */
 696   ID(mov); DR(A); SM(None, SADDR);
 697
 698 /** 1110 1001                   mov     %0, %e!1                        */
 699   ID(mov); DR(B); SM(None, IMMU(2));
 700
 701 /** 0111 0rba                   mov     %0, %1                          */
 702   ID(mov); DRB(rba); SR(A);
 703
 704 /** 1110 1000                   mov     %0, %1                          */
 705   ID(mov); DR(B); SM(None, SADDR);
 706
 707 /** 1111 1001                   mov     %0, %e!1                        */
 708   ID(mov); DR(C); SM(None, IMMU(2));
 709
 710 /** 1111 1000                   mov     %0, %1                          */
 711   ID(mov); DR(C); SM(None, SADDR);
 712
 713 /** 1101 1001                   mov     %0, %e!1                        */
 714   ID(mov); DR(X); SM(None, IMMU(2));
 715
 716 /** 1101 1000                   mov     %0, %1                          */
 717   ID(mov); DR(X); SM(None, SADDR);
 718
 719 /** 1001 1110 1111 1100         mov     %0, %1                          */
 720   ID(mov); DR(CS); SR(A);
 721
 722 /** 0100 0001                   mov     %0, #%1                         */
 723   ID(mov); DR(ES); SC(IMMU(1));
 724
 725 /** 1001 1110 1111 1101         mov     %0, %1                          */
 726   ID(mov); DR(ES); SR(A);
 727
 728 /** 0110 0001 1011 1000         mov     %0, %1                          */
 729   ID(mov); DR(ES); SM(None, SADDR);
 730
 731 /** 0001 1001                   mov     %e0, #%1                        */
 732   ID(mov); DM(B, IMMU(2)); SC(IMMU(1));
 733
 734 /** 0001 1000                   mov     %e0, %1                         */
 735   ID(mov); DM(B, IMMU(2)); SR(A);
 736
 737 /** 0011 1001                   mov     %e0, #%1                        */
 738   ID(mov); DM(BC, IMMU(2)); SC(IMMU(1));
 739
 740 /** 0100 1000                   mov     %e0, %1                         */
 741   ID(mov); DM(BC, IMMU(2)); SR(A);
 742
 743 /** 0011 1000                   mov     %e0, #%1                        */
 744   ID(mov); DM(C, IMMU(2)); SC(IMMU(1));
 745
 746 /** 0010 1000                   mov     %e0, %1                         */
 747   ID(mov); DM(C, IMMU(2)); SR(A);
 748
 749 /** 1100 1101                   mov     %0, #%1                         */
 750   ID(mov); DM(None, SADDR); SC(IMMU(1));
 751
 752 /** 1001 1101                   mov     %0, %1                          */
 753   ID(mov); DM(None, SADDR); SR(A);
 754
 755 /** 1100 1110                   mov     %s0, #%1                        */
 756   op0 = SFR;
 757   op1 = IMMU(1);
 758   ID(mov); DM(None, op0); SC(op1);
 759   if (op0 == 0xffffb && isa == RL78_ISA_G14)
 760     switch (op1)
 761       {
 762       case 0x01:
 763         rl78->syntax = "mulhu"; ID(mulhu);
 764         break;
 765       case 0x02:
 766         rl78->syntax = "mulh"; ID(mulh);
 767         break;
 768       case 0x03:
 769         rl78->syntax = "divhu"; ID(divhu);
 770         break;
 771       case 0x04:
 772         rl78->syntax = "divwu <old-encoding>"; ID(divwu);
 773         break;
 774       case 0x05:
 775         rl78->syntax = "machu"; ID(machu);
 776         break;
 777       case 0x06:
 778         rl78->syntax = "mach"; ID(mach);
 779         break;
 780       case 0x0b:
 781         rl78->syntax = "divwu"; ID(divwu);
 782         break;
 783       }
 784
 785 /** 1001 1110                   mov     %s0, %1                         */
 786   ID(mov); DM(None, SFR); SR(A);
 787
 788 /*----------------------------------------------------------------------*/
 789
 790 /** 0111 0001 1bit 0001         mov1    %e0, cy                         */
 791   ID(mov); DM(HL, 0); DB(bit); SCY();
 792
 793 /** 0111 0001 1bit 1001         mov1    %e0, cy                         */
 794   ID(mov); DR(A); DB(bit); SCY();
 795
 796 /** 0111 0001 1bit 0100         mov1    cy, %e1                         */
 797   ID(mov); DCY(); SM(HL, 0); SB(bit);
 798
 799 /** 0111 0001 1bit 1100         mov1    cy, %e1                         */
 800   ID(mov); DCY(); SR(A); SB(bit);
 801
 802 /** 0111 0001 0bit 0100         mov1    cy, %1                          */
 803   ID(mov); DCY(); SM(None, SADDR); SB(bit);
 804
 805 /** 0111 0001 0bit 1100         mov1    cy, %s1                         */
 806   ID(mov); DCY(); SM(None, SFR); SB(bit);
 807
 808 /** 0111 0001 0bit 0001         mov1    %0, cy                          */
 809   ID(mov); DM(None, SADDR); DB(bit); SCY();
 810
 811 /** 0111 0001 0bit 1001         mov1    %s0, cy                         */
 812   ID(mov); DM(None, SFR); DB(bit); SCY();
 813
 814 /*----------------------------------------------------------------------*/
 815
 816 /** 0110 0001 1100 1110         movs    %ea0, %1                        */
 817   ID(mov); DM(HL, IMMU(1)); SR(X); Fzc;
 818
 819 /*----------------------------------------------------------------------*/
 820
 821 /** 1011 1111                   movw    %e!0, %1                        */
 822   ID(mov); W(); DM(None, IMMU(2)); SR(AX);
 823
 824 /** 1011 1001                   movw    %e0, %1                         */
 825   ID(mov); W(); DM(DE, 0); SR(AX);
 826
 827 /** 1011 1010                   movw    %ea0, %1                                */
 828   ID(mov); W(); DM(DE, IMMU(1)); SR(AX);
 829
 830 /** 1011 1011                   movw    %e0, %1                         */
 831   ID(mov); W(); DM(HL, 0); SR(AX);
 832
 833 /** 1011 1100                   movw    %ea0, %1                        */
 834   ID(mov); W(); DM(HL, IMMU(1)); SR(AX);
 835
 836 /** 1011 1000                   movw    %a0, %1                         */
 837   ID(mov); W(); DM(SP, IMMU(1)); SR(AX);
 838
 839 /** 1010 1111                   movw    %0, %e!1                        */
 840   ID(mov); W(); DR(AX); SM(None, IMMU(2));
 841
 842
 843 /** 1010 1001                   movw    %0, %e1                         */
 844   ID(mov); W(); DR(AX); SM(DE, 0);
 845
 846 /** 1010 1010                   movw    %0, %ea1                                */
 847   ID(mov); W(); DR(AX); SM(DE, IMMU(1));
 848
 849 /** 1010 1011                   movw    %0, %e1                         */
 850   ID(mov); W(); DR(AX); SM(HL, 0);
 851
 852 /** 1010 1100                   movw    %0, %ea1                        */
 853   ID(mov); W(); DR(AX); SM(HL, IMMU(1));
 854
 855 /** 1010 1000                   movw    %0, %a1                         */
 856   ID(mov); W(); DR(AX); SM(SP, IMMU(1));
 857
 858 /** 0011 0rg0                   movw    %0, #%1                         */
 859   ID(mov); W(); DRW(rg); SC(IMMU(2));
 860
 861 /** 0001 0ra1                   movw    %0, %1                          */
 862   ID(mov); W(); DR(AX); SRW(ra);
 863
 864 /** 0001 0ra0                   movw    %0, %1                          */
 865   ID(mov); W(); DRW(ra); SR(AX);
 866
 867 /** 0101 1001                   movw    %0, %e1                         */
 868   ID(mov); W(); DR(AX); SM(B, IMMU(2));
 869
 870 /** 0110 1001                   movw    %0, %e1                         */
 871   ID(mov); W(); DR(AX); SM(C, IMMU(2));
 872
 873 /** 0111 1001                   movw    %0, %e1                         */
 874   ID(mov); W(); DR(AX); SM(BC, IMMU(2));
 875
 876 /** 0101 1000                   movw    %e0, %1                         */
 877   ID(mov); W(); DM(B, IMMU(2)); SR(AX);
 878
 879 /** 0110 1000                   movw    %e0, %1                         */
 880   ID(mov); W(); DM(C, IMMU(2)); SR(AX);
 881
 882 /** 0111 1000                   movw    %e0, %1                         */
 883   ID(mov); W(); DM(BC, IMMU(2)); SR(AX);
 884
 885 /** 1010 1101                   movw    %0, %1                          */
 886   ID(mov); W(); DR(AX); SM(None, SADDR);
 887
 888 /** 1010 1110                   movw    %0, %s1                         */
 889   ID(mov); W(); DR(AX); SM(None, SFR);
 890
 891 /** 11ra 1011                   movw    %0, %es!1                       */
 892   ID(mov); W(); DRW(ra); SM(None, IMMU(2));
 893
 894 /** 11ra 1010                   movw    %0, %1                          */
 895   ID(mov); W(); DRW(ra); SM(None, SADDR);
 896
 897 /** 1100 1001                   movw    %0, #%1                         */
 898   ID(mov); W(); DM(None, SADDR); SC(IMMU(2));
 899
 900 /** 1011 1101                   movw    %0, %1                          */
 901   ID(mov); W(); DM(None, SADDR); SR(AX);
 902
 903 /** 1100 1011                   movw    %s0, #%1                        */
 904   ID(mov); W(); DM(None, SFR); SC(IMMU(2));
 905
 906 /** 1011 1110                   movw    %s0, %1                         */
 907   ID(mov); W(); DM(None, SFR); SR(AX);
 908
 909 /*----------------------------------------------------------------------*/
 910
 911 /** 1101 0110                   mulu    x                               */
 912   ID(mulu);
 913
 914 /*----------------------------------------------------------------------*/
 915
 916 /** 0000 0000                   nop                                     */
 917   ID(nop);
 918
 919 /*----------------------------------------------------------------------*/
 920
 921 /** 0111 0001 1100 0000         not1    cy                              */
 922   ID(xor); DCY(); SC(1);
 923
 924 /*----------------------------------------------------------------------*/
 925
 926 /** 1110 0101                   oneb    %e!0                            */
 927   ID(mov); DM(None, IMMU(2)); SC(1);
 928
 929 /** 1110 00rg                   oneb    %0                              */
 930   ID(mov); DRB(rg); SC(1);
 931
 932 /** 1110 0100                   oneb    %0                              */
 933   ID(mov); DM(None, SADDR); SC(1);
 934
 935 /*----------------------------------------------------------------------*/
 936
 937 /** 1110 0110                   onew    %0                              */
 938   ID(mov); DR(AX); SC(1);
 939
 940 /** 1110 0111                   onew    %0                              */
 941   ID(mov); DR(BC); SC(1);
 942
 943 /*----------------------------------------------------------------------*/
 944
 945 /** 0110 1111                   or      %0, %e!1                        */
 946   ID(or); DR(A); SM(None, IMMU(2)); Fz;
 947
 948 /** 0110 1101                   or      %0, %e1                         */
 949   ID(or); DR(A); SM(HL, 0); Fz;
 950
 951 /** 0110 0001 1110 0000         or      %0, %e1                         */
 952   ID(or); DR(A); SM2(HL, B, 0); Fz;
 953
 954 /** 0110 1110                   or      %0, %ea1                        */
 955   ID(or); DR(A); SM(HL, IMMU(1)); Fz;
 956
 957 /** 0110 0001 1110 0010         or      %0, %e1                         */
 958   ID(or); DR(A); SM2(HL, C, 0); Fz;
 959
 960 /** 0110 1100                   or      %0, #%1                         */
 961   ID(or); DR(A); SC(IMMU(1)); Fz;
 962
 963 /** 0110 0001 0110 1rba         or      %0, %1                          */
 964   ID(or); DR(A); SRB(rba); Fz;
 965
 966 /** 0110 0001 0110 0reg         or      %0, %1                          */
 967   ID(or); DRB(reg); SR(A); Fz;
 968
 969 /** 0110 1011                   or      %0, %1                          */
 970   ID(or); DR(A); SM(None, SADDR); Fz;
 971
 972 /** 0110 1010                   or      %0, #%1                         */
 973   ID(or); DM(None, SADDR); SC(IMMU(1)); Fz;
 974
 975 /*----------------------------------------------------------------------*/
 976
 977 /** 0111 0001 1bit 0110         or1     cy, %e1                         */
 978   ID(or); DCY(); SM(HL, 0); SB(bit);
 979
 980 /** 0111 0001 1bit 1110         or1     cy, %1                          */
 981   ID(or); DCY(); SR(A); SB(bit);
 982
 983 /** 0111 0001 0bit 1110         or1     cy, %s1                         */
 984   ID(or); DCY(); SM(None, SFR); SB(bit);
 985
 986 /** 0111 0001 0bit 0110         or1     cy, %s1                         */
 987   ID(or); DCY(); SM(None, SADDR); SB(bit);
 988
 989 /*----------------------------------------------------------------------*/
 990
 991 /** 1100 0rg0                   pop     %0                              */
 992   ID(mov); W(); DRW(rg); SPOP();
 993
 994 /** 0110 0001 1100 1101         pop     %s0                             */
 995   ID(mov); W(); DR(PSW); SPOP();
 996
 997 /*----------------------------------------------------------------------*/
 998
 999 /** 1100 0rg1                   push    %1                              */
1000   ID(mov); W(); DPUSH(); SRW(rg);
1001
1002 /** 0110 0001 1101 1101         push    %s1                             */
1003   ID(mov); W(); DPUSH(); SR(PSW);
1004
1005 /*----------------------------------------------------------------------*/
1006
1007 /** 1101 0111                   ret                                     */
1008   ID(ret);
1009
1010 /** 0110 0001 1111 1100         reti                                    */
1011   ID(reti);
1012
1013 /** 0110 0001 1110 1100         retb                                    */
1014   ID(reti);
1015
1016 /*----------------------------------------------------------------------*/
1017
1018 /** 0110 0001 1110 1011         rol     %0, %1                          */
1019   ID(rol); DR(A); SC(1);
1020
1021 /** 0110 0001 1101 1100         rolc    %0, %1                          */
1022   ID(rolc); DR(A); SC(1);
1023
1024 /** 0110 0001 111r 1110         rolwc   %0, %1                          */
1025   ID(rolc); W(); DRW(r); SC(1);
1026
1027 /** 0110 0001 1101 1011         ror     %0, %1                          */
1028   ID(ror); DR(A); SC(1);
1029
1030 /** 0110 0001 1111 1011         rorc    %0, %1                          */
1031   ID(rorc); DR(A); SC(1);
1032
1033 /*----------------------------------------------------------------------*/
1034
1035 /* Note that the branch insns need to be listed before the shift
1036    ones, as "shift count of zero" means "branch insn" */
1037
1038 /** 0011 0001 0cnt 1011         sar     %0, %1                          */
1039   ID(sar); DR(A); SC(cnt);
1040
1041 /** 0011 0001 wcnt 1111         sarw    %0, %1                          */
1042   ID(sar); W(); DR(AX); SC(wcnt);
1043
1044 /*----------------------------------------------------------------------*/
1045
1046 /** 0110 0001 11rb 1111         sel     rb%1                            */
1047   ID(sel); SC(rb);
1048
1049 /*----------------------------------------------------------------------*/
1050
1051 /** 0111 0001 0bit 0000         set1    %e!0                            */
1052   ID(mov); DM(None, IMMU(2)); DB(bit); SC(1);
1053
1054 /** 0111 0001 1bit 0010         set1    %e0                             */
1055   ID(mov); DM(HL, 0); DB(bit); SC(1);
1056
1057 /** 0111 0001 1bit 1010         set1    %0                              */
1058   ID(mov); DR(A); DB(bit); SC(1);
1059
1060 /** 0111 0001 1000 0000         set1    cy                              */
1061   ID(mov); DCY(); SC(1);
1062
1063 /** 0111 0001 0bit 1010         set1    %s0                             */
1064   op0 = SFR;
1065   ID(mov); DM(None, op0); DB(bit); SC(1);
1066   if (op0 == RL78_SFR_PSW && bit == 7)
1067     rl78->syntax = "ei";
1068
1069 /** 0111 0001 0bit 0010         set1    %0                              */
1070   ID(mov); DM(None, SADDR); DB(bit); SC(1);
1071
1072 /*----------------------------------------------------------------------*/
1073
1074 /** 0011 0001 0cnt 1001         shl     %0, %1                          */
1075   ID(shl); DR(A); SC(cnt);
1076
1077 /** 0011 0001 0cnt 1000         shl     %0, %1                          */
1078   ID(shl); DR(B); SC(cnt);
1079
1080 /** 0011 0001 0cnt 0111         shl     %0, %1                          */
1081   ID(shl); DR(C); SC(cnt);
1082
1083 /** 0011 0001 wcnt 1101         shlw    %0, %1                          */
1084   ID(shl); W(); DR(AX); SC(wcnt);
1085
1086 /** 0011 0001 wcnt 1100         shlw    %0, %1                          */
1087   ID(shl); W(); DR(BC); SC(wcnt);
1088
1089 /*----------------------------------------------------------------------*/
1090
1091 /** 0011 0001 0cnt 1010         shr     %0, %1                          */
1092   ID(shr); DR(A); SC(cnt);
1093
1094 /** 0011 0001 wcnt 1110         shrw    %0, %1                          */
1095   ID(shr); W(); DR(AX); SC(wcnt);
1096
1097 /*----------------------------------------------------------------------*/
1098
1099 /** 0110 0001 1100 1000         sk%c1                                   */
1100   ID(skip); COND(C);
1101
1102 /** 0110 0001 1110 0011         sk%c1                                   */
1103   ID(skip); COND(H);
1104
1105 /** 0110 0001 1101 1000         sk%c1                                   */
1106   ID(skip); COND(NC);
1107
1108 /** 0110 0001 1111 0011         sk%c1                                   */
1109   ID(skip); COND(NH);
1110
1111 /** 0110 0001 1111 1000         sk%c1                                   */
1112   ID(skip); COND(NZ);
1113
1114 /** 0110 0001 1110 1000         sk%c1                                   */
1115   ID(skip); COND(Z);
1116
1117 /*----------------------------------------------------------------------*/
1118
1119 /** 0110 0001 1111 1101 stop                                            */
1120   ID(stop);
1121
1122 /*----------------------------------------------------------------------*/
1123
1124 /** 0010 1111                   sub     %0, %e!1                        */
1125   ID(sub); DR(A); SM(None, IMMU(2)); Fzac;
1126
1127 /** 0010 1101                   sub     %0, %e1                         */
1128   ID(sub); DR(A); SM(HL, 0); Fzac;
1129
1130 /** 0110 0001 1010 000          sub     %0, %e1                         */
1131   ID(sub); DR(A); SM2(HL, B, 0); Fzac;
1132
1133 /** 0010 1110                   sub     %0, %ea1                        */
1134   ID(sub); DR(A); SM(HL, IMMU(1)); Fzac;
1135
1136 /** 0110 0001 1010 0010         sub     %0, %e1                         */
1137   ID(sub); DR(A); SM2(HL, C, 0); Fzac;
1138
1139 /** 0010 1100                   sub     %0, #%1                         */
1140   ID(sub); DR(A); SC(IMMU(1)); Fzac;
1141
1142 /** 0110 0001 0010 1rba         sub     %0, %1                          */
1143   ID(sub); DR(A); SRB(rba); Fzac;
1144
1145 /** 0010 1011                   sub     %0, %1                          */
1146   ID(sub); DR(A); SM(None, SADDR); Fzac;
1147
1148 /** 0110 0001 0010 0reg         sub     %0, %1                          */
1149   ID(sub); DRB(reg); SR(A); Fzac;
1150
1151 /** 0010 1010                   sub     %0, #%1                         */
1152   ID(sub); DM(None, SADDR); SC(IMMU(1)); Fzac;
1153
1154 /*----------------------------------------------------------------------*/
1155
1156 /** 0011 1111                   subc    %0, %e!1                        */
1157   ID(subc); DR(A); SM(None, IMMU(2)); Fzac;
1158
1159 /** 0011 1101                   subc    %0, %e1                         */
1160   ID(subc); DR(A); SM(HL, 0); Fzac;
1161
1162 /** 0110 0001 1011 0000         subc    %0, %e1                         */
1163   ID(subc); DR(A); SM2(HL, B, 0); Fzac;
1164
1165 /** 0110 0001 1011 0010         subc    %0, %e1                         */
1166   ID(subc); DR(A); SM2(HL, C, 0); Fzac;
1167
1168 /** 0011 1110                   subc    %0, %ea1                        */
1169   ID(subc); DR(A); SM(HL, IMMU(1)); Fzac;
1170
1171 /** 0011 1100                   subc    %0, #%1                         */
1172   ID(subc); DR(A); SC(IMMU(1)); Fzac;
1173
1174 /** 0110 0001 0011 1rba         subc    %0, %1                          */
1175   ID(subc); DR(A); SRB(rba); Fzac;
1176
1177 /** 0110 0001 0011 0reg         subc    %0, %1                          */
1178   ID(subc); DRB(reg); SR(A); Fzac;
1179
1180 /** 0011 1011                   subc    %0, %1                          */
1181   ID(subc); DR(A); SM(None, SADDR); Fzac;
1182
1183 /** 0011 1010                   subc    %0, #%1                         */
1184   ID(subc); DM(None, SADDR); SC(IMMU(1)); Fzac;
1185
1186 /*----------------------------------------------------------------------*/
1187
1188 /** 0010 0010                   subw    %0, %e!1                        */
1189   ID(sub); W(); DR(AX); SM(None, IMMU(2)); Fzac;
1190
1191 /** 0110 0001 0010 1001         subw    %0, %ea1                        */
1192   ID(sub); W(); DR(AX); SM(HL, IMMU(1)); Fzac;
1193
1194 /** 0010 0100                   subw    %0, #%1                         */
1195   ID(sub); W(); DR(AX); SC(IMMU(2)); Fzac;
1196
1197 /** 0010 0rw1                   subw    %0, %1                          */
1198   ID(sub); W(); DR(AX); SRW(rw); Fzac;
1199
1200 /** 0010 0110                   subw    %0, %1                          */
1201   ID(sub); W(); DR(AX); SM(None, SADDR); Fzac;
1202
1203 /** 0010 0000                   subw    %0, #%1                         */
1204   ID(sub); W(); DR(SP); SC(IMMU(1)); Fzac;
1205
1206 /*----------------------------------------------------------------------*/
1207
1208 /** 0110 0001 1010 1010         xch     %0, %e!1                        */
1209   ID(xch); DR(A); SM(None, IMMU(2));
1210
1211 /** 0110 0001 1010 1110         xch     %0, %e1                         */
1212   ID(xch); DR(A); SM(DE, 0);
1213
1214 /** 0110 0001 1010 1111         xch     %0, %ea1                                */
1215   ID(xch); DR(A); SM(DE, IMMU(1));
1216
1217 /** 0110 0001 1010 1100         xch     %0, %e1                         */
1218   ID(xch); DR(A); SM(HL, 0);
1219
1220 /** 0110 0001 1011 1001         xch     %0, %e1                         */
1221   ID(xch); DR(A); SM2(HL, B, 0);
1222
1223 /** 0110 0001 1010 1101         xch     %0, %ea1                        */
1224   ID(xch); DR(A); SM(HL, IMMU(1));
1225
1226 /** 0110 0001 1010 1001         xch     %0, %e1                         */
1227   ID(xch); DR(A); SM2(HL, C, 0);
1228
1229 /** 0110 0001 1000 1reg         xch     %0, %1                          */
1230   /* Note: DECW uses reg == X, so this must follow DECW */
1231   ID(xch); DR(A); SRB(reg);
1232
1233 /** 0110 0001 1010 1000         xch     %0, %1                          */
1234   ID(xch); DR(A); SM(None, SADDR);
1235
1236 /** 0110 0001 1010 1011         xch     %0, %s1                         */
1237   ID(xch); DR(A); SM(None, SFR);
1238
1239 /** 0000 1000                   xch     a, x                            */
1240   ID(xch); DR(A); SR(X);
1241
1242 /*----------------------------------------------------------------------*/
1243
1244 /** 0011 0ra1                   xchw    %0, %1                          */
1245   ID(xch); W(); DR(AX); SRW(ra);
1246
1247 /*----------------------------------------------------------------------*/
1248
1249 /** 0111 1111                   xor     %0, %e!1                        */
1250   ID(xor); DR(A); SM(None, IMMU(2)); Fz;
1251
1252 /** 0111 1101                   xor     %0, %e1                         */
1253   ID(xor); DR(A); SM(HL, 0); Fz;
1254
1255 /** 0110 0001 1111 0000         xor     %0, %e1                         */
1256   ID(xor); DR(A); SM2(HL, B, 0); Fz;
1257
1258 /** 0111 1110                   xor     %0, %ea1                        */
1259   ID(xor); DR(A); SM(HL, IMMU(1)); Fz;
1260
1261 /** 0110 0001 1111 0010         xor     %0, %e1                         */
1262   ID(xor); DR(A); SM2(HL, C, 0); Fz;
1263
1264 /** 0111 1100                   xor     %0, #%1                         */
1265   ID(xor); DR(A); SC(IMMU(1)); Fz;
1266
1267 /** 0110 0001 0111 1rba         xor     %0, %1                          */
1268   ID(xor); DR(A); SRB(rba); Fz;
1269
1270 /** 0110 0001 0111 0reg         xor     %0, %1                          */
1271   ID(xor); DRB(reg); SR(A); Fz;
1272
1273 /** 0111 1011                   xor     %0, %1                          */
1274   ID(xor); DR(A); SM(None, SADDR); Fz;
1275
1276 /** 0111 1010                   xor     %0, #%1                         */
1277   ID(xor); DM(None, SADDR); SC(IMMU(1)); Fz;
1278
1279 /*----------------------------------------------------------------------*/
1280
1281 /** 0111 0001 1bit 0111         xor1    cy, %e1                         */
1282   ID(xor); DCY(); SM(HL, 0); SB(bit);
1283
1284 /** 0111 0001 1bit 1111         xor1    cy, %1                          */
1285   ID(xor); DCY(); SR(A); SB(bit);
1286
1287 /** 0111 0001 0bit 1111         xor1    cy, %s1                         */
1288   ID(xor); DCY(); SM(None, SFR); SB(bit);
1289
1290 /** 0111 0001 0bit 0111         xor1    cy, %s1                         */
1291   ID(xor); DCY(); SM(None, SADDR); SB(bit);
1292
1293 /*----------------------------------------------------------------------*/
1294
1295 /** */
1296
1297   return rl78->n_bytes;
1298 }