sim/ppc/registers.h

   1 /*  This file is part of the program psim.
   2
   3     Copyright 1994, 1997, 2003 Andrew Cagney
   4
   5     This program is free software; you can redistribute it and/or modify
   6     it under the terms of the GNU General Public License as published by
   7     the Free Software Foundation; either version 3 of the License, or
   8     (at your option) any later version.
   9
  10     This program is distributed in the hope that it will be useful,
  11     but WITHOUT ANY WARRANTY; without even the implied warranty of
  12     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13     GNU General Public License for more details.
  14
  15     You should have received a copy of the GNU General Public License
  16     along with this program; if not, see <http://www.gnu.org/licenses/>.
  17
  18     */
  19
  20
  21 #ifndef _REGISTERS_H_
  22 #define _REGISTERS_H_
  23
  24
  25 /*
  26  * The PowerPC registers
  27  *
  28  */
  29
  30 /* FIXME:
  31
  32    For the moment use macro's to determine if the E500 or Altivec
  33    registers should be included.  IGEN should instead of a :register:
  34    field to facilitate the specification and generation of per ISA
  35    registers.  */
  36
  37 #ifdef WITH_E500
  38 #include "e500_registers.h"
  39 #endif
  40 #if WITH_ALTIVEC
  41 #include "altivec_registers.h"
  42 #endif
  43
  44 /**
  45  ** General Purpose Registers
  46  **/
  47
  48 typedef signed_word gpreg;
  49
  50
  51
  52 /**
  53  ** Floating Point Registers
  54  **/
  55
  56 typedef uint64_t fpreg;
  57
  58
  59
  60 /**
  61  ** The condition register
  62  **
  63  **/
  64
  65 typedef uint32_t creg;
  66
  67 /* The following sub bits are defined for the condition register */
  68 enum {
  69   cr_i_negative = BIT4(0),
  70   cr_i_positive = BIT4(1),
  71   cr_i_zero = BIT4(2),
  72   cr_i_summary_overflow = BIT4(3),
  73 #if 0
  74   /* cr0 - integer status */
  75   cr0_i_summary_overflow_bit = 3,
  76   cr0_i_negative = BIT32(0),
  77   cr0_i_positive = BIT32(1),
  78   cr0_i_zero = BIT32(2),
  79   cr0_i_summary_overflow = BIT32(3),
  80   cr0_i_mask = MASK32(0,3),
  81 #endif
  82   /* cr1 - floating-point status */
  83   cr1_i_floating_point_exception_summary_bit = 4,
  84   cr1_i_floating_point_enabled_exception_summary_bit = 5,
  85   cr1_i_floating_point_invalid_operation_exception_summary_bit = 6,
  86   cr1_i_floating_point_overflow_exception_bit = 7,
  87   cr1_i_floating_point_exception_summary = BIT32(4),
  88   cr1_i_floating_point_enabled_exception_summary = BIT32(5),
  89   cr1_i_floating_point_invalid_operation_exception_summary = BIT32(6),
  90   cr1_i_floating_point_overflow_exception = BIT32(7),
  91   cr1_i_mask = MASK32(4,7),
  92 };
  93
  94
  95 /* Condition register 1 contains the result of floating point arithmetic */
  96 enum {
  97   cr_fp_exception = BIT4(0),
  98   cr_fp_enabled_exception = BIT4(1),
  99   cr_fp_invalid_exception = BIT4(2),
 100   cr_fp_overflow_exception = BIT4(3),
 101 };
 102
 103
 104
 105 /**
 106  ** Floating-Point Status and Control Register
 107  **/
 108
 109 typedef uint32_t fpscreg;
 110 enum {
 111   fpscr_fx_bit = 0,
 112   fpscr_fx = BIT32(0),
 113   fpscr_fex_bit = 1,
 114   fpscr_fex = BIT32(1),
 115   fpscr_vx_bit = 2,
 116   fpscr_vx = BIT32(2),
 117   fpscr_ox_bit = 3,
 118   fpscr_ox = BIT32(3),
 119   fpscr_ux = BIT32(4),
 120   fpscr_zx = BIT32(5),
 121   fpscr_xx = BIT32(6),
 122   fpscr_vxsnan = BIT32(7), /* SNAN */
 123   fpscr_vxisi = BIT32(8), /* INF - INF */
 124   fpscr_vxidi = BIT32(9), /* INF / INF */
 125   fpscr_vxzdz = BIT32(10), /* 0 / 0 */
 126   fpscr_vximz = BIT32(11), /* INF * 0 */
 127   fpscr_vxvc = BIT32(12),
 128   fpscr_fr = BIT32(13),
 129   fpscr_fi = BIT32(14),
 130   fpscr_fprf = MASK32(15, 19),
 131   fpscr_c = BIT32(15),
 132   fpscr_fpcc_bit = 16, /* well sort of */
 133   fpscr_fpcc = MASK32(16, 19),
 134   fpscr_fl = BIT32(16),
 135   fpscr_fg = BIT32(17),
 136   fpscr_fe = BIT32(18),
 137   fpscr_fu = BIT32(19),
 138   fpscr_rf_quiet_nan = fpscr_c | fpscr_fu,
 139   fpscr_rf_neg_infinity = fpscr_fl | fpscr_fu,
 140   fpscr_rf_neg_normal_number = fpscr_fl,
 141   fpscr_rf_neg_denormalized_number = fpscr_c | fpscr_fl,
 142   fpscr_rf_neg_zero = fpscr_c | fpscr_fe,
 143   fpscr_rf_pos_zero = fpscr_fe,
 144   fpscr_rf_pos_denormalized_number = fpscr_c | fpscr_fg,
 145   fpscr_rf_pos_normal_number = fpscr_fg,
 146   fpscr_rf_pos_infinity = fpscr_fg | fpscr_fu,
 147   fpscr_reserved_20 = BIT32(20),
 148   fpscr_vxsoft = BIT32(21),
 149   fpscr_vxsqrt = BIT32(22),
 150   fpscr_vxcvi = BIT32(23),
 151   fpscr_ve = BIT32(24),
 152   fpscr_oe = BIT32(25),
 153   fpscr_ue = BIT32(26),
 154   fpscr_ze = BIT32(27),
 155   fpscr_xe = BIT32(28),
 156   fpscr_ni = BIT32(29),
 157   fpscr_rn = MASK32(30, 31),
 158   fpscr_rn_round_to_nearest = 0,
 159   fpscr_rn_round_towards_zero = MASK32(31,31),
 160   fpscr_rn_round_towards_pos_infinity = MASK32(30,30),
 161   fpscr_rn_round_towards_neg_infinity = MASK32(30,31),
 162   fpscr_vx_bits = (fpscr_vxsnan | fpscr_vxisi | fpscr_vxidi
 163                    | fpscr_vxzdz | fpscr_vximz | fpscr_vxvc
 164                    | fpscr_vxsoft | fpscr_vxsqrt | fpscr_vxcvi),
 165 };
 166
 167
 168
 169 /**
 170  ** XER Register
 171  **/
 172
 173 typedef uint32_t xereg;
 174
 175 enum {
 176   xer_summary_overflow = BIT32(0), xer_summary_overflow_bit = 0,
 177   xer_carry = BIT32(2), xer_carry_bit = 2,
 178   xer_overflow = BIT32(1),
 179   xer_reserved_3_24 = MASK32(3,24),
 180   xer_byte_count_mask = MASK32(25,31)
 181 };
 182
 183
 184 /**
 185  ** SPR's
 186  **/
 187
 188 #include "spreg.h"
 189
 190
 191 /**
 192  ** Segment Registers
 193  **/
 194
 195 typedef uint32_t sreg;
 196 enum {
 197   nr_of_srs = 16
 198 };
 199
 200
 201 /**
 202  ** Machine state register
 203  **/
 204 typedef unsigned_word msreg; /* 32 or 64 bits */
 205
 206 enum {
 207 #if (WITH_TARGET_WORD_BITSIZE == 64)
 208   msr_64bit_mode = BIT(0),
 209 #endif
 210 #if (WITH_TARGET_WORD_BITSIZE == 32)
 211   msr_64bit_mode = 0,
 212 #endif
 213   msr_power_management_enable = BIT(45),
 214   msr_tempoary_gpr_remapping = BIT(46), /* 603 specific */
 215   msr_interrupt_little_endian_mode = BIT(47),
 216   msr_external_interrupt_enable = BIT(48),
 217   msr_problem_state = BIT(49),
 218   msr_floating_point_available = BIT(50),
 219   msr_machine_check_enable = BIT(51),
 220   msr_floating_point_exception_mode_0 = BIT(52),
 221   msr_single_step_trace_enable = BIT(53),
 222   msr_branch_trace_enable = BIT(54),
 223   msr_floating_point_exception_mode_1 = BIT(55),
 224   msr_interrupt_prefix = BIT(57),
 225   msr_instruction_relocate = BIT(58),
 226   msr_data_relocate = BIT(59),
 227   msr_recoverable_interrupt = BIT(62),
 228   msr_little_endian_mode = BIT(63)
 229 };
 230
 231 enum {
 232   srr1_hash_table_or_ibat_miss = BIT(33),
 233   srr1_direct_store_error_exception = BIT(35),
 234   srr1_protection_violation = BIT(36),
 235   srr1_segment_table_miss = BIT(42),
 236   srr1_floating_point_enabled = BIT(43),
 237   srr1_illegal_instruction = BIT(44),
 238   srr1_priviliged_instruction = BIT(45),
 239   srr1_trap = BIT(46),
 240   srr1_subsequent_instruction = BIT(47)
 241 };
 242
 243 /**
 244  ** storage interrupt registers
 245  **/
 246
 247 typedef enum {
 248   dsisr_direct_store_error_exception = BIT32(0),
 249   dsisr_hash_table_or_dbat_miss = BIT32(1),
 250   dsisr_protection_violation = BIT32(4),
 251   dsisr_earwax_violation = BIT32(5),
 252   dsisr_store_operation = BIT32(6),
 253   dsisr_segment_table_miss = BIT32(10),
 254   dsisr_earwax_disabled = BIT32(11)
 255 } dsisr_status;
 256
 257
 258
 259 /**
 260  ** And the registers proper
 261  **/
 262 typedef struct _registers {
 263
 264   gpreg gpr[32];
 265   fpreg fpr[32];
 266   creg cr;
 267   fpscreg fpscr;
 268
 269   /* Machine state register */
 270   msreg msr;
 271
 272   /* Spr's */
 273   spreg spr[nr_of_sprs];
 274
 275   /* Segment Registers */
 276   sreg sr[nr_of_srs];
 277
 278 #if WITH_ALTIVEC
 279   struct altivec_regs altivec;
 280 #endif
 281 #if WITH_E500
 282   struct e500_regs e500;
 283 #endif
 284
 285 } registers;
 286
 287 /* dump out all the registers */
 288
 289 INLINE_REGISTERS\
 290 (void) registers_dump
 291 (registers *regs);
 292
 293
 294 /* return information on a register based on name */
 295
 296 typedef enum {
 297   reg_invalid,
 298   reg_gpr, reg_fpr, reg_spr, reg_msr,
 299   reg_cr, reg_fpscr, reg_pc, reg_sr,
 300   reg_insns, reg_stalls, reg_cycles,
 301 #ifdef WITH_ALTIVEC
 302   reg_vr, reg_vscr,
 303 #endif
 304 #ifdef WITH_E500
 305   reg_acc, reg_gprh, reg_evr,
 306 #endif
 307   nr_register_types
 308 } register_types;
 309
 310 typedef struct {
 311   register_types type;
 312   int index;
 313   int size;
 314 } register_descriptions;
 315
 316 INLINE_REGISTERS\
 317 (register_descriptions) register_description
 318 (const char reg[]);
 319
 320
 321 /* Special purpose registers by their more common names */
 322
 323 #define SPREG(N)        cpu_registers(processor)->spr[N]
 324 #define XER             SPREG(spr_xer)
 325 #define LR              SPREG(spr_lr)
 326 #define CTR             SPREG(spr_ctr)
 327 #define SRR0            SPREG(spr_srr0)
 328 #define SRR1            SPREG(spr_srr1)
 329 #define DAR             SPREG(spr_dar)
 330 #define DSISR           SPREG(spr_dsisr)
 331
 332 /* general purpose registers - indexed access */
 333 #define GPR(N)          cpu_registers(processor)->gpr[N]
 334
 335 /* segment registers */
 336 #define SEGREG(N)       cpu_registers(processor)->sr[N]
 337
 338 /* condition register */
 339 #define CR              cpu_registers(processor)->cr
 340
 341 /* machine status register */
 342 #define MSR             cpu_registers(processor)->msr
 343
 344 /* floating-point status condition register */
 345 #define FPSCR           cpu_registers(processor)->fpscr
 346
 347 #endif /* _REGISTERS_H_ */