sim/testsuite/bfin/c_dsp32mac_dr_a1_i.s

   1 //Original:/testcases/core/c_dsp32mac_dr_a1_i/c_dsp32mac_dr_a1_i.dsp
   2 // Spec Reference: dsp32mac dr a1 i (signed int)
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8
   9
  10 A1 = A0 = 0;
  11
  12 // The result accumulated in A , and stored to a reg half
  13 imm32 r0, 0xa3545abd;
  14 imm32 r1, 0xbdbcfec7;
  15 imm32 r2, 0xc1248679;
  16 imm32 r3, 0xd0069007;
  17 imm32 r4, 0xefbc4569;
  18 imm32 r5, 0xcd35500b;
  19 imm32 r6, 0xe00c800d;
  20 imm32 r7, 0xf78e900f;
  21 R0.H = ( A1 = R1.L * R0.L ), A0 = R1.L * R0.L (IS);
  22 R1 = A1.w;
  23 R2.H = ( A1 = R2.L * R3.H ), A0 = R2.H * R3.L (IS);
  24 R3 = A1.w;
  25 R4.H = ( A1 = R4.H * R5.L ), A0 += R4.H * R5.H (IS);
  26 R5 = A1.w;
  27 R6.H = ( A1 = R6.H * R7.H ), A0 += R6.L * R7.H (IS);
  28 R7 = A1.w;
  29 CHECKREG r0, 0x80005ABD;
  30 CHECKREG r1, 0xFF910EEB;
  31 CHECKREG r2, 0x7FFF8679;
  32 CHECKREG r3, 0x16C676D6;
  33 CHECKREG r4, 0x80004569;
  34 CHECKREG r5, 0xFAEA0D14;
  35 CHECKREG r6, 0x7FFF800D;
  36 CHECKREG r7, 0x010DDAA8;
  37
  38 // The result accumulated in A , and stored to a reg half (MNOP)
  39 imm32 r0, 0x63548abd;
  40 imm32 r1, 0x7dbcfec7;
  41 imm32 r2, 0xa1245679;
  42 imm32 r3, 0xb0069007;
  43 imm32 r4, 0xcfbc4569;
  44 imm32 r5, 0xFFFF8000;
  45 imm32 r6, 0x7FFF800D;
  46 imm32 r7, 0x00007FFF;
  47 R0.H = ( A1 = R1.L * R0.L ) (IS);
  48 R1 = A1.w;
  49 R2.H = ( A1 += R2.L * R3.H ) (IS);
  50 R3 = A1.w;
  51 R4.H = ( A1 = R4.H * R5.L ) (IS);
  52 R5 = A1.w;
  53 R6.H = ( A1 = R6.H * R7.H ) (IS);
  54 R7 = A1.w;
  55 CHECKREG r0, 0x7FFF8ABD;
  56 CHECKREG r1, 0x008F5EEB;
  57 CHECKREG r2, 0x80005679;
  58 CHECKREG r3, 0xE58B95C1;
  59 CHECKREG r4, 0x7FFF4569;
  60 CHECKREG r5, 0x18220000;
  61 CHECKREG r6, 0x0000800D;
  62 CHECKREG r7, 0x00000000;
  63
  64 // The result accumulated in A , and stored to a reg half (MNOP)
  65 imm32 r0, 0x5354babd;
  66 imm32 r1, 0x6dbcdec7;
  67 imm32 r2, 0x7124e679;
  68 imm32 r3, 0x80067007;
  69 imm32 r4, 0x9fbc4569;
  70 imm32 r5, 0xa235900b;
  71 imm32 r6, 0xb00c300d;
  72 imm32 r7, 0xc78ea00f;
  73  R0.H = A1 , A0 = R1.L * R0.L (IS);
  74 R1 = A1.w;
  75  R2.H = A1 , A0 = R2.H * R3.L (IS);
  76 R3 = A1.w;
  77  R4.H = A1 , A0 = R4.H * R5.H (IS);
  78 R5 = A1.w;
  79  R6.H = A1 , A0 += R6.L * R7.H (IS);
  80 R7 = A1.w;
  81 CHECKREG r0, 0x0000BABD;
  82 CHECKREG r1, 0x00000000;
  83 CHECKREG r2, 0x0000E679;
  84 CHECKREG r3, 0x00000000;
  85 CHECKREG r4, 0x00004569;
  86 CHECKREG r5, 0x00000000;
  87 CHECKREG r6, 0x0000300D;
  88 CHECKREG r7, 0x00000000;
  89
  90 // The result accumulated in A , and stored to a reg half
  91 imm32 r0, 0x33545abd;
  92 imm32 r1, 0x5dbcfec7;
  93 imm32 r2, 0x71245679;
  94 imm32 r3, 0x90060007;
  95 imm32 r4, 0xafbc4569;
  96 imm32 r5, 0xd235900b;
  97 imm32 r6, 0xc00ca00d;
  98 imm32 r7, 0x678ed00f;
  99 R0.H = ( A1 = R1.L * R0.L ) (M), A0 += R1.L * R0.L (IS);
 100 R1 = A1.w;
 101 R2.H = ( A1 += R2.L * R3.H ) (M), A0 = R2.H * R3.L (IS);
 102 R3 = A0.w;
 103 R4.H = ( A1 += R4.H * R5.L ) (M), A0 = R4.H * R5.H (IS);
 104 R5 = A1.w;
 105 R6.H = ( A1 = R6.H * R7.H ) (M), A0 += R6.L * R7.H (IS);
 106 R7 = A0.w;
 107 CHECKREG r0, 0x80005ABD;
 108 CHECKREG r1, 0xFF910EEB;
 109 CHECKREG r2, 0x7FFF5679;
 110 CHECKREG r3, 0x000317FC;
 111 CHECKREG r4, 0x7FFF4569;
 112 CHECKREG r5, 0x030D72D5;
 113 CHECKREG r6, 0x8000A00D;
 114 CHECKREG r7, 0xE78B9C22;
 115
 116 // The result accumulated in A1 MM=0, and stored to a reg half (MNOP)
 117 imm32 r0, 0x83545abd;
 118 imm32 r1, 0xa8bcfec7;
 119 imm32 r2, 0xc1845679;
 120 imm32 r3, 0x1c080007;
 121 imm32 r4, 0xe1cc8569;
 122 imm32 r5, 0x921c080b;
 123 imm32 r6, 0x7901908d;
 124 imm32 r7, 0x679e9008;
 125 R0.H = ( A1 += R1.L * R0.L ) (M,IS);
 126 R1 = A1.w;
 127 R2.H = ( A1 = R2.L * R3.H ) (M,IS);
 128 R3 = A1.w;
 129 R4.H = ( A1 += R4.H * R5.L ) (M,IS);
 130 R5 = A1.w;
 131 R6.H = ( A1 = R6.H * R7.H ) (M,IS);
 132 R7 = A1.w;
 133 CHECKREG r0, 0x80005ABD;
 134 CHECKREG r1, 0xE5B26993;
 135 CHECKREG r2, 0x7FFF5679;
 136 CHECKREG r3, 0x0977EFC8;
 137 CHECKREG r4, 0x7FFF8569;
 138 CHECKREG r5, 0x0885038C;
 139 CHECKREG r6, 0x7FFF908D;
 140 CHECKREG r7, 0x30FA159E;
 141
 142 imm32 r0, 0x03545abd;
 143 imm32 r1, 0x1dbcfec7;
 144 imm32 r2, 0x21248679;
 145 imm32 r3, 0x30069007;
 146 imm32 r4, 0x4fbc4569;
 147 imm32 r5, 0x5d35500b;
 148 imm32 r6, 0x600c800d;
 149 imm32 r7, 0x778e900f;
 150 R0.H = ( A1 -= R1.L * R0.L ), A0 = R1.L * R0.L (IS);
 151 R1 = A1.w;
 152 R2.H = ( A1 = R2.L * R3.H ), A0 -= R2.H * R3.L (IS);
 153 R3 = A1.w;
 154 R4.H = ( A1 -= R4.H * R5.L ), A0 += R4.H * R5.H (IS);
 155 R5 = A1.w;
 156 R6.H = ( A1 -= R6.H * R7.H ), A0 -= R6.L * R7.H (IS);
 157 R7 = A1.w;
 158 CHECKREG r0, 0x7FFF5ABD;
 159 CHECKREG r1, 0x316906B3;
 160 CHECKREG r2, 0x80008679;
 161 CHECKREG r3, 0xE933D6D6;
 162 CHECKREG r4, 0x80004569;
 163 CHECKREG r5, 0xD045A9C2;
 164 CHECKREG r6, 0x8000800D;
 165 CHECKREG r7, 0xA36ACF1A;
 166
 167 // The result accumulated in A , and stored to a reg half (MNOP)
 168 imm32 r0, 0x63540abd;
 169 imm32 r1, 0x7dbc1ec7;
 170 imm32 r2, 0xa1242679;
 171 imm32 r3, 0x40063007;
 172 imm32 r4, 0x1fbc4569;
 173 imm32 r5, 0x2FFF4000;
 174 imm32 r6, 0x7FFF800D;
 175 imm32 r7, 0x10007FFF;
 176 R0.H = ( A1 -= R1.L * R0.L ) (IS);
 177 R1 = A1.w;
 178 R2.H = ( A1 -= R2.L * R3.H ) (IS);
 179 R3 = A1.w;
 180 R4.H = ( A1 -= R4.H * R5.L ) (IS);
 181 R5 = A1.w;
 182 R6.H = ( A1 -= R6.H * R7.H ) (IS);
 183 R7 = A1.w;
 184 CHECKREG r0, 0x80000ABD;
 185 CHECKREG r1, 0xA220502F;
 186 CHECKREG r2, 0x80002679;
 187 CHECKREG r3, 0x98812959;
 188 CHECKREG r4, 0x80004569;
 189 CHECKREG r5, 0x90922959;
 190 CHECKREG r6, 0x8000800D;
 191 CHECKREG r7, 0x88923959;
 192
 193 // The result accumulated in A , and stored to a reg half (MNOP)
 194 imm32 r0, 0x2354babd;
 195 imm32 r1, 0x3dbcdec7;
 196 imm32 r2, 0x7424e679;
 197 imm32 r3, 0x80067007;
 198 imm32 r4, 0x95bc4569;
 199 imm32 r5, 0xa235900b;
 200 imm32 r6, 0xb06c300d;
 201 imm32 r7, 0xc787a00f;
 202  R0.H = A1 , A0 -= R1.L * R0.L (IS);
 203 R1 = A1.w;
 204  R2.H = A1 , A0 -= R2.H * R3.L (IS);
 205 R3 = A1.w;
 206  R4.H = A1 , A0 -= R4.H * R5.H (IS);
 207 R5 = A1.w;
 208  R6.H = A1 , A0 -= R6.L * R7.H (IS);
 209 R7 = A1.w;
 210 CHECKREG r0, 0x8000BABD;
 211 CHECKREG r1, 0x88923959;
 212 CHECKREG r2, 0x8000E679;
 213 CHECKREG r3, 0x88923959;
 214 CHECKREG r4, 0x80004569;
 215 CHECKREG r5, 0x88923959;
 216 CHECKREG r6, 0x8000300D;
 217 CHECKREG r7, 0x88923959;
 218
 219 // The result accumulated in A , and stored to a reg half
 220 imm32 r0, 0x33545abd;
 221 imm32 r1, 0x5dbcfec7;
 222 imm32 r2, 0x71245679;
 223 imm32 r3, 0x90060007;
 224 imm32 r4, 0xafbc4569;
 225 imm32 r5, 0xd235900b;
 226 imm32 r6, 0xc00ca00d;
 227 imm32 r7, 0x678ed00f;
 228 R0.H = ( A1 -= R1.L * R0.L ) (M), A0 += R1.L * R0.L (IS);
 229 R1 = A1.w;
 230 R2.H = ( A1 -= R2.L * R3.H ) (M), A0 = R2.H * R3.L (IS);
 231 R3 = A0.w;
 232 R4.H = ( A1 += R4.H * R5.L ) (M), A0 -= R4.H * R5.H (IS);
 233 R5 = A1.w;
 234 R6.H = ( A1 -= R6.H * R7.H ) (M), A0 += R6.L * R7.H (IS);
 235 R7 = A0.w;
 236 CHECKREG r0, 0x80005ABD;
 237 CHECKREG r1, 0x89012A6E;
 238 CHECKREG r2, 0x80005679;
 239 CHECKREG r3, 0x000317FC;
 240 CHECKREG r4, 0x80004569;
 241 CHECKREG r5, 0x2B3160AC;
 242 CHECKREG r6, 0x8000A00D;
 243 CHECKREG r7, 0xCAD78046;
 244
 245 // The result accumulated in A1 MM=0, and stored to a reg half (MNOP)
 246 imm32 r0, 0x83545abd;
 247 imm32 r1, 0xa8bcfec7;
 248 imm32 r2, 0xc1845679;
 249 imm32 r3, 0x1c080007;
 250 imm32 r4, 0xe1cc8569;
 251 imm32 r5, 0x921c080b;
 252 imm32 r6, 0x7901908d;
 253 imm32 r7, 0x679e9008;
 254 R0.H = ( A1 -= R1.L * R0.L ) (M,IS);
 255 R1 = A1.w;
 256 R2.H = ( A1 -= R2.L * R3.H ) (M,IS);
 257 R3 = A1.w;
 258 R4.H = ( A1 -= R4.H * R5.L ) (M,IS);
 259 R5 = A1.w;
 260 R6.H = ( A1 -= R6.H * R7.H ) (M,IS);
 261 R7 = A1.w;
 262 CHECKREG r0, 0x80005ABD;
 263 CHECKREG r1, 0x457EF719;
 264 CHECKREG r2, 0x80005679;
 265 CHECKREG r3, 0x3C070751;
 266 CHECKREG r4, 0x80008569;
 267 CHECKREG r5, 0x3CF9F38D;
 268 CHECKREG r6, 0x8000908D;
 269 CHECKREG r7, 0x0BFFDDEF;
 270
 271
 272
 273 pass