sim/testsuite/bfin/c_dsp32mac_pair_a1a0_is.s

   1 //Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1a0_is/c_dsp32mac_pair_a1a0_is.dsp
   2 // Spec Reference: dsp32mac pair a1a0 IS
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8         A1 = A0 = 0;
   9
  10 // The result accumulated in A       , and stored to a reg half
  11         imm32 r0, 0x63545abd;
  12         imm32 r1, 0x86bcfec7;
  13         imm32 r2, 0xa8645679;
  14         imm32 r3, 0x00860007;
  15         imm32 r4, 0xefb86569;
  16         imm32 r5, 0x1235860b;
  17         imm32 r6, 0x000c086d;
  18         imm32 r7, 0x678e0086;
  19         R7 = ( A1 += R4.L * R0.L ),  R6 = ( A0 = R4.L * R0.L )  (ISS2);
  20         P1 = A1.w;
  21         P2 = A0.w;
  22         R1 = ( A1 = R3.L * R1.L ),  R0 = ( A0 = R3.H * R1.L )  (ISS2);
  23         P3 = A1.w;
  24         P4 = A0.w;
  25         R3 = ( A1 = R7.L * R2.L ),  R2 = ( A0 += R7.H * R2.H )  (ISS2);
  26         P5 = A1.w;
  27         SP = A0.w;
  28         R5 = ( A1 += R5.L * R6.L ),  R4 = ( A0 += R5.L * R6.H )  (ISS2);
  29         FP = A1.w;
  30         CHECKREG r0, 0xFFFEB854;
  31         CHECKREG r1, 0xFFFFEEE2;
  32         CHECKREG r2, 0xCECAD1AC;
  33         CHECKREG r3, 0xB509D374;
  34         CHECKREG r4, 0x8A4CA32E;
  35         CHECKREG r5, 0x1EC2C250;
  36         CHECKREG r6, 0x47E3910A;
  37         CHECKREG r7, 0x47E3910A;
  38         CHECKREG p1, 0x23F1C885;
  39         CHECKREG p2, 0x23F1C885;
  40         CHECKREG p3, 0xFFFFF771;
  41         CHECKREG p4, 0xFFFF5C2A;
  42         CHECKREG p5, 0xDA84E9BA;
  43         CHECKREG sp, 0xE76568D6;
  44         CHECKREG fp, 0x0F616128;
  45
  46         imm32 r0, 0x98764abd;
  47         imm32 r1, 0xa1bcf4c7;
  48         imm32 r2, 0xa1145649;
  49         imm32 r3, 0x00010005;
  50         imm32 r4, 0xefbc1569;
  51         imm32 r5, 0x1235010b;
  52         imm32 r6, 0x000c001d;
  53         imm32 r7, 0x678e0001;
  54         R5 = ( A1 += R4.L * R0.H ),  R4 = ( A0 = R4.L * R0.L )  (ISS2);
  55         P1 = A1.w;
  56         P2 = A0.w;
  57         R1 = ( A1 = R2.L * R3.H ),  R0 = ( A0 = R2.H * R3.L )  (ISS2);
  58         P2 = A0.w;
  59         P3 = A1.w;
  60         P4 = A0.w;
  61         R3 = ( A1 = R7.L * R5.H ),  R2 = ( A0 += R7.H * R5.H )  (ISS2);
  62         P5 = A1.w;
  63         SP = A0.w;
  64         R1 = ( A1 += R6.L * R1.H ),  R0 = ( A0 += R6.L * R1.H )  (ISS2);
  65         FP = A0.w;
  66         CHECKREG r0, 0x0ADC2224;
  67         CHECKREG r1, 0x00001AE2;
  68         CHECKREG r2, 0x0ADC2224;
  69         CHECKREG r3, 0x00001AE2;
  70         CHECKREG r4, 0x0C80510A;
  71         CHECKREG r5, 0x0D712F1C;
  72         CHECKREG r6, 0x000C001D;
  73         CHECKREG r7, 0x678E0001;
  74         CHECKREG p1, 0x06B8978E;
  75         CHECKREG p2, 0xFFFE2564;
  76         CHECKREG p3, 0x00005649;
  77         CHECKREG p4, 0xFFFE2564;
  78         CHECKREG p5, 0x00000D71;
  79         CHECKREG sp, 0x056E1112;
  80         CHECKREG fp, 0x056E1112;
  81
  82         imm32 r0, 0x7136459d;
  83         imm32 r1, 0xabd69ec7;
  84         imm32 r2, 0x71145679;
  85         imm32 r3, 0x08010007;
  86         imm32 r4, 0xef9c1569;
  87         imm32 r5, 0x1225010b;
  88         imm32 r6, 0x0003401d;
  89         imm32 r7, 0x678e0561;
  90         R5 = ( A1 += R1.H * R0.L ),  R4 = ( A0 = R1.L * R0.L )  (ISS2);
  91         P1 = A1.w;
  92         P2 = A0.w;
  93         R7 = ( A1 = R6.H * R3.L ),  R6 = ( A0 = R6.H * R3.L )  (ISS2);
  94         P3 = A1.w;
  95         P4 = A0.w;
  96         R1 = ( A1 = R4.H * R5.L ),  R0 = ( A0 += R4.H * R5.H )  (ISS2);
  97         P5 = A1.w;
  98         SP = A0.w;
  99         R5 = ( A1 += R2.H * R7.L ),  R4 = ( A0 += R2.L * R7.H )  (ISS2);
 100         FP = A0.w;
 101         CHECKREG r0, 0x12E88AAA;
 102         CHECKREG r1, 0xE779EB80;
 103         CHECKREG r2, 0x71145679;
 104         CHECKREG r3, 0x08010007;
 105         CHECKREG r4, 0x12E88AAA;
 106         CHECKREG r5, 0xE79F0610;
 107         CHECKREG r6, 0x0000002A;
 108         CHECKREG r7, 0x0000002A;
 109         CHECKREG p1, 0xE91D1DAF;
 110         CHECKREG p2, 0xE590030B;
 111         CHECKREG p3, 0x00000015;
 112         CHECKREG p5, 0xF3BCF5C0;
 113         CHECKREG p4, 0x00000015;
 114         CHECKREG sp, 0x09744555;
 115         CHECKREG fp, 0x09744555;
 116
 117         imm32 r0, 0x123489bd;
 118         imm32 r1, 0x91bcfec7;
 119         imm32 r2, 0xa9145679;
 120         imm32 r3, 0xd0910007;
 121         imm32 r4, 0xedb91569;
 122         imm32 r5, 0xd235910b;
 123         imm32 r6, 0x0d0c0999;
 124         imm32 r7, 0x67de0009;
 125         R1 = ( A1 += R5.H * R3.H ),  R0 = ( A0 = R5.L * R3.L )  (ISS2);
 126         P1 = A1.w;
 127         P2 = A0.w;
 128         R3 = ( A1 = R2.H * R1.H ),  R2 = ( A0 = R2.H * R1.L )  (ISS2);
 129         P3 = A1.w;
 130         P4 = A0.w;
 131         R5 = ( A1 = R7.H * R0.H ),  R4 = ( A0 += R7.H * R0.H )  (ISS2);
 132         P5 = A1.w;
 133         SP = A0.w;
 134         R7 = ( A1 += R4.H * R6.H ),  R6 = ( A0 += R4.L * R6.H )  (ISS2);
 135         FP = A0.w;
 136         CHECKREG r0, 0xFFF9EE9A;
 137         CHECKREG r1, 0xF897461A;
 138         CHECKREG r2, 0xD0654810;
 139         CHECKREG r3, 0x05083598;
 140         CHECKREG r4, 0xD05F99EC;
 141         CHECKREG r5, 0xFFFA51DC;
 142         CHECKREG r6, 0xC5F8000C;
 143         CHECKREG r7, 0xFB1F80C4;
 144         CHECKREG p1, 0xFC4BA30D;
 145         CHECKREG p2, 0xFFFCF74D;
 146         CHECKREG p3, 0x02841ACC;
 147         CHECKREG p4, 0xE832A408;
 148         CHECKREG p5, 0xFFFD28EE;
 149         CHECKREG sp, 0xE82FCCF6;
 150         CHECKREG fp, 0xE2FC0006;
 151
 152         imm32 r0, 0x63545abd;
 153         imm32 r1, 0x86bcfec7;
 154         imm32 r2, 0xa8645679;
 155         imm32 r3, 0x00860007;
 156         imm32 r4, 0xefb86569;
 157         imm32 r5, 0x1235860b;
 158         imm32 r6, 0x000c086d;
 159         imm32 r7, 0x678e0086;
 160         R7 = ( A1 += R1.L * R0.L ) (M),  R6 = ( A0 = R1.L * R0.L )  (ISS2);
 161         P1 = A1.w;
 162         P2 = A0.w;
 163         R1 = ( A1 = R2.L * R3.L ) (M),  R0 = ( A0 = R2.H * R3.L )  (ISS2);
 164         P3 = A1.w;
 165         P4 = A0.w;
 166         R3 = ( A1 = R7.L * R4.L ) (M),  R2 = ( A0 += R7.H * R4.H )  (ISS2);
 167         P5 = A1.w;
 168         SP = A0.w;
 169         R5 = ( A1 += R6.L * R5.L ) (M),  R4 = ( A0 += R6.L * R5.H )  (ISS2);
 170         FP = A0.w;
 171         CHECKREG r0, 0xFFFB3578;
 172         CHECKREG r1, 0x0004BA9E;
 173         CHECKREG r2, 0x00B650E8;
 174         CHECKREG r3, 0xB2D59E54;
 175         CHECKREG r4, 0x04F4C384;
 176         CHECKREG r5, 0xD21436B8;
 177         CHECKREG r6, 0xFF221DD6;
 178         CHECKREG r7, 0xFA419E9A;
 179         CHECKREG p1, 0xFD20CF4D;
 180         CHECKREG p2, 0xFF910EEB;
 181         CHECKREG p3, 0x00025D4F;
 182         CHECKREG p4, 0xFFFD9ABC;
 183         CHECKREG p5, 0xD96ACF2A;
 184         CHECKREG sp, 0x005B2874;
 185         CHECKREG fp, 0x027A61C2;
 186
 187         imm32 r0, 0x98764abd;
 188         imm32 r1, 0xa1bcf4c7;
 189         imm32 r2, 0xa1145649;
 190         imm32 r3, 0x00010005;
 191         imm32 r4, 0xefbc1569;
 192         imm32 r5, 0x1235010b;
 193         imm32 r6, 0x000c001d;
 194         imm32 r7, 0x678e0001;
 195         R5 = A1,  R4 = ( A0 = R1.L * R0.L )  (ISS2);
 196         P1 = A1.w;
 197         P2 = A0.w;
 198         R1 = A1,  R0 = ( A0 = R4.H * R3.L )  (ISS2);
 199         P3 = A1.w;
 200         P4 = A0.w;
 201         R3 = A1,  R2 = ( A0 += R2.H * R5.H )  (ISS2);
 202         P5 = A1.w;
 203         SP = A0.w;
 204         R1 = A1,  R0 = ( A0 += R6.L * R7.H )  (ISS2);
 205         FP = A1.w;
 206         CHECKREG r0, 0x22252FC0;
 207         CHECKREG r1, 0xD21436B8;
 208         CHECKREG r2, 0x220DB994;
 209         CHECKREG r3, 0xD21436B8;
 210         CHECKREG r4, 0xF97279D6;
 211         CHECKREG r5, 0xD21436B8;
 212         CHECKREG r6, 0x000C001D;
 213         CHECKREG r7, 0x678E0001;
 214         CHECKREG p1, 0xE90A1B5C;
 215         CHECKREG p2, 0xFCB93CEB;
 216         CHECKREG p3, 0xE90A1B5C;
 217         CHECKREG p4, 0xFFFFDF3A;
 218         CHECKREG p5, 0xE90A1B5C;
 219         CHECKREG sp, 0x1106DCCA;
 220         CHECKREG fp, 0xE90A1B5C;
 221
 222         imm32 r0, 0x7136459d;
 223         imm32 r1, 0xabd69ec7;
 224         imm32 r2, 0x71145679;
 225         imm32 r3, 0x08010007;
 226         imm32 r4, 0xef9c1569;
 227         imm32 r5, 0x1225010b;
 228         imm32 r6, 0x0003401d;
 229         imm32 r7, 0x678e0561;
 230         R5 = ( A1 += R1.H * R0.L ) (M),  R4 = ( A0 = R1.L * R0.L )  (ISS2);
 231         P1 = A1.w;
 232         P2 = A0.w;
 233         R7 = A1,  R6 = ( A0 = R2.H * R3.L )  (ISS2);
 234         P3 = A1.w;
 235         P4 = A0.w;
 236         R1 = ( A1 = R4.H * R5.L ) (M),  R0 = ( A0 += R4.H * R5.H )  (ISS2);
 237         P5 = A1.w;
 238         SP = A0.w;
 239         R5 = A1,  R4 = ( A0 += R6.L * R7.H )  (ISS2);
 240         FP = A1.w;
 241         CHECKREG r0, 0x25E6F698;
 242         CHECKREG r1, 0xDBFA4500;
 243         CHECKREG r2, 0x71145679;
 244         CHECKREG r3, 0x08010007;
 245         CHECKREG r4, 0x042A6938;
 246         CHECKREG r5, 0xDBFA4500;
 247         CHECKREG r6, 0x00062F18;
 248         CHECKREG r7, 0xA44E5734;
 249         CHECKREG p1, 0xD2272B9A;
 250         CHECKREG p2, 0xE590030B;
 251         CHECKREG p3, 0xD2272B9A;
 252         CHECKREG p4, 0x0003178C;
 253         CHECKREG p5, 0xEDFD2280;
 254         CHECKREG sp, 0x12F37B4C;
 255         CHECKREG fp, 0xEDFD2280;
 256
 257         imm32 r0, 0x123489bd;
 258         imm32 r1, 0x91bcfec7;
 259         imm32 r2, 0xa9145679;
 260         imm32 r3, 0xd0910007;
 261         imm32 r4, 0xedb91569;
 262         imm32 r5, 0xd235910b;
 263         imm32 r6, 0x0d0c0999;
 264         imm32 r7, 0x67de0009;
 265         R1 = A1,  R0 = ( A0 = R5.L * R3.L )  (ISS2);
 266         P1 = A1.w;
 267         P2 = A0.w;
 268         R3 = ( A1 = R2.H * R1.H ) (M),  R2 = ( A0 = R2.H * R1.L )  (ISS2);
 269         P3 = A1.w;
 270         P4 = A0.w;
 271         R5 = ( A1 = R7.H * R0.H ) (M),  R4 = ( A0 += R7.H * R0.H )  (ISS2);
 272         P5 = A0.w;
 273         SP = A1.w;
 274         R7 = A1,  R6 = ( A0 += R4.L * R6.H )  (ISS2);
 275         FP = A0.w;
 276         CHECKREG r0, 0xFFF9EE9A;
 277         CHECKREG r1, 0xDBFA4500;
 278         CHECKREG r2, 0xD124C800;
 279         CHECKREG r3, 0x80000000;
 280         CHECKREG r4, 0xD11F19DC;
 281         CHECKREG r5, 0x7FFFFFFF;
 282         CHECKREG r6, 0xD3C1DE7C;
 283         CHECKREG r7, 0x7FFFFFFF;
 284         CHECKREG p1, 0xEDFD2280;
 285         CHECKREG p2, 0xFFFCF74D;
 286         CHECKREG p3, 0xB54F3988;
 287         CHECKREG p4, 0xE8926400;
 288         CHECKREG p5, 0xE88F8CEE;
 289         CHECKREG sp, 0x67DB28EE;
 290         CHECKREG fp, 0xE9E0EF3E;
 291
 292         pass