1 //Original
:testcases
/core
/c_ldstidxl_ld_dr_xh
/c_ldstidxl_ld_dr_xh.dsp
2 // Spec Reference
: c_ldstidxl load dreg XH
(ld with indexed addressing
)
5 .include "testutils.inc"
19 I1
= P3; P3
= I0; I3
= SP; SP
= I2;
20 loadsym p1
, DATA_ADDR_1
, 0x00;
21 loadsym p2
, DATA_ADDR_2
, 0xA0;
22 loadsym i1
, DATA_ADDR_1
, 0x70;
23 loadsym p4
, DATA_ADDR_2
, 0x70;
24 loadsym p5
, DATA_ADDR_1
, 0x70;
25 loadsym fp
, DATA_ADDR_2
, 0x70;
26 loadsym i3
, DATA_ADDR_1
, 0x70;
29 R0 = W
[ P1
+ 154 ] (X
);
30 R1 = W
[ P1
+ 84 ] (X
);
31 R2 = W
[ P1
+ 48 ] (X
);
32 R3 = W
[ P1
+ 10 ] (X
);
33 R4 = W
[ P1
+ 34 ] (X
);
34 R5 = W
[ P1
+ 20 ] (X
);
35 R6 = W
[ P1
+ 126 ] (X
);
36 R7 = W
[ P1
+ 154 ] (X
);
37 CHECKREG
r0, 0x00000405;
38 CHECKREG
r1, 0x00002425;
39 CHECKREG
r2, 0xFFFF8485;
40 CHECKREG
r3, 0x00000809;
41 CHECKREG
r4, 0x00001122;
42 CHECKREG
r5, 0x00001617;
43 CHECKREG
r6, 0x00006263;
44 CHECKREG
r7, 0x00000405;
46 R0 = W
[ P2
+ -120 ] (X
);
47 R1 = W
[ P2
+ -114 ] (X
);
48 R2 = W
[ P2
+ -36 ] (X
);
49 R3 = W
[ P2
+ -22 ] (X
);
50 R4 = W
[ P2
+ -44 ] (X
);
51 R5 = W
[ P2
+ -6 ] (X
);
52 R6 = W
[ P2
+ -52 ] (X
);
53 R7 = W
[ P2
+ -146 ] (X
);
54 CHECKREG
r0, 0xFFFFD5D6;
55 CHECKREG
r1, 0xFFFFD7D8;
56 CHECKREG
r2, 0x0000565A;
57 CHECKREG
r3, 0xFFFFA667;
58 CHECKREG
r4, 0xFFFF99EA;
59 CHECKREG
r5, 0x00004C4D;
60 CHECKREG
r6, 0xFFFF99EA;
61 CHECKREG
r7, 0x00004C4D;
63 R0 = W
[ P3
+ 56 ] (X
);
64 R1 = W
[ P3
+ 62 ] (X
);
65 R2 = W
[ P3
+ -64 ] (X
);
66 R3 = W
[ P3
+ 60 ] (X
);
67 R4 = W
[ P3
+ -56 ] (X
);
68 R5 = W
[ P3
+ 10 ] (X
);
69 R6 = W
[ P3
+ -28 ] (X
);
70 R7 = W
[ P3
+ -110 ] (X
);
71 CHECKREG
r0, 0x00001617;
72 CHECKREG
r1, 0x00001819;
73 CHECKREG
r2, 0xFFFF8485;
74 CHECKREG
r3, 0x00001A1B;
75 CHECKREG
r4, 0xFFFF8283;
76 CHECKREG
r5, 0x00005859;
77 CHECKREG
r6, 0x00002425;
78 CHECKREG
r7, 0x00000001;
80 R0 = W
[ P4
+ 42 ] (X
);
81 R1 = W
[ P4
+ -40 ] (X
);
82 R2 = W
[ P4
+ 38 ] (X
);
83 R3 = W
[ P4
+ -32 ] (X
);
84 R4 = W
[ P4
+ 28 ] (X
);
85 R5 = W
[ P4
+ 26 ] (X
);
86 R6 = W
[ P4
+ -22 ] (X
);
87 R7 = W
[ P4
+ 106 ] (X
);
88 CHECKREG
r0, 0x00004C4D;
89 CHECKREG
r1, 0xFFFF99EA;
90 CHECKREG
r2, 0x00004849;
91 CHECKREG
r3, 0xFFFF99EA;
92 CHECKREG
r4, 0x00004243;
93 CHECKREG
r5, 0xFFFFA667;
94 CHECKREG
r6, 0xFFFF98E8;
95 CHECKREG
r7, 0xFFFF95E8;
97 R0 = W
[ P5
+ -14 ] (X
);
98 R1 = W
[ P5
+ 12 ] (X
);
99 R2 = W
[ P5
+ -6 ] (X
);
100 R3 = W
[ P5
+ 4 ] (X
);
101 R4 = W
[ P5
+ 0 ] (X
);
102 R5 = W
[ P5
+ -2 ] (X
);
103 R6 = W
[ P5
+ 8 ] (X
);
104 R7 = W
[ P5
+ -108 ] (X
);
105 CHECKREG
r0, 0x00003435;
106 CHECKREG
r1, 0x00006465;
107 CHECKREG
r2, 0x00004243;
108 CHECKREG
r3, 0x00005657;
109 CHECKREG
r4, 0x00005253;
110 CHECKREG
r5, 0x00004647;
111 CHECKREG
r6, 0x00006061;
112 CHECKREG
r7, 0x00000607;
114 R0 = W
[ FP
+ 90 ] (X
);
115 R1 = W
[ FP
+ -14 ] (X
);
116 R2 = W
[ FP
+ 42 ] (X
);
117 R3 = W
[ FP
+ -66 ] (X
);
118 R4 = W
[ FP
+ 26 ] (X
);
119 R5 = W
[ FP
+ -34 ] (X
);
120 R6 = W
[ FP
+ 38 ] (X
);
121 R7 = W
[ FP
+ -98 ] (X
);
122 CHECKREG
r0, 0xFFFF91E8;
123 CHECKREG
r1, 0xFFFF91E8;
124 CHECKREG
r2, 0x00004C4D;
125 CHECKREG
r3, 0xFFFFD7D8;
126 CHECKREG
r4, 0xFFFFA667;
127 CHECKREG
r5, 0xFFFF95E8;
128 CHECKREG
r6, 0x00004849;
129 CHECKREG
r7, 0x00004C4D;
131 R0 = W
[ SP
+ 46 ] (X
);
132 R1 = W
[ SP
+ -42 ] (X
);
133 R2 = W
[ SP
+ 48 ] (X
);
134 R3 = W
[ SP
+ 50 ] (X
);
135 R4 = W
[ SP
+ -102 ] (X
);
136 R5 = W
[ SP
+ 82 ] (X
);
137 R6 = W
[ SP
+ 62 ] (X
);
138 R7 = W
[ SP
+ 46 ] (X
);
139 CHECKREG
r0, 0x00000809;
140 CHECKREG
r1, 0x00000506;
141 CHECKREG
r2, 0x00000E0F;
142 CHECKREG
r3, 0x00000C0D;
143 CHECKREG
r4, 0x00000809;
144 CHECKREG
r5, 0x00007475;
145 CHECKREG
r6, 0x00001819;
146 CHECKREG
r7, 0x00000809;
151 // Pre-load memory with known data
152 // More data is defined than will actually
be used