sim/testsuite/bfin/dbg_tr_basic.S

   1 //Original:/proj/frio/dv/testcases/debug/dbg_tr_basic/dbg_tr_basic.dsp
   2 // Description: Verify the basic functionality of TBUFPWR and TBUFEN in
   3 //              Supervisor mode
   4 # mach: bfin
   5 # sim: --environment operating
   6
   7 #include "test.h"
   8 .include "testutils.inc"
   9 start
  10
  11 include(std.inc)
  12 include(mmrs.inc)
  13 include(selfcheck.inc)
  14
  15 #ifndef ITABLE
  16 #define ITABLE           0xF0000000
  17 #endif
  18
  19 // This test embeds .text offsets, so pad our test so it lines up.
  20 .space 0x70
  21
  22 // Boot code
  23
  24  BOOT :
  25 INIT_R_REGS(0);                             // Initialize Dregs
  26 INIT_P_REGS(0);                             // Initialize Pregs
  27
  28 CHECK_INIT(p5,   0x00BFFFFC);
  29
  30 LD32(p0, EVT0);              // Setup Event Vectors and Handlers
  31
  32 LD32_LABEL(r0, EHANDLE);    // Emulation Handler (Int0)
  33         [ P0 ++ ] = R0;
  34
  35 LD32_LABEL(r0, RHANDLE);    // Reset Handler (Int1)
  36         [ P0 ++ ] = R0;
  37
  38 LD32_LABEL(r0, NHANDLE);    // NMI Handler (Int2)
  39         [ P0 ++ ] = R0;
  40
  41 LD32_LABEL(r0, XHANDLE);    // Exception Handler (Int3)
  42         [ P0 ++ ] = R0;
  43
  44         [ P0 ++ ] = R0;                // IVT4 not used
  45
  46 LD32_LABEL(r0, HWHANDLE);   // HW Error Handler (Int5)
  47         [ P0 ++ ] = R0;
  48
  49 LD32_LABEL(r0, THANDLE);    // Timer Handler (Int6)
  50         [ P0 ++ ] = R0;
  51
  52 LD32_LABEL(r0, I7HANDLE);   // IVG7 Handler
  53         [ P0 ++ ] = R0;
  54
  55 LD32_LABEL(r0, I8HANDLE);   // IVG8 Handler
  56         [ P0 ++ ] = R0;
  57
  58 LD32_LABEL(r0, I9HANDLE);   // IVG9 Handler
  59         [ P0 ++ ] = R0;
  60
  61 LD32_LABEL(r0, I10HANDLE);  // IVG10 Handler
  62         [ P0 ++ ] = R0;
  63
  64 LD32_LABEL(r0, I11HANDLE);  // IVG11 Handler
  65         [ P0 ++ ] = R0;
  66
  67 LD32_LABEL(r0, I12HANDLE);  // IVG12 Handler
  68         [ P0 ++ ] = R0;
  69
  70 LD32_LABEL(r0, I13HANDLE);  // IVG13 Handler
  71         [ P0 ++ ] = R0;
  72
  73 LD32_LABEL(r0, I14HANDLE);  // IVG14 Handler
  74         [ P0 ++ ] = R0;
  75
  76 LD32_LABEL(r0, I15HANDLE);  // IVG15 Handler
  77         [ P0 ++ ] = R0;
  78
  79 LD32(p0, EVT_OVERRIDE);
  80         R0 = 0;
  81         [ P0 ++ ] = R0;
  82         R0 = -1;     // Change this to mask interrupts (*)
  83         [ P0 ] = R0;   // IMASK
  84
  85 LD32_LABEL(p1, START);
  86
  87 LD32(p0, EVT15);
  88         [ P0 ] = P1;   // IVG15 (General) handler (Int 15) load with start
  89
  90 LD32_LABEL(r7, DUMMY);
  91 RETI = r7;
  92 RAISE 15;    // after we RTI, INT 15 should be taken
  93
  94 NOP;        // Workaround for Bug 217
  95 RTI;
  96 NOP;
  97 NOP;
  98 NOP;
  99 DUMMY:
 100           NOP;
 101 NOP;
 102 NOP;
 103 NOP;
 104
 105
 106
 107  START :
 108 WR_MMR(TBUFCTL, 0x00000000, p0, r0);        // Turn ON trace Buffer
 109                                                     //   TBUFPWR   = 0
 110                                                     //   TBUFEN    = 0
 111                                                     //   TBUFOVF   = 0
 112                                                     //   CMPLP     = 0
 113 NOP;
 114 NOP;
 115 NOP;
 116 NOP;
 117 NOP;
 118             NOP;
 119 NOP;
 120 JUMP.S label1;                                                          //
 121         R4.L = 0x1111;                             // Will be killed
 122         R4.H = 0x1111;                             // Will be killed
 123 NOP;
 124 NOP;
 125 NOP;
 126 label2: R5.H = 0x7777;          //
 127         R5.L = 0x7888;
 128 JUMP.S label3;          //
 129         R6.L = 0x1111;                             // Will be killed
 130         R6.H = 0x1111;                             // Will be killed
 131 NOP;
 132 NOP;
 133 NOP;
 134 NOP;
 135 NOP;
 136 label1: R4.H = 0x5555;          //
 137         R4.L = 0x6666;
 138 NOP;
 139 WR_MMR(TBUFCTL, 0x00000002, p0, r0);        //
 140                                                     //   TBUFPWR   = 0
 141                                                     //   TBUFEN    = 1
 142                                                     //   TBUFOVF   = 0
 143                                                     //   CMPLP     = 0
 144 NOP;
 145 NOP;
 146 NOP;
 147 NOP;
 148 JUMP.S label2;          //
 149         R5.L = 0x1111;     // Will be killed
 150         R5.H = 0x1111;     // Will be killed
 151 NOP;
 152 NOP;
 153 NOP;
 154 NOP;
 155 label3: R6.H = 0x7999;          //
 156         R6.L = 0x7aaa;
 157 NOP;
 158 NOP;
 159 WR_MMR(TBUFCTL, 0x00000001, p0, r0);
 160                 NOP;
 161                 NOP;
 162                 NOP;
 163 WR_MMR(TBUFCTL, 0x00000003, p0, r0);        // Turn ON trace Buffer
 164                                                     //   TBUFPWR   = 1
 165                                                     //   TBUFEN    = 1
 166                                                     //   TBUFOVF   = 0
 167                                                     //   CMPLP     = 0
 168 NOP;
 169 NOP;
 170 NOP;
 171 NOP;
 172 JUMP.S label4;          //
 173         R5.L = 0x1111;     // Will be killed
 174         R5.H = 0x1111;     // Will be killed
 175 NOP;
 176 NOP;
 177 NOP;
 178 NOP;
 179
 180 label4: R6.H = 0x1aaa;          //
 181         R6.L = 0x2222;
 182 NOP;
 183 NOP;
 184 NOP;
 185 NOP;
 186
 187 WR_MMR(TBUFCTL, 0x00000001, p0, r0);        // Turn OFF trace Buffer
 188
 189 NOP;
 190 NOP;
 191 NOP;
 192 NOP;
 193         // Read the contents of the Trace Buffer
 194
 195 RD_MMR(TBUFSTAT, p0, r2);
 196 CHECKREG(r2,    0x00000001);
 197
 198         // Read 3rd Entry of the Trace Buffer
 199 RD_MMR(TBUF,    p0,     r0);
 200 CHECKREG(r0,    0x000002d2);
 201
 202 RD_MMR(TBUFSTAT, p0, r2);
 203 CHECKREG(r2,    0x00000001);
 204
 205 RD_MMR(TBUF,    p0,     r1);
 206 CHECKREG(r1,    0x000002c0);
 207
 208 RD_MMR(TBUFSTAT, p0, r2);
 209 CHECKREG(r2,    0x00000000);
 210
 211
 212 WR_MMR(TBUFCTL, 0x00000000, p0, r0);        // Turn OFF trace Buffer Power
 213
 214 NOP;
 215 NOP;
 216 NOP;
 217 NOP;
 218 NOP;
 219 NOP;
 220 dbg_pass;        // Call Endtest Macro
 221
 222
 223
 224 //*********************************************************************
 225 //
 226 // Handlers for Events
 227 //
 228
 229 EHANDLE:            // Emulation Handler 0
 230 RTE;
 231
 232 RHANDLE:            // Reset Handler 1
 233 RTI;
 234
 235 NHANDLE:            // NMI Handler 2
 236 RTN;
 237
 238 XHANDLE:            // Exception Handler 3
 239 RTX;
 240
 241 HWHANDLE:           // HW Error Handler 5
 242 RTI;
 243
 244 THANDLE:            // Timer Handler 6
 245 RTI;
 246
 247 I7HANDLE:           // IVG 7 Handler
 248 RTI;
 249
 250 I8HANDLE:           // IVG 8 Handler
 251 RTI;
 252
 253 I9HANDLE:           // IVG 9 Handler
 254 RTI;
 255
 256 I10HANDLE:          // IVG 10 Handler
 257 RTI;
 258
 259 I11HANDLE:          // IVG 11 Handler
 260 RTI;
 261
 262 I12HANDLE:          // IVG 12 Handler
 263 RTI;
 264
 265 I13HANDLE:          // IVG 13 Handler
 266 RTI;
 267
 268 I14HANDLE:          // IVG 14 Handler
 269 RTI;
 270
 271 I15HANDLE:          // IVG 15 Handler
 272 RTI;