[gdb/syscalls] Sync with strace v6.13
[binutils-gdb.git] / sim / testsuite / d10v / t-mvtc.s
blob0b463ae935f09a7807700e383f4db339fac374d7
1 # mach: all
2 # output:
3 # sim: --environment operating
4 # as: -W
6 .include "t-macros.i"
8 start
10 ;;; Try out each bit in the PSW
12 loadpsw2 PSW_SM
13 checkpsw2 1 PSW_SM
15 loadpsw2 PSW_01
16 checkpsw2 2 0 ;; PSW_01
18 loadpsw2 PSW_EA
19 checkpsw2 3 PSW_EA
21 loadpsw2 PSW_DB
22 checkpsw2 4 PSW_DB
24 loadpsw2 PSW_DM
25 checkpsw2 5 0 ;; PSW_DM
27 loadpsw2 PSW_IE
28 checkpsw2 6 PSW_IE
30 loadpsw2 PSW_RP
31 checkpsw2 7 PSW_RP
33 loadpsw2 PSW_MD
34 checkpsw2 8 PSW_MD
36 loadpsw2 PSW_FX|PSW_ST
37 checkpsw2 9 PSW_FX|PSW_ST
39 ;; loadpsw2 PSW_ST
40 ;; checkpsw2 10
42 loadpsw2 PSW_10
43 checkpsw2 11 0 ;; PSW_10
45 loadpsw2 PSW_11
46 checkpsw2 12 0 ;; PSW_11
48 loadpsw2 PSW_F0
49 checkpsw2 13 PSW_F0
51 loadpsw2 PSW_F1
52 checkpsw2 14 PSW_F1
54 loadpsw2 PSW_14
55 checkpsw2 15 0 ;; PSW_14
57 loadpsw2 PSW_C
58 checkpsw2 16 PSW_C
61 ;;; Check that bit 0 (LSB) of the MOD_E & MOD_S registers are stuck at ZERO.
63 ldi r6, #0xdead
64 mvtc r6, cr10
65 ldi r6, #0xbeef
66 mvtc r6, cr11
68 mvfc r7, cr10
69 check 17 r7 0xdeac
70 mvfc r7, cr11
71 check 18 r7 0xbeee
73 ;;; Check that certain bits of the PSW, DPSW and BPSW are hardwired to zero
75 psw_ffff:
76 ldi r6, 0xffff
77 mvtc r6, psw
78 mvfc r7, psw
79 check 18 r7 0xb7cd
81 bpsw_ffff:
82 ldi r6, 0xffff
83 mvtc r6, bpsw
84 mvfc r7, bpsw
85 check 18 r7 0xb7cd
87 dpsw_ffff:
88 ldi r6, 0xffff
89 mvtc r6, dpsw
90 mvfc r7, dpsw
91 check 18 r7 0xb7cd
93 ;;; Another check. Very similar
95 psw_dfff:
96 ldi r6, 0xdfff
97 mvtc r6, psw
98 mvfc r7, psw
99 check 18 r7 0x97cd
101 bpsw_dfff:
102 ldi r6, 0xdfff
103 mvtc r6, bpsw
104 mvfc r7, bpsw
105 check 18 r7 0x97cd
107 dpsw_dfff:
108 ldi r6, 0xdfff
109 mvtc r6, dpsw
110 mvfc r7, dpsw
111 check 18 r7 0x97cd
113 ;;; And again.
115 psw_8005:
116 ldi r6, 0x8005
117 mvtc r6, psw
118 mvfc r7, psw
119 check 18 r7 0x8005
121 bpsw_8005:
122 ldi r6, 0x8005
123 mvtc r6, bpsw
124 mvfc r7, bpsw
125 check 18 r7 0x8005
127 dpsw_8005:
128 ldi r6, 0x8005
129 mvtc r6, dpsw
130 mvfc r7, dpsw
131 check 18 r7 0x8005
134 exit0