sim/testsuite/frv/cand.cgs

   1 # frv testcase for cand $GRi,$GRj,$GRk
   2 # mach: all
   3
   4         .include "testutils.inc"
   5
   6         start
   7
   8         .global cand
   9 cand:
  10         set_spr_immed   0x1b1b,cccr
  11
  12         set_gr_limmed   0xaaaa,0xaaaa,gr7
  13         set_gr_limmed   0x5555,0x5555,gr8
  14         set_icc         0x0b,0          ; Set mask opposite of expected
  15         cand            gr7,gr8,gr8,cc0,1
  16         test_icc        1 0 1 1 icc0
  17         test_gr_immed   0,gr8
  18
  19         set_gr_limmed   0xffff,0x0000,gr8
  20         set_icc         0x04,0          ; Set mask opposite of expected
  21         cand            gr7,gr8,gr8,cc0,1
  22         test_icc        0 1 0 0 icc0
  23         test_gr_limmed  0xaaaa,0x0000,gr8
  24
  25         set_gr_limmed   0x0000,0xffff,gr8
  26         set_icc         0x0d,0          ; Set mask opposite of expected
  27         cand            gr7,gr8,gr8,cc4,1
  28         test_icc        1 1 0 1 icc0
  29         test_gr_limmed  0x0000,0xaaaa,gr8
  30
  31         set_gr_limmed   0xaaaa,0xaaaa,gr7
  32         set_gr_limmed   0x5555,0x5555,gr8
  33         set_icc         0x0b,0          ; Set mask opposite of expected
  34         cand            gr7,gr8,gr8,cc0,0
  35         test_icc        1 0 1 1 icc0
  36         test_gr_limmed  0x5555,0x5555,gr8
  37
  38         set_gr_limmed   0xffff,0x0000,gr8
  39         set_icc         0x04,0          ; Set mask opposite of expected
  40         cand            gr7,gr8,gr8,cc0,0
  41         test_icc        0 1 0 0 icc0
  42         test_gr_limmed  0xffff,0x0000,gr8
  43
  44         set_gr_limmed   0x0000,0xffff,gr8
  45         set_icc         0x0d,0          ; Set mask opposite of expected
  46         cand            gr7,gr8,gr8,cc4,0
  47         test_icc        1 1 0 1 icc0
  48         test_gr_limmed  0x0000,0xffff,gr8
  49
  50         set_gr_limmed   0xaaaa,0xaaaa,gr7
  51         set_gr_limmed   0x5555,0x5555,gr8
  52         set_icc         0x0b,1          ; Set mask opposite of expected
  53         cand            gr7,gr8,gr8,cc1,0
  54         test_icc        1 0 1 1 icc1
  55         test_gr_immed   0,gr8
  56
  57         set_gr_limmed   0xffff,0x0000,gr8
  58         set_icc         0x04,1          ; Set mask opposite of expected
  59         cand            gr7,gr8,gr8,cc1,0
  60         test_icc        0 1 0 0 icc1
  61         test_gr_limmed  0xaaaa,0x0000,gr8
  62
  63         set_gr_limmed   0x0000,0xffff,gr8
  64         set_icc         0x0d,1          ; Set mask opposite of expected
  65         cand            gr7,gr8,gr8,cc5,0
  66         test_icc        1 1 0 1 icc1
  67         test_gr_limmed  0x0000,0xaaaa,gr8
  68
  69         set_gr_limmed   0xaaaa,0xaaaa,gr7
  70         set_gr_limmed   0x5555,0x5555,gr8
  71         set_icc         0x0b,1          ; Set mask opposite of expected
  72         cand            gr7,gr8,gr8,cc1,1
  73         test_icc        1 0 1 1 icc1
  74         test_gr_limmed  0x5555,0x5555,gr8
  75
  76         set_gr_limmed   0xffff,0x0000,gr8
  77         set_icc         0x04,1          ; Set mask opposite of expected
  78         cand            gr7,gr8,gr8,cc1,1
  79         test_icc        0 1 0 0 icc1
  80         test_gr_limmed  0xffff,0x0000,gr8
  81
  82         set_gr_limmed   0x0000,0xffff,gr8
  83         set_icc         0x0d,1          ; Set mask opposite of expected
  84         cand            gr7,gr8,gr8,cc5,1
  85         test_icc        1 1 0 1 icc1
  86         test_gr_limmed  0x0000,0xffff,gr8
  87
  88         set_gr_limmed   0xaaaa,0xaaaa,gr7
  89         set_gr_limmed   0x5555,0x5555,gr8
  90         set_icc         0x0b,2          ; Set mask opposite of expected
  91         cand            gr7,gr8,gr8,cc2,0
  92         test_icc        1 0 1 1 icc2
  93         test_gr_limmed  0x5555,0x5555,gr8
  94
  95         set_gr_limmed   0xffff,0x0000,gr8
  96         set_icc         0x04,2          ; Set mask opposite of expected
  97         cand            gr7,gr8,gr8,cc2,0
  98         test_icc        0 1 0 0 icc2
  99         test_gr_limmed  0xffff,0x0000,gr8
 100
 101         set_gr_limmed   0x0000,0xffff,gr8
 102         set_icc         0x0d,2          ; Set mask opposite of expected
 103         cand            gr7,gr8,gr8,cc6,1
 104         test_icc        1 1 0 1 icc2
 105         test_gr_limmed  0x0000,0xffff,gr8
 106
 107         set_gr_limmed   0xaaaa,0xaaaa,gr7
 108         set_gr_limmed   0x5555,0x5555,gr8
 109         set_icc         0x0b,3          ; Set mask opposite of expected
 110         cand            gr7,gr8,gr8,cc3,0
 111         test_icc        1 0 1 1 icc3
 112         test_gr_limmed  0x5555,0x5555,gr8
 113
 114         set_gr_limmed   0xffff,0x0000,gr8
 115         set_icc         0x04,3          ; Set mask opposite of expected
 116         cand            gr7,gr8,gr8,cc3,0
 117         test_icc        0 1 0 0 icc3
 118         test_gr_limmed  0xffff,0x0000,gr8
 119
 120         set_gr_limmed   0x0000,0xffff,gr8
 121         set_icc         0x0d,3          ; Set mask opposite of expected
 122         cand            gr7,gr8,gr8,cc7,1
 123         test_icc        1 1 0 1 icc3
 124         test_gr_limmed  0x0000,0xffff,gr8
 125
 126         pass