| blob | 397832c3bedea79cbeda30649d52311a85e78e9f |
1 # frv testcase for fdcmps $FRi,$FRj,$FCCi_2
2 # mach: fr500 fr550 frv
4 .include "testutils.inc"
6 float_constants
7 start
8 load_float_constants
9 load_float_constants1
11 .global fdcmps
12 fdcmps:
13 set_fcc 0x7,0 ; Set mask opposite of expected
14 set_fcc 0x7,1 ; Set mask opposite of expected
15 fdcmps fr0,fr0,fcc0
16 test_fcc 0x8,0
17 test_fcc 0x8,1
18 set_fcc 0xb,0 ; Set mask opposite of expected
19 set_fcc 0xb,1 ; Set mask opposite of expected
20 fdcmps fr0,fr4,fcc0
21 test_fcc 0x4,0
22 test_fcc 0x4,1
23 set_fcc 0xb,0 ; Set mask opposite of expected
24 set_fcc 0xb,1 ; Set mask opposite of expected
25 fdcmps fr0,fr8,fcc0
26 test_fcc 0x4,0
27 test_fcc 0x4,1
28 set_fcc 0xb,0 ; Set mask opposite of expected
29 set_fcc 0xb,1 ; Set mask opposite of expected
30 fdcmps fr0,fr12,fcc0
31 test_fcc 0x4,0
32 test_fcc 0x4,1
33 set_fcc 0xb,0 ; Set mask opposite of expected
34 set_fcc 0xb,1 ; Set mask opposite of expected
35 fdcmps fr0,fr16,fcc0
36 test_fcc 0x4,0
37 test_fcc 0x4,1
38 set_fcc 0xb,0 ; Set mask opposite of expected
39 set_fcc 0xb,1 ; Set mask opposite of expected
40 fdcmps fr0,fr20,fcc0
41 test_fcc 0x4,0
42 test_fcc 0x4,1
43 set_fcc 0xb,0 ; Set mask opposite of expected
44 set_fcc 0xb,1 ; Set mask opposite of expected
45 fdcmps fr0,fr24,fcc0
46 test_fcc 0x4,0
47 test_fcc 0x4,1
48 set_fcc 0xb,0 ; Set mask opposite of expected
49 set_fcc 0xb,1 ; Set mask opposite of expected
50 fdcmps fr0,fr28,fcc0
51 test_fcc 0x4,0
52 test_fcc 0x4,1
53 set_fcc 0xb,0 ; Set mask opposite of expected
54 set_fcc 0xb,1 ; Set mask opposite of expected
55 fdcmps fr0,fr32,fcc0
56 test_fcc 0x4,0
57 test_fcc 0x4,1
58 set_fcc 0xb,0 ; Set mask opposite of expected
59 set_fcc 0xb,1 ; Set mask opposite of expected
60 fdcmps fr0,fr36,fcc0
61 test_fcc 0x4,0
62 test_fcc 0x4,1
63 set_fcc 0xb,0 ; Set mask opposite of expected
64 set_fcc 0xb,1 ; Set mask opposite of expected
65 fdcmps fr0,fr40,fcc0
66 test_fcc 0x4,0
67 test_fcc 0x4,1
68 set_fcc 0xb,0 ; Set mask opposite of expected
69 set_fcc 0xb,1 ; Set mask opposite of expected
70 fdcmps fr0,fr44,fcc0
71 test_fcc 0x4,0
72 test_fcc 0x4,1
73 set_fcc 0xb,0 ; Set mask opposite of expected
74 set_fcc 0xb,1 ; Set mask opposite of expected
75 fdcmps fr0,fr48,fcc0
76 test_fcc 0x4,0
77 test_fcc 0x4,1
78 set_fcc 0xb,0 ; Set mask opposite of expected
79 set_fcc 0xb,1 ; Set mask opposite of expected
80 fdcmps fr0,fr52,fcc0
81 test_fcc 0x4,0
82 test_fcc 0x4,1
83 set_fcc 0xe,0 ; Set mask opposite of expected
84 set_fcc 0xe,1 ; Set mask opposite of expected
85 fdcmps fr0,fr56,fcc0
86 test_fcc 0x1,0
87 test_fcc 0x1,1
88 set_fcc 0xe,0 ; Set mask opposite of expected
89 set_fcc 0xe,1 ; Set mask opposite of expected
90 fdcmps fr0,fr60,fcc0
91 test_fcc 0x1,0
92 test_fcc 0x1,1
94 set_fcc 0xd,0 ; Set mask opposite of expected
95 set_fcc 0xd,1 ; Set mask opposite of expected
96 fdcmps fr4,fr0,fcc0
97 test_fcc 0x2,0
98 test_fcc 0x2,1
99 set_fcc 0x7,0 ; Set mask opposite of expected
100 set_fcc 0x7,1 ; Set mask opposite of expected
101 fdcmps fr4,fr4,fcc0
102 test_fcc 0x8,0
103 test_fcc 0x8,1
104 set_fcc 0xb,0 ; Set mask opposite of expected
105 set_fcc 0xb,1 ; Set mask opposite of expected
106 fdcmps fr4,fr8,fcc0
107 test_fcc 0x4,0
108 test_fcc 0x4,1
109 set_fcc 0xb,0 ; Set mask opposite of expected
110 set_fcc 0xb,1 ; Set mask opposite of expected
111 fdcmps fr4,fr12,fcc0
112 test_fcc 0x4,0
113 test_fcc 0x4,1
114 set_fcc 0xb,0 ; Set mask opposite of expected
115 set_fcc 0xb,1 ; Set mask opposite of expected
116 fdcmps fr4,fr16,fcc0
117 test_fcc 0x4,0
118 test_fcc 0x4,1
119 set_fcc 0xb,0 ; Set mask opposite of expected
120 set_fcc 0xb,1 ; Set mask opposite of expected
121 fdcmps fr4,fr20,fcc0
122 test_fcc 0x4,0
123 test_fcc 0x4,1
124 set_fcc 0xb,0 ; Set mask opposite of expected
125 set_fcc 0xb,1 ; Set mask opposite of expected
126 fdcmps fr4,fr24,fcc0
127 test_fcc 0x4,0
128 test_fcc 0x4,1
129 set_fcc 0xb,0 ; Set mask opposite of expected
130 set_fcc 0xb,1 ; Set mask opposite of expected
131 fdcmps fr4,fr28,fcc0
132 test_fcc 0x4,0
133 test_fcc 0x4,1
134 set_fcc 0xb,0 ; Set mask opposite of expected
135 set_fcc 0xb,1 ; Set mask opposite of expected
136 fdcmps fr4,fr32,fcc0
137 test_fcc 0x4,0
138 test_fcc 0x4,1
139 set_fcc 0xb,0 ; Set mask opposite of expected
140 set_fcc 0xb,1 ; Set mask opposite of expected
141 fdcmps fr4,fr36,fcc0
142 test_fcc 0x4,0
143 test_fcc 0x4,1
144 set_fcc 0xb,0 ; Set mask opposite of expected
145 set_fcc 0xb,1 ; Set mask opposite of expected
146 fdcmps fr4,fr40,fcc0
147 test_fcc 0x4,0
148 test_fcc 0x4,1
149 set_fcc 0xb,0 ; Set mask opposite of expected
150 set_fcc 0xb,1 ; Set mask opposite of expected
151 fdcmps fr4,fr44,fcc0
152 test_fcc 0x4,0
153 test_fcc 0x4,1
154 set_fcc 0xb,0 ; Set mask opposite of expected
155 set_fcc 0xb,1 ; Set mask opposite of expected
156 fdcmps fr4,fr48,fcc0
157 test_fcc 0x4,0
158 test_fcc 0x4,1
159 set_fcc 0xb,0 ; Set mask opposite of expected
160 set_fcc 0xb,1 ; Set mask opposite of expected
161 fdcmps fr4,fr52,fcc0
162 test_fcc 0x4,0
163 test_fcc 0x4,1
164 set_fcc 0xe,0 ; Set mask opposite of expected
165 set_fcc 0xe,1 ; Set mask opposite of expected
166 fdcmps fr4,fr56,fcc0
167 test_fcc 0x1,0
168 test_fcc 0x1,1
169 set_fcc 0xe,0 ; Set mask opposite of expected
170 set_fcc 0xe,1 ; Set mask opposite of expected
171 fdcmps fr4,fr60,fcc0
172 test_fcc 0x1,0
173 test_fcc 0x1,1
175 set_fcc 0xd,0 ; Set mask opposite of expected
176 set_fcc 0xd,1 ; Set mask opposite of expected
177 fdcmps fr8,fr0,fcc0
178 test_fcc 0x2,0
179 test_fcc 0x2,1
180 set_fcc 0xd,0 ; Set mask opposite of expected
181 set_fcc 0xd,1 ; Set mask opposite of expected
182 fdcmps fr8,fr4,fcc0
183 test_fcc 0x2,0
184 test_fcc 0x2,1
185 set_fcc 0x7,0 ; Set mask opposite of expected
186 set_fcc 0x7,1 ; Set mask opposite of expected
187 fdcmps fr8,fr8,fcc0
188 test_fcc 0x8,0
189 test_fcc 0x8,1
190 set_fcc 0xb,0 ; Set mask opposite of expected
191 set_fcc 0xb,1 ; Set mask opposite of expected
192 fdcmps fr8,fr12,fcc0
193 test_fcc 0x4,0
194 test_fcc 0x4,1
195 set_fcc 0xb,0 ; Set mask opposite of expected
196 set_fcc 0xb,1 ; Set mask opposite of expected
197 fdcmps fr8,fr16,fcc0
198 test_fcc 0x4,0
199 test_fcc 0x4,1
200 set_fcc 0xb,0 ; Set mask opposite of expected
201 set_fcc 0xb,1 ; Set mask opposite of expected
202 fdcmps fr8,fr20,fcc0
203 test_fcc 0x4,0
204 test_fcc 0x4,1
205 set_fcc 0xb,0 ; Set mask opposite of expected
206 set_fcc 0xb,1 ; Set mask opposite of expected
207 fdcmps fr8,fr24,fcc0
208 test_fcc 0x4,0
209 test_fcc 0x4,1
210 set_fcc 0xb,0 ; Set mask opposite of expected
211 set_fcc 0xb,1 ; Set mask opposite of expected
212 fdcmps fr8,fr28,fcc0
213 test_fcc 0x4,0
214 test_fcc 0x4,1
215 set_fcc 0xb,0 ; Set mask opposite of expected
216 set_fcc 0xb,1 ; Set mask opposite of expected
217 fdcmps fr8,fr32,fcc0
218 test_fcc 0x4,0
219 test_fcc 0x4,1
220 set_fcc 0xb,0 ; Set mask opposite of expected
221 set_fcc 0xb,1 ; Set mask opposite of expected
222 fdcmps fr8,fr36,fcc0
223 test_fcc 0x4,0
224 test_fcc 0x4,1
225 set_fcc 0xb,0 ; Set mask opposite of expected
226 set_fcc 0xb,1 ; Set mask opposite of expected
227 fdcmps fr8,fr40,fcc0
228 test_fcc 0x4,0
229 test_fcc 0x4,1
230 set_fcc 0xb,0 ; Set mask opposite of expected
231 set_fcc 0xb,1 ; Set mask opposite of expected
232 fdcmps fr8,fr44,fcc0
233 test_fcc 0x4,0
234 test_fcc 0x4,1
235 set_fcc 0xb,0 ; Set mask opposite of expected
236 set_fcc 0xb,1 ; Set mask opposite of expected
237 fdcmps fr8,fr48,fcc0
238 test_fcc 0x4,0
239 test_fcc 0x4,1
240 set_fcc 0xb,0 ; Set mask opposite of expected
241 set_fcc 0xb,1 ; Set mask opposite of expected
242 fdcmps fr8,fr52,fcc0
243 test_fcc 0x4,0
244 test_fcc 0x4,1
245 set_fcc 0xe,0 ; Set mask opposite of expected
246 set_fcc 0xe,1 ; Set mask opposite of expected
247 fdcmps fr8,fr56,fcc0
248 test_fcc 0x1,0
249 test_fcc 0x1,1
250 set_fcc 0xe,0 ; Set mask opposite of expected
251 set_fcc 0xe,1 ; Set mask opposite of expected
252 fdcmps fr8,fr60,fcc0
253 test_fcc 0x1,0
254 test_fcc 0x1,1
256 set_fcc 0xd,0 ; Set mask opposite of expected
257 set_fcc 0xd,1 ; Set mask opposite of expected
258 fdcmps fr12,fr0,fcc0
259 test_fcc 0x2,0
260 test_fcc 0x2,1
261 set_fcc 0xd,0 ; Set mask opposite of expected
262 set_fcc 0xd,1 ; Set mask opposite of expected
263 fdcmps fr12,fr4,fcc0
264 test_fcc 0x2,0
265 test_fcc 0x2,1
266 set_fcc 0xd,0 ; Set mask opposite of expected
267 set_fcc 0xd,1 ; Set mask opposite of expected
268 fdcmps fr12,fr8,fcc0
269 test_fcc 0x2,0
270 test_fcc 0x2,1
271 set_fcc 0x7,0 ; Set mask opposite of expected
272 set_fcc 0x7,1 ; Set mask opposite of expected
273 fdcmps fr12,fr12,fcc0
274 test_fcc 0x8,0
275 test_fcc 0x8,1
276 set_fcc 0xb,0 ; Set mask opposite of expected
277 set_fcc 0xb,1 ; Set mask opposite of expected
278 fdcmps fr12,fr16,fcc0
279 test_fcc 0x4,0
280 test_fcc 0x4,1
281 set_fcc 0xb,0 ; Set mask opposite of expected
282 set_fcc 0xb,1 ; Set mask opposite of expected
283 fdcmps fr12,fr20,fcc0
284 test_fcc 0x4,0
285 test_fcc 0x4,1
286 set_fcc 0xb,0 ; Set mask opposite of expected
287 set_fcc 0xb,1 ; Set mask opposite of expected
288 fdcmps fr12,fr24,fcc0
289 test_fcc 0x4,0
290 test_fcc 0x4,1
291 set_fcc 0xb,0 ; Set mask opposite of expected
292 set_fcc 0xb,1 ; Set mask opposite of expected
293 fdcmps fr12,fr28,fcc0
294 test_fcc 0x4,0
295 test_fcc 0x4,1
296 set_fcc 0xb,0 ; Set mask opposite of expected
297 set_fcc 0xb,1 ; Set mask opposite of expected
298 fdcmps fr12,fr32,fcc0
299 test_fcc 0x4,0
300 test_fcc 0x4,1
301 set_fcc 0xb,0 ; Set mask opposite of expected
302 set_fcc 0xb,1 ; Set mask opposite of expected
303 fdcmps fr12,fr36,fcc0
304 test_fcc 0x4,0
305 test_fcc 0x4,1
306 set_fcc 0xb,0 ; Set mask opposite of expected
307 set_fcc 0xb,1 ; Set mask opposite of expected
308 fdcmps fr12,fr40,fcc0
309 test_fcc 0x4,0
310 test_fcc 0x4,1
311 set_fcc 0xb,0 ; Set mask opposite of expected
312 set_fcc 0xb,1 ; Set mask opposite of expected
313 fdcmps fr12,fr44,fcc0
314 test_fcc 0x4,0
315 test_fcc 0x4,1
316 set_fcc 0xb,0 ; Set mask opposite of expected
317 set_fcc 0xb,1 ; Set mask opposite of expected
318 fdcmps fr12,fr48,fcc0
319 test_fcc 0x4,0
320 test_fcc 0x4,1
321 set_fcc 0xb,0 ; Set mask opposite of expected
322 set_fcc 0xb,1 ; Set mask opposite of expected
323 fdcmps fr12,fr52,fcc0
324 test_fcc 0x4,0
325 test_fcc 0x4,1
326 set_fcc 0xe,0 ; Set mask opposite of expected
327 set_fcc 0xe,1 ; Set mask opposite of expected
328 fdcmps fr12,fr56,fcc0
329 test_fcc 0x1,0
330 test_fcc 0x1,1
331 set_fcc 0xe,0 ; Set mask opposite of expected
332 set_fcc 0xe,1 ; Set mask opposite of expected
333 fdcmps fr12,fr60,fcc0
334 test_fcc 0x1,0
335 test_fcc 0x1,1
337 set_fcc 0xd,0 ; Set mask opposite of expected
338 set_fcc 0xd,1 ; Set mask opposite of expected
339 fdcmps fr16,fr0,fcc0
340 test_fcc 0x2,0
341 test_fcc 0x2,1
342 set_fcc 0xd,0 ; Set mask opposite of expected
343 set_fcc 0xd,1 ; Set mask opposite of expected
344 fdcmps fr16,fr4,fcc0
345 test_fcc 0x2,0
346 test_fcc 0x2,1
347 set_fcc 0xd,0 ; Set mask opposite of expected
348 set_fcc 0xd,1 ; Set mask opposite of expected
349 fdcmps fr16,fr8,fcc0
350 test_fcc 0x2,0
351 test_fcc 0x2,1
352 set_fcc 0xd,0 ; Set mask opposite of expected
353 set_fcc 0xd,1 ; Set mask opposite of expected
354 fdcmps fr16,fr12,fcc0
355 test_fcc 0x2,0
356 test_fcc 0x2,1
357 set_fcc 0x7,0 ; Set mask opposite of expected
358 set_fcc 0x7,1 ; Set mask opposite of expected
359 fdcmps fr16,fr16,fcc0
360 test_fcc 0x8,0
361 test_fcc 0x8,1
362 set_fcc 0x7,0 ; Set mask opposite of expected
363 set_fcc 0x7,1 ; Set mask opposite of expected
364 fdcmps fr16,fr20,fcc0
365 test_fcc 0x8,0
366 test_fcc 0x8,1
367 set_fcc 0xb,0 ; Set mask opposite of expected
368 set_fcc 0xb,1 ; Set mask opposite of expected
369 fdcmps fr16,fr24,fcc0
370 test_fcc 0x4,0
371 test_fcc 0x4,1
372 set_fcc 0xb,0 ; Set mask opposite of expected
373 set_fcc 0xb,1 ; Set mask opposite of expected
374 fdcmps fr16,fr28,fcc0
375 test_fcc 0x4,0
376 test_fcc 0x4,1
377 set_fcc 0xb,0 ; Set mask opposite of expected
378 set_fcc 0xb,1 ; Set mask opposite of expected
379 fdcmps fr16,fr32,fcc0
380 test_fcc 0x4,0
381 test_fcc 0x4,1
382 set_fcc 0xb,0 ; Set mask opposite of expected
383 set_fcc 0xb,1 ; Set mask opposite of expected
384 fdcmps fr16,fr36,fcc0
385 test_fcc 0x4,0
386 test_fcc 0x4,1
387 set_fcc 0xb,0 ; Set mask opposite of expected
388 set_fcc 0xb,1 ; Set mask opposite of expected
389 fdcmps fr16,fr40,fcc0
390 test_fcc 0x4,0
391 test_fcc 0x4,1
392 set_fcc 0xb,0 ; Set mask opposite of expected
393 set_fcc 0xb,1 ; Set mask opposite of expected
394 fdcmps fr16,fr44,fcc0
395 test_fcc 0x4,0
396 test_fcc 0x4,1
397 set_fcc 0xb,0 ; Set mask opposite of expected
398 set_fcc 0xb,1 ; Set mask opposite of expected
399 fdcmps fr16,fr48,fcc0
400 test_fcc 0x4,0
401 test_fcc 0x4,1
402 set_fcc 0xb,0 ; Set mask opposite of expected
403 set_fcc 0xb,1 ; Set mask opposite of expected
404 fdcmps fr16,fr52,fcc0
405 test_fcc 0x4,0
406 test_fcc 0x4,1
407 set_fcc 0xe,0 ; Set mask opposite of expected
408 set_fcc 0xe,1 ; Set mask opposite of expected
409 fdcmps fr16,fr56,fcc0
410 test_fcc 0x1,0
411 test_fcc 0x1,1
412 set_fcc 0xe,0 ; Set mask opposite of expected
413 set_fcc 0xe,1 ; Set mask opposite of expected
414 fdcmps fr16,fr60,fcc0
415 test_fcc 0x1,0
416 test_fcc 0x1,1
418 set_fcc 0xd,0 ; Set mask opposite of expected
419 set_fcc 0xd,1 ; Set mask opposite of expected
420 fdcmps fr20,fr0,fcc0
421 test_fcc 0x2,0
422 test_fcc 0x2,1
423 set_fcc 0xd,0 ; Set mask opposite of expected
424 set_fcc 0xd,1 ; Set mask opposite of expected
425 fdcmps fr20,fr4,fcc0
426 test_fcc 0x2,0
427 test_fcc 0x2,1
428 set_fcc 0xd,0 ; Set mask opposite of expected
429 set_fcc 0xd,1 ; Set mask opposite of expected
430 fdcmps fr20,fr8,fcc0
431 test_fcc 0x2,0
432 test_fcc 0x2,1
433 set_fcc 0xd,0 ; Set mask opposite of expected
434 set_fcc 0xd,1 ; Set mask opposite of expected
435 fdcmps fr20,fr12,fcc0
436 test_fcc 0x2,0
437 test_fcc 0x2,1
438 set_fcc 0x7,0 ; Set mask opposite of expected
439 set_fcc 0x7,1 ; Set mask opposite of expected
440 fdcmps fr20,fr16,fcc0
441 test_fcc 0x8,0
442 test_fcc 0x8,1
443 set_fcc 0x7,0 ; Set mask opposite of expected
444 set_fcc 0x7,1 ; Set mask opposite of expected
445 fdcmps fr20,fr20,fcc0
446 test_fcc 0x8,0
447 test_fcc 0x8,1
448 set_fcc 0xb,0 ; Set mask opposite of expected
449 set_fcc 0xb,1 ; Set mask opposite of expected
450 fdcmps fr20,fr24,fcc0
451 test_fcc 0x4,0
452 test_fcc 0x4,1
453 set_fcc 0xb,0 ; Set mask opposite of expected
454 set_fcc 0xb,1 ; Set mask opposite of expected
455 fdcmps fr20,fr28,fcc0
456 test_fcc 0x4,0
457 test_fcc 0x4,1
458 set_fcc 0xb,0 ; Set mask opposite of expected
459 set_fcc 0xb,1 ; Set mask opposite of expected
460 fdcmps fr20,fr32,fcc0
461 test_fcc 0x4,0
462 test_fcc 0x4,1
463 set_fcc 0xb,0 ; Set mask opposite of expected
464 set_fcc 0xb,1 ; Set mask opposite of expected
465 fdcmps fr20,fr36,fcc0
466 test_fcc 0x4,0
467 test_fcc 0x4,1
468 set_fcc 0xb,0 ; Set mask opposite of expected
469 set_fcc 0xb,1 ; Set mask opposite of expected
470 fdcmps fr20,fr40,fcc0
471 test_fcc 0x4,0
472 test_fcc 0x4,1
473 set_fcc 0xb,0 ; Set mask opposite of expected
474 set_fcc 0xb,1 ; Set mask opposite of expected
475 fdcmps fr20,fr44,fcc0
476 test_fcc 0x4,0
477 test_fcc 0x4,1
478 set_fcc 0xb,0 ; Set mask opposite of expected
479 set_fcc 0xb,1 ; Set mask opposite of expected
480 fdcmps fr20,fr48,fcc0
481 test_fcc 0x4,0
482 test_fcc 0x4,1
483 set_fcc 0xb,0 ; Set mask opposite of expected
484 set_fcc 0xb,1 ; Set mask opposite of expected
485 fdcmps fr20,fr52,fcc0
486 test_fcc 0x4,0
487 test_fcc 0x4,1
488 set_fcc 0xe,0 ; Set mask opposite of expected
489 set_fcc 0xe,1 ; Set mask opposite of expected
490 fdcmps fr20,fr56,fcc0
491 test_fcc 0x1,0
492 test_fcc 0x1,1
493 set_fcc 0xe,0 ; Set mask opposite of expected
494 set_fcc 0xe,1 ; Set mask opposite of expected
495 fdcmps fr20,fr60,fcc0
496 test_fcc 0x1,0
497 test_fcc 0x1,1
499 set_fcc 0xd,0 ; Set mask opposite of expected
500 set_fcc 0xd,1 ; Set mask opposite of expected
501 fdcmps fr24,fr0,fcc0
502 test_fcc 0x2,0
503 test_fcc 0x2,1
504 set_fcc 0xd,0 ; Set mask opposite of expected
505 set_fcc 0xd,1 ; Set mask opposite of expected
506 fdcmps fr24,fr4,fcc0
507 test_fcc 0x2,0
508 test_fcc 0x2,1
509 set_fcc 0xd,0 ; Set mask opposite of expected
510 set_fcc 0xd,1 ; Set mask opposite of expected
511 fdcmps fr24,fr8,fcc0
512 test_fcc 0x2,0
513 test_fcc 0x2,1
514 set_fcc 0xd,0 ; Set mask opposite of expected
515 set_fcc 0xd,1 ; Set mask opposite of expected
516 fdcmps fr24,fr12,fcc0
517 test_fcc 0x2,0
518 test_fcc 0x2,1
519 set_fcc 0xd,0 ; Set mask opposite of expected
520 set_fcc 0xd,1 ; Set mask opposite of expected
521 fdcmps fr24,fr16,fcc0
522 test_fcc 0x2,0
523 test_fcc 0x2,1
524 set_fcc 0xd,0 ; Set mask opposite of expected
525 set_fcc 0xd,1 ; Set mask opposite of expected
526 fdcmps fr24,fr20,fcc0
527 test_fcc 0x2,0
528 test_fcc 0x2,1
529 set_fcc 0x7,0 ; Set mask opposite of expected
530 set_fcc 0x7,1 ; Set mask opposite of expected
531 fdcmps fr24,fr24,fcc0
532 test_fcc 0x8,0
533 test_fcc 0x8,1
534 set_fcc 0xb,0 ; Set mask opposite of expected
535 set_fcc 0xb,1 ; Set mask opposite of expected
536 fdcmps fr24,fr28,fcc0
537 test_fcc 0x4,0
538 test_fcc 0x4,1
539 set_fcc 0xb,0 ; Set mask opposite of expected
540 set_fcc 0xb,1 ; Set mask opposite of expected
541 fdcmps fr24,fr32,fcc0
542 test_fcc 0x4,0
543 test_fcc 0x4,1
544 set_fcc 0xb,0 ; Set mask opposite of expected
545 set_fcc 0xb,1 ; Set mask opposite of expected
546 fdcmps fr24,fr36,fcc0
547 test_fcc 0x4,0
548 test_fcc 0x4,1
549 set_fcc 0xb,0 ; Set mask opposite of expected
550 set_fcc 0xb,1 ; Set mask opposite of expected
551 fdcmps fr24,fr40,fcc0
552 test_fcc 0x4,0
553 test_fcc 0x4,1
554 set_fcc 0xb,0 ; Set mask opposite of expected
555 set_fcc 0xb,1 ; Set mask opposite of expected
556 fdcmps fr24,fr44,fcc0
557 test_fcc 0x4,0
558 test_fcc 0x4,1
559 set_fcc 0xb,0 ; Set mask opposite of expected
560 set_fcc 0xb,1 ; Set mask opposite of expected
561 fdcmps fr24,fr48,fcc0
562 test_fcc 0x4,0
563 test_fcc 0x4,1
564 set_fcc 0xb,0 ; Set mask opposite of expected
565 set_fcc 0xb,1 ; Set mask opposite of expected
566 fdcmps fr24,fr52,fcc0
567 test_fcc 0x4,0
568 test_fcc 0x4,1
569 set_fcc 0xe,0 ; Set mask opposite of expected
570 set_fcc 0xe,1 ; Set mask opposite of expected
571 fdcmps fr24,fr56,fcc0
572 test_fcc 0x1,0
573 test_fcc 0x1,1
574 set_fcc 0xe,0 ; Set mask opposite of expected
575 set_fcc 0xe,1 ; Set mask opposite of expected
576 fdcmps fr24,fr60,fcc0
577 test_fcc 0x1,0
578 test_fcc 0x1,1
580 set_fcc 0xd,0 ; Set mask opposite of expected
581 set_fcc 0xd,1 ; Set mask opposite of expected
582 fdcmps fr28,fr0,fcc0
583 test_fcc 0x2,0
584 test_fcc 0x2,1
585 set_fcc 0xd,0 ; Set mask opposite of expected
586 set_fcc 0xd,1 ; Set mask opposite of expected
587 fdcmps fr28,fr4,fcc0
588 test_fcc 0x2,0
589 test_fcc 0x2,1
590 set_fcc 0xd,0 ; Set mask opposite of expected
591 set_fcc 0xd,1 ; Set mask opposite of expected
592 fdcmps fr28,fr8,fcc0
593 test_fcc 0x2,0
594 test_fcc 0x2,1
595 set_fcc 0xd,0 ; Set mask opposite of expected
596 set_fcc 0xd,1 ; Set mask opposite of expected
597 fdcmps fr28,fr12,fcc0
598 test_fcc 0x2,0
599 test_fcc 0x2,1
600 set_fcc 0xd,0 ; Set mask opposite of expected
601 set_fcc 0xd,1 ; Set mask opposite of expected
602 fdcmps fr28,fr16,fcc0
603 test_fcc 0x2,0
604 test_fcc 0x2,1
605 set_fcc 0xd,0 ; Set mask opposite of expected
606 set_fcc 0xd,1 ; Set mask opposite of expected
607 fdcmps fr28,fr20,fcc0
608 test_fcc 0x2,0
609 test_fcc 0x2,1
610 set_fcc 0xd,0 ; Set mask opposite of expected
611 set_fcc 0xd,1 ; Set mask opposite of expected
612 fdcmps fr28,fr24,fcc0
613 test_fcc 0x2,0
614 test_fcc 0x2,1
615 set_fcc 0x7,0 ; Set mask opposite of expected
616 set_fcc 0x7,1 ; Set mask opposite of expected
617 fdcmps fr28,fr28,fcc0
618 test_fcc 0x8,0
619 test_fcc 0x8,1
620 set_fcc 0xb,0 ; Set mask opposite of expected
621 set_fcc 0xb,1 ; Set mask opposite of expected
622 fdcmps fr28,fr32,fcc0
623 test_fcc 0x4,0
624 test_fcc 0x4,1
625 set_fcc 0xb,0 ; Set mask opposite of expected
626 set_fcc 0xb,1 ; Set mask opposite of expected
627 fdcmps fr28,fr36,fcc0
628 test_fcc 0x4,0
629 test_fcc 0x4,1
630 set_fcc 0xb,0 ; Set mask opposite of expected
631 set_fcc 0xb,1 ; Set mask opposite of expected
632 fdcmps fr28,fr40,fcc0
633 test_fcc 0x4,0
634 test_fcc 0x4,1
635 set_fcc 0xb,0 ; Set mask opposite of expected
636 set_fcc 0xb,1 ; Set mask opposite of expected
637 fdcmps fr28,fr44,fcc0
638 test_fcc 0x4,0
639 test_fcc 0x4,1
640 set_fcc 0xb,0 ; Set mask opposite of expected
641 set_fcc 0xb,1 ; Set mask opposite of expected
642 fdcmps fr28,fr48,fcc0
643 test_fcc 0x4,0
644 test_fcc 0x4,1
645 set_fcc 0xb,0 ; Set mask opposite of expected
646 set_fcc 0xb,1 ; Set mask opposite of expected
647 fdcmps fr28,fr52,fcc0
648 test_fcc 0x4,0
649 test_fcc 0x4,1
650 set_fcc 0xe,0 ; Set mask opposite of expected
651 set_fcc 0xe,1 ; Set mask opposite of expected
652 fdcmps fr28,fr56,fcc0
653 test_fcc 0x1,0
654 test_fcc 0x1,1
655 set_fcc 0xe,0 ; Set mask opposite of expected
656 set_fcc 0xe,1 ; Set mask opposite of expected
657 fdcmps fr28,fr60,fcc0
658 test_fcc 0x1,0
659 test_fcc 0x1,1
661 set_fcc 0xd,0 ; Set mask opposite of expected
662 set_fcc 0xd,1 ; Set mask opposite of expected
663 fdcmps fr48,fr0,fcc0
664 test_fcc 0x2,0
665 test_fcc 0x2,1
666 set_fcc 0xd,0 ; Set mask opposite of expected
667 set_fcc 0xd,1 ; Set mask opposite of expected
668 fdcmps fr48,fr4,fcc0
669 test_fcc 0x2,0
670 test_fcc 0x2,1
671 set_fcc 0xd,0 ; Set mask opposite of expected
672 set_fcc 0xd,1 ; Set mask opposite of expected
673 fdcmps fr48,fr8,fcc0
674 test_fcc 0x2,0
675 test_fcc 0x2,1
676 set_fcc 0xd,0 ; Set mask opposite of expected
677 set_fcc 0xd,1 ; Set mask opposite of expected
678 fdcmps fr48,fr12,fcc0
679 test_fcc 0x2,0
680 test_fcc 0x2,1
681 set_fcc 0xd,0 ; Set mask opposite of expected
682 set_fcc 0xd,1 ; Set mask opposite of expected
683 fdcmps fr48,fr16,fcc0
684 test_fcc 0x2,0
685 test_fcc 0x2,1
686 set_fcc 0xd,0 ; Set mask opposite of expected
687 set_fcc 0xd,1 ; Set mask opposite of expected
688 fdcmps fr48,fr20,fcc0
689 test_fcc 0x2,0
690 test_fcc 0x2,1
691 set_fcc 0xd,0 ; Set mask opposite of expected
692 set_fcc 0xd,1 ; Set mask opposite of expected
693 fdcmps fr48,fr24,fcc0
694 test_fcc 0x2,0
695 test_fcc 0x2,1
696 set_fcc 0xd,0 ; Set mask opposite of expected
697 set_fcc 0xd,1 ; Set mask opposite of expected
698 fdcmps fr48,fr28,fcc0
699 test_fcc 0x2,0
700 test_fcc 0x2,1
701 set_fcc 0xd,0 ; Set mask opposite of expected
702 set_fcc 0xd,1 ; Set mask opposite of expected
703 fdcmps fr48,fr32,fcc0
704 test_fcc 0x2,0
705 test_fcc 0x2,1
706 set_fcc 0xd,0 ; Set mask opposite of expected
707 set_fcc 0xd,1 ; Set mask opposite of expected
708 fdcmps fr48,fr36,fcc0
709 test_fcc 0x2,0
710 test_fcc 0x2,1
711 set_fcc 0xd,0 ; Set mask opposite of expected
712 set_fcc 0xd,1 ; Set mask opposite of expected
713 fdcmps fr48,fr40,fcc0
714 test_fcc 0x2,0
715 test_fcc 0x2,1
716 set_fcc 0xd,0 ; Set mask opposite of expected
717 set_fcc 0xd,1 ; Set mask opposite of expected
718 fdcmps fr48,fr44,fcc0
719 test_fcc 0x2,0
720 test_fcc 0x2,1
721 set_fcc 0x7,0 ; Set mask opposite of expected
722 set_fcc 0x7,1 ; Set mask opposite of expected
723 fdcmps fr48,fr48,fcc0
724 test_fcc 0x8,0
725 test_fcc 0x8,1
726 set_fcc 0xb,0 ; Set mask opposite of expected
727 set_fcc 0xb,1 ; Set mask opposite of expected
728 fdcmps fr48,fr52,fcc0
729 test_fcc 0x4,0
730 test_fcc 0x4,1
731 set_fcc 0xe,0 ; Set mask opposite of expected
732 set_fcc 0xe,1 ; Set mask opposite of expected
733 fdcmps fr48,fr56,fcc0
734 test_fcc 0x1,0
735 test_fcc 0x1,1
736 set_fcc 0xe,0 ; Set mask opposite of expected
737 set_fcc 0xe,1 ; Set mask opposite of expected
738 fdcmps fr48,fr60,fcc0
739 test_fcc 0x1,0
740 test_fcc 0x1,1
742 set_fcc 0xd,0 ; Set mask opposite of expected
743 set_fcc 0xd,1 ; Set mask opposite of expected
744 fdcmps fr52,fr0,fcc0
745 test_fcc 0x2,0
746 test_fcc 0x2,1
747 set_fcc 0xd,0 ; Set mask opposite of expected
748 set_fcc 0xd,1 ; Set mask opposite of expected
749 fdcmps fr52,fr4,fcc0
750 test_fcc 0x2,0
751 test_fcc 0x2,1
752 set_fcc 0xd,0 ; Set mask opposite of expected
753 set_fcc 0xd,1 ; Set mask opposite of expected
754 fdcmps fr52,fr8,fcc0
755 test_fcc 0x2,0
756 test_fcc 0x2,1
757 set_fcc 0xd,0 ; Set mask opposite of expected
758 set_fcc 0xd,1 ; Set mask opposite of expected
759 fdcmps fr52,fr12,fcc0
760 test_fcc 0x2,0
761 test_fcc 0x2,1
762 set_fcc 0xd,0 ; Set mask opposite of expected
763 set_fcc 0xd,1 ; Set mask opposite of expected
764 fdcmps fr52,fr16,fcc0
765 test_fcc 0x2,0
766 test_fcc 0x2,1
767 set_fcc 0xd,0 ; Set mask opposite of expected
768 set_fcc 0xd,1 ; Set mask opposite of expected
769 fdcmps fr52,fr20,fcc0
770 test_fcc 0x2,0
771 test_fcc 0x2,1
772 set_fcc 0xd,0 ; Set mask opposite of expected
773 set_fcc 0xd,1 ; Set mask opposite of expected
774 fdcmps fr52,fr24,fcc0
775 test_fcc 0x2,0
776 test_fcc 0x2,1
777 set_fcc 0xd,0 ; Set mask opposite of expected
778 set_fcc 0xd,1 ; Set mask opposite of expected
779 fdcmps fr52,fr28,fcc0
780 test_fcc 0x2,0
781 test_fcc 0x2,1
782 set_fcc 0xd,0 ; Set mask opposite of expected
783 set_fcc 0xd,1 ; Set mask opposite of expected
784 fdcmps fr52,fr32,fcc0
785 test_fcc 0x2,0
786 test_fcc 0x2,1
787 set_fcc 0xd,0 ; Set mask opposite of expected
788 set_fcc 0xd,1 ; Set mask opposite of expected
789 fdcmps fr52,fr36,fcc0
790 test_fcc 0x2,0
791 test_fcc 0x2,1
792 set_fcc 0xd,0 ; Set mask opposite of expected
793 set_fcc 0xd,1 ; Set mask opposite of expected
794 fdcmps fr52,fr40,fcc0
795 test_fcc 0x2,0
796 test_fcc 0x2,1
797 set_fcc 0xd,0 ; Set mask opposite of expected
798 set_fcc 0xd,1 ; Set mask opposite of expected
799 fdcmps fr52,fr44,fcc0
800 test_fcc 0x2,0
801 test_fcc 0x2,1
802 set_fcc 0xd,0 ; Set mask opposite of expected
803 set_fcc 0xd,1 ; Set mask opposite of expected
804 fdcmps fr52,fr48,fcc0
805 test_fcc 0x2,0
806 test_fcc 0x2,1
807 set_fcc 0x7,0 ; Set mask opposite of expected
808 set_fcc 0x7,1 ; Set mask opposite of expected
809 fdcmps fr52,fr52,fcc0
810 test_fcc 0x8,0
811 test_fcc 0x8,1
812 set_fcc 0xe,0 ; Set mask opposite of expected
813 set_fcc 0xe,1 ; Set mask opposite of expected
814 fdcmps fr52,fr56,fcc0
815 test_fcc 0x1,0
816 test_fcc 0x1,1
817 set_fcc 0xe,0 ; Set mask opposite of expected
818 set_fcc 0xe,1 ; Set mask opposite of expected
819 fdcmps fr52,fr60,fcc0
820 test_fcc 0x1,0
821 test_fcc 0x1,1
823 set_fcc 0xe,0 ; Set mask opposite of expected
824 set_fcc 0xe,1 ; Set mask opposite of expected
825 fdcmps fr56,fr0,fcc0
826 test_fcc 0x1,0
827 test_fcc 0x1,1
828 set_fcc 0xe,0 ; Set mask opposite of expected
829 set_fcc 0xe,1 ; Set mask opposite of expected
830 fdcmps fr56,fr4,fcc0
831 test_fcc 0x1,0
832 test_fcc 0x1,1
833 set_fcc 0xe,0 ; Set mask opposite of expected
834 set_fcc 0xe,1 ; Set mask opposite of expected
835 fdcmps fr56,fr8,fcc0
836 test_fcc 0x1,0
837 test_fcc 0x1,1
838 set_fcc 0xe,0 ; Set mask opposite of expected
839 set_fcc 0xe,1 ; Set mask opposite of expected
840 fdcmps fr56,fr12,fcc0
841 test_fcc 0x1,0
842 test_fcc 0x1,1
843 set_fcc 0xe,0 ; Set mask opposite of expected
844 set_fcc 0xe,1 ; Set mask opposite of expected
845 fdcmps fr56,fr16,fcc0
846 test_fcc 0x1,0
847 test_fcc 0x1,1
848 set_fcc 0xe,0 ; Set mask opposite of expected
849 set_fcc 0xe,1 ; Set mask opposite of expected
850 fdcmps fr56,fr20,fcc0
851 test_fcc 0x1,0
852 test_fcc 0x1,1
853 set_fcc 0xe,0 ; Set mask opposite of expected
854 set_fcc 0xe,1 ; Set mask opposite of expected
855 fdcmps fr56,fr24,fcc0
856 test_fcc 0x1,0
857 test_fcc 0x1,1
858 set_fcc 0xe,0 ; Set mask opposite of expected
859 set_fcc 0xe,1 ; Set mask opposite of expected
860 fdcmps fr56,fr28,fcc0
861 test_fcc 0x1,0
862 test_fcc 0x1,1
863 set_fcc 0xe,0 ; Set mask opposite of expected
864 set_fcc 0xe,1 ; Set mask opposite of expected
865 fdcmps fr56,fr32,fcc0
866 test_fcc 0x1,0
867 test_fcc 0x1,1
868 set_fcc 0xe,0 ; Set mask opposite of expected
869 set_fcc 0xe,1 ; Set mask opposite of expected
870 fdcmps fr56,fr36,fcc0
871 test_fcc 0x1,0
872 test_fcc 0x1,1
873 set_fcc 0xe,0 ; Set mask opposite of expected
874 set_fcc 0xe,1 ; Set mask opposite of expected
875 fdcmps fr56,fr40,fcc0
876 test_fcc 0x1,0
877 test_fcc 0x1,1
878 set_fcc 0xe,0 ; Set mask opposite of expected
879 set_fcc 0xe,1 ; Set mask opposite of expected
880 fdcmps fr56,fr44,fcc0
881 test_fcc 0x1,0
882 test_fcc 0x1,1
883 set_fcc 0xe,0 ; Set mask opposite of expected
884 set_fcc 0xe,1 ; Set mask opposite of expected
885 fdcmps fr56,fr48,fcc0
886 test_fcc 0x1,0
887 test_fcc 0x1,1
888 set_fcc 0xe,0 ; Set mask opposite of expected
889 set_fcc 0xe,1 ; Set mask opposite of expected
890 fdcmps fr56,fr52,fcc0
891 test_fcc 0x1,0
892 test_fcc 0x1,1
893 set_fcc 0xe,0 ; Set mask opposite of expected
894 set_fcc 0xe,1 ; Set mask opposite of expected
895 fdcmps fr56,fr56,fcc0
896 test_fcc 0x1,0
897 test_fcc 0x1,1
898 set_fcc 0xe,0 ; Set mask opposite of expected
899 set_fcc 0xe,1 ; Set mask opposite of expected
900 fdcmps fr56,fr60,fcc0
901 test_fcc 0x1,0
902 test_fcc 0x1,1
904 set_fcc 0xe,0 ; Set mask opposite of expected
905 set_fcc 0xe,1 ; Set mask opposite of expected
906 fdcmps fr60,fr0,fcc0
907 test_fcc 0x1,0
908 test_fcc 0x1,1
909 set_fcc 0xe,0 ; Set mask opposite of expected
910 set_fcc 0xe,1 ; Set mask opposite of expected
911 fdcmps fr60,fr4,fcc0
912 test_fcc 0x1,0
913 test_fcc 0x1,1
914 set_fcc 0xe,0 ; Set mask opposite of expected
915 set_fcc 0xe,1 ; Set mask opposite of expected
916 fdcmps fr60,fr8,fcc0
917 test_fcc 0x1,0
918 test_fcc 0x1,1
919 set_fcc 0xe,0 ; Set mask opposite of expected
920 set_fcc 0xe,1 ; Set mask opposite of expected
921 fdcmps fr60,fr12,fcc0
922 test_fcc 0x1,0
923 test_fcc 0x1,1
924 set_fcc 0xe,0 ; Set mask opposite of expected
925 set_fcc 0xe,1 ; Set mask opposite of expected
926 fdcmps fr60,fr16,fcc0
927 test_fcc 0x1,0
928 test_fcc 0x1,1
929 set_fcc 0xe,0 ; Set mask opposite of expected
930 set_fcc 0xe,1 ; Set mask opposite of expected
931 fdcmps fr60,fr20,fcc0
932 test_fcc 0x1,0
933 test_fcc 0x1,1
934 set_fcc 0xe,0 ; Set mask opposite of expected
935 set_fcc 0xe,1 ; Set mask opposite of expected
936 fdcmps fr60,fr24,fcc0
937 test_fcc 0x1,0
938 test_fcc 0x1,1
939 set_fcc 0xe,0 ; Set mask opposite of expected
940 set_fcc 0xe,1 ; Set mask opposite of expected
941 fdcmps fr60,fr28,fcc0
942 test_fcc 0x1,0
943 test_fcc 0x1,1
944 set_fcc 0xe,0 ; Set mask opposite of expected
945 set_fcc 0xe,1 ; Set mask opposite of expected
946 fdcmps fr60,fr32,fcc0
947 test_fcc 0x1,0
948 test_fcc 0x1,1
949 set_fcc 0xe,0 ; Set mask opposite of expected
950 set_fcc 0xe,1 ; Set mask opposite of expected
951 fdcmps fr60,fr36,fcc0
952 test_fcc 0x1,0
953 test_fcc 0x1,1
954 set_fcc 0xe,0 ; Set mask opposite of expected
955 set_fcc 0xe,1 ; Set mask opposite of expected
956 fdcmps fr60,fr40,fcc0
957 test_fcc 0x1,0
958 test_fcc 0x1,1
959 set_fcc 0xe,0 ; Set mask opposite of expected
960 set_fcc 0xe,1 ; Set mask opposite of expected
961 fdcmps fr60,fr44,fcc0
962 test_fcc 0x1,0
963 test_fcc 0x1,1
964 set_fcc 0xe,0 ; Set mask opposite of expected
965 set_fcc 0xe,1 ; Set mask opposite of expected
966 fdcmps fr60,fr48,fcc0
967 test_fcc 0x1,0
968 test_fcc 0x1,1
969 set_fcc 0xe,0 ; Set mask opposite of expected
970 set_fcc 0xe,1 ; Set mask opposite of expected
971 fdcmps fr60,fr52,fcc0
972 test_fcc 0x1,0
973 test_fcc 0x1,1
974 set_fcc 0xe,0 ; Set mask opposite of expected
975 set_fcc 0xe,1 ; Set mask opposite of expected
976 fdcmps fr60,fr56,fcc0
977 test_fcc 0x1,0
978 test_fcc 0x1,1
979 set_fcc 0xe,0 ; Set mask opposite of expected
980 set_fcc 0xe,1 ; Set mask opposite of expected
981 fdcmps fr60,fr60,fcc0
982 test_fcc 0x1,0
983 test_fcc 0x1,1
985 pass