sim/testsuite/frv/fr550/cmcpxru.cgs

   1 # frv testcase for cmcpxru $GRi,$GRj,$GRk,$CCi,$cond
   2 # mach: all
   3
   4         .include "../testutils.inc"
   5
   6         start
   7
   8         .global cmcpxru
   9 cmcpxru:
  10         set_spr_immed   0x1b1b,cccr
  11
  12         set_fr_iimmed   4,2,fr7         ; multiply small numbers
  13         set_fr_iimmed   5,3,fr8
  14         cmcpxru         fr7,fr8,acc0,cc0,1
  15         test_accg_immed         0,accg0
  16         test_acc_immed  14,acc0
  17
  18         set_fr_iimmed   1,2,fr7         ; multiply by 1
  19         set_fr_iimmed   3,1,fr8
  20         cmcpxru         fr7,fr8,acc0,cc0,1
  21         test_accg_immed         0,accg0
  22         test_acc_immed  1,acc0
  23
  24         set_fr_iimmed   0,2,fr7         ; multiply by 0
  25         set_fr_iimmed   2,0,fr8
  26         cmcpxru         fr7,fr8,acc0,cc0,1
  27         test_accg_immed         0,accg0
  28         test_acc_immed  0,acc0
  29
  30         set_fr_iimmed   0x3fff,1,fr7    ; 15 bit result
  31         set_fr_iimmed   2,0x0001,fr8
  32         cmcpxru         fr7,fr8,acc0,cc0,1
  33         test_accg_immed         0,accg0
  34         test_acc_limmed 0x0000,0x7ffd,acc0
  35
  36         set_fr_iimmed   0x4000,1,fr7    ; 16 bit result
  37         set_fr_iimmed   4,0x0001,fr8
  38         cmcpxru         fr7,fr8,acc0,cc0,1
  39         test_accg_immed         0,accg0
  40         test_acc_limmed 0x0000,0xffff,acc0
  41
  42         set_fr_iimmed   0x8000,1,fr7    ; 17 bit result
  43         set_fr_iimmed   4,0x0001,fr8
  44         cmcpxru         fr7,fr8,acc0,cc0,1
  45         test_accg_immed         0,accg0
  46         test_acc_immed  0x0001ffff,acc0
  47
  48         set_fr_iimmed   0x7fff,0x0000,fr7       ; max positive result
  49         set_fr_iimmed   0x7fff,0x7fff,fr8
  50         cmcpxru         fr7,fr8,acc0,cc4,1
  51         test_accg_immed         0,accg0
  52         test_acc_immed  0x3fff0001,acc0
  53
  54         set_fr_iimmed   0x8000,0x8000,fr7       ; max positive result
  55         set_fr_iimmed   0x8000,0x0000,fr8
  56         cmcpxru         fr7,fr8,acc0,cc4,1
  57         test_accg_immed         0,accg0
  58         test_acc_limmed 0x4000,0x0000,acc0
  59
  60         set_fr_iimmed   0xffff,0x0000,fr7       ; max positive result
  61         set_fr_iimmed   0xffff,0xffff,fr8
  62         cmcpxru         fr7,fr8,acc0,cc4,1
  63         test_accg_immed         0,accg0
  64         test_acc_limmed 0xfffe,0x0001,acc0
  65
  66         set_fr_iimmed   0x0000,0x0001,fr7       ; saturation
  67         set_fr_iimmed   0xffff,0x0001,fr8
  68         cmcpxru         fr7,fr8,acc0,cc4,1
  69         test_spr_bits   0x3c,2,0x8,msr0         ; msr0.sie is set
  70         test_spr_bits   2,1,1,msr0              ; msr0.ovf is set
  71         test_spr_bits   1,0,1,msr0              ; msr0.aovf is set
  72         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt is set
  73         test_accg_immed         0,accg0
  74         test_acc_immed  0,acc0
  75
  76         set_fr_iimmed   0x0000,0xffff,fr7       ; saturation
  77         set_fr_iimmed   0xffff,0xffff,fr8
  78         cmcpxru         fr7,fr8,acc0,cc4,1
  79         test_spr_bits   0x3c,2,0x8,msr0         ; msr0.sie is set
  80         test_spr_bits   2,1,1,msr0              ; msr0.ovf is set
  81         test_spr_bits   1,0,1,msr0              ; msr0.aovf is set
  82         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt is set
  83         test_accg_immed         0,accg0
  84         test_acc_immed  0,acc0
  85
  86         set_fr_iimmed   0xfffe,0xffff,fr7       ; saturation
  87         set_fr_iimmed   0xffff,0xffff,fr8
  88         cmcpxru         fr7,fr8,acc0,cc4,1
  89         test_spr_bits   0x3c,2,0x8,msr0         ; msr0.sie is set
  90         test_spr_bits   2,1,1,msr0              ; msr0.ovf is set
  91         test_spr_bits   1,0,1,msr0              ; msr0.aovf is set
  92         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt is set
  93         test_accg_immed         0,accg0
  94         test_acc_immed  0,acc0
  95
  96         set_fr_iimmed   4,2,fr7         ; multiply small numbers
  97         set_fr_iimmed   5,3,fr8
  98         cmcpxru         fr7,fr8,acc0,cc1,0
  99         test_accg_immed         0,accg0
 100         test_acc_immed  14,acc0
 101
 102         set_fr_iimmed   1,2,fr7         ; multiply by 1
 103         set_fr_iimmed   3,1,fr8
 104         cmcpxru         fr7,fr8,acc0,cc1,0
 105         test_accg_immed         0,accg0
 106         test_acc_immed  1,acc0
 107
 108         set_fr_iimmed   0,2,fr7         ; multiply by 0
 109         set_fr_iimmed   2,0,fr8
 110         cmcpxru         fr7,fr8,acc0,cc1,0
 111         test_accg_immed         0,accg0
 112         test_acc_immed  0,acc0
 113
 114         set_fr_iimmed   0x3fff,1,fr7    ; 15 bit result
 115         set_fr_iimmed   2,0x0001,fr8
 116         cmcpxru         fr7,fr8,acc0,cc1,0
 117         test_accg_immed         0,accg0
 118         test_acc_limmed 0x0000,0x7ffd,acc0
 119
 120         set_fr_iimmed   0x4000,1,fr7    ; 16 bit result
 121         set_fr_iimmed   4,0x0001,fr8
 122         cmcpxru         fr7,fr8,acc0,cc1,0
 123         test_accg_immed         0,accg0
 124         test_acc_limmed 0x0000,0xffff,acc0
 125
 126         set_fr_iimmed   0x8000,1,fr7    ; 17 bit result
 127         set_fr_iimmed   4,0x0001,fr8
 128         cmcpxru         fr7,fr8,acc0,cc1,0
 129         test_accg_immed         0,accg0
 130         test_acc_immed  0x0001ffff,acc0
 131
 132         set_fr_iimmed   0x7fff,0x0000,fr7       ; max positive result
 133         set_fr_iimmed   0x7fff,0x7fff,fr8
 134         cmcpxru         fr7,fr8,acc0,cc5,0
 135         test_accg_immed         0,accg0
 136         test_acc_immed  0x3fff0001,acc0
 137
 138         set_fr_iimmed   0x8000,0x8000,fr7       ; max positive result
 139         set_fr_iimmed   0x8000,0x0000,fr8
 140         cmcpxru         fr7,fr8,acc0,cc5,0
 141         test_accg_immed         0,accg0
 142         test_acc_limmed 0x4000,0x0000,acc0
 143
 144         set_fr_iimmed   0xffff,0x0000,fr7       ; max positive result
 145         set_fr_iimmed   0xffff,0xffff,fr8
 146         cmcpxru         fr7,fr8,acc0,cc5,0
 147         test_accg_immed         0,accg0
 148         test_acc_limmed 0xfffe,0x0001,acc0
 149
 150         set_fr_iimmed   0x0000,0x0001,fr7       ; saturation
 151         set_fr_iimmed   0xffff,0x0001,fr8
 152         cmcpxru         fr7,fr8,acc0,cc5,0
 153         test_spr_bits   0x3c,2,0x8,msr0         ; msr0.sie is set
 154         test_spr_bits   2,1,1,msr0              ; msr0.ovf is set
 155         test_spr_bits   1,0,1,msr0              ; msr0.aovf is set
 156         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt is set
 157         test_accg_immed         0,accg0
 158         test_acc_immed  0,acc0
 159
 160         set_fr_iimmed   0x0000,0xffff,fr7       ; saturation
 161         set_fr_iimmed   0xffff,0xffff,fr8
 162         cmcpxru         fr7,fr8,acc0,cc5,0
 163         test_spr_bits   0x3c,2,0x8,msr0         ; msr0.sie is set
 164         test_spr_bits   2,1,1,msr0              ; msr0.ovf is set
 165         test_spr_bits   1,0,1,msr0              ; msr0.aovf is set
 166         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt is set
 167         test_accg_immed         0,accg0
 168         test_acc_immed  0,acc0
 169
 170         set_fr_iimmed   0xfffe,0xffff,fr7       ; saturation
 171         set_fr_iimmed   0xffff,0xffff,fr8
 172         cmcpxru         fr7,fr8,acc0,cc5,0
 173         test_spr_bits   0x3c,2,0x8,msr0         ; msr0.sie is set
 174         test_spr_bits   2,1,1,msr0              ; msr0.ovf is set
 175         test_spr_bits   1,0,1,msr0              ; msr0.aovf is set
 176         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt is set
 177         test_accg_immed         0,accg0
 178         test_acc_immed  0,acc0
 179
 180         set_spr_immed   0,msr0
 181         set_accg_immed  0x00000011,accg0
 182         set_acc_immed   0x11111111,acc0
 183         set_fr_iimmed   4,2,fr7         ; multiply small numbers
 184         set_fr_iimmed   5,3,fr8
 185         cmcpxru         fr7,fr8,acc0,cc0,0
 186         test_accg_immed         0x00000011,accg0
 187         test_acc_immed  0x11111111,acc0
 188
 189         set_fr_iimmed   1,2,fr7         ; multiply by 1
 190         set_fr_iimmed   3,1,fr8
 191         cmcpxru         fr7,fr8,acc0,cc0,0
 192         test_accg_immed         0x00000011,accg0
 193         test_acc_immed  0x11111111,acc0
 194
 195         set_fr_iimmed   0,2,fr7         ; multiply by 0
 196         set_fr_iimmed   2,0,fr8
 197         cmcpxru         fr7,fr8,acc0,cc0,0
 198         test_accg_immed         0x00000011,accg0
 199         test_acc_immed  0x11111111,acc0
 200
 201         set_fr_iimmed   0x3fff,1,fr7    ; 15 bit result
 202         set_fr_iimmed   2,0x0001,fr8
 203         cmcpxru         fr7,fr8,acc0,cc0,0
 204         test_accg_immed         0x00000011,accg0
 205         test_acc_immed  0x11111111,acc0
 206
 207         set_fr_iimmed   0x4000,1,fr7    ; 16 bit result
 208         set_fr_iimmed   4,0x0001,fr8
 209         cmcpxru         fr7,fr8,acc0,cc0,0
 210         test_accg_immed         0x00000011,accg0
 211         test_acc_immed  0x11111111,acc0
 212
 213         set_fr_iimmed   0x8000,1,fr7    ; 17 bit result
 214         set_fr_iimmed   4,0x0001,fr8
 215         cmcpxru         fr7,fr8,acc0,cc0,0
 216         test_accg_immed         0x00000011,accg0
 217         test_acc_immed  0x11111111,acc0
 218
 219         set_fr_iimmed   0x7fff,0x0000,fr7       ; max positive result
 220         set_fr_iimmed   0x7fff,0x7fff,fr8
 221         cmcpxru         fr7,fr8,acc0,cc4,0
 222         test_accg_immed         0x00000011,accg0
 223         test_acc_immed  0x11111111,acc0
 224
 225         set_fr_iimmed   0x8000,0x8000,fr7       ; max positive result
 226         set_fr_iimmed   0x8000,0x0000,fr8
 227         cmcpxru         fr7,fr8,acc0,cc4,0
 228         test_accg_immed         0x00000011,accg0
 229         test_acc_immed  0x11111111,acc0
 230
 231         set_fr_iimmed   0xffff,0x0000,fr7       ; max positive result
 232         set_fr_iimmed   0xffff,0xffff,fr8
 233         cmcpxru         fr7,fr8,acc0,cc4,0
 234         test_accg_immed         0x00000011,accg0
 235         test_acc_immed  0x11111111,acc0
 236
 237         set_fr_iimmed   0x0000,0x0001,fr7       ; saturation
 238         set_fr_iimmed   0xffff,0x0001,fr8
 239         cmcpxru         fr7,fr8,acc0,cc4,0
 240         test_spr_bits   0x3c,2,0x0,msr0         ; msr0.sie is clear
 241         test_spr_bits   2,1,0,msr0              ; msr0.ovf is clear
 242         test_spr_bits   1,0,0,msr0              ; msr0.aovf is clear
 243         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt is always set
 244         test_accg_immed         0x00000011,accg0
 245         test_acc_immed  0x11111111,acc0
 246
 247         set_fr_iimmed   0x0000,0xffff,fr7       ; saturation
 248         set_fr_iimmed   0xffff,0xffff,fr8
 249         cmcpxru         fr7,fr8,acc0,cc4,0
 250         test_spr_bits   0x3c,2,0x0,msr0         ; msr0.sie is clear
 251         test_spr_bits   2,1,0,msr0              ; msr0.ovf is clear
 252         test_spr_bits   1,0,0,msr0              ; msr0.aovf is clear
 253         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt is always set
 254         test_accg_immed         0x00000011,accg0
 255         test_acc_immed  0x11111111,acc0
 256
 257         set_fr_iimmed   0xfffe,0xffff,fr7       ; saturation
 258         set_fr_iimmed   0xffff,0xffff,fr8
 259         cmcpxru         fr7,fr8,acc0,cc4,0
 260         test_spr_bits   0x3c,2,0x0,msr0         ; msr0.sie is clear
 261         test_spr_bits   2,1,0,msr0              ; msr0.ovf is clear
 262         test_spr_bits   1,0,0,msr0              ; msr0.aovf is clear
 263         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt is always set
 264         test_accg_immed         0x00000011,accg0
 265         test_acc_immed  0x11111111,acc0
 266
 267         set_spr_immed   0,msr0
 268         set_accg_immed  0x00000011,accg0
 269         set_acc_immed   0x11111111,acc0
 270         set_fr_iimmed   4,2,fr7         ; multiply small numbers
 271         set_fr_iimmed   5,3,fr8
 272         cmcpxru         fr7,fr8,acc0,cc1,1
 273         test_accg_immed         0x00000011,accg0
 274         test_acc_immed  0x11111111,acc0
 275
 276         set_fr_iimmed   1,2,fr7         ; multiply by 1
 277         set_fr_iimmed   3,1,fr8
 278         cmcpxru         fr7,fr8,acc0,cc1,1
 279         test_accg_immed         0x00000011,accg0
 280         test_acc_immed  0x11111111,acc0
 281
 282         set_fr_iimmed   0,2,fr7         ; multiply by 0
 283         set_fr_iimmed   2,0,fr8
 284         cmcpxru         fr7,fr8,acc0,cc1,1
 285         test_accg_immed         0x00000011,accg0
 286         test_acc_immed  0x11111111,acc0
 287
 288         set_fr_iimmed   0x3fff,1,fr7    ; 15 bit result
 289         set_fr_iimmed   2,0x0001,fr8
 290         cmcpxru         fr7,fr8,acc0,cc1,1
 291         test_accg_immed         0x00000011,accg0
 292         test_acc_immed  0x11111111,acc0
 293
 294         set_fr_iimmed   0x4000,1,fr7    ; 16 bit result
 295         set_fr_iimmed   4,0x0001,fr8
 296         cmcpxru         fr7,fr8,acc0,cc1,1
 297         test_accg_immed         0x00000011,accg0
 298         test_acc_immed  0x11111111,acc0
 299
 300         set_fr_iimmed   0x8000,1,fr7    ; 17 bit result
 301         set_fr_iimmed   4,0x0001,fr8
 302         cmcpxru         fr7,fr8,acc0,cc1,1
 303         test_accg_immed         0x00000011,accg0
 304         test_acc_immed  0x11111111,acc0
 305
 306         set_fr_iimmed   0x7fff,0x0000,fr7       ; max positive result
 307         set_fr_iimmed   0x7fff,0x7fff,fr8
 308         cmcpxru         fr7,fr8,acc0,cc5,1
 309         test_accg_immed         0x00000011,accg0
 310         test_acc_immed  0x11111111,acc0
 311
 312         set_fr_iimmed   0x8000,0x8000,fr7       ; max positive result
 313         set_fr_iimmed   0x8000,0x0000,fr8
 314         cmcpxru         fr7,fr8,acc0,cc5,1
 315         test_accg_immed         0x00000011,accg0
 316         test_acc_immed  0x11111111,acc0
 317
 318         set_fr_iimmed   0xffff,0x0000,fr7       ; max positive result
 319         set_fr_iimmed   0xffff,0xffff,fr8
 320         cmcpxru         fr7,fr8,acc0,cc5,1
 321         test_accg_immed         0x00000011,accg0
 322         test_acc_immed  0x11111111,acc0
 323
 324         set_fr_iimmed   0x0000,0x0001,fr7       ; saturation
 325         set_fr_iimmed   0xffff,0x0001,fr8
 326         cmcpxru         fr7,fr8,acc0,cc5,1
 327         test_spr_bits   0x3c,2,0x0,msr0         ; msr0.sie is clear
 328         test_spr_bits   2,1,0,msr0              ; msr0.ovf is clear
 329         test_spr_bits   1,0,0,msr0              ; msr0.aovf is clear
 330         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt is always set
 331         test_accg_immed         0x00000011,accg0
 332         test_acc_immed  0x11111111,acc0
 333
 334         set_fr_iimmed   0x0000,0xffff,fr7       ; saturation
 335         set_fr_iimmed   0xffff,0xffff,fr8
 336         cmcpxru         fr7,fr8,acc0,cc5,1
 337         test_spr_bits   0x3c,2,0x0,msr0         ; msr0.sie is clear
 338         test_spr_bits   2,1,0,msr0              ; msr0.ovf is clear
 339         test_spr_bits   1,0,0,msr0              ; msr0.aovf is clear
 340         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt is always set
 341         test_accg_immed         0x00000011,accg0
 342         test_acc_immed  0x11111111,acc0
 343
 344         set_fr_iimmed   0xfffe,0xffff,fr7       ; saturation
 345         set_fr_iimmed   0xffff,0xffff,fr8
 346         cmcpxru         fr7,fr8,acc0,cc5,1
 347         test_spr_bits   0x3c,2,0x0,msr0         ; msr0.sie is clear
 348         test_spr_bits   2,1,0,msr0              ; msr0.ovf is clear
 349         test_spr_bits   1,0,0,msr0              ; msr0.aovf is clear
 350         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt is always set
 351         test_accg_immed         0x00000011,accg0
 352         test_acc_immed  0x11111111,acc0
 353
 354         set_spr_immed   0,msr0
 355         set_accg_immed  0x00000011,accg0
 356         set_acc_immed   0x11111111,acc0
 357         set_fr_iimmed   4,2,fr7         ; multiply small numbers
 358         set_fr_iimmed   5,3,fr8
 359         cmcpxru         fr7,fr8,acc0,cc2,1
 360         test_accg_immed         0x00000011,accg0
 361         test_acc_immed  0x11111111,acc0
 362
 363         set_fr_iimmed   1,2,fr7         ; multiply by 1
 364         set_fr_iimmed   3,1,fr8
 365         cmcpxru         fr7,fr8,acc0,cc2,1
 366         test_accg_immed         0x00000011,accg0
 367         test_acc_immed  0x11111111,acc0
 368
 369         set_fr_iimmed   0,2,fr7         ; multiply by 0
 370         set_fr_iimmed   2,0,fr8
 371         cmcpxru         fr7,fr8,acc0,cc2,1
 372         test_accg_immed         0x00000011,accg0
 373         test_acc_immed  0x11111111,acc0
 374
 375         set_fr_iimmed   0x3fff,1,fr7    ; 15 bit result
 376         set_fr_iimmed   2,0x0001,fr8
 377         cmcpxru         fr7,fr8,acc0,cc2,1
 378         test_accg_immed         0x00000011,accg0
 379         test_acc_immed  0x11111111,acc0
 380
 381         set_fr_iimmed   0x4000,1,fr7    ; 16 bit result
 382         set_fr_iimmed   4,0x0001,fr8
 383         cmcpxru         fr7,fr8,acc0,cc2,1
 384         test_accg_immed         0x00000011,accg0
 385         test_acc_immed  0x11111111,acc0
 386
 387         set_fr_iimmed   0x8000,1,fr7    ; 17 bit result
 388         set_fr_iimmed   4,0x0001,fr8
 389         cmcpxru         fr7,fr8,acc0,cc2,1
 390         test_accg_immed         0x00000011,accg0
 391         test_acc_immed  0x11111111,acc0
 392
 393         set_fr_iimmed   0x7fff,0x0000,fr7       ; max positive result
 394         set_fr_iimmed   0x7fff,0x7fff,fr8
 395         cmcpxru         fr7,fr8,acc0,cc6,1
 396         test_accg_immed         0x00000011,accg0
 397         test_acc_immed  0x11111111,acc0
 398
 399         set_fr_iimmed   0x8000,0x8000,fr7       ; max positive result
 400         set_fr_iimmed   0x8000,0x0000,fr8
 401         cmcpxru         fr7,fr8,acc0,cc6,1
 402         test_accg_immed         0x00000011,accg0
 403         test_acc_immed  0x11111111,acc0
 404
 405         set_fr_iimmed   0xffff,0x0000,fr7       ; max positive result
 406         set_fr_iimmed   0xffff,0xffff,fr8
 407         cmcpxru         fr7,fr8,acc0,cc6,1
 408         test_accg_immed         0x00000011,accg0
 409         test_acc_immed  0x11111111,acc0
 410
 411         set_fr_iimmed   0x0000,0x0001,fr7       ; saturation
 412         set_fr_iimmed   0xffff,0x0001,fr8
 413         cmcpxru         fr7,fr8,acc0,cc6,1
 414         test_spr_bits   0x3c,2,0x0,msr0         ; msr0.sie is clear
 415         test_spr_bits   2,1,0,msr0              ; msr0.ovf is clear
 416         test_spr_bits   1,0,0,msr0              ; msr0.aovf is clear
 417         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt is always set
 418         test_accg_immed         0x00000011,accg0
 419         test_acc_immed  0x11111111,acc0
 420
 421         set_fr_iimmed   0x0000,0xffff,fr7       ; saturation
 422         set_fr_iimmed   0xffff,0xffff,fr8
 423         cmcpxru         fr7,fr8,acc0,cc6,1
 424         test_spr_bits   0x3c,2,0x0,msr0         ; msr0.sie is clear
 425         test_spr_bits   2,1,0,msr0              ; msr0.ovf is clear
 426         test_spr_bits   1,0,0,msr0              ; msr0.aovf is clear
 427         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt is always set
 428         test_accg_immed         0x00000011,accg0
 429         test_acc_immed  0x11111111,acc0
 430
 431         set_fr_iimmed   0xfffe,0xffff,fr7       ; saturation
 432         set_fr_iimmed   0xffff,0xffff,fr8
 433         cmcpxru         fr7,fr8,acc0,cc6,1
 434         test_spr_bits   0x3c,2,0x0,msr0         ; msr0.sie is clear
 435         test_spr_bits   2,1,0,msr0              ; msr0.ovf is clear
 436         test_spr_bits   1,0,0,msr0              ; msr0.aovf is clear
 437         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt is always set
 438         test_accg_immed         0x00000011,accg0
 439         test_acc_immed  0x11111111,acc0
 440 ;
 441         set_spr_immed   0,msr0
 442         set_accg_immed  0x00000011,accg0
 443         set_acc_immed   0x11111111,acc0
 444         set_fr_iimmed   4,2,fr7         ; multiply small numbers
 445         set_fr_iimmed   5,3,fr8
 446         cmcpxru         fr7,fr8,acc0,cc3,1
 447         test_accg_immed         0x00000011,accg0
 448         test_acc_immed  0x11111111,acc0
 449
 450         set_fr_iimmed   1,2,fr7         ; multiply by 1
 451         set_fr_iimmed   3,1,fr8
 452         cmcpxru         fr7,fr8,acc0,cc3,1
 453         test_accg_immed         0x00000011,accg0
 454         test_acc_immed  0x11111111,acc0
 455
 456         set_fr_iimmed   0,2,fr7         ; multiply by 0
 457         set_fr_iimmed   2,0,fr8
 458         cmcpxru         fr7,fr8,acc0,cc3,1
 459         test_accg_immed         0x00000011,accg0
 460         test_acc_immed  0x11111111,acc0
 461
 462         set_fr_iimmed   0x3fff,1,fr7    ; 15 bit result
 463         set_fr_iimmed   2,0x0001,fr8
 464         cmcpxru         fr7,fr8,acc0,cc3,1
 465         test_accg_immed         0x00000011,accg0
 466         test_acc_immed  0x11111111,acc0
 467
 468         set_fr_iimmed   0x4000,1,fr7    ; 16 bit result
 469         set_fr_iimmed   4,0x0001,fr8
 470         cmcpxru         fr7,fr8,acc0,cc3,1
 471         test_accg_immed         0x00000011,accg0
 472         test_acc_immed  0x11111111,acc0
 473
 474         set_fr_iimmed   0x8000,1,fr7    ; 17 bit result
 475         set_fr_iimmed   4,0x0001,fr8
 476         cmcpxru         fr7,fr8,acc0,cc3,1
 477         test_accg_immed         0x00000011,accg0
 478         test_acc_immed  0x11111111,acc0
 479
 480         set_fr_iimmed   0x7fff,0x0000,fr7       ; max positive result
 481         set_fr_iimmed   0x7fff,0x7fff,fr8
 482         cmcpxru         fr7,fr8,acc0,cc7,1
 483         test_accg_immed         0x00000011,accg0
 484         test_acc_immed  0x11111111,acc0
 485
 486         set_fr_iimmed   0x8000,0x8000,fr7       ; max positive result
 487         set_fr_iimmed   0x8000,0x0000,fr8
 488         cmcpxru         fr7,fr8,acc0,cc7,1
 489         test_accg_immed         0x00000011,accg0
 490         test_acc_immed  0x11111111,acc0
 491
 492         set_fr_iimmed   0xffff,0x0000,fr7       ; max positive result
 493         set_fr_iimmed   0xffff,0xffff,fr8
 494         cmcpxru         fr7,fr8,acc0,cc7,1
 495         test_accg_immed         0x00000011,accg0
 496         test_acc_immed  0x11111111,acc0
 497
 498         set_fr_iimmed   0x0000,0x0001,fr7       ; saturation
 499         set_fr_iimmed   0xffff,0x0001,fr8
 500         cmcpxru         fr7,fr8,acc0,cc7,1
 501         test_spr_bits   0x3c,2,0x0,msr0         ; msr0.sie is clear
 502         test_spr_bits   2,1,0,msr0              ; msr0.ovf is clear
 503         test_spr_bits   1,0,0,msr0              ; msr0.aovf is clear
 504         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt is always set
 505         test_accg_immed         0x00000011,accg0
 506         test_acc_immed  0x11111111,acc0
 507
 508         set_fr_iimmed   0x0000,0xffff,fr7       ; saturation
 509         set_fr_iimmed   0xffff,0xffff,fr8
 510         cmcpxru         fr7,fr8,acc0,cc7,1
 511         test_spr_bits   0x3c,2,0x0,msr0         ; msr0.sie is clear
 512         test_spr_bits   2,1,0,msr0              ; msr0.ovf is clear
 513         test_spr_bits   1,0,0,msr0              ; msr0.aovf is clear
 514         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt is always set
 515         test_accg_immed         0x00000011,accg0
 516         test_acc_immed  0x11111111,acc0
 517
 518         set_fr_iimmed   0xfffe,0xffff,fr7       ; saturation
 519         set_fr_iimmed   0xffff,0xffff,fr8
 520         cmcpxru         fr7,fr8,acc0,cc7,1
 521         test_spr_bits   0x3c,2,0x0,msr0         ; msr0.sie is clear
 522         test_spr_bits   2,1,0,msr0              ; msr0.ovf is clear
 523         test_spr_bits   1,0,0,msr0              ; msr0.aovf is clear
 524         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt is always set
 525         test_accg_immed         0x00000011,accg0
 526         test_acc_immed  0x11111111,acc0
 527
 528         pass