sim/testsuite/frv/fr550/cmqmachs.cgs

   1 # frv testcase for cmqmachs $GRi,$GRj,$ACCk,$CCi,$cond
   2 # mach: all
   3
   4         .include "../testutils.inc"
   5
   6         start
   7
   8         .global cmqmachs
   9 cmqmachs:
  10         set_spr_immed   0x1b1b,cccr
  11
  12         ; Positive operands
  13         set_spr_immed   0,msr0
  14         set_accg_immed  0,accg0
  15         set_acc_immed   0,acc0
  16         set_accg_immed  0,accg1
  17         set_acc_immed   0,acc1
  18         set_accg_immed  0,accg2
  19         set_acc_immed   0,acc2
  20         set_accg_immed  0,accg3
  21         set_acc_immed   0,acc3
  22         set_fr_iimmed   2,3,fr8         ; multiply small numbers
  23         set_fr_iimmed   3,2,fr10
  24         set_fr_iimmed   0,1,fr9         ; multiply by 0
  25         set_fr_iimmed   2,0,fr11
  26         cmqmachs        fr8,fr10,acc0,cc0,1
  27         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  28         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  29         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  30         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
  31         test_accg_immed         0,accg0
  32         test_acc_immed  6,acc0
  33         test_accg_immed         0,accg1
  34         test_acc_immed  6,acc1
  35         test_accg_immed         0,accg2
  36         test_acc_immed  0,acc2
  37         test_accg_immed         0,accg3
  38         test_acc_immed  0,acc3
  39
  40         set_fr_iimmed   2,1,fr8         ; multiply by 1
  41         set_fr_iimmed   1,2,fr10
  42         set_fr_iimmed   0x3fff,2,fr9    ; 15 bit result
  43         set_fr_iimmed   2,0x3fff,fr11
  44         cmqmachs        fr8,fr10,acc0,cc0,1
  45         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  46         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  47         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  48         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
  49         test_accg_immed         0,accg0
  50         test_acc_immed  8,acc0
  51         test_accg_immed         0,accg1
  52         test_acc_immed  8,acc1
  53         test_accg_immed         0,accg2
  54         test_acc_limmed 0,0x7ffe,acc2
  55         test_accg_immed         0,accg3
  56         test_acc_limmed 0,0x7ffe,acc3
  57
  58         set_fr_iimmed   0x4000,2,fr8    ; 16 bit result
  59         set_fr_iimmed   2,0x4000,fr10
  60         set_fr_iimmed   0x7fff,0x7fff,fr9       ; max positive result
  61         set_fr_iimmed   0x7fff,0x7fff,fr11
  62         cmqmachs        fr8,fr10,acc0,cc0,1
  63         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  64         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  65         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  66         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
  67         test_accg_immed         0,accg0
  68         test_acc_limmed 0x0000,0x8008,acc0
  69         test_accg_immed         0,accg1
  70         test_acc_limmed 0x0000,0x8008,acc1
  71         test_accg_immed         0,accg2
  72         test_acc_limmed 0x3fff,0x7fff,acc2
  73         test_accg_immed         0,accg3
  74         test_acc_limmed 0x3fff,0x7fff,acc3
  75
  76         ; Mixed operands
  77         set_fr_iimmed   2,0xfffd,fr8            ; multiply small numbers
  78         set_fr_iimmed   0xfffd,2,fr10
  79         set_fr_iimmed   0xfffe,1,fr9            ; multiply by 1
  80         set_fr_iimmed   1,0xfffe,fr11
  81         cmqmachs        fr8,fr10,acc0,cc0,1
  82         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  83         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  84         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  85         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
  86         test_accg_immed         0,accg0
  87         test_acc_limmed 0x0000,0x8002,acc0
  88         test_accg_immed         0,accg1
  89         test_acc_limmed 0x0000,0x8002,acc1
  90         test_accg_immed         0,accg2
  91         test_acc_limmed 0x3fff,0x7ffd,acc2
  92         test_accg_immed         0,accg3
  93         test_acc_limmed 0x3fff,0x7ffd,acc3
  94
  95         set_fr_iimmed   0xfffe,0,fr8            ; multiply by 0
  96         set_fr_iimmed   0,0xfffe,fr10
  97         set_fr_iimmed   0x2001,0xfffe,fr9       ; 15 bit result
  98         set_fr_iimmed   0xfffe,0x2001,fr11
  99         cmqmachs        fr8,fr10,acc0,cc0,1
 100         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 101         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 102         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 103         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 104         test_accg_immed         0,accg0
 105         test_acc_limmed 0x0000,0x8002,acc0
 106         test_accg_immed         0,accg1
 107         test_acc_limmed 0x0000,0x8002,acc1
 108         test_accg_immed         0,accg2
 109         test_acc_limmed 0x3fff,0x3ffb,acc2
 110         test_accg_immed         0,accg3
 111         test_acc_limmed 0x3fff,0x3ffb,acc3
 112
 113         set_fr_iimmed   0x4000,0xfffe,fr8       ; 16 bit result
 114         set_fr_iimmed   0xfffe,0x4000,fr10
 115         set_fr_iimmed   0x7fff,0x8000,fr9       ; max negative result
 116         set_fr_iimmed   0x8000,0x7fff,fr11
 117         cmqmachs        fr8,fr10,acc0,cc4,1
 118         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 119         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 120         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 121         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 122         test_accg_immed         0,accg0
 123         test_acc_limmed 0x0000,0x0002,acc0
 124         test_accg_immed         0,accg1
 125         test_acc_limmed 0x0000,0x0002,acc1
 126         test_accg_immed         0xff,accg2
 127         test_acc_limmed 0xffff,0xbffb,acc2
 128         test_accg_immed         0xff,accg3
 129         test_acc_limmed 0xffff,0xbffb,acc3
 130
 131         ; Negative operands
 132         set_fr_iimmed   0xfffe,0xfffd,fr8               ; multiply small numbers
 133         set_fr_iimmed   0xfffd,0xfffe,fr10
 134         set_fr_iimmed   0xffff,0xfffe,fr9               ; multiply by -1
 135         set_fr_iimmed   0xfffe,0xffff,fr11
 136         cmqmachs        fr8,fr10,acc0,cc4,1
 137         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 138         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 139         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 140         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 141         test_accg_immed         0,accg0
 142         test_acc_limmed 0x0000,0x0008,acc0
 143         test_accg_immed         0,accg1
 144         test_acc_limmed 0x0000,0x0008,acc1
 145         test_accg_immed         0xff,accg2
 146         test_acc_limmed 0xffff,0xbffd,acc2
 147         test_accg_immed         0xff,accg3
 148         test_acc_limmed 0xffff,0xbffd,acc3
 149
 150         set_fr_iimmed   0x8001,0x8001,fr8       ; almost max positive result
 151         set_fr_iimmed   0x8001,0x8001,fr10
 152         set_fr_iimmed   0x8000,0x8000,fr9       ; max positive result
 153         set_fr_iimmed   0x8000,0x8000,fr11
 154         cmqmachs        fr8,fr10,acc0,cc4,1
 155         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 156         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 157         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 158         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 159         test_accg_immed         0,accg0
 160         test_acc_immed  0x3fff0009,acc0
 161         test_accg_immed         0,accg1
 162         test_acc_immed  0x3fff0009,acc1
 163         test_accg_immed         0,accg2
 164         test_acc_immed  0x3fffbffd,acc2
 165         test_accg_immed         0,accg3
 166         test_acc_immed  0x3fffbffd,acc3
 167
 168         set_accg_immed  0x7f,accg0              ; saturation
 169         set_acc_immed   0xffffffff,acc0
 170         set_accg_immed  0x7f,accg1
 171         set_acc_immed   0xffffffff,acc1
 172         set_accg_immed  0x7f,accg2              ; saturation
 173         set_acc_immed   0xffffffff,acc2
 174         set_accg_immed  0x7f,accg3
 175         set_acc_immed   0xffffffff,acc3
 176         set_fr_iimmed   1,1,fr8
 177         set_fr_iimmed   1,1,fr10
 178         set_fr_iimmed   0x7fff,0x7fff,fr9       ; saturation
 179         set_fr_iimmed   0x7fff,0x7fff,fr11
 180         cmqmachs        fr8,fr10,acc0,cc4,1
 181         test_spr_bits   0x3c,2,0xf,msr0         ; msr0.sie is set
 182         test_spr_bits   2,1,1,msr0              ; msr0.ovf is set
 183         test_spr_bits   1,0,1,msr0              ; msr0.aovf is set
 184         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt is set
 185         test_accg_immed         0x7f,accg0
 186         test_acc_limmed 0xffff,0xffff,acc0
 187         test_accg_immed         0x7f,accg1
 188         test_acc_limmed 0xffff,0xffff,acc1
 189         test_accg_immed         0x7f,accg2
 190         test_acc_limmed 0xffff,0xffff,acc2
 191         test_accg_immed         0x7f,accg3
 192         test_acc_limmed 0xffff,0xffff,acc3
 193
 194         set_accg_immed  0x80,accg0              ; saturation
 195         set_acc_immed   0,acc0
 196         set_accg_immed  0x80,accg1
 197         set_acc_immed   0,acc1
 198         set_accg_immed  0x80,accg2              ; saturation
 199         set_acc_immed   0,acc2
 200         set_accg_immed  0x80,accg3
 201         set_acc_immed   0,acc3
 202         set_fr_iimmed   0xffff,0,fr8
 203         set_fr_iimmed   1,0xffff,fr10
 204         set_fr_iimmed   0x0000,0x8000,fr9       ; saturation
 205         set_fr_iimmed   0x7fff,0x7fff,fr11
 206         cmqmachs        fr8,fr10,acc0,cc4,1
 207         test_spr_bits   0x3c,2,0x9,msr0         ; msr0.sie is set
 208         test_spr_bits   2,1,1,msr0              ; msr0.ovf is set
 209         test_spr_bits   1,0,1,msr0              ; msr0.aovf is set
 210         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt is set
 211         test_accg_immed         0x80,accg0
 212         test_acc_immed  0,acc0
 213         test_accg_immed         0x80,accg1
 214         test_acc_immed  0,acc1
 215         test_accg_immed         0x80,accg2
 216         test_acc_immed  0,acc2
 217         test_accg_immed         0x80,accg3
 218         test_acc_immed  0,acc3
 219
 220         ; Positive operands
 221         set_spr_immed   0,msr0
 222         set_accg_immed  0,accg0
 223         set_acc_immed   0,acc0
 224         set_accg_immed  0,accg1
 225         set_acc_immed   0,acc1
 226         set_accg_immed  0,accg2
 227         set_acc_immed   0,acc2
 228         set_accg_immed  0,accg3
 229         set_acc_immed   0,acc3
 230         set_fr_iimmed   2,3,fr8         ; multiply small numbers
 231         set_fr_iimmed   3,2,fr10
 232         set_fr_iimmed   0,1,fr9         ; multiply by 0
 233         set_fr_iimmed   2,0,fr11
 234         cmqmachs        fr8,fr10,acc0,cc1,0
 235         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 236         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 237         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 238         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 239         test_accg_immed         0,accg0
 240         test_acc_immed  6,acc0
 241         test_accg_immed         0,accg1
 242         test_acc_immed  6,acc1
 243         test_accg_immed         0,accg2
 244         test_acc_immed  0,acc2
 245         test_accg_immed         0,accg3
 246         test_acc_immed  0,acc3
 247
 248         set_fr_iimmed   2,1,fr8         ; multiply by 1
 249         set_fr_iimmed   1,2,fr10
 250         set_fr_iimmed   0x3fff,2,fr9    ; 15 bit result
 251         set_fr_iimmed   2,0x3fff,fr11
 252         cmqmachs        fr8,fr10,acc0,cc1,0
 253         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 254         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 255         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 256         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 257         test_accg_immed         0,accg0
 258         test_acc_immed  8,acc0
 259         test_accg_immed         0,accg1
 260         test_acc_immed  8,acc1
 261         test_accg_immed         0,accg2
 262         test_acc_limmed 0,0x7ffe,acc2
 263         test_accg_immed         0,accg3
 264         test_acc_limmed 0,0x7ffe,acc3
 265
 266         set_fr_iimmed   0x4000,2,fr8    ; 16 bit result
 267         set_fr_iimmed   2,0x4000,fr10
 268         set_fr_iimmed   0x7fff,0x7fff,fr9       ; max positive result
 269         set_fr_iimmed   0x7fff,0x7fff,fr11
 270         cmqmachs        fr8,fr10,acc0,cc1,0
 271         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 272         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 273         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 274         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 275         test_accg_immed         0,accg0
 276         test_acc_limmed 0x0000,0x8008,acc0
 277         test_accg_immed         0,accg1
 278         test_acc_limmed 0x0000,0x8008,acc1
 279         test_accg_immed         0,accg2
 280         test_acc_limmed 0x3fff,0x7fff,acc2
 281         test_accg_immed         0,accg3
 282         test_acc_limmed 0x3fff,0x7fff,acc3
 283
 284         ; Mixed operands
 285         set_fr_iimmed   2,0xfffd,fr8            ; multiply small numbers
 286         set_fr_iimmed   0xfffd,2,fr10
 287         set_fr_iimmed   0xfffe,1,fr9            ; multiply by 1
 288         set_fr_iimmed   1,0xfffe,fr11
 289         cmqmachs        fr8,fr10,acc0,cc1,0
 290         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 291         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 292         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 293         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 294         test_accg_immed         0,accg0
 295         test_acc_limmed 0x0000,0x8002,acc0
 296         test_accg_immed         0,accg1
 297         test_acc_limmed 0x0000,0x8002,acc1
 298         test_accg_immed         0,accg2
 299         test_acc_limmed 0x3fff,0x7ffd,acc2
 300         test_accg_immed         0,accg3
 301         test_acc_limmed 0x3fff,0x7ffd,acc3
 302
 303         set_fr_iimmed   0xfffe,0,fr8            ; multiply by 0
 304         set_fr_iimmed   0,0xfffe,fr10
 305         set_fr_iimmed   0x2001,0xfffe,fr9       ; 15 bit result
 306         set_fr_iimmed   0xfffe,0x2001,fr11
 307         cmqmachs        fr8,fr10,acc0,cc1,0
 308         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 309         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 310         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 311         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 312         test_accg_immed         0,accg0
 313         test_acc_limmed 0x0000,0x8002,acc0
 314         test_accg_immed         0,accg1
 315         test_acc_limmed 0x0000,0x8002,acc1
 316         test_accg_immed         0,accg2
 317         test_acc_limmed 0x3fff,0x3ffb,acc2
 318         test_accg_immed         0,accg3
 319         test_acc_limmed 0x3fff,0x3ffb,acc3
 320
 321         set_fr_iimmed   0x4000,0xfffe,fr8       ; 16 bit result
 322         set_fr_iimmed   0xfffe,0x4000,fr10
 323         set_fr_iimmed   0x7fff,0x8000,fr9       ; max negative result
 324         set_fr_iimmed   0x8000,0x7fff,fr11
 325         cmqmachs        fr8,fr10,acc0,cc5,0
 326         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 327         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 328         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 329         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 330         test_accg_immed         0,accg0
 331         test_acc_limmed 0x0000,0x0002,acc0
 332         test_accg_immed         0,accg1
 333         test_acc_limmed 0x0000,0x0002,acc1
 334         test_accg_immed         0xff,accg2
 335         test_acc_limmed 0xffff,0xbffb,acc2
 336         test_accg_immed         0xff,accg3
 337         test_acc_limmed 0xffff,0xbffb,acc3
 338
 339         ; Negative operands
 340         set_fr_iimmed   0xfffe,0xfffd,fr8               ; multiply small numbers
 341         set_fr_iimmed   0xfffd,0xfffe,fr10
 342         set_fr_iimmed   0xffff,0xfffe,fr9               ; multiply by -1
 343         set_fr_iimmed   0xfffe,0xffff,fr11
 344         cmqmachs        fr8,fr10,acc0,cc5,0
 345         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 346         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 347         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 348         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 349         test_accg_immed         0,accg0
 350         test_acc_limmed 0x0000,0x0008,acc0
 351         test_accg_immed         0,accg1
 352         test_acc_limmed 0x0000,0x0008,acc1
 353         test_accg_immed         0xff,accg2
 354         test_acc_limmed 0xffff,0xbffd,acc2
 355         test_accg_immed         0xff,accg3
 356         test_acc_limmed 0xffff,0xbffd,acc3
 357
 358         set_fr_iimmed   0x8001,0x8001,fr8       ; almost max positive result
 359         set_fr_iimmed   0x8001,0x8001,fr10
 360         set_fr_iimmed   0x8000,0x8000,fr9       ; max positive result
 361         set_fr_iimmed   0x8000,0x8000,fr11
 362         cmqmachs        fr8,fr10,acc0,cc5,0
 363         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 364         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 365         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 366         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 367         test_accg_immed         0,accg0
 368         test_acc_immed  0x3fff0009,acc0
 369         test_accg_immed         0,accg1
 370         test_acc_immed  0x3fff0009,acc1
 371         test_accg_immed         0,accg2
 372         test_acc_immed  0x3fffbffd,acc2
 373         test_accg_immed         0,accg3
 374         test_acc_immed  0x3fffbffd,acc3
 375
 376         set_accg_immed  0x7f,accg0              ; saturation
 377         set_acc_immed   0xffffffff,acc0
 378         set_accg_immed  0x7f,accg1
 379         set_acc_immed   0xffffffff,acc1
 380         set_accg_immed  0x7f,accg2              ; saturation
 381         set_acc_immed   0xffffffff,acc2
 382         set_accg_immed  0x7f,accg3
 383         set_acc_immed   0xffffffff,acc3
 384         set_fr_iimmed   1,1,fr8
 385         set_fr_iimmed   1,1,fr10
 386         set_fr_iimmed   0x7fff,0x7fff,fr9       ; saturation
 387         set_fr_iimmed   0x7fff,0x7fff,fr11
 388         cmqmachs        fr8,fr10,acc0,cc5,0
 389         test_spr_bits   0x3c,2,0xf,msr0         ; msr0.sie is set
 390         test_spr_bits   2,1,1,msr0              ; msr0.ovf is set
 391         test_spr_bits   1,0,1,msr0              ; msr0.aovf is set
 392         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt is set
 393         test_accg_immed         0x7f,accg0
 394         test_acc_limmed 0xffff,0xffff,acc0
 395         test_accg_immed         0x7f,accg1
 396         test_acc_limmed 0xffff,0xffff,acc1
 397         test_accg_immed         0x7f,accg2
 398         test_acc_limmed 0xffff,0xffff,acc2
 399         test_accg_immed         0x7f,accg3
 400         test_acc_limmed 0xffff,0xffff,acc3
 401
 402         set_accg_immed  0x80,accg0              ; saturation
 403         set_acc_immed   0,acc0
 404         set_accg_immed  0x80,accg1
 405         set_acc_immed   0,acc1
 406         set_accg_immed  0x80,accg2              ; saturation
 407         set_acc_immed   0,acc2
 408         set_accg_immed  0x80,accg3
 409         set_acc_immed   0,acc3
 410         set_fr_iimmed   0xffff,0,fr8
 411         set_fr_iimmed   1,0xffff,fr10
 412         set_fr_iimmed   0x0000,0x8000,fr9       ; saturation
 413         set_fr_iimmed   0x7fff,0x7fff,fr11
 414         cmqmachs        fr8,fr10,acc0,cc5,0
 415         test_spr_bits   0x3c,2,0x9,msr0         ; msr0.sie is set
 416         test_spr_bits   2,1,1,msr0              ; msr0.ovf is set
 417         test_spr_bits   1,0,1,msr0              ; msr0.aovf is set
 418         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt is set
 419         test_accg_immed         0x80,accg0
 420         test_acc_immed  0,acc0
 421         test_accg_immed         0x80,accg1
 422         test_acc_immed  0,acc1
 423         test_accg_immed         0x80,accg2
 424         test_acc_immed  0,acc2
 425         test_accg_immed         0x80,accg3
 426         test_acc_immed  0,acc3
 427
 428         ; Positive operands
 429         set_spr_immed   0,msr0
 430         set_accg_immed  0x00000011,accg0
 431         set_acc_immed   0x11111111,acc0
 432         set_accg_immed  0x00000022,accg1
 433         set_acc_immed   0x22222222,acc1
 434         set_accg_immed  0x00000033,accg2
 435         set_acc_immed   0x33333333,acc2
 436         set_accg_immed  0x00000044,accg3
 437         set_acc_immed   0x44444444,acc3
 438         set_fr_iimmed   2,3,fr8         ; multiply small numbers
 439         set_fr_iimmed   3,2,fr10
 440         set_fr_iimmed   0,1,fr9         ; multiply by 0
 441         set_fr_iimmed   2,0,fr11
 442         cmqmachs        fr8,fr10,acc0,cc0,0
 443         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 444         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 445         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 446         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 447         test_accg_immed         0x00000011,accg0
 448         test_acc_immed  0x11111111,acc0
 449         test_accg_immed         0x00000022,accg1
 450         test_acc_immed  0x22222222,acc1
 451         test_accg_immed         0x00000033,accg2
 452         test_acc_immed  0x33333333,acc2
 453         test_accg_immed         0x00000044,accg3
 454         test_acc_immed  0x44444444,acc3
 455
 456         set_fr_iimmed   2,1,fr8         ; multiply by 1
 457         set_fr_iimmed   1,2,fr10
 458         set_fr_iimmed   0x3fff,2,fr9    ; 15 bit result
 459         set_fr_iimmed   2,0x3fff,fr11
 460         cmqmachs        fr8,fr10,acc0,cc0,0
 461         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 462         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 463         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 464         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 465         test_accg_immed         0x00000011,accg0
 466         test_acc_immed  0x11111111,acc0
 467         test_accg_immed         0x00000022,accg1
 468         test_acc_immed  0x22222222,acc1
 469         test_accg_immed         0x00000033,accg2
 470         test_acc_immed  0x33333333,acc2
 471         test_accg_immed         0x00000044,accg3
 472         test_acc_immed  0x44444444,acc3
 473
 474         set_fr_iimmed   0x4000,2,fr8    ; 16 bit result
 475         set_fr_iimmed   2,0x4000,fr10
 476         set_fr_iimmed   0x7fff,0x7fff,fr9       ; max positive result
 477         set_fr_iimmed   0x7fff,0x7fff,fr11
 478         cmqmachs        fr8,fr10,acc0,cc0,0
 479         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 480         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 481         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 482         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 483         test_accg_immed         0x00000011,accg0
 484         test_acc_immed  0x11111111,acc0
 485         test_accg_immed         0x00000022,accg1
 486         test_acc_immed  0x22222222,acc1
 487         test_accg_immed         0x00000033,accg2
 488         test_acc_immed  0x33333333,acc2
 489         test_accg_immed         0x00000044,accg3
 490         test_acc_immed  0x44444444,acc3
 491
 492         ; Mixed operands
 493         set_fr_iimmed   2,0xfffd,fr8            ; multiply small numbers
 494         set_fr_iimmed   0xfffd,2,fr10
 495         set_fr_iimmed   0xfffe,1,fr9            ; multiply by 1
 496         set_fr_iimmed   1,0xfffe,fr11
 497         cmqmachs        fr8,fr10,acc0,cc0,0
 498         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 499         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 500         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 501         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 502         test_accg_immed         0x00000011,accg0
 503         test_acc_immed  0x11111111,acc0
 504         test_accg_immed         0x00000022,accg1
 505         test_acc_immed  0x22222222,acc1
 506         test_accg_immed         0x00000033,accg2
 507         test_acc_immed  0x33333333,acc2
 508         test_accg_immed         0x00000044,accg3
 509         test_acc_immed  0x44444444,acc3
 510
 511         set_fr_iimmed   0xfffe,0,fr8            ; multiply by 0
 512         set_fr_iimmed   0,0xfffe,fr10
 513         set_fr_iimmed   0x2001,0xfffe,fr9       ; 15 bit result
 514         set_fr_iimmed   0xfffe,0x2001,fr11
 515         cmqmachs        fr8,fr10,acc0,cc0,0
 516         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 517         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 518         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 519         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 520         test_accg_immed         0x00000011,accg0
 521         test_acc_immed  0x11111111,acc0
 522         test_accg_immed         0x00000022,accg1
 523         test_acc_immed  0x22222222,acc1
 524         test_accg_immed         0x00000033,accg2
 525         test_acc_immed  0x33333333,acc2
 526         test_accg_immed         0x00000044,accg3
 527         test_acc_immed  0x44444444,acc3
 528
 529         set_fr_iimmed   0x4000,0xfffe,fr8       ; 16 bit result
 530         set_fr_iimmed   0xfffe,0x4000,fr10
 531         set_fr_iimmed   0x7fff,0x8000,fr9       ; max negative result
 532         set_fr_iimmed   0x8000,0x7fff,fr11
 533         cmqmachs        fr8,fr10,acc0,cc4,0
 534         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 535         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 536         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 537         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 538         test_accg_immed         0x00000011,accg0
 539         test_acc_immed  0x11111111,acc0
 540         test_accg_immed         0x00000022,accg1
 541         test_acc_immed  0x22222222,acc1
 542         test_accg_immed         0x00000033,accg2
 543         test_acc_immed  0x33333333,acc2
 544         test_accg_immed         0x00000044,accg3
 545         test_acc_immed  0x44444444,acc3
 546
 547         ; Negative operands
 548         set_fr_iimmed   0xfffe,0xfffd,fr8               ; multiply small numbers
 549         set_fr_iimmed   0xfffd,0xfffe,fr10
 550         set_fr_iimmed   0xffff,0xfffe,fr9               ; multiply by -1
 551         set_fr_iimmed   0xfffe,0xffff,fr11
 552         cmqmachs        fr8,fr10,acc0,cc4,0
 553         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 554         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 555         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 556         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 557         test_accg_immed         0x00000011,accg0
 558         test_acc_immed  0x11111111,acc0
 559         test_accg_immed         0x00000022,accg1
 560         test_acc_immed  0x22222222,acc1
 561         test_accg_immed         0x00000033,accg2
 562         test_acc_immed  0x33333333,acc2
 563         test_accg_immed         0x00000044,accg3
 564         test_acc_immed  0x44444444,acc3
 565
 566         set_fr_iimmed   0x8001,0x8001,fr8       ; almost max positive result
 567         set_fr_iimmed   0x8001,0x8001,fr10
 568         set_fr_iimmed   0x8000,0x8000,fr9       ; max positive result
 569         set_fr_iimmed   0x8000,0x8000,fr11
 570         cmqmachs        fr8,fr10,acc0,cc4,0
 571         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 572         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 573         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 574         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 575         test_accg_immed         0x00000011,accg0
 576         test_acc_immed  0x11111111,acc0
 577         test_accg_immed         0x00000022,accg1
 578         test_acc_immed  0x22222222,acc1
 579         test_accg_immed         0x00000033,accg2
 580         test_acc_immed  0x33333333,acc2
 581         test_accg_immed         0x00000044,accg3
 582         test_acc_immed  0x44444444,acc3
 583
 584         set_accg_immed  0x7f,accg0              ; saturation
 585         set_acc_immed   0xffffffff,acc0
 586         set_accg_immed  0x7f,accg1
 587         set_acc_immed   0xffffffff,acc1
 588         set_accg_immed  0x7f,accg2              ; saturation
 589         set_acc_immed   0xffffffff,acc2
 590         set_accg_immed  0x7f,accg3
 591         set_acc_immed   0xffffffff,acc3
 592         set_fr_iimmed   1,1,fr8
 593         set_fr_iimmed   1,1,fr10
 594         set_fr_iimmed   0x7fff,0x7fff,fr9       ; saturation
 595         set_fr_iimmed   0x7fff,0x7fff,fr11
 596         cmqmachs        fr8,fr10,acc0,cc4,0
 597         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 598         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 599         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 600         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 601         test_accg_immed         0x7f,accg0              ; saturation
 602         test_acc_immed  0xffffffff,acc0
 603         test_accg_immed         0x7f,accg1
 604         test_acc_immed  0xffffffff,acc1
 605         test_accg_immed         0x7f,accg2              ; saturation
 606         test_acc_immed  0xffffffff,acc2
 607         test_accg_immed         0x7f,accg3
 608         test_acc_immed  0xffffffff,acc3
 609
 610         set_accg_immed  0x80,accg0              ; saturation
 611         set_acc_immed   0,acc0
 612         set_accg_immed  0x80,accg1
 613         set_acc_immed   0,acc1
 614         set_accg_immed  0x80,accg2              ; saturation
 615         set_acc_immed   0,acc2
 616         set_accg_immed  0x80,accg3
 617         set_acc_immed   0,acc3
 618         set_fr_iimmed   0xffff,0,fr8
 619         set_fr_iimmed   1,0xffff,fr10
 620         set_fr_iimmed   0x0000,0x8000,fr9       ; saturation
 621         set_fr_iimmed   0x7fff,0x7fff,fr11
 622         cmqmachs        fr8,fr10,acc0,cc4,0
 623         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 624         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 625         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 626         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 627         test_accg_immed         0x80,accg0              ; saturation
 628         test_acc_immed  0,acc0
 629         test_accg_immed         0x80,accg1
 630         test_acc_immed  0,acc1
 631         test_accg_immed         0x80,accg2              ; saturation
 632         test_acc_immed  0,acc2
 633         test_accg_immed         0x80,accg3
 634         test_acc_immed  0,acc3
 635
 636         ; Positive operands
 637         set_spr_immed   0,msr0
 638         set_accg_immed  0x00000011,accg0
 639         set_acc_immed   0x11111111,acc0
 640         set_accg_immed  0x00000022,accg1
 641         set_acc_immed   0x22222222,acc1
 642         set_accg_immed  0x00000033,accg2
 643         set_acc_immed   0x33333333,acc2
 644         set_accg_immed  0x00000044,accg3
 645         set_acc_immed   0x44444444,acc3
 646         set_fr_iimmed   2,3,fr8         ; multiply small numbers
 647         set_fr_iimmed   3,2,fr10
 648         set_fr_iimmed   0,1,fr9         ; multiply by 0
 649         set_fr_iimmed   2,0,fr11
 650         cmqmachs        fr8,fr10,acc0,cc1,1
 651         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 652         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 653         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 654         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 655         test_accg_immed         0x00000011,accg0
 656         test_acc_immed  0x11111111,acc0
 657         test_accg_immed         0x00000022,accg1
 658         test_acc_immed  0x22222222,acc1
 659         test_accg_immed         0x00000033,accg2
 660         test_acc_immed  0x33333333,acc2
 661         test_accg_immed         0x00000044,accg3
 662         test_acc_immed  0x44444444,acc3
 663
 664         set_fr_iimmed   2,1,fr8         ; multiply by 1
 665         set_fr_iimmed   1,2,fr10
 666         set_fr_iimmed   0x3fff,2,fr9    ; 15 bit result
 667         set_fr_iimmed   2,0x3fff,fr11
 668         cmqmachs        fr8,fr10,acc0,cc1,1
 669         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 670         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 671         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 672         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 673         test_accg_immed         0x00000011,accg0
 674         test_acc_immed  0x11111111,acc0
 675         test_accg_immed         0x00000022,accg1
 676         test_acc_immed  0x22222222,acc1
 677         test_accg_immed         0x00000033,accg2
 678         test_acc_immed  0x33333333,acc2
 679         test_accg_immed         0x00000044,accg3
 680         test_acc_immed  0x44444444,acc3
 681
 682         set_fr_iimmed   0x4000,2,fr8    ; 16 bit result
 683         set_fr_iimmed   2,0x4000,fr10
 684         set_fr_iimmed   0x7fff,0x7fff,fr9       ; max positive result
 685         set_fr_iimmed   0x7fff,0x7fff,fr11
 686         cmqmachs        fr8,fr10,acc0,cc1,1
 687         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 688         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 689         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 690         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 691         test_accg_immed         0x00000011,accg0
 692         test_acc_immed  0x11111111,acc0
 693         test_accg_immed         0x00000022,accg1
 694         test_acc_immed  0x22222222,acc1
 695         test_accg_immed         0x00000033,accg2
 696         test_acc_immed  0x33333333,acc2
 697         test_accg_immed         0x00000044,accg3
 698         test_acc_immed  0x44444444,acc3
 699
 700         ; Mixed operands
 701         set_fr_iimmed   2,0xfffd,fr8            ; multiply small numbers
 702         set_fr_iimmed   0xfffd,2,fr10
 703         set_fr_iimmed   0xfffe,1,fr9            ; multiply by 1
 704         set_fr_iimmed   1,0xfffe,fr11
 705         cmqmachs        fr8,fr10,acc0,cc1,1
 706         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 707         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 708         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 709         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 710         test_accg_immed         0x00000011,accg0
 711         test_acc_immed  0x11111111,acc0
 712         test_accg_immed         0x00000022,accg1
 713         test_acc_immed  0x22222222,acc1
 714         test_accg_immed         0x00000033,accg2
 715         test_acc_immed  0x33333333,acc2
 716         test_accg_immed         0x00000044,accg3
 717         test_acc_immed  0x44444444,acc3
 718
 719         set_fr_iimmed   0xfffe,0,fr8            ; multiply by 0
 720         set_fr_iimmed   0,0xfffe,fr10
 721         set_fr_iimmed   0x2001,0xfffe,fr9       ; 15 bit result
 722         set_fr_iimmed   0xfffe,0x2001,fr11
 723         cmqmachs        fr8,fr10,acc0,cc1,1
 724         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 725         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 726         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 727         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 728         test_accg_immed         0x00000011,accg0
 729         test_acc_immed  0x11111111,acc0
 730         test_accg_immed         0x00000022,accg1
 731         test_acc_immed  0x22222222,acc1
 732         test_accg_immed         0x00000033,accg2
 733         test_acc_immed  0x33333333,acc2
 734         test_accg_immed         0x00000044,accg3
 735         test_acc_immed  0x44444444,acc3
 736
 737         set_fr_iimmed   0x4000,0xfffe,fr8       ; 16 bit result
 738         set_fr_iimmed   0xfffe,0x4000,fr10
 739         set_fr_iimmed   0x7fff,0x8000,fr9       ; max negative result
 740         set_fr_iimmed   0x8000,0x7fff,fr11
 741         cmqmachs        fr8,fr10,acc0,cc5,1
 742         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 743         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 744         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 745         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 746         test_accg_immed         0x00000011,accg0
 747         test_acc_immed  0x11111111,acc0
 748         test_accg_immed         0x00000022,accg1
 749         test_acc_immed  0x22222222,acc1
 750         test_accg_immed         0x00000033,accg2
 751         test_acc_immed  0x33333333,acc2
 752         test_accg_immed         0x00000044,accg3
 753         test_acc_immed  0x44444444,acc3
 754
 755         ; Negative operands
 756         set_fr_iimmed   0xfffe,0xfffd,fr8               ; multiply small numbers
 757         set_fr_iimmed   0xfffd,0xfffe,fr10
 758         set_fr_iimmed   0xffff,0xfffe,fr9               ; multiply by -1
 759         set_fr_iimmed   0xfffe,0xffff,fr11
 760         cmqmachs        fr8,fr10,acc0,cc5,1
 761         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 762         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 763         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 764         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 765         test_accg_immed         0x00000011,accg0
 766         test_acc_immed  0x11111111,acc0
 767         test_accg_immed         0x00000022,accg1
 768         test_acc_immed  0x22222222,acc1
 769         test_accg_immed         0x00000033,accg2
 770         test_acc_immed  0x33333333,acc2
 771         test_accg_immed         0x00000044,accg3
 772         test_acc_immed  0x44444444,acc3
 773
 774         set_fr_iimmed   0x8001,0x8001,fr8       ; almost max positive result
 775         set_fr_iimmed   0x8001,0x8001,fr10
 776         set_fr_iimmed   0x8000,0x8000,fr9       ; max positive result
 777         set_fr_iimmed   0x8000,0x8000,fr11
 778         cmqmachs        fr8,fr10,acc0,cc5,1
 779         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 780         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 781         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 782         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 783         test_accg_immed         0x00000011,accg0
 784         test_acc_immed  0x11111111,acc0
 785         test_accg_immed         0x00000022,accg1
 786         test_acc_immed  0x22222222,acc1
 787         test_accg_immed         0x00000033,accg2
 788         test_acc_immed  0x33333333,acc2
 789         test_accg_immed         0x00000044,accg3
 790         test_acc_immed  0x44444444,acc3
 791
 792         set_accg_immed  0x7f,accg0              ; saturation
 793         set_acc_immed   0xffffffff,acc0
 794         set_accg_immed  0x7f,accg1
 795         set_acc_immed   0xffffffff,acc1
 796         set_accg_immed  0x7f,accg2              ; saturation
 797         set_acc_immed   0xffffffff,acc2
 798         set_accg_immed  0x7f,accg3
 799         set_acc_immed   0xffffffff,acc3
 800         set_fr_iimmed   1,1,fr8
 801         set_fr_iimmed   1,1,fr10
 802         set_fr_iimmed   0x7fff,0x7fff,fr9       ; saturation
 803         set_fr_iimmed   0x7fff,0x7fff,fr11
 804         cmqmachs        fr8,fr10,acc0,cc5,1
 805         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 806         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 807         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 808         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 809         test_accg_immed         0x7f,accg0              ; saturation
 810         test_acc_immed  0xffffffff,acc0
 811         test_accg_immed         0x7f,accg1
 812         test_acc_immed  0xffffffff,acc1
 813         test_accg_immed         0x7f,accg2              ; saturation
 814         test_acc_immed  0xffffffff,acc2
 815         test_accg_immed         0x7f,accg3
 816         test_acc_immed  0xffffffff,acc3
 817
 818         set_accg_immed  0x80,accg0              ; saturation
 819         set_acc_immed   0,acc0
 820         set_accg_immed  0x80,accg1
 821         set_acc_immed   0,acc1
 822         set_accg_immed  0x80,accg2              ; saturation
 823         set_acc_immed   0,acc2
 824         set_accg_immed  0x80,accg3
 825         set_acc_immed   0,acc3
 826         set_fr_iimmed   0xffff,0,fr8
 827         set_fr_iimmed   1,0xffff,fr10
 828         set_fr_iimmed   0x0000,0x8000,fr9       ; saturation
 829         set_fr_iimmed   0x7fff,0x7fff,fr11
 830         cmqmachs        fr8,fr10,acc0,cc5,1
 831         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 832         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 833         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 834         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 835         test_accg_immed         0x80,accg0              ; saturation
 836         test_acc_immed  0,acc0
 837         test_accg_immed         0x80,accg1
 838         test_acc_immed  0,acc1
 839         test_accg_immed         0x80,accg2              ; saturation
 840         test_acc_immed  0,acc2
 841         test_accg_immed         0x80,accg3
 842         test_acc_immed  0,acc3
 843
 844         ; Positive operands
 845         set_spr_immed   0,msr0
 846         set_accg_immed  0x00000011,accg0
 847         set_acc_immed   0x11111111,acc0
 848         set_accg_immed  0x00000022,accg1
 849         set_acc_immed   0x22222222,acc1
 850         set_accg_immed  0x00000033,accg2
 851         set_acc_immed   0x33333333,acc2
 852         set_accg_immed  0x00000044,accg3
 853         set_acc_immed   0x44444444,acc3
 854         set_fr_iimmed   2,3,fr8         ; multiply small numbers
 855         set_fr_iimmed   3,2,fr10
 856         set_fr_iimmed   0,1,fr9         ; multiply by 0
 857         set_fr_iimmed   2,0,fr11
 858         cmqmachs        fr8,fr10,acc0,cc2,1
 859         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 860         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 861         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 862         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 863         test_accg_immed         0x00000011,accg0
 864         test_acc_immed  0x11111111,acc0
 865         test_accg_immed         0x00000022,accg1
 866         test_acc_immed  0x22222222,acc1
 867         test_accg_immed         0x00000033,accg2
 868         test_acc_immed  0x33333333,acc2
 869         test_accg_immed         0x00000044,accg3
 870         test_acc_immed  0x44444444,acc3
 871
 872         set_fr_iimmed   2,1,fr8         ; multiply by 1
 873         set_fr_iimmed   1,2,fr10
 874         set_fr_iimmed   0x3fff,2,fr9    ; 15 bit result
 875         set_fr_iimmed   2,0x3fff,fr11
 876         cmqmachs        fr8,fr10,acc0,cc2,1
 877         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 878         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 879         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 880         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 881         test_accg_immed         0x00000011,accg0
 882         test_acc_immed  0x11111111,acc0
 883         test_accg_immed         0x00000022,accg1
 884         test_acc_immed  0x22222222,acc1
 885         test_accg_immed         0x00000033,accg2
 886         test_acc_immed  0x33333333,acc2
 887         test_accg_immed         0x00000044,accg3
 888         test_acc_immed  0x44444444,acc3
 889
 890         set_fr_iimmed   0x4000,2,fr8    ; 16 bit result
 891         set_fr_iimmed   2,0x4000,fr10
 892         set_fr_iimmed   0x7fff,0x7fff,fr9       ; max positive result
 893         set_fr_iimmed   0x7fff,0x7fff,fr11
 894         cmqmachs        fr8,fr10,acc0,cc2,1
 895         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 896         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 897         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 898         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 899         test_accg_immed         0x00000011,accg0
 900         test_acc_immed  0x11111111,acc0
 901         test_accg_immed         0x00000022,accg1
 902         test_acc_immed  0x22222222,acc1
 903         test_accg_immed         0x00000033,accg2
 904         test_acc_immed  0x33333333,acc2
 905         test_accg_immed         0x00000044,accg3
 906         test_acc_immed  0x44444444,acc3
 907
 908         ; Mixed operands
 909         set_fr_iimmed   2,0xfffd,fr8            ; multiply small numbers
 910         set_fr_iimmed   0xfffd,2,fr10
 911         set_fr_iimmed   0xfffe,1,fr9            ; multiply by 1
 912         set_fr_iimmed   1,0xfffe,fr11
 913         cmqmachs        fr8,fr10,acc0,cc2,1
 914         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 915         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 916         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 917         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 918         test_accg_immed         0x00000011,accg0
 919         test_acc_immed  0x11111111,acc0
 920         test_accg_immed         0x00000022,accg1
 921         test_acc_immed  0x22222222,acc1
 922         test_accg_immed         0x00000033,accg2
 923         test_acc_immed  0x33333333,acc2
 924         test_accg_immed         0x00000044,accg3
 925         test_acc_immed  0x44444444,acc3
 926
 927         set_fr_iimmed   0xfffe,0,fr8            ; multiply by 0
 928         set_fr_iimmed   0,0xfffe,fr10
 929         set_fr_iimmed   0x2001,0xfffe,fr9       ; 15 bit result
 930         set_fr_iimmed   0xfffe,0x2001,fr11
 931         cmqmachs        fr8,fr10,acc0,cc2,1
 932         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 933         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 934         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 935         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 936         test_accg_immed         0x00000011,accg0
 937         test_acc_immed  0x11111111,acc0
 938         test_accg_immed         0x00000022,accg1
 939         test_acc_immed  0x22222222,acc1
 940         test_accg_immed         0x00000033,accg2
 941         test_acc_immed  0x33333333,acc2
 942         test_accg_immed         0x00000044,accg3
 943         test_acc_immed  0x44444444,acc3
 944
 945         set_fr_iimmed   0x4000,0xfffe,fr8       ; 16 bit result
 946         set_fr_iimmed   0xfffe,0x4000,fr10
 947         set_fr_iimmed   0x7fff,0x8000,fr9       ; max negative result
 948         set_fr_iimmed   0x8000,0x7fff,fr11
 949         cmqmachs        fr8,fr10,acc0,cc6,1
 950         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 951         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 952         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 953         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 954         test_accg_immed         0x00000011,accg0
 955         test_acc_immed  0x11111111,acc0
 956         test_accg_immed         0x00000022,accg1
 957         test_acc_immed  0x22222222,acc1
 958         test_accg_immed         0x00000033,accg2
 959         test_acc_immed  0x33333333,acc2
 960         test_accg_immed         0x00000044,accg3
 961         test_acc_immed  0x44444444,acc3
 962
 963         ; Negative operands
 964         set_fr_iimmed   0xfffe,0xfffd,fr8               ; multiply small numbers
 965         set_fr_iimmed   0xfffd,0xfffe,fr10
 966         set_fr_iimmed   0xffff,0xfffe,fr9               ; multiply by -1
 967         set_fr_iimmed   0xfffe,0xffff,fr11
 968         cmqmachs        fr8,fr10,acc0,cc6,1
 969         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 970         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 971         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 972         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 973         test_accg_immed         0x00000011,accg0
 974         test_acc_immed  0x11111111,acc0
 975         test_accg_immed         0x00000022,accg1
 976         test_acc_immed  0x22222222,acc1
 977         test_accg_immed         0x00000033,accg2
 978         test_acc_immed  0x33333333,acc2
 979         test_accg_immed         0x00000044,accg3
 980         test_acc_immed  0x44444444,acc3
 981
 982         set_fr_iimmed   0x8001,0x8001,fr8       ; almost max positive result
 983         set_fr_iimmed   0x8001,0x8001,fr10
 984         set_fr_iimmed   0x8000,0x8000,fr9       ; max positive result
 985         set_fr_iimmed   0x8000,0x8000,fr11
 986         cmqmachs        fr8,fr10,acc0,cc6,1
 987         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 988         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 989         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 990         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 991         test_accg_immed         0x00000011,accg0
 992         test_acc_immed  0x11111111,acc0
 993         test_accg_immed         0x00000022,accg1
 994         test_acc_immed  0x22222222,acc1
 995         test_accg_immed         0x00000033,accg2
 996         test_acc_immed  0x33333333,acc2
 997         test_accg_immed         0x00000044,accg3
 998         test_acc_immed  0x44444444,acc3
 999
1000         set_accg_immed  0x7f,accg0              ; saturation
1001         set_acc_immed   0xffffffff,acc0
1002         set_accg_immed  0x7f,accg1
1003         set_acc_immed   0xffffffff,acc1
1004         set_accg_immed  0x7f,accg2              ; saturation
1005         set_acc_immed   0xffffffff,acc2
1006         set_accg_immed  0x7f,accg3
1007         set_acc_immed   0xffffffff,acc3
1008         set_fr_iimmed   1,1,fr8
1009         set_fr_iimmed   1,1,fr10
1010         set_fr_iimmed   0x7fff,0x7fff,fr9       ; saturation
1011         set_fr_iimmed   0x7fff,0x7fff,fr11
1012         cmqmachs        fr8,fr10,acc0,cc6,1
1013         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
1014         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
1015         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
1016         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
1017         test_accg_immed         0x7f,accg0              ; saturation
1018         test_acc_immed  0xffffffff,acc0
1019         test_accg_immed         0x7f,accg1
1020         test_acc_immed  0xffffffff,acc1
1021         test_accg_immed         0x7f,accg2              ; saturation
1022         test_acc_immed  0xffffffff,acc2
1023         test_accg_immed         0x7f,accg3
1024         test_acc_immed  0xffffffff,acc3
1025
1026         set_accg_immed  0x80,accg0              ; saturation
1027         set_acc_immed   0,acc0
1028         set_accg_immed  0x80,accg1
1029         set_acc_immed   0,acc1
1030         set_accg_immed  0x80,accg2              ; saturation
1031         set_acc_immed   0,acc2
1032         set_accg_immed  0x80,accg3
1033         set_acc_immed   0,acc3
1034         set_fr_iimmed   0xffff,0,fr8
1035         set_fr_iimmed   1,0xffff,fr10
1036         set_fr_iimmed   0x0000,0x8000,fr9       ; saturation
1037         set_fr_iimmed   0x7fff,0x7fff,fr11
1038         cmqmachs        fr8,fr10,acc0,cc6,1
1039         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
1040         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
1041         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
1042         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
1043         test_accg_immed         0x80,accg0              ; saturation
1044         test_acc_immed  0,acc0
1045         test_accg_immed         0x80,accg1
1046         test_acc_immed  0,acc1
1047         test_accg_immed         0x80,accg2              ; saturation
1048         test_acc_immed  0,acc2
1049         test_accg_immed         0x80,accg3
1050         test_acc_immed  0,acc3
1051 ;
1052         ; Positive operands
1053         set_spr_immed   0,msr0
1054         set_accg_immed  0x00000011,accg0
1055         set_acc_immed   0x11111111,acc0
1056         set_accg_immed  0x00000022,accg1
1057         set_acc_immed   0x22222222,acc1
1058         set_accg_immed  0x00000033,accg2
1059         set_acc_immed   0x33333333,acc2
1060         set_accg_immed  0x00000044,accg3
1061         set_acc_immed   0x44444444,acc3
1062         set_fr_iimmed   2,3,fr8         ; multiply small numbers
1063         set_fr_iimmed   3,2,fr10
1064         set_fr_iimmed   0,1,fr9         ; multiply by 0
1065         set_fr_iimmed   2,0,fr11
1066         cmqmachs        fr8,fr10,acc0,cc3,1
1067         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
1068         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
1069         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
1070         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
1071         test_accg_immed         0x00000011,accg0
1072         test_acc_immed  0x11111111,acc0
1073         test_accg_immed         0x00000022,accg1
1074         test_acc_immed  0x22222222,acc1
1075         test_accg_immed         0x00000033,accg2
1076         test_acc_immed  0x33333333,acc2
1077         test_accg_immed         0x00000044,accg3
1078         test_acc_immed  0x44444444,acc3
1079
1080         set_fr_iimmed   2,1,fr8         ; multiply by 1
1081         set_fr_iimmed   1,2,fr10
1082         set_fr_iimmed   0x3fff,2,fr9    ; 15 bit result
1083         set_fr_iimmed   2,0x3fff,fr11
1084         cmqmachs        fr8,fr10,acc0,cc3,1
1085         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
1086         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
1087         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
1088         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
1089         test_accg_immed         0x00000011,accg0
1090         test_acc_immed  0x11111111,acc0
1091         test_accg_immed         0x00000022,accg1
1092         test_acc_immed  0x22222222,acc1
1093         test_accg_immed         0x00000033,accg2
1094         test_acc_immed  0x33333333,acc2
1095         test_accg_immed         0x00000044,accg3
1096         test_acc_immed  0x44444444,acc3
1097
1098         set_fr_iimmed   0x4000,2,fr8    ; 16 bit result
1099         set_fr_iimmed   2,0x4000,fr10
1100         set_fr_iimmed   0x7fff,0x7fff,fr9       ; max positive result
1101         set_fr_iimmed   0x7fff,0x7fff,fr11
1102         cmqmachs        fr8,fr10,acc0,cc3,1
1103         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
1104         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
1105         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
1106         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
1107         test_accg_immed         0x00000011,accg0
1108         test_acc_immed  0x11111111,acc0
1109         test_accg_immed         0x00000022,accg1
1110         test_acc_immed  0x22222222,acc1
1111         test_accg_immed         0x00000033,accg2
1112         test_acc_immed  0x33333333,acc2
1113         test_accg_immed         0x00000044,accg3
1114         test_acc_immed  0x44444444,acc3
1115
1116         ; Mixed operands
1117         set_fr_iimmed   2,0xfffd,fr8            ; multiply small numbers
1118         set_fr_iimmed   0xfffd,2,fr10
1119         set_fr_iimmed   0xfffe,1,fr9            ; multiply by 1
1120         set_fr_iimmed   1,0xfffe,fr11
1121         cmqmachs        fr8,fr10,acc0,cc3,1
1122         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
1123         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
1124         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
1125         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
1126         test_accg_immed         0x00000011,accg0
1127         test_acc_immed  0x11111111,acc0
1128         test_accg_immed         0x00000022,accg1
1129         test_acc_immed  0x22222222,acc1
1130         test_accg_immed         0x00000033,accg2
1131         test_acc_immed  0x33333333,acc2
1132         test_accg_immed         0x00000044,accg3
1133         test_acc_immed  0x44444444,acc3
1134
1135         set_fr_iimmed   0xfffe,0,fr8            ; multiply by 0
1136         set_fr_iimmed   0,0xfffe,fr10
1137         set_fr_iimmed   0x2001,0xfffe,fr9       ; 15 bit result
1138         set_fr_iimmed   0xfffe,0x2001,fr11
1139         cmqmachs        fr8,fr10,acc0,cc3,1
1140         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
1141         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
1142         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
1143         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
1144         test_accg_immed         0x00000011,accg0
1145         test_acc_immed  0x11111111,acc0
1146         test_accg_immed         0x00000022,accg1
1147         test_acc_immed  0x22222222,acc1
1148         test_accg_immed         0x00000033,accg2
1149         test_acc_immed  0x33333333,acc2
1150         test_accg_immed         0x00000044,accg3
1151         test_acc_immed  0x44444444,acc3
1152
1153         set_fr_iimmed   0x4000,0xfffe,fr8       ; 16 bit result
1154         set_fr_iimmed   0xfffe,0x4000,fr10
1155         set_fr_iimmed   0x7fff,0x8000,fr9       ; max negative result
1156         set_fr_iimmed   0x8000,0x7fff,fr11
1157         cmqmachs        fr8,fr10,acc0,cc7,1
1158         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
1159         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
1160         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
1161         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
1162         test_accg_immed         0x00000011,accg0
1163         test_acc_immed  0x11111111,acc0
1164         test_accg_immed         0x00000022,accg1
1165         test_acc_immed  0x22222222,acc1
1166         test_accg_immed         0x00000033,accg2
1167         test_acc_immed  0x33333333,acc2
1168         test_accg_immed         0x00000044,accg3
1169         test_acc_immed  0x44444444,acc3
1170
1171         ; Negative operands
1172         set_fr_iimmed   0xfffe,0xfffd,fr8               ; multiply small numbers
1173         set_fr_iimmed   0xfffd,0xfffe,fr10
1174         set_fr_iimmed   0xffff,0xfffe,fr9               ; multiply by -1
1175         set_fr_iimmed   0xfffe,0xffff,fr11
1176         cmqmachs        fr8,fr10,acc0,cc7,1
1177         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
1178         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
1179         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
1180         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
1181         test_accg_immed         0x00000011,accg0
1182         test_acc_immed  0x11111111,acc0
1183         test_accg_immed         0x00000022,accg1
1184         test_acc_immed  0x22222222,acc1
1185         test_accg_immed         0x00000033,accg2
1186         test_acc_immed  0x33333333,acc2
1187         test_accg_immed         0x00000044,accg3
1188         test_acc_immed  0x44444444,acc3
1189
1190         set_fr_iimmed   0x8001,0x8001,fr8       ; almost max positive result
1191         set_fr_iimmed   0x8001,0x8001,fr10
1192         set_fr_iimmed   0x8000,0x8000,fr9       ; max positive result
1193         set_fr_iimmed   0x8000,0x8000,fr11
1194         cmqmachs        fr8,fr10,acc0,cc7,1
1195         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
1196         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
1197         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
1198         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
1199         test_accg_immed         0x00000011,accg0
1200         test_acc_immed  0x11111111,acc0
1201         test_accg_immed         0x00000022,accg1
1202         test_acc_immed  0x22222222,acc1
1203         test_accg_immed         0x00000033,accg2
1204         test_acc_immed  0x33333333,acc2
1205         test_accg_immed         0x00000044,accg3
1206         test_acc_immed  0x44444444,acc3
1207
1208         set_accg_immed  0x7f,accg0              ; saturation
1209         set_acc_immed   0xffffffff,acc0
1210         set_accg_immed  0x7f,accg1
1211         set_acc_immed   0xffffffff,acc1
1212         set_accg_immed  0x7f,accg2              ; saturation
1213         set_acc_immed   0xffffffff,acc2
1214         set_accg_immed  0x7f,accg3
1215         set_acc_immed   0xffffffff,acc3
1216         set_fr_iimmed   1,1,fr8
1217         set_fr_iimmed   1,1,fr10
1218         set_fr_iimmed   0x7fff,0x7fff,fr9       ; saturation
1219         set_fr_iimmed   0x7fff,0x7fff,fr11
1220         cmqmachs        fr8,fr10,acc0,cc7,1
1221         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
1222         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
1223         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
1224         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
1225         test_accg_immed         0x7f,accg0              ; saturation
1226         test_acc_immed  0xffffffff,acc0
1227         test_accg_immed         0x7f,accg1
1228         test_acc_immed  0xffffffff,acc1
1229         test_accg_immed         0x7f,accg2              ; saturation
1230         test_acc_immed  0xffffffff,acc2
1231         test_accg_immed         0x7f,accg3
1232         test_acc_immed  0xffffffff,acc3
1233
1234         set_accg_immed  0x80,accg0              ; saturation
1235         set_acc_immed   0,acc0
1236         set_accg_immed  0x80,accg1
1237         set_acc_immed   0,acc1
1238         set_accg_immed  0x80,accg2              ; saturation
1239         set_acc_immed   0,acc2
1240         set_accg_immed  0x80,accg3
1241         set_acc_immed   0,acc3
1242         set_fr_iimmed   0xffff,0,fr8
1243         set_fr_iimmed   1,0xffff,fr10
1244         set_fr_iimmed   0x0000,0x8000,fr9       ; saturation
1245         set_fr_iimmed   0x7fff,0x7fff,fr11
1246         cmqmachs        fr8,fr10,acc0,cc7,1
1247         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
1248         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
1249         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
1250         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
1251         test_accg_immed         0x80,accg0              ; saturation
1252         test_acc_immed  0,acc0
1253         test_accg_immed         0x80,accg1
1254         test_acc_immed  0,acc1
1255         test_accg_immed         0x80,accg2              ; saturation
1256         test_acc_immed  0,acc2
1257         test_accg_immed         0x80,accg3
1258         test_acc_immed  0,acc3
1259
1260         pass
1261
1262