sim/testsuite/frv/fr550/cmsubhss.cgs

   1 # frv testcase for cmsubhss $FRi,$FRj,$FRj,$CCi,$cond
   2 # mach: all
   3
   4         .include "../testutils.inc"
   5
   6         start
   7
   8         .global cmsubhss
   9 cmsubhss:
  10         set_spr_immed   0x1b1b,cccr
  11
  12         set_fr_iimmed   0x0000,0x0000,fr10
  13         set_fr_iimmed   0x0000,0x0000,fr11
  14         cmsubhss        fr10,fr11,fr12,cc0,1
  15         test_fr_limmed  0x0000,0x0000,fr12
  16         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  17         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  18         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  19         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
  20
  21         set_fr_iimmed   0xdead,0x0000,fr10
  22         set_fr_iimmed   0x0000,0xbeef,fr11
  23         cmsubhss        fr10,fr11,fr12,cc0,1
  24         test_fr_limmed  0xdead,0x4111,fr12
  25         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  26         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  27         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  28         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
  29
  30         set_fr_iimmed   0x0000,0xdead,fr10
  31         set_fr_iimmed   0xbeef,0x0000,fr11
  32         cmsubhss        fr10,fr11,fr12,cc0,1
  33         test_fr_limmed  0x4111,0xdead,fr12
  34         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  35         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  36         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  37         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
  38
  39         set_fr_iimmed   0x1234,0x5678,fr10
  40         set_fr_iimmed   0x1111,0x1111,fr11
  41         cmsubhss        fr10,fr11,fr12,cc0,1
  42         test_fr_limmed  0x0123,0x4567,fr12
  43         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  44         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  45         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  46         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
  47
  48         set_fr_iimmed   0x1234,0x5678,fr10
  49         set_fr_iimmed   0xffff,0xffff,fr11
  50         cmsubhss        fr10,fr11,fr12,cc0,1
  51         test_fr_limmed  0x1235,0x5679,fr12
  52         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  53         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  54         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  55         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
  56
  57         set_spr_immed   0,msr0
  58         set_fr_iimmed   0x7ffe,0x7ffe,fr10
  59         set_fr_iimmed   0xfffe,0xffff,fr11
  60         cmsubhss        fr10,fr11,fr12,cc4,1
  61         test_fr_limmed  0x7fff,0x7fff,fr12
  62         test_spr_bits   0x3c,2,0x8,msr0         ; msr0.sie is set
  63         test_spr_bits   2,1,1,msr0              ; msr0.ovf set
  64         test_spr_bits   1,0,1,msr0              ; msr0.aovf set
  65         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
  66
  67         set_spr_immed   0,msr0
  68         set_fr_iimmed   0x8001,0x8001,fr10
  69         set_fr_iimmed   0x0001,0x0002,fr11
  70         cmsubhss        fr10,fr11,fr12,cc4,1
  71         test_fr_limmed  0x8000,0x8000,fr12
  72         test_spr_bits   0x3c,2,0x4,msr0         ; msr0.sie is set
  73         test_spr_bits   2,1,1,msr0              ; msr0.ovf set
  74         test_spr_bits   1,0,1,msr0              ; msr0.aovf set
  75         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
  76
  77         set_spr_immed   0,msr0
  78         set_fr_iimmed   0x8001,0x8001,fr10
  79         set_fr_iimmed   0x0002,0x0001,fr11
  80         cmsubhss        fr10,fr11,fr12,cc4,1
  81         test_fr_limmed  0x8000,0x8000,fr12
  82         test_spr_bits   0x3c,2,0x8,msr0         ; msr0.sie is set
  83         test_spr_bits   2,1,1,msr0              ; msr0.ovf set
  84         test_spr_bits   1,0,1,msr0              ; msr0.aovf set
  85         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
  86
  87         set_spr_immed   0,msr0
  88         set_fr_iimmed   0x0001,0x0001,fr10
  89         set_fr_iimmed   0x8000,0x8000,fr11
  90         cmsubhss.p      fr10,fr10,fr12,cc4,1
  91         cmsubhss        fr11,fr10,fr13,cc4,1
  92         test_fr_limmed  0x0000,0x0000,fr12
  93         test_fr_limmed  0x8000,0x8000,fr13
  94         test_spr_bits   0x3c,2,0xc,msr0         ; msr0.sie is set
  95         test_spr_bits   2,1,1,msr0              ; msr0.ovf set
  96         test_spr_bits   1,0,1,msr0              ; msr0.aovf set
  97         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
  98
  99         set_spr_immed   0,msr0
 100         set_fr_iimmed   0x0000,0x0000,fr10
 101         set_fr_iimmed   0x0000,0x0000,fr11
 102         cmsubhss        fr10,fr11,fr12,cc1,0
 103         test_fr_limmed  0x0000,0x0000,fr12
 104         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 105         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 106         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 107         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 108
 109         set_fr_iimmed   0xdead,0x0000,fr10
 110         set_fr_iimmed   0x0000,0xbeef,fr11
 111         cmsubhss        fr10,fr11,fr12,cc1,0
 112         test_fr_limmed  0xdead,0x4111,fr12
 113         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 114         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 115         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 116         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 117
 118         set_fr_iimmed   0x0000,0xdead,fr10
 119         set_fr_iimmed   0xbeef,0x0000,fr11
 120         cmsubhss        fr10,fr11,fr12,cc1,0
 121         test_fr_limmed  0x4111,0xdead,fr12
 122         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 123         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 124         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 125         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 126
 127         set_fr_iimmed   0x1234,0x5678,fr10
 128         set_fr_iimmed   0x1111,0x1111,fr11
 129         cmsubhss        fr10,fr11,fr12,cc1,0
 130         test_fr_limmed  0x0123,0x4567,fr12
 131         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 132         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 133         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 134         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 135
 136         set_fr_iimmed   0x1234,0x5678,fr10
 137         set_fr_iimmed   0xffff,0xffff,fr11
 138         cmsubhss        fr10,fr11,fr12,cc1,0
 139         test_fr_limmed  0x1235,0x5679,fr12
 140         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 141         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 142         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 143         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 144
 145         set_spr_immed   0,msr0
 146         set_fr_iimmed   0x7ffe,0x7ffe,fr10
 147         set_fr_iimmed   0xfffe,0xffff,fr11
 148         cmsubhss        fr10,fr11,fr12,cc5,0
 149         test_fr_limmed  0x7fff,0x7fff,fr12
 150         test_spr_bits   0x3c,2,0x8,msr0         ; msr0.sie is set
 151         test_spr_bits   2,1,1,msr0              ; msr0.ovf set
 152         test_spr_bits   1,0,1,msr0              ; msr0.aovf set
 153         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
 154
 155         set_spr_immed   0,msr0
 156         set_fr_iimmed   0x8001,0x8001,fr10
 157         set_fr_iimmed   0x0001,0x0002,fr11
 158         cmsubhss        fr10,fr11,fr12,cc5,0
 159         test_fr_limmed  0x8000,0x8000,fr12
 160         test_spr_bits   0x3c,2,0x4,msr0         ; msr0.sie is set
 161         test_spr_bits   2,1,1,msr0              ; msr0.ovf set
 162         test_spr_bits   1,0,1,msr0              ; msr0.aovf set
 163         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
 164
 165         set_spr_immed   0,msr0
 166         set_fr_iimmed   0x8001,0x8001,fr10
 167         set_fr_iimmed   0x0002,0x0001,fr11
 168         cmsubhss        fr10,fr11,fr12,cc5,0
 169         test_fr_limmed  0x8000,0x8000,fr12
 170         test_spr_bits   0x3c,2,0x8,msr0         ; msr0.sie is set
 171         test_spr_bits   2,1,1,msr0              ; msr0.ovf set
 172         test_spr_bits   1,0,1,msr0              ; msr0.aovf set
 173         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
 174
 175         set_spr_immed   0,msr0
 176         set_fr_iimmed   0x0001,0x0001,fr10
 177         set_fr_iimmed   0x8000,0x8000,fr11
 178         cmsubhss.p      fr10,fr10,fr12,cc5,0
 179         cmsubhss        fr11,fr10,fr13,cc5,0
 180         test_fr_limmed  0x0000,0x0000,fr12
 181         test_fr_limmed  0x8000,0x8000,fr13
 182         test_spr_bits   0x3c,2,0xc,msr0         ; msr0.sie is set
 183         test_spr_bits   2,1,1,msr0              ; msr0.ovf set
 184         test_spr_bits   1,0,1,msr0              ; msr0.aovf set
 185         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
 186
 187         set_fr_iimmed   0xdead,0xbeef,fr12
 188         set_spr_immed   0,msr0
 189         set_fr_iimmed   0x0000,0x0000,fr10
 190         set_fr_iimmed   0x0000,0x0000,fr11
 191         cmsubhss        fr10,fr11,fr12,cc0,0
 192         test_fr_limmed  0xdead,0xbeef,fr12
 193         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 194         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 195         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 196         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 197
 198         set_fr_iimmed   0xdead,0x0000,fr10
 199         set_fr_iimmed   0x0000,0xbeef,fr11
 200         cmsubhss        fr10,fr11,fr12,cc0,0
 201         test_fr_limmed  0xdead,0xbeef,fr12
 202         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 203         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 204         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 205         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 206
 207         set_fr_iimmed   0x0000,0xdead,fr10
 208         set_fr_iimmed   0xbeef,0x0000,fr11
 209         cmsubhss        fr10,fr11,fr12,cc0,0
 210         test_fr_limmed  0xdead,0xbeef,fr12
 211         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 212         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 213         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 214         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 215
 216         set_fr_iimmed   0x1234,0x5678,fr10
 217         set_fr_iimmed   0x1111,0x1111,fr11
 218         cmsubhss        fr10,fr11,fr12,cc0,0
 219         test_fr_limmed  0xdead,0xbeef,fr12
 220         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 221         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 222         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 223         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 224
 225         set_fr_iimmed   0x1234,0x5678,fr10
 226         set_fr_iimmed   0xffff,0xffff,fr11
 227         cmsubhss        fr10,fr11,fr12,cc0,0
 228         test_fr_limmed  0xdead,0xbeef,fr12
 229         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 230         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 231         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 232         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 233
 234         set_spr_immed   0,msr0
 235         set_fr_iimmed   0x7ffe,0x7ffe,fr10
 236         set_fr_iimmed   0xfffe,0xffff,fr11
 237         cmsubhss        fr10,fr11,fr12,cc4,0
 238         test_fr_limmed  0xdead,0xbeef,fr12
 239         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 240         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 241         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 242         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 243
 244         set_spr_immed   0,msr0
 245         set_fr_iimmed   0x8001,0x8001,fr10
 246         set_fr_iimmed   0x0001,0x0002,fr11
 247         cmsubhss        fr10,fr11,fr12,cc4,0
 248         test_fr_limmed  0xdead,0xbeef,fr12
 249         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 250         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 251         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 252         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 253
 254         set_spr_immed   0,msr0
 255         set_fr_iimmed   0x8001,0x8001,fr10
 256         set_fr_iimmed   0x0002,0x0001,fr11
 257         cmsubhss        fr10,fr11,fr12,cc4,0
 258         test_fr_limmed  0xdead,0xbeef,fr12
 259         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 260         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 261         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 262         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 263
 264         set_fr_iimmed   0xbeef,0xdead,fr13
 265         set_spr_immed   0,msr0
 266         set_fr_iimmed   0x0001,0x0001,fr10
 267         set_fr_iimmed   0x8000,0x8000,fr11
 268         cmsubhss.p      fr10,fr10,fr12,cc4,0
 269         cmsubhss        fr11,fr10,fr13,cc4,0
 270         test_fr_limmed  0xdead,0xbeef,fr12
 271         test_fr_limmed  0xbeef,0xdead,fr13
 272         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 273         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 274         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 275         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 276
 277         set_fr_iimmed   0xdead,0xbeef,fr12
 278         set_spr_immed   0,msr0
 279         set_fr_iimmed   0x0000,0x0000,fr10
 280         set_fr_iimmed   0x0000,0x0000,fr11
 281         cmsubhss        fr10,fr11,fr12,cc1,1
 282         test_fr_limmed  0xdead,0xbeef,fr12
 283         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 284         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 285         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 286         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 287
 288         set_fr_iimmed   0xdead,0x0000,fr10
 289         set_fr_iimmed   0x0000,0xbeef,fr11
 290         cmsubhss        fr10,fr11,fr12,cc1,1
 291         test_fr_limmed  0xdead,0xbeef,fr12
 292         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 293         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 294         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 295         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 296
 297         set_fr_iimmed   0x0000,0xdead,fr10
 298         set_fr_iimmed   0xbeef,0x0000,fr11
 299         cmsubhss        fr10,fr11,fr12,cc1,1
 300         test_fr_limmed  0xdead,0xbeef,fr12
 301         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 302         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 303         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 304         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 305
 306         set_fr_iimmed   0x1234,0x5678,fr10
 307         set_fr_iimmed   0x1111,0x1111,fr11
 308         cmsubhss        fr10,fr11,fr12,cc1,1
 309         test_fr_limmed  0xdead,0xbeef,fr12
 310         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 311         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 312         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 313         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 314
 315         set_fr_iimmed   0x1234,0x5678,fr10
 316         set_fr_iimmed   0xffff,0xffff,fr11
 317         cmsubhss        fr10,fr11,fr12,cc1,1
 318         test_fr_limmed  0xdead,0xbeef,fr12
 319         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 320         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 321         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 322         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 323
 324         set_spr_immed   0,msr0
 325         set_fr_iimmed   0x7ffe,0x7ffe,fr10
 326         set_fr_iimmed   0xfffe,0xffff,fr11
 327         cmsubhss        fr10,fr11,fr12,cc5,1
 328         test_fr_limmed  0xdead,0xbeef,fr12
 329         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 330         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 331         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 332         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 333
 334         set_spr_immed   0,msr0
 335         set_fr_iimmed   0x8001,0x8001,fr10
 336         set_fr_iimmed   0x0001,0x0002,fr11
 337         cmsubhss        fr10,fr11,fr12,cc5,1
 338         test_fr_limmed  0xdead,0xbeef,fr12
 339         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 340         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 341         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 342         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 343
 344         set_spr_immed   0,msr0
 345         set_fr_iimmed   0x8001,0x8001,fr10
 346         set_fr_iimmed   0x0002,0x0001,fr11
 347         cmsubhss        fr10,fr11,fr12,cc5,1
 348         test_fr_limmed  0xdead,0xbeef,fr12
 349         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 350         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 351         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 352         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 353
 354         set_fr_iimmed   0xbeef,0xdead,fr13
 355         set_spr_immed   0,msr0
 356         set_fr_iimmed   0x0001,0x0001,fr10
 357         set_fr_iimmed   0x8000,0x8000,fr11
 358         cmsubhss.p      fr10,fr10,fr12,cc5,1
 359         cmsubhss        fr11,fr10,fr13,cc5,1
 360         test_fr_limmed  0xdead,0xbeef,fr12
 361         test_fr_limmed  0xbeef,0xdead,fr13
 362         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 363         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 364         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 365         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 366
 367         set_fr_iimmed   0xdead,0xbeef,fr12
 368         set_spr_immed   0,msr0
 369         set_fr_iimmed   0x0000,0x0000,fr10
 370         set_fr_iimmed   0x0000,0x0000,fr11
 371         cmsubhss        fr10,fr11,fr12,cc2,1
 372         test_fr_limmed  0xdead,0xbeef,fr12
 373         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 374         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 375         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 376         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 377
 378         set_fr_iimmed   0xdead,0x0000,fr10
 379         set_fr_iimmed   0x0000,0xbeef,fr11
 380         cmsubhss        fr10,fr11,fr12,cc2,0
 381         test_fr_limmed  0xdead,0xbeef,fr12
 382         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 383         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 384         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 385         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 386
 387         set_fr_iimmed   0x0000,0xdead,fr10
 388         set_fr_iimmed   0xbeef,0x0000,fr11
 389         cmsubhss        fr10,fr11,fr12,cc2,1
 390         test_fr_limmed  0xdead,0xbeef,fr12
 391         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 392         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 393         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 394         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 395
 396         set_fr_iimmed   0x1234,0x5678,fr10
 397         set_fr_iimmed   0x1111,0x1111,fr11
 398         cmsubhss        fr10,fr11,fr12,cc2,0
 399         test_fr_limmed  0xdead,0xbeef,fr12
 400         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 401         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 402         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 403         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 404
 405         set_fr_iimmed   0x1234,0x5678,fr10
 406         set_fr_iimmed   0xffff,0xffff,fr11
 407         cmsubhss        fr10,fr11,fr12,cc2,1
 408         test_fr_limmed  0xdead,0xbeef,fr12
 409         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 410         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 411         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 412         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 413
 414         set_spr_immed   0,msr0
 415         set_fr_iimmed   0x7ffe,0x7ffe,fr10
 416         set_fr_iimmed   0xfffe,0xffff,fr11
 417         cmsubhss        fr10,fr11,fr12,cc6,0
 418         test_fr_limmed  0xdead,0xbeef,fr12
 419         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 420         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 421         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 422         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 423
 424         set_spr_immed   0,msr0
 425         set_fr_iimmed   0x8001,0x8001,fr10
 426         set_fr_iimmed   0x0001,0x0002,fr11
 427         cmsubhss        fr10,fr11,fr12,cc6,1
 428         test_fr_limmed  0xdead,0xbeef,fr12
 429         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 430         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 431         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 432         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 433
 434         set_spr_immed   0,msr0
 435         set_fr_iimmed   0x8001,0x8001,fr10
 436         set_fr_iimmed   0x0002,0x0001,fr11
 437         cmsubhss        fr10,fr11,fr12,cc6,0
 438         test_fr_limmed  0xdead,0xbeef,fr12
 439         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 440         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 441         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 442         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 443
 444         set_fr_iimmed   0xbeef,0xdead,fr13
 445         set_spr_immed   0,msr0
 446         set_fr_iimmed   0x0001,0x0001,fr10
 447         set_fr_iimmed   0x8000,0x8000,fr11
 448         cmsubhss.p      fr10,fr10,fr12,cc6,1
 449         cmsubhss        fr11,fr10,fr13,cc6,0
 450         test_fr_limmed  0xdead,0xbeef,fr12
 451         test_fr_limmed  0xbeef,0xdead,fr13
 452         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 453         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 454         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 455         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 456 ;
 457         set_fr_iimmed   0xdead,0xbeef,fr12
 458         set_spr_immed   0,msr0
 459         set_fr_iimmed   0x0000,0x0000,fr10
 460         set_fr_iimmed   0x0000,0x0000,fr11
 461         cmsubhss        fr10,fr11,fr12,cc3,1
 462         test_fr_limmed  0xdead,0xbeef,fr12
 463         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 464         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 465         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 466         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 467
 468         set_fr_iimmed   0xdead,0x0000,fr10
 469         set_fr_iimmed   0x0000,0xbeef,fr11
 470         cmsubhss        fr10,fr11,fr12,cc3,0
 471         test_fr_limmed  0xdead,0xbeef,fr12
 472         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 473         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 474         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 475         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 476
 477         set_fr_iimmed   0x0000,0xdead,fr10
 478         set_fr_iimmed   0xbeef,0x0000,fr11
 479         cmsubhss        fr10,fr11,fr12,cc3,1
 480         test_fr_limmed  0xdead,0xbeef,fr12
 481         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 482         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 483         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 484         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 485
 486         set_fr_iimmed   0x1234,0x5678,fr10
 487         set_fr_iimmed   0x1111,0x1111,fr11
 488         cmsubhss        fr10,fr11,fr12,cc3,0
 489         test_fr_limmed  0xdead,0xbeef,fr12
 490         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 491         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 492         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 493         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 494
 495         set_fr_iimmed   0x1234,0x5678,fr10
 496         set_fr_iimmed   0xffff,0xffff,fr11
 497         cmsubhss        fr10,fr11,fr12,cc3,1
 498         test_fr_limmed  0xdead,0xbeef,fr12
 499         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 500         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 501         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 502         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 503
 504         set_spr_immed   0,msr0
 505         set_fr_iimmed   0x7ffe,0x7ffe,fr10
 506         set_fr_iimmed   0xfffe,0xffff,fr11
 507         cmsubhss        fr10,fr11,fr12,cc7,0
 508         test_fr_limmed  0xdead,0xbeef,fr12
 509         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 510         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 511         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 512         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 513
 514         set_spr_immed   0,msr0
 515         set_fr_iimmed   0x8001,0x8001,fr10
 516         set_fr_iimmed   0x0001,0x0002,fr11
 517         cmsubhss        fr10,fr11,fr12,cc7,1
 518         test_fr_limmed  0xdead,0xbeef,fr12
 519         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 520         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 521         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 522         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 523
 524         set_spr_immed   0,msr0
 525         set_fr_iimmed   0x8001,0x8001,fr10
 526         set_fr_iimmed   0x0002,0x0001,fr11
 527         cmsubhss        fr10,fr11,fr12,cc7,0
 528         test_fr_limmed  0xdead,0xbeef,fr12
 529         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 530         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 531         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 532         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 533
 534         set_fr_iimmed   0xbeef,0xdead,fr13
 535         set_spr_immed   0,msr0
 536         set_fr_iimmed   0x0001,0x0001,fr10
 537         set_fr_iimmed   0x8000,0x8000,fr11
 538         cmsubhss.p      fr10,fr10,fr12,cc7,1
 539         cmsubhss        fr11,fr10,fr13,cc7,0
 540         test_fr_limmed  0xdead,0xbeef,fr12
 541         test_fr_limmed  0xbeef,0xdead,fr13
 542         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 543         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 544         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 545         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 546
 547         pass