sim/testsuite/frv/fr550/cmsubhus.cgs

   1 # frv testcase for cmsubhus $FRi,$FRj,$FRj,$CCi,$cond
   2 # mach: all
   3
   4         .include "../testutils.inc"
   5
   6         start
   7
   8         .global cmsubhus
   9 cmsubhus:
  10         set_spr_immed   0x1b1b,cccr
  11
  12         set_fr_iimmed   0x0000,0x0000,fr10
  13         set_fr_iimmed   0x0000,0x0000,fr11
  14         cmsubhus        fr10,fr11,fr12,cc0,1
  15         test_fr_limmed  0x0000,0x0000,fr12
  16         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  17         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  18         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  19         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
  20
  21         set_fr_iimmed   0xdead,0xbeef,fr10
  22         set_fr_iimmed   0x0000,0x0000,fr11
  23         cmsubhus        fr10,fr11,fr12,cc0,1
  24         test_fr_limmed  0xdead,0xbeef,fr12
  25         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  26         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  27         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  28         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
  29
  30         set_fr_iimmed   0x1234,0x5678,fr10
  31         set_fr_iimmed   0x1111,0x1111,fr11
  32         cmsubhus        fr10,fr11,fr12,cc0,1
  33         test_fr_limmed  0x0123,0x4567,fr12
  34         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  35         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  36         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  37         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
  38
  39         set_fr_iimmed   0x7ffe,0x7ffe,fr10
  40         set_fr_iimmed   0x0002,0x0001,fr11
  41         cmsubhus        fr10,fr11,fr12,cc0,1
  42         test_fr_limmed  0x7ffc,0x7ffd,fr12
  43         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  44         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  45         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  46         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
  47
  48         set_fr_iimmed   0x0001,0x0001,fr10
  49         set_fr_iimmed   0x0001,0x0002,fr11
  50         cmsubhus        fr10,fr11,fr12,cc4,1
  51         test_fr_limmed  0x0000,0x0000,fr12
  52         test_spr_bits   0x3c,2,0x4,msr0         ; msr0.sie is set
  53         test_spr_bits   2,1,1,msr0              ; msr0.ovf set
  54         test_spr_bits   1,0,1,msr0              ; msr0.aovf set
  55         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
  56
  57         set_spr_immed   0,msr0
  58         set_fr_iimmed   0x0001,0x0001,fr10
  59         set_fr_iimmed   0x0002,0x0001,fr11
  60         cmsubhus        fr10,fr11,fr12,cc4,1
  61         test_fr_limmed  0x0000,0x0000,fr12
  62         test_spr_bits   0x3c,2,0x8,msr0         ; msr0.sie is set
  63         test_spr_bits   2,1,1,msr0              ; msr0.ovf set
  64         test_spr_bits   1,0,1,msr0              ; msr0.aovf set
  65         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
  66
  67         set_spr_immed   0,msr0
  68         set_fr_iimmed   0x0001,0x0001,fr10
  69         set_fr_iimmed   0x0002,0x0002,fr11
  70         cmsubhus.p      fr10,fr10,fr12,cc4,1
  71         cmsubhus        fr10,fr11,fr13,cc4,1
  72         test_fr_limmed  0x0000,0x0000,fr12
  73         test_fr_limmed  0x0000,0x0000,fr13
  74         test_spr_bits   0x3c,2,0xc,msr0         ; msr0.sie is set
  75         test_spr_bits   2,1,1,msr0              ; msr0.ovf set
  76         test_spr_bits   1,0,1,msr0              ; msr0.aovf set
  77         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
  78
  79         set_spr_immed   0,msr0
  80         set_fr_iimmed   0x0000,0x0000,fr10
  81         set_fr_iimmed   0x0000,0x0000,fr11
  82         cmsubhus        fr10,fr11,fr12,cc1,0
  83         test_fr_limmed  0x0000,0x0000,fr12
  84         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  85         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  86         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  87         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
  88
  89         set_fr_iimmed   0xdead,0xbeef,fr10
  90         set_fr_iimmed   0x0000,0x0000,fr11
  91         cmsubhus        fr10,fr11,fr12,cc1,0
  92         test_fr_limmed  0xdead,0xbeef,fr12
  93         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  94         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  95         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  96         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
  97
  98         set_fr_iimmed   0x1234,0x5678,fr10
  99         set_fr_iimmed   0x1111,0x1111,fr11
 100         cmsubhus        fr10,fr11,fr12,cc1,0
 101         test_fr_limmed  0x0123,0x4567,fr12
 102         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 103         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 104         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 105         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 106
 107         set_fr_iimmed   0x7ffe,0x7ffe,fr10
 108         set_fr_iimmed   0x0002,0x0001,fr11
 109         cmsubhus        fr10,fr11,fr12,cc1,0
 110         test_fr_limmed  0x7ffc,0x7ffd,fr12
 111         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 112         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 113         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 114         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 115
 116         set_fr_iimmed   0x0001,0x0001,fr10
 117         set_fr_iimmed   0x0001,0x0002,fr11
 118         cmsubhus        fr10,fr11,fr12,cc5,0
 119         test_fr_limmed  0x0000,0x0000,fr12
 120         test_spr_bits   0x3c,2,0x4,msr0         ; msr0.sie is set
 121         test_spr_bits   2,1,1,msr0              ; msr0.ovf set
 122         test_spr_bits   1,0,1,msr0              ; msr0.aovf set
 123         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
 124
 125         set_spr_immed   0,msr0
 126         set_fr_iimmed   0x0001,0x0001,fr10
 127         set_fr_iimmed   0x0002,0x0001,fr11
 128         cmsubhus        fr10,fr11,fr12,cc5,0
 129         test_fr_limmed  0x0000,0x0000,fr12
 130         test_spr_bits   0x3c,2,0x8,msr0         ; msr0.sie is set
 131         test_spr_bits   2,1,1,msr0              ; msr0.ovf set
 132         test_spr_bits   1,0,1,msr0              ; msr0.aovf set
 133         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
 134
 135         set_spr_immed   0,msr0
 136         set_fr_iimmed   0x0001,0x0001,fr10
 137         set_fr_iimmed   0x0002,0x0002,fr11
 138         cmsubhus.p      fr10,fr10,fr12,cc5,0
 139         cmsubhus        fr10,fr11,fr13,cc5,0
 140         test_fr_limmed  0x0000,0x0000,fr12
 141         test_fr_limmed  0x0000,0x0000,fr13
 142         test_spr_bits   0x3c,2,0xc,msr0         ; msr0.sie is set
 143         test_spr_bits   2,1,1,msr0              ; msr0.ovf set
 144         test_spr_bits   1,0,1,msr0              ; msr0.aovf set
 145         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
 146
 147         set_fr_iimmed   0xdead,0xbeef,fr12
 148         set_spr_immed   0,msr0
 149         set_fr_iimmed   0x0000,0x0000,fr10
 150         set_fr_iimmed   0x0000,0x0000,fr11
 151         cmsubhus        fr10,fr11,fr12,cc0,0
 152         test_fr_limmed  0xdead,0xbeef,fr12
 153         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 154         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 155         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 156         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 157
 158         set_fr_iimmed   0xbeef,0xdead,fr10
 159         set_fr_iimmed   0x0000,0x0000,fr11
 160         cmsubhus        fr10,fr11,fr12,cc0,0
 161         test_fr_limmed  0xdead,0xbeef,fr12
 162         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 163         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 164         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 165         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 166
 167         set_fr_iimmed   0x1234,0x5678,fr10
 168         set_fr_iimmed   0x1111,0x1111,fr11
 169         cmsubhus        fr10,fr11,fr12,cc0,0
 170         test_fr_limmed  0xdead,0xbeef,fr12
 171         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 172         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 173         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 174         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 175
 176         set_fr_iimmed   0x7ffe,0x7ffe,fr10
 177         set_fr_iimmed   0x0002,0x0001,fr11
 178         cmsubhus        fr10,fr11,fr12,cc0,0
 179         test_fr_limmed  0xdead,0xbeef,fr12
 180         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 181         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 182         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 183         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 184
 185         set_fr_iimmed   0x0001,0x0001,fr10
 186         set_fr_iimmed   0x0001,0x0002,fr11
 187         cmsubhus        fr10,fr11,fr12,cc4,0
 188         test_fr_limmed  0xdead,0xbeef,fr12
 189         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 190         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 191         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 192         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 193
 194         set_spr_immed   0,msr0
 195         set_fr_iimmed   0x0001,0x0001,fr10
 196         set_fr_iimmed   0x0002,0x0001,fr11
 197         cmsubhus        fr10,fr11,fr12,cc4,0
 198         test_fr_limmed  0xdead,0xbeef,fr12
 199         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 200         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 201         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 202         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 203
 204         set_fr_iimmed   0xbeef,0xdead,fr13
 205         set_spr_immed   0,msr0
 206         set_fr_iimmed   0x0001,0x0001,fr10
 207         set_fr_iimmed   0x0002,0x0002,fr11
 208         cmsubhus.p      fr10,fr10,fr12,cc4,0
 209         cmsubhus        fr10,fr11,fr13,cc4,0
 210         test_fr_limmed  0xdead,0xbeef,fr12
 211         test_fr_limmed  0xbeef,0xdead,fr13
 212         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 213         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 214         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 215         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 216
 217         set_fr_iimmed   0xdead,0xbeef,fr12
 218         set_spr_immed   0,msr0
 219         set_fr_iimmed   0x0000,0x0000,fr10
 220         set_fr_iimmed   0x0000,0x0000,fr11
 221         cmsubhus        fr10,fr11,fr12,cc1,1
 222         test_fr_limmed  0xdead,0xbeef,fr12
 223         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 224         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 225         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 226         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 227
 228         set_fr_iimmed   0xbeef,0xdead,fr10
 229         set_fr_iimmed   0x0000,0x0000,fr11
 230         cmsubhus        fr10,fr11,fr12,cc1,1
 231         test_fr_limmed  0xdead,0xbeef,fr12
 232         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 233         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 234         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 235         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 236
 237         set_fr_iimmed   0x1234,0x5678,fr10
 238         set_fr_iimmed   0x1111,0x1111,fr11
 239         cmsubhus        fr10,fr11,fr12,cc1,1
 240         test_fr_limmed  0xdead,0xbeef,fr12
 241         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 242         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 243         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 244         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 245
 246         set_fr_iimmed   0x7ffe,0x7ffe,fr10
 247         set_fr_iimmed   0x0002,0x0001,fr11
 248         cmsubhus        fr10,fr11,fr12,cc1,1
 249         test_fr_limmed  0xdead,0xbeef,fr12
 250         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 251         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 252         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 253         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 254
 255         set_fr_iimmed   0x0001,0x0001,fr10
 256         set_fr_iimmed   0x0001,0x0002,fr11
 257         cmsubhus        fr10,fr11,fr12,cc5,1
 258         test_fr_limmed  0xdead,0xbeef,fr12
 259         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 260         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 261         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 262         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 263
 264         set_spr_immed   0,msr0
 265         set_fr_iimmed   0x0001,0x0001,fr10
 266         set_fr_iimmed   0x0002,0x0001,fr11
 267         cmsubhus        fr10,fr11,fr12,cc5,1
 268         test_fr_limmed  0xdead,0xbeef,fr12
 269         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 270         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 271         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 272         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 273
 274         set_fr_iimmed   0xbeef,0xdead,fr13
 275         set_spr_immed   0,msr0
 276         set_fr_iimmed   0x0001,0x0001,fr10
 277         set_fr_iimmed   0x0002,0x0002,fr11
 278         cmsubhus.p      fr10,fr10,fr12,cc5,1
 279         cmsubhus        fr10,fr11,fr13,cc5,1
 280         test_fr_limmed  0xdead,0xbeef,fr12
 281         test_fr_limmed  0xbeef,0xdead,fr13
 282         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 283         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 284         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 285         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 286
 287         set_fr_iimmed   0xdead,0xbeef,fr12
 288         set_spr_immed   0,msr0
 289         set_fr_iimmed   0x0000,0x0000,fr10
 290         set_fr_iimmed   0x0000,0x0000,fr11
 291         cmsubhus        fr10,fr11,fr12,cc2,0
 292         test_fr_limmed  0xdead,0xbeef,fr12
 293         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 294         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 295         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 296         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 297
 298         set_fr_iimmed   0xbeef,0xdead,fr10
 299         set_fr_iimmed   0x0000,0x0000,fr11
 300         cmsubhus        fr10,fr11,fr12,cc2,1
 301         test_fr_limmed  0xdead,0xbeef,fr12
 302         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 303         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 304         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 305         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 306
 307         set_fr_iimmed   0x1234,0x5678,fr10
 308         set_fr_iimmed   0x1111,0x1111,fr11
 309         cmsubhus        fr10,fr11,fr12,cc2,0
 310         test_fr_limmed  0xdead,0xbeef,fr12
 311         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 312         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 313         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 314         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 315
 316         set_fr_iimmed   0x7ffe,0x7ffe,fr10
 317         set_fr_iimmed   0x0002,0x0001,fr11
 318         cmsubhus        fr10,fr11,fr12,cc2,1
 319         test_fr_limmed  0xdead,0xbeef,fr12
 320         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 321         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 322         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 323         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 324
 325         set_fr_iimmed   0x0001,0x0001,fr10
 326         set_fr_iimmed   0x0001,0x0002,fr11
 327         cmsubhus        fr10,fr11,fr12,cc6,0
 328         test_fr_limmed  0xdead,0xbeef,fr12
 329         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 330         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 331         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 332         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 333
 334         set_spr_immed   0,msr0
 335         set_fr_iimmed   0x0001,0x0001,fr10
 336         set_fr_iimmed   0x0002,0x0001,fr11
 337         cmsubhus        fr10,fr11,fr12,cc6,1
 338         test_fr_limmed  0xdead,0xbeef,fr12
 339         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 340         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 341         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 342         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 343
 344         set_fr_iimmed   0xbeef,0xdead,fr13
 345         set_spr_immed   0,msr0
 346         set_fr_iimmed   0x0001,0x0001,fr10
 347         set_fr_iimmed   0x0002,0x0002,fr11
 348         cmsubhus.p      fr10,fr10,fr12,cc6,0
 349         cmsubhus        fr10,fr11,fr13,cc6,1
 350         test_fr_limmed  0xdead,0xbeef,fr12
 351         test_fr_limmed  0xbeef,0xdead,fr13
 352         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 353         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 354         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 355         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 356 ;
 357         set_fr_iimmed   0xdead,0xbeef,fr12
 358         set_spr_immed   0,msr0
 359         set_fr_iimmed   0x0000,0x0000,fr10
 360         set_fr_iimmed   0x0000,0x0000,fr11
 361         cmsubhus        fr10,fr11,fr12,cc3,0
 362         test_fr_limmed  0xdead,0xbeef,fr12
 363         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 364         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 365         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 366         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 367
 368         set_fr_iimmed   0xbeef,0xdead,fr10
 369         set_fr_iimmed   0x0000,0x0000,fr11
 370         cmsubhus        fr10,fr11,fr12,cc3,1
 371         test_fr_limmed  0xdead,0xbeef,fr12
 372         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 373         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 374         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 375         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 376
 377         set_fr_iimmed   0x1234,0x5678,fr10
 378         set_fr_iimmed   0x1111,0x1111,fr11
 379         cmsubhus        fr10,fr11,fr12,cc3,0
 380         test_fr_limmed  0xdead,0xbeef,fr12
 381         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 382         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 383         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 384         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 385
 386         set_fr_iimmed   0x7ffe,0x7ffe,fr10
 387         set_fr_iimmed   0x0002,0x0001,fr11
 388         cmsubhus        fr10,fr11,fr12,cc3,1
 389         test_fr_limmed  0xdead,0xbeef,fr12
 390         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 391         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 392         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 393         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 394
 395         set_fr_iimmed   0x0001,0x0001,fr10
 396         set_fr_iimmed   0x0001,0x0002,fr11
 397         cmsubhus        fr10,fr11,fr12,cc7,0
 398         test_fr_limmed  0xdead,0xbeef,fr12
 399         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 400         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 401         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 402         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 403
 404         set_spr_immed   0,msr0
 405         set_fr_iimmed   0x0001,0x0001,fr10
 406         set_fr_iimmed   0x0002,0x0001,fr11
 407         cmsubhus        fr10,fr11,fr12,cc7,1
 408         test_fr_limmed  0xdead,0xbeef,fr12
 409         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 410         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 411         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 412         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 413
 414         set_fr_iimmed   0xbeef,0xdead,fr13
 415         set_spr_immed   0,msr0
 416         set_fr_iimmed   0x0001,0x0001,fr10
 417         set_fr_iimmed   0x0002,0x0002,fr11
 418         cmsubhus.p      fr10,fr10,fr12,cc7,0
 419         cmsubhus        fr10,fr11,fr13,cc7,1
 420         test_fr_limmed  0xdead,0xbeef,fr12
 421         test_fr_limmed  0xbeef,0xdead,fr13
 422         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 423         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 424         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 425         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 426
 427         pass