1 # FRV testcase for dcpl GRi,GRj,lock
4 .include "../testutils.inc"
10 or_spr_immed 0xc8000000,hsr0 ; caches enabled -- copy-back mode
12 ; preload and lock all the lines in set 0 of the data cache
13 set_gr_immed 0x70000,gr10
15 set_mem_immed 0x11111111,gr10
16 test_mem_immed 0x11111111,gr10
18 inc_gr_immed 0x2000,gr10
21 set_mem_immed 0x22222222,gr10
22 test_mem_immed 0x22222222,gr10
24 inc_gr_immed 0x2000,gr10
27 set_mem_immed 0x33333333,gr10
28 test_mem_immed 0x33333333,gr10
30 inc_gr_immed 0x2000,gr10
33 set_mem_immed 0x44444444,gr10
34 test_mem_immed 0x44444444,gr10
36 ; Now write to another address which should be in the same set
37 ; the write should go through to memory, since all the lines in the
39 inc_gr_immed 0x2000,gr10
40 set_mem_immed 0xdeadbeef,gr10
41 test_mem_immed 0xdeadbeef,gr10
43 ; Invalidate the data cache. Only the last value stored should have made
44 ; it through to memory
45 set_gr_immed 0x70000,gr10
46 invalidate_data_cache gr10
49 inc_gr_immed 0x2000,gr10
50 invalidate_data_cache gr10
53 inc_gr_immed 0x2000,gr10
54 invalidate_data_cache gr10
57 inc_gr_immed 0x2000,gr10
58 invalidate_data_cache gr10
61 inc_gr_immed 0x2000,gr10
62 invalidate_data_cache gr10
63 test_mem_immed 0xdeadbeef,gr10