sim/testsuite/frv/fr550/mmrdhu.cgs

   1 # frv testcase for mmrdhu $GRi,$GRj,$GRk
   2 # mach: all
   3
   4         .include "../testutils.inc"
   5
   6         start
   7
   8         .global mmrdhu
   9 mmrdhu:
  10         set_accg_immed  0x80,accg0
  11         set_acc_immed   0,acc0
  12         set_accg_immed  0x80,accg1
  13         set_acc_immed   0,acc1
  14
  15         set_fr_iimmed   3,2,fr7         ; multiply small numbers
  16         set_fr_iimmed   2,3,fr8
  17         mmrdhu          fr7,fr8,acc0
  18         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  19         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  20         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  21         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
  22         test_accg_immed         0x7f,accg0
  23         test_acc_immed  0xfffffffa,acc0
  24         test_accg_immed         0x7f,accg1
  25         test_acc_immed  0xfffffffa,acc1
  26
  27         set_fr_iimmed   1,2,fr7         ; multiply by 1
  28         set_fr_iimmed   2,1,fr8
  29         mmrdhu          fr7,fr8,acc0
  30         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  31         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  32         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  33         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
  34         test_accg_immed         0x7f,accg0
  35         test_acc_immed  0xfffffff8,acc0
  36         test_accg_immed         0x7f,accg1
  37         test_acc_immed  0xfffffff8,acc1
  38
  39         set_fr_iimmed   0,2,fr7         ; multiply by 0
  40         set_fr_iimmed   2,0,fr8
  41         mmrdhu          fr7,fr8,acc0
  42         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  43         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  44         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  45         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
  46         test_accg_immed         0x7f,accg0
  47         test_acc_immed  0xfffffff8,acc0
  48         test_accg_immed         0x7f,accg1
  49         test_acc_immed  0xfffffff8,acc1
  50
  51         set_fr_iimmed   0x3fff,2,fr7    ; 15 bit result
  52         set_fr_iimmed   2,0x3fff,fr8
  53         mmrdhu          fr7,fr8,acc0
  54         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  55         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  56         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  57         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
  58         test_accg_immed         0x7f,accg0
  59         test_acc_limmed 0xffff,0x7ffa,acc0
  60         test_accg_immed         0x7f,accg1
  61         test_acc_limmed 0xffff,0x7ffa,acc1
  62
  63         set_fr_iimmed   0x4000,2,fr7    ; 16 bit result
  64         set_fr_iimmed   2,0x4000,fr8
  65         mmrdhu          fr7,fr8,acc0
  66         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  67         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  68         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  69         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
  70         test_accg_immed         0x7f,accg0
  71         test_acc_limmed 0xfffe,0xfffa,acc0
  72         test_accg_immed         0x7f,accg1
  73         test_acc_limmed 0xfffe,0xfffa,acc1
  74
  75         set_fr_iimmed   0x8000,2,fr7    ; 17 bit result
  76         set_fr_iimmed   2,0x8000,fr8
  77         mmrdhu          fr7,fr8,acc0
  78         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  79         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  80         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  81         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
  82         test_accg_immed         0x7f,accg0
  83         test_acc_limmed 0xfffd,0xfffa,acc0
  84         test_accg_immed         0x7f,accg1
  85         test_acc_limmed 0xfffd,0xfffa,acc1
  86
  87         set_fr_iimmed   0x7fff,0x7fff,fr7       ; max positive result
  88         set_fr_iimmed   0x7fff,0x7fff,fr8
  89         mmrdhu          fr7,fr8,acc0
  90         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  91         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  92         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  93         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
  94         test_accg_immed         0x7f,accg0
  95         test_acc_limmed 0xbffe,0xfff9,acc0
  96         test_accg_immed         0x7f,accg1
  97         test_acc_limmed 0xbffe,0xfff9,acc1
  98
  99         set_fr_iimmed   0x8000,0x8000,fr7       ; max positive result
 100         set_fr_iimmed   0x8000,0x8000,fr8
 101         mmrdhu          fr7,fr8,acc0
 102         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 103         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 104         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 105         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 106         test_accg_immed         0x7f,accg0
 107         test_acc_limmed 0x7ffe,0xfff9,acc0
 108         test_accg_immed         0x7f,accg1
 109         test_acc_limmed 0x7ffe,0xfff9,acc1
 110
 111         set_fr_iimmed   0xffff,0xffff,fr7       ; max positive result
 112         set_fr_iimmed   0xffff,0xffff,fr8
 113         mmrdhu          fr7,fr8,acc0
 114         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 115         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 116         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 117         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 118         test_accg_immed         0x7e,accg0
 119         test_acc_limmed 0x8000,0xfff8,acc0
 120         test_accg_immed         0x7e,accg1
 121         test_acc_limmed 0x8000,0xfff8,acc1
 122
 123         set_accg_immed  0,accg0         ; saturation
 124         set_acc_immed   0,acc0
 125         set_accg_immed  0,accg1
 126         set_acc_immed   0,acc1
 127         set_fr_iimmed   1,1,fr7
 128         set_fr_iimmed   1,1,fr8
 129         mmrdhu          fr7,fr8,acc0
 130         test_spr_bits   0x3c,2,0xc,msr0         ; msr0.sie is set
 131         test_spr_bits   2,1,1,msr0              ; msr0.ovf is set
 132         test_spr_bits   1,0,1,msr0              ; msr0.aovf is set
 133         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt is set
 134         test_accg_immed         0,accg0
 135         test_acc_immed  0,acc0
 136         test_accg_immed         0,accg1
 137         test_acc_immed  0,acc1
 138
 139         set_fr_iimmed   0x0000,0xffff,fr7
 140         set_fr_iimmed   0xffff,0xffff,fr8
 141         mmrdhu          fr7,fr8,acc0
 142         test_spr_bits   0x3c,2,0x4,msr0         ; msr0.sie is set
 143         test_spr_bits   2,1,1,msr0              ; msr0.ovf is set
 144         test_spr_bits   1,0,1,msr0              ; msr0.aovf is set
 145         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt is set
 146         test_accg_immed         0,accg0
 147         test_acc_immed  0,acc0
 148         test_accg_immed         0,accg1
 149         test_acc_immed  0,acc1
 150
 151         pass