sim/testsuite/frv/fr550/msubaccs.cgs

   1 # frv testcase for msubaccs $ACC40Si,$ACC40Sk
   2 # mach: all
   3
   4         .include "../testutils.inc"
   5
   6         start
   7
   8         .global msubaccs
   9 msubaccs:
  10         set_accg_immed  0,accg0
  11         set_acc_immed   0x00000000,acc0
  12         set_accg_immed  0,accg1
  13         set_acc_immed   0x00000000,acc1
  14         msubaccs        acc0,acc3
  15         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  16         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  17         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  18         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
  19         test_accg_immed 0,accg3
  20         test_acc_limmed 0x0000,0x0000,acc3
  21
  22         set_accg_immed  0,accg0
  23         set_acc_immed   0xdead0000,acc0
  24         set_accg_immed  0,accg1
  25         set_acc_immed   0x0000beef,acc1
  26         msubaccs        acc0,acc3
  27         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  28         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  29         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  30         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
  31         test_accg_immed 0,accg3
  32         test_acc_limmed 0xdeac,0x4111,acc3
  33
  34         set_accg_immed  0,accg0
  35         set_acc_immed   0x0000dead,acc0
  36         set_accg_immed  0,accg1
  37         set_acc_immed   0xbeef0000,acc1
  38         msubaccs        acc0,acc3
  39         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  40         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  41         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  42         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
  43         test_accg_immed 0xff,accg3
  44         test_acc_limmed 0x4111,0xdead,acc3
  45
  46         set_accg_immed  0,accg0
  47         set_acc_immed   0x12345678,acc0
  48         set_accg_immed  0,accg1
  49         set_acc_immed   0x11111111,acc1
  50         msubaccs        acc0,acc3
  51         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  52         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  53         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  54         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
  55         test_accg_immed 0,accg3
  56         test_acc_limmed 0x0123,0x4567,acc3
  57
  58         set_accg_immed  0,accg0
  59         set_acc_immed   0x12345678,acc0
  60         set_accg_immed  0,accg1
  61         set_acc_immed   0xffffffff,acc1
  62         msubaccs        acc0,acc3
  63         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  64         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  65         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  66         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
  67         test_accg_immed 0xff,accg3
  68         test_acc_limmed 0x1234,0x5679,acc3
  69
  70         set_accg_immed  0,accg0
  71         set_acc_immed   0x12345678,acc0
  72         set_accg_immed  0xff,accg1
  73         set_acc_immed   0xffffffff,acc1
  74         msubaccs        acc0,acc3
  75         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  76         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  77         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  78         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
  79         test_accg_immed 0,accg3
  80         test_acc_limmed 0x1234,0x5679,acc3
  81
  82         set_spr_immed   0,msr0
  83         set_accg_immed  0x7f,accg0
  84         set_acc_immed   0xfffffffe,acc0
  85         set_accg_immed  0xff,accg1
  86         set_acc_immed   0xfffffffe,acc1
  87         msubaccs        acc0,acc3
  88         test_spr_bits   0x3c,2,0x8,msr0         ; msr0.sie is set
  89         test_spr_bits   2,1,1,msr0              ; msr0.ovf set
  90         test_spr_bits   1,0,1,msr0              ; msr0.aovf set
  91         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
  92         test_accg_immed 0x7f,accg3
  93         test_acc_limmed 0xffff,0xffff,acc3
  94
  95         set_spr_immed   0,msr0
  96         set_accg_immed  0x80,accg0
  97         set_acc_immed   0x00000001,acc0
  98         set_accg_immed  0,accg1
  99         set_acc_immed   0x00000002,acc1
 100         msubaccs        acc0,acc3
 101         test_spr_bits   0x3c,2,0x8,msr0         ; msr0.sie is set
 102         test_spr_bits   2,1,1,msr0              ; msr0.ovf set
 103         test_spr_bits   1,0,1,msr0              ; msr0.aovf set
 104         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
 105         test_accg_immed 0x80,accg3
 106         test_acc_limmed 0x0000,0x0000,acc3
 107
 108         set_spr_immed   0,msr0
 109         set_accg_immed  0,accg0
 110         set_acc_immed   0x00000001,acc0
 111         set_accg_immed  0,accg1
 112         set_acc_immed   0x00000001,acc1
 113         set_accg_immed  0,accg4
 114         set_acc_immed   0x00000001,acc4
 115         set_accg_immed  0x80,accg5
 116         set_acc_immed   0x00000000,acc5
 117         msubaccs.p      acc0,acc1
 118         msubaccs        acc4,acc5
 119         test_spr_bits   0x3c,2,0x8,msr0         ; msr0.sie is set
 120         test_spr_bits   2,1,1,msr0              ; msr0.ovf set
 121         test_spr_bits   1,0,1,msr0              ; msr0.aovf set
 122         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
 123         test_accg_immed 0,accg1
 124         test_acc_limmed 0x0000,0x0000,acc1
 125         test_accg_immed 0x7f,accg5
 126         test_acc_limmed 0xffff,0xffff,acc5
 127
 128         pass