sim/testsuite/frv/fteq.cgs

   1 # frv testcase for fteq $FCCi_2,$GRi,$GRj
   2 # mach: all
   3
   4         .include "testutils.inc"
   5
   6         start
   7
   8         .global fteq
   9 fteq:
  10         and_spr_immed   -4081,tbr               ; clear tbr.tt
  11         set_gr_spr      tbr,gr7
  12         inc_gr_immed    2112,gr7                ; address of exception handler
  13         set_bctrlr_0_0  gr7     ; bctrlr 0,0
  14
  15         set_spr_immed   128,lcr
  16         set_gr_immed    0,gr7
  17         set_gr_immed    4,gr8
  18
  19         set_spr_addr    bad,lr
  20         set_fcc         0x0 0
  21         fteq            fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  22
  23         set_spr_addr    bad,lr
  24         set_fcc         0x1 0
  25         fteq            fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  26
  27         set_spr_addr    bad,lr
  28         set_fcc         0x2 0
  29         fteq            fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  30
  31         set_spr_addr    bad,lr
  32         set_fcc         0x3 0
  33         fteq            fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  34
  35         set_spr_addr    bad,lr
  36         set_fcc         0x4 0
  37         fteq            fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  38
  39         set_spr_addr    bad,lr
  40         set_fcc         0x5 0
  41         fteq            fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  42
  43         set_spr_addr    bad,lr
  44         set_fcc         0x6 0
  45         fteq            fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  46
  47         set_spr_addr    bad,lr
  48         set_fcc         0x7 0
  49         fteq            fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  50
  51         set_psr_et      1
  52         set_spr_addr    ok8,lr
  53         set_fcc         0x8 0
  54         fteq            fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  55         fail
  56 ok8:
  57         set_psr_et      1
  58         set_spr_addr    ok9,lr
  59         set_fcc         0x9 0
  60         fteq            fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  61         fail
  62 ok9:
  63         set_psr_et      1
  64         set_spr_addr    oka,lr
  65         set_fcc         0xa 0
  66         fteq            fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  67         fail
  68 oka:
  69         set_psr_et      1
  70         set_spr_addr    okb,lr
  71         set_fcc         0xb 0
  72         fteq            fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  73         fail
  74 okb:
  75         set_psr_et      1
  76         set_spr_addr    okc,lr
  77         set_fcc         0xc 0
  78         fteq            fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  79         fail
  80 okc:
  81         set_psr_et      1
  82         set_spr_addr    okd,lr
  83         set_fcc         0xd 0
  84         fteq            fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  85         fail
  86 okd:
  87         set_psr_et      1
  88         set_spr_addr    oke,lr
  89         set_fcc         0xe 0
  90         fteq            fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  91         fail
  92 oke:
  93         set_psr_et      1
  94         set_spr_addr    okf,lr
  95         set_fcc         0xf 0
  96         fteq            fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  97         fail
  98 okf:
  99         pass
 100 bad:
 101         fail