Automatic date update in version.in
[binutils-gdb.git] / sim / testsuite / frv / fto.cgs
blob82035f4bec0a7ed55d5437d3c2e74dec987a69b5
1 # frv testcase for fto $FCCi_2,$GRi,$GRj
2 # mach: all
4         .include "testutils.inc"
6         start
8         .global fto
9 fto:
10         and_spr_immed   -4081,tbr               ; clear tbr.tt
11         set_gr_spr      tbr,gr7
12         inc_gr_immed    2112,gr7                ; address of exception handler
13         set_bctrlr_0_0  gr7     ; bctrlr 0,0
15         set_spr_immed   128,lcr
16         set_gr_immed    0,gr7
17         set_gr_immed    4,gr8
19         set_spr_addr    bad,lr
20         set_fcc         0x0 0
21         fto             fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
23         set_spr_addr    bad,lr
24         set_fcc         0x1 0
25         fto             fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
27         set_psr_et      1
28         set_spr_addr    ok2,lr
29         set_fcc         0x2 0
30         fto             fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
31         fail
32 ok2:
33         set_psr_et      1
34         set_spr_addr    ok3,lr
35         set_fcc         0x3 0
36         fto             fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
37         fail
38 ok3:
39         set_psr_et      1
40         set_spr_addr    ok4,lr
41         set_fcc         0x4 0
42         fto             fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
43         fail
44 ok4:
45         set_psr_et      1
46         set_spr_addr    ok5,lr
47         set_fcc         0x5 0
48         fto             fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
49         fail
50 ok5:
51         set_psr_et      1
52         set_spr_addr    ok6,lr
53         set_fcc         0x6 0
54         fto             fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
55         fail
56 ok6:
57         set_psr_et      1
58         set_spr_addr    ok7,lr
59         set_fcc         0x7 0
60         fto             fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
61         fail
62 ok7:
63         set_psr_et      1
64         set_spr_addr    ok8,lr
65         set_fcc         0x8 0
66         fto             fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
67         fail
68 ok8:
69         set_psr_et      1
70         set_spr_addr    ok9,lr
71         set_fcc         0x9 0
72         fto             fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
73         fail
74 ok9:
75         set_psr_et      1
76         set_spr_addr    oka,lr
77         set_fcc         0xa 0
78         fto             fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
79         fail
80 oka:
81         set_psr_et      1
82         set_spr_addr    okb,lr
83         set_fcc         0xb 0
84         fto             fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
85         fail
86 okb:
87         set_psr_et      1
88         set_spr_addr    okc,lr
89         set_fcc         0xc 0
90         fto             fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
91         fail
92 okc:
93         set_psr_et      1
94         set_spr_addr    okd,lr
95         set_fcc         0xd 0
96         fto             fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
97         fail
98 okd:
99         set_psr_et      1
100         set_spr_addr    oke,lr
101         set_fcc         0xe 0
102         fto             fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
103         fail
104 oke:
105         set_psr_et      1
106         set_spr_addr    okf,lr
107         set_fcc         0xf 0
108         fto             fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
109         fail
110 okf:
111         pass
112 bad:
113         fail