sim/testsuite/frv/interrupts/compound-fr550.cgs

   1 # frv testcase to generate compound exception
   2 # mach: fr550
   3         .include "testutils.inc"
   4
   5         start
   6
   7         .global align
   8 align:
   9         and_spr_immed   -4081,tbr               ; clear tbr.tt
  10         set_gr_spr      tbr,gr17
  11         inc_gr_immed    0x200,gr17              ; address of exception handler
  12         set_bctrlr_0_0  gr17
  13         set_spr_immed   128,lcr
  14         set_spr_addr    ok1,lr
  15         or_spr_immed    0x04000000,fsr0         ; enabled div/0 fp_exception
  16         set_psr_et      1
  17
  18         set_gr_immed    0,gr15
  19         set_fr_iimmed   0x7f7f,0xffff,fr0
  20         set_fr_iimmed   0x0000,0x0000,fr1
  21
  22         and_spr_immed   0xfffffffe,isr          ; enable mem_address_not_aligned
  23         set_gr_addr     dividef,gr16
  24         set_gr_addr     dividei,gr17
  25         set_gr_immed    0xdeadbeef,gr8
  26         inc_gr_immed    2,sp                    ; misalign
  27 store:  sti.p           gr8,@(sp,0)             ; misaligned - no exception
  28 dividef:fdivs.p         fr0,fr1,fr2             ; fp_exception
  29 dividei:sdiv            gr1,gr0,gr1             ; division exception
  30         test_gr_immed   1,gr15
  31
  32         pass
  33
  34 ; exception handler
  35 ok1:
  36         ; check fp_exception
  37         test_spr_immed  0x5,esfr1               ; esr2 and esr0 are active
  38         test_spr_gr     epcr2,gr16
  39         test_spr_bits   0x0001,0,0x1,esr2       ; esr2 is valid
  40         test_spr_bits   0x003e,1,0xd,esr2       ; esr2.ec is set
  41         test_spr_bits   0x0800,11,0x0,esr2      ; esr2.eav is clear
  42
  43         ; check on fp_exception
  44         test_spr_bits   0x100000,20,0x0,fsr0    ; fsr0.qne is clear
  45         test_spr_bits   0xe0000,17,0x1,fsr0     ; fsr0.ftt is set
  46         test_spr_bits   0xfc00,10,0x0,fsr0      ; fsr0.aexc is clear
  47
  48         ; check interrupt on dividei
  49         test_spr_bits   0x0001,0,0x1,esr0       ; esr0 is valid
  50         test_spr_bits   0x003e,1,0x13,esr0      ; esr0.ec is set
  51
  52         inc_gr_immed    1,gr15
  53         rett            0
  54         fail