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[binutils-gdb.git] / sim / testsuite / frv / mdasaccs.cgs
blob0535b6295b205bde29abf2cc3a0f2857bea37a42
1 # frv testcase for mdasaccs $ACC40Si,$ACC40Sk
2 # mach: fr400
4         .include "testutils.inc"
6         start
8         .global mdasaccs
9 mdasaccs:
10         set_accg_immed  0,accg0
11         set_acc_immed   0x00000000,acc0
12         set_accg_immed  0,accg1
13         set_acc_immed   0x00000000,acc1
14         set_accg_immed  0,accg2
15         set_acc_immed   0xdead0000,acc2
16         set_accg_immed  0,accg3
17         set_acc_immed   0x0000beef,acc3
18         mdasaccs        acc0,acc0
19         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
20         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
21         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
22         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
23         test_accg_immed 0,accg0
24         test_acc_limmed 0x0000,0x0000,acc0
25         test_accg_immed 0,accg1
26         test_acc_limmed 0x0000,0x0000,acc1
27         test_accg_immed 0,accg2
28         test_acc_limmed 0xdead,0xbeef,acc2
29         test_accg_immed 0,accg3
30         test_acc_limmed 0xdeac,0x4111,acc3
32         set_accg_immed  0,accg0
33         set_acc_immed   0x0000dead,acc0
34         set_accg_immed  0,accg1
35         set_acc_immed   0xbeef0000,acc1
36         set_accg_immed  0,accg2
37         set_acc_immed   0x12345678,acc2
38         set_accg_immed  0,accg3
39         set_acc_immed   0x11111111,acc3
40         mdasaccs        acc0,acc0
41         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
42         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
43         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
44         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
45         test_accg_immed 0,accg0
46         test_acc_limmed 0xbeef,0xdead,acc0
47         test_accg_immed 0xff,accg1
48         test_acc_limmed 0x4111,0xdead,acc1
49         test_accg_immed 0,accg2
50         test_acc_limmed 0x2345,0x6789,acc2
51         test_accg_immed 0,accg3
52         test_acc_limmed 0x0123,0x4567,acc3
54         set_accg_immed  0,accg0
55         set_acc_immed   0x12345678,acc0
56         set_accg_immed  0,accg1
57         set_acc_immed   0xffffffff,acc1
58         set_accg_immed  0,accg2
59         set_acc_immed   0x12345678,acc2
60         set_accg_immed  0xff,accg3
61         set_acc_immed   0xffffffff,acc3
62         mdasaccs        acc0,acc0
63         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
64         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
65         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
66         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
67         test_accg_immed 1,accg0
68         test_acc_limmed 0x1234,0x5677,acc0
69         test_accg_immed 0xff,accg1
70         test_acc_limmed 0x1234,0x5679,acc1
71         test_accg_immed 0,accg2
72         test_acc_limmed 0x1234,0x5677,acc2
73         test_accg_immed 0,accg3
74         test_acc_limmed 0x1234,0x5679,acc3
76         set_spr_immed   0,msr0
77         set_accg_immed  0x7f,accg0
78         set_acc_immed   0xfffe7ffe,acc0
79         set_accg_immed  0x0,accg1
80         set_acc_immed   0x00020001,acc1
81         set_accg_immed  0x80,accg2
82         set_acc_immed   0x00000001,acc2
83         set_accg_immed  0xff,accg3
84         set_acc_immed   0xfffffffe,acc3
85         mdasaccs        acc0,acc0
86         test_spr_bits   0x3c,2,0xa,msr0         ; msr0.sie is set
87         test_spr_bits   2,1,1,msr0              ; msr0.ovf set
88         test_spr_bits   1,0,1,msr0              ; msr0.aovf set
89         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
90         test_accg_immed 0x7f,accg0
91         test_acc_limmed 0xffff,0xffff,acc0
92         test_accg_immed 0x7f,accg1
93         test_acc_limmed 0xfffc,0x7ffd,acc1
94         test_accg_immed 0x80,accg2
95         test_acc_limmed 0x0000,0x0000,acc2
96         test_accg_immed 0x80,accg3
97         test_acc_limmed 0x0000,0x0003,acc3
99         set_spr_immed   0,msr0
100         set_accg_immed  0,accg0
101         set_acc_immed   0x00000001,acc0
102         set_accg_immed  0,accg1
103         set_acc_immed   0x00000001,acc1
104         set_accg_immed  0,accg2
105         set_acc_immed   0x00000001,acc2
106         set_accg_immed  0x7f,accg3
107         set_acc_immed   0xffffffff,acc3
108         mdasaccs        acc0,acc0
109         test_spr_bits   0x3c,2,0x2,msr0         ; msr0.sie set
110         test_spr_bits   2,1,1,msr0              ; msr0.ovf set
111         test_spr_bits   1,0,1,msr0              ; msr0.aovf set
112         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
113         test_accg_immed 0,accg0
114         test_acc_limmed 0x0000,0x0002,acc0
115         test_accg_immed 0,accg1
116         test_acc_limmed 0x0000,0x0000,acc1
117         test_accg_immed 0x7f,accg2
118         test_acc_limmed 0xffff,0xffff,acc2
119         test_accg_immed 0x80,accg3
120         test_acc_limmed 0x0000,0x0002,acc3
122         pass