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[binutils-gdb.git] / sim / testsuite / frv / mdsubaccs.cgs
blob73d2e2dc899e4ccb12346300d4ba4305e2c366cc
1 # frv testcase for mdsubaccs $ACC40Si,$ACC40Sk
2 # mach: fr400
4         .include "testutils.inc"
6         start
8         .global mdsubaccs
9 mdsubaccs:
10         set_accg_immed  0,accg0
11         set_acc_immed   0x00000000,acc0
12         set_accg_immed  0,accg1
13         set_acc_immed   0x00000000,acc1
14         set_accg_immed  0,accg2
15         set_acc_immed   0xdead0000,acc2
16         set_accg_immed  0,accg3
17         set_acc_immed   0x0000beef,acc3
18         mdsubaccs       acc0,acc2
19         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
20         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
21         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
22         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
23         test_accg_immed 0,accg2
24         test_acc_limmed 0x0000,0x0000,acc2
25         test_accg_immed 0,accg3
26         test_acc_limmed 0xdeac,0x4111,acc3
28         set_accg_immed  0,accg0
29         set_acc_immed   0x0000dead,acc0
30         set_accg_immed  0,accg1
31         set_acc_immed   0xbeef0000,acc1
32         set_accg_immed  0,accg2
33         set_acc_immed   0x12345678,acc2
34         set_accg_immed  0,accg3
35         set_acc_immed   0x11111111,acc3
36         mdsubaccs       acc0,acc2
37         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
38         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
39         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
40         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
41         test_accg_immed 0xff,accg2
42         test_acc_limmed 0x4111,0xdead,acc2
43         test_accg_immed 0,accg3
44         test_acc_limmed 0x0123,0x4567,acc3
46         set_accg_immed  0,accg0
47         set_acc_immed   0x12345678,acc0
48         set_accg_immed  0,accg1
49         set_acc_immed   0xffffffff,acc1
50         set_accg_immed  0,accg2
51         set_acc_immed   0x12345678,acc2
52         set_accg_immed  0xff,accg3
53         set_acc_immed   0xffffffff,acc3
54         mdsubaccs       acc0,acc2
55         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
56         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
57         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
58         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
59         test_accg_immed 0xff,accg2
60         test_acc_limmed 0x1234,0x5679,acc2
61         test_accg_immed 0,accg3
62         test_acc_limmed 0x1234,0x5679,acc3
64         set_spr_immed   0,msr0
65         set_accg_immed  0x7f,accg0
66         set_acc_immed   0xfffffffe,acc0
67         set_accg_immed  0xff,accg1
68         set_acc_immed   0xfffffffe,acc1
69         set_accg_immed  0x80,accg2
70         set_acc_immed   0x00000001,acc2
71         set_accg_immed  0,accg3
72         set_acc_immed   0x00000002,acc3
73         mdsubaccs       acc0,acc2
74         test_spr_bits   0x3c,2,0xc,msr0         ; msr0.sie is set
75         test_spr_bits   2,1,1,msr0              ; msr0.ovf set
76         test_spr_bits   1,0,1,msr0              ; msr0.aovf set
77         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
78         test_accg_immed 0x7f,accg2
79         test_acc_limmed 0xffff,0xffff,acc2
80         test_accg_immed 0x80,accg3
81         test_acc_limmed 0x0000,0x0000,acc3
83         set_spr_immed   0,msr0
84         set_accg_immed  0,accg0
85         set_acc_immed   0x00000001,acc0
86         set_accg_immed  0,accg1
87         set_acc_immed   0x00000001,acc1
88         set_accg_immed  0,accg2
89         set_acc_immed   0x00000001,acc2
90         set_accg_immed  0x80,accg3
91         set_acc_immed   0x00000000,acc3
92         mdsubaccs       acc0,acc2
93         test_spr_bits   0x3c,2,4,msr0           ; msr0.sie is set
94         test_spr_bits   2,1,1,msr0              ; msr0.ovf is set
95         test_spr_bits   1,0,1,msr0              ; msr0.aovf set
96         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
97         test_accg_immed 0,accg2
98         test_acc_limmed 0x0000,0x0000,acc2
99         test_accg_immed 0x7f,accg3
100         test_acc_limmed 0xffff,0xffff,acc3
102         pass