sim/testsuite/frv/msubhus.cgs

   1 # frv testcase for msubhus $FRi,$FRj,$FRj
   2 # mach: frv fr500 fr400
   3
   4         .include "testutils.inc"
   5
   6         start
   7
   8         .global msubhus
   9 msubhus:
  10         set_fr_iimmed   0x0000,0x0000,fr10
  11         set_fr_iimmed   0x0000,0x0000,fr11
  12         msubhus         fr10,fr11,fr12
  13         test_fr_limmed  0x0000,0x0000,fr12
  14         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  15         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  16         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  17         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
  18
  19         set_fr_iimmed   0xdead,0xbeef,fr10
  20         set_fr_iimmed   0x0000,0x0000,fr11
  21         msubhus         fr10,fr11,fr12
  22         test_fr_limmed  0xdead,0xbeef,fr12
  23         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  24         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  25         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  26         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
  27
  28         set_fr_iimmed   0x1234,0x5678,fr10
  29         set_fr_iimmed   0x1111,0x1111,fr11
  30         msubhus         fr10,fr11,fr12
  31         test_fr_limmed  0x0123,0x4567,fr12
  32         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  33         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  34         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  35         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
  36
  37         set_fr_iimmed   0x7ffe,0x7ffe,fr10
  38         set_fr_iimmed   0x0002,0x0001,fr11
  39         msubhus         fr10,fr11,fr12
  40         test_fr_limmed  0x7ffc,0x7ffd,fr12
  41         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  42         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  43         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  44         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
  45
  46         set_fr_iimmed   0x0001,0x0001,fr10
  47         set_fr_iimmed   0x0001,0x0002,fr11
  48         msubhus         fr10,fr11,fr12
  49         test_fr_limmed  0x0000,0x0000,fr12
  50         test_spr_bits   0x3c,2,0x4,msr0         ; msr0.sie is set
  51         test_spr_bits   2,1,1,msr0              ; msr0.ovf set
  52         test_spr_bits   1,0,1,msr0              ; msr0.aovf set
  53         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
  54
  55         set_spr_immed   0,msr0
  56         set_fr_iimmed   0x0001,0x0001,fr10
  57         set_fr_iimmed   0x0002,0x0001,fr11
  58         msubhus         fr10,fr11,fr12
  59         test_fr_limmed  0x0000,0x0000,fr12
  60         test_spr_bits   0x3c,2,0x8,msr0         ; msr0.sie is set
  61         test_spr_bits   2,1,1,msr0              ; msr0.ovf set
  62         test_spr_bits   1,0,1,msr0              ; msr0.aovf set
  63         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
  64
  65         set_spr_immed   0,msr0
  66         set_spr_immed   0,msr1
  67         set_fr_iimmed   0x0001,0x0001,fr10
  68         set_fr_iimmed   0x0002,0x0002,fr11
  69         msubhus.p       fr10,fr10,fr12
  70         msubhus         fr10,fr11,fr13
  71         test_fr_limmed  0x0000,0x0000,fr12
  72         test_fr_limmed  0x0000,0x0000,fr13
  73         test_spr_bits   0x3c,2,0x0,msr0         ; msr0.sie is clear
  74         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  75         test_spr_bits   0x3c,2,0xc,msr1         ; msr1.sie is set
  76         test_spr_bits   2,1,1,msr1              ; msr1.ovf set
  77         test_spr_bits   1,0,1,msr0              ; msr0.aovf set
  78         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
  79
  80         pass