Automatic date update in version.in
[binutils-gdb.git] / sim / testsuite / frv / tieq.cgs
blob5dfc0e66f19e8eec846b25f32824ae81879d6b0d
1 # frv testcase for tieq $ICCi_2,$GRi,$s12
2 # mach: all
4         .include "testutils.inc"
6         start
8         .global tieq
9 tieq:
10         and_spr_immed   -4081,tbr               ; clear tbr.tt
11         set_gr_spr      tbr,gr7
12         inc_gr_immed    2112,gr7                ; address of exception handler
13         set_bctrlr_0_0  gr7     ; bctrlr 0,0
15         set_spr_immed   128,lcr
16         set_gr_immed    0,gr7
18         set_spr_addr    bad,lr
19         set_icc         0x0 0
20         tieq            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
22         set_spr_addr    bad,lr
23         set_icc         0x1 0
24         tieq            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
26         set_spr_addr    bad,lr
27         set_icc         0x2 0
28         tieq            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
30         set_spr_addr    bad,lr
31         set_icc         0x3 0
32         tieq            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
34         set_psr_et      1
35         set_spr_addr    ok4,lr
36         set_icc         0x4 0
37         tieq            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
38         fail
39 ok4:
40         set_psr_et      1
41         set_spr_addr    ok5,lr
42         set_icc         0x5 0
43         tieq            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
44         fail
45 ok5:
46         set_psr_et      1
47         set_spr_addr    ok6,lr
48         set_icc         0x6 0
49         tieq            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
50         fail
51 ok6:
52         set_psr_et      1
53         set_spr_addr    ok7,lr
54         set_icc         0x7 0
55         tieq            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
56         fail
57 ok7:
58         set_psr_et      1
59         set_spr_addr    bad,lr
60         set_icc         0x8 0
61         tieq            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
63         set_spr_addr    bad,lr
64         set_icc         0x9 0
65         tieq            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
67         set_spr_addr    bad,lr
68         set_icc         0xa 0
69         tieq            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
71         set_spr_addr    bad,lr
72         set_icc         0xb 0
73         tieq            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
75         set_psr_et      1
76         set_spr_addr    okc,lr
77         set_icc         0xc 0
78         tieq            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
79         fail
80 okc:
81         set_psr_et      1
82         set_spr_addr    okd,lr
83         set_icc         0xd 0
84         tieq            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
85         fail
86 okd:
87         set_psr_et      1
88         set_spr_addr    oke,lr
89         set_icc         0xe 0
90         tieq            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
91         fail
92 oke:
93         set_psr_et      1
94         set_spr_addr    okf,lr
95         set_icc         0xf 0
96         tieq            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
97         fail
98 okf:
99         pass
100 bad:
101         fail