RISC-V: Cleanup the imply code and test cases for vendor xsf extensions.
[binutils-gdb.git] / sim / testsuite / frv / tigt.cgs
blob163d92f179f717db34436fbb3fa1accc05fa6f1e
1 # frv testcase for tigt $ICCi_2,$GRi,$s12
2 # mach: all
4         .include "testutils.inc"
6         start
8         .global tigt
9 tigt:
10         and_spr_immed   -4081,tbr               ; clear tbr.tt
11         set_gr_spr      tbr,gr7
12         inc_gr_immed    2112,gr7                ; address of exception handler
13         set_bctrlr_0_0  gr7     ; bctrlr 0,0
15         set_spr_immed   128,lcr
16         set_gr_immed    0,gr7
18         set_psr_et      1
19         set_spr_addr    ok0,lr
20         set_icc         0x0 0
21         tigt            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
22         fail
23 ok0:
24         set_psr_et      1
25         set_spr_addr    ok1,lr
26         set_icc         0x1 0
27         tigt            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
28         fail
29 ok1:
30         set_spr_addr    bad,lr
31         set_icc         0x2 0
32         tigt            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
34         set_spr_addr    bad,lr
35         set_icc         0x3 0
36         tigt            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
38         set_spr_addr    bad,lr
39         set_icc         0x4 0
40         tigt            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
42         set_spr_addr    bad,lr
43         set_icc         0x5 0
44         tigt            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
46         set_spr_addr    bad,lr
47         set_icc         0x6 0
48         tigt            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
50         set_spr_addr    bad,lr
51         set_icc         0x7 0
52         tigt            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
54         set_spr_addr    bad,lr
55         set_icc         0x8 0
56         tigt            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
58         set_spr_addr    bad,lr
59         set_icc         0x9 0
60         tigt            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
62         set_psr_et      1
63         set_spr_addr    oka,lr
64         set_icc         0xa 0
65         tigt            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
66         fail
67 oka:
68         set_psr_et      1
69         set_spr_addr    okb,lr
70         set_icc         0xb 0
71         tigt            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
72         fail
73 okb:
74         set_spr_addr    bad,lr
75         set_icc         0xc 0
76         tigt            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
78         set_spr_addr    bad,lr
79         set_icc         0xd 0
80         tigt            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
82         set_spr_addr    bad,lr
83         set_icc         0xe 0
84         tigt            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
86         set_spr_addr    bad,lr
87         set_icc         0xf 0
88         tigt            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
90         pass
91 bad:
92         fail