sim/testsuite/frv/tinc.cgs

   1 # frv testcase for tinc $ICCi_2,$GRi,$s12
   2 # mach: all
   3
   4         .include "testutils.inc"
   5
   6         start
   7
   8         .global tinc
   9 tinc:
  10         and_spr_immed   -4081,tbr               ; clear tbr.tt
  11         set_gr_spr      tbr,gr7
  12         inc_gr_immed    2112,gr7                ; address of exception handler
  13         set_bctrlr_0_0  gr7     ; bctrlr 0,0
  14
  15         set_spr_immed   128,lcr
  16         set_gr_immed    0,gr7
  17
  18         set_psr_et      1
  19         set_spr_addr    ok0,lr
  20         set_icc         0x0 0
  21         tinc            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  22         fail
  23 ok0:
  24         set_spr_addr    bad,lr
  25         set_icc         0x1 0
  26         tinc            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  27
  28         set_psr_et      1
  29         set_spr_addr    ok2,lr
  30         set_icc         0x2 0
  31         tinc            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  32         fail
  33 ok2:
  34         set_spr_addr    bad,lr
  35         set_icc         0x3 0
  36         tinc            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  37
  38         set_psr_et      1
  39         set_spr_addr    ok4,lr
  40         set_icc         0x4 0
  41         tinc            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  42         fail
  43 ok4:
  44         set_spr_addr    bad,lr
  45         set_icc         0x5 0
  46         tinc            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  47
  48         set_psr_et      1
  49         set_spr_addr    ok6,lr
  50         set_icc         0x6 0
  51         tinc            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  52         fail
  53 ok6:
  54         set_spr_addr    bad,lr
  55         set_icc         0x7 0
  56         tinc            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  57
  58         set_psr_et      1
  59         set_spr_addr    ok8,lr
  60         set_icc         0x8 0
  61         tinc            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  62         fail
  63 ok8:
  64         set_spr_addr    bad,lr
  65         set_icc         0x9 0
  66         tinc            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  67
  68         set_psr_et      1
  69         set_spr_addr    oka,lr
  70         set_icc         0xa 0
  71         tinc            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  72         fail
  73 oka:
  74         set_spr_addr    bad,lr
  75         set_icc         0xb 0
  76         tinc            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  77
  78         set_psr_et      1
  79         set_spr_addr    okc,lr
  80         set_icc         0xc 0
  81         tinc            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  82         fail
  83 okc:
  84         set_spr_addr    bad,lr
  85         set_icc         0xd 0
  86         tinc            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  87
  88         set_psr_et      1
  89         set_spr_addr    oke,lr
  90         set_icc         0xe 0
  91         tinc            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  92         fail
  93 oke:
  94         set_spr_addr    bad,lr
  95         set_icc         0xf 0
  96         tinc            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  97
  98         pass
  99 bad:
 100         fail