sim/testsuite/frv/tine.cgs

   1 # frv testcase for tine $ICCi_2,$GRi,$s12
   2 # mach: all
   3
   4         .include "testutils.inc"
   5
   6         start
   7
   8         .global tine
   9 tine:
  10         and_spr_immed   -4081,tbr               ; clear tbr.tt
  11         set_gr_spr      tbr,gr7
  12         inc_gr_immed    2112,gr7                ; address of exception handler
  13         set_bctrlr_0_0  gr7     ; bctrlr 0,0
  14
  15         set_spr_immed   128,lcr
  16         set_gr_immed    0,gr7
  17
  18         set_psr_et      1
  19         set_spr_addr    ok0,lr
  20         set_icc         0x0 0
  21         tine            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  22         fail
  23 ok0:
  24         set_psr_et      1
  25         set_spr_addr    ok1,lr
  26         set_icc         0x1 0
  27         tine            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  28         fail
  29 ok1:
  30         set_psr_et      1
  31         set_spr_addr    ok2,lr
  32         set_icc         0x2 0
  33         tine            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  34         fail
  35 ok2:
  36         set_psr_et      1
  37         set_spr_addr    ok3,lr
  38         set_icc         0x3 0
  39         tine            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  40         fail
  41 ok3:
  42         set_spr_addr    bad,lr
  43         set_icc         0x4 0
  44         tine            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  45
  46         set_spr_addr    bad,lr
  47         set_icc         0x5 0
  48         tine            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  49
  50         set_spr_addr    bad,lr
  51         set_icc         0x6 0
  52         tine            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  53
  54         set_spr_addr    bad,lr
  55         set_icc         0x7 0
  56         tine            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  57
  58         set_psr_et      1
  59         set_spr_addr    ok8,lr
  60         set_icc         0x8 0
  61         tine            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  62         fail
  63 ok8:
  64         set_psr_et      1
  65         set_spr_addr    ok9,lr
  66         set_icc         0x9 0
  67         tine            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  68         fail
  69 ok9:
  70         set_psr_et      1
  71         set_spr_addr    oka,lr
  72         set_icc         0xa 0
  73         tine            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  74         fail
  75 oka:
  76         set_psr_et      1
  77         set_spr_addr    okb,lr
  78         set_icc         0xb 0
  79         tine            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  80         fail
  81 okb:
  82         set_spr_addr    bad,lr
  83         set_icc         0xc 0
  84         tine            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  85
  86         set_spr_addr    bad,lr
  87         set_icc         0xd 0
  88         tine            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  89
  90         set_spr_addr    bad,lr
  91         set_icc         0xe 0
  92         tine            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  93
  94         set_spr_addr    bad,lr
  95         set_icc         0xf 0
  96         tine            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  97
  98         pass
  99 bad:
 100         fail