tc-i386.c fix for oss-fuzz gas fuzzing
[binutils-gdb.git] / sim / testsuite / sh / pshlr.s
blob64e5a4372e8e677d955cbf2b83947602bb31cbc6
1 # sh testcase for pshl <reg>
2 # mach: shdsp
3 # as(shdsp): -defsym sim_cpu=1 -dsp
5 .include "testutils.inc"
7 start
9 pshl_reg: ! shift arithmetic, register operand
10 set_grs_a5a5
11 lds r0, a0
12 pcopy a0, a1
13 lds r0, x0
14 lds r0, x1
15 lds r0, y0
16 lds r0, y1
17 pcopy x0, m0
18 pcopy y1, m1
20 set_sreg 0x10000, x0
21 set_sreg 0x0, y0
22 pshl x0, y0, x0
23 assert_sreg 0x10000, x0
24 pneg y0, y0
25 pshl x0, y0, x0
26 assert_sreg 0x10000, x0
28 set_sreg 0x10000, y0
29 pshl x0, y0, x0
30 assert_sreg 0x20000, x0
31 pneg y0, y0
32 pshl x0, y0, x0
33 assert_sreg 0x10000, x0
35 set_sreg 0x20000, y0
36 pshl x0, y0, x0
37 assert_sreg 0x40000, x0
38 pneg y0, y0
39 pshl x0, y0, x0
40 assert_sreg 0x10000, x0
42 set_sreg 0x30000, y0
43 pshl x0, y0, x0
44 assert_sreg 0x80000, x0
45 pneg y0, y0
46 pshl x0, y0, x0
47 assert_sreg 0x10000, x0
49 set_sreg 0x40000, y0
50 pshl x0, y0, x0
51 assert_sreg 0x100000, x0
52 pneg y0, y0
53 pshl x0, y0, x0
54 assert_sreg 0x10000, x0
56 set_sreg 0x50000, y0
57 pshl x0, y0, x0
58 assert_sreg 0x200000, x0
59 pneg y0, y0
60 pshl x0, y0, x0
61 assert_sreg 0x10000, x0
63 set_sreg 0x60000, y0
64 pshl x0, y0, x0
65 assert_sreg 0x400000, x0
66 pneg y0, y0
67 pshl x0, y0, x0
68 assert_sreg 0x10000, x0
70 set_sreg 0x70000, y0
71 pshl x0, y0, x0
72 assert_sreg 0x800000, x0
73 pneg y0, y0
74 pshl x0, y0, x0
75 assert_sreg 0x10000, x0
77 set_sreg 0x80000, y0
78 pshl x0, y0, x0
79 assert_sreg 0x1000000, x0
80 pneg y0, y0
81 pshl x0, y0, x0
82 assert_sreg 0x10000, x0
84 set_sreg 0x90000, y0
85 pshl x0, y0, x0
86 assert_sreg 0x2000000, x0
87 pneg y0, y0
88 pshl x0, y0, x0
89 assert_sreg 0x10000, x0
91 set_sreg 0xa0000, y0
92 pshl x0, y0, x0
93 assert_sreg 0x4000000, x0
94 pneg y0, y0
95 pshl x0, y0, x0
96 assert_sreg 0x10000, x0
98 set_sreg 0xb0000, y0
99 pshl x0, y0, x0
100 assert_sreg 0x8000000, x0
101 pneg y0, y0
102 pshl x0, y0, x0
103 assert_sreg 0x10000, x0
105 set_sreg 0xc0000, y0
106 pshl x0, y0, x0
107 assert_sreg 0x10000000, x0
108 pneg y0, y0
109 pshl x0, y0, x0
110 assert_sreg 0x10000, x0
112 set_sreg 0xd0000, y0
113 pshl x0, y0, x0
114 assert_sreg 0x20000000, x0
115 pneg y0, y0
116 pshl x0, y0, x0
117 assert_sreg 0x10000, x0
119 set_sreg 0xe0000, y0
120 pshl x0, y0, x0
121 assert_sreg 0x40000000, x0
122 pneg y0, y0
123 pshl x0, y0, x0
124 assert_sreg 0x10000, x0
126 set_sreg 0xf0000, y0
127 pshl x0, y0, x0
128 assert_sreg 0x80000000, x0
129 pneg y0, y0
130 pshl x0, y0, x0
131 assert_sreg 0x10000, x0
133 set_sreg 0x100000, y0
134 pshl x0, y0, x0
135 assert_sreg 0x00000000, x0
136 pneg y0, y0
137 pshl x0, y0, x0
138 assert_sreg 0x0, x0
140 test_grs_a5a5
141 assert_sreg2 0xa5a5a5a5, a0
142 assert_sreg2 0xa5a5a5a5, a1
143 assert_sreg 0xa5a5a5a5, x1
144 assert_sreg 0xa5a5a5a5, y1
145 assert_sreg2 0xa5a5a5a5, m0
146 assert_sreg2 0xa5a5a5a5, m1
149 pass
150 exit 0