sim/testsuite/sh/shll.s

   1 # sh testcase for shll
   2 # mach: all
   3 # as(sh):       -defsym sim_cpu=0
   4 # as(shdsp):    -defsym sim_cpu=1 -dsp
   5
   6         .include "testutils.inc"
   7
   8         start
   9
  10 shll:
  11         set_grs_a5a5
  12         mov #1, r1
  13         shll r1
  14         assertreg 2, r1
  15         shll r1
  16         assertreg 4, r1
  17         shll r1
  18         assertreg 8, r1
  19         shll r1
  20         assertreg 16, r1
  21         shll r1
  22         assertreg 32, r1
  23         shll r1
  24         assertreg 64, r1
  25         shll r1
  26         assertreg 0x80, r1
  27         shll r1
  28         assertreg 0x100, r1
  29         shll r1
  30         assertreg 0x200, r1
  31         shll r1
  32         assertreg 0x400, r1
  33         shll r1
  34         assertreg 0x800, r1
  35         shll r1
  36         assertreg 0x1000, r1
  37         shll r1
  38         assertreg 0x2000, r1
  39         shll r1
  40         assertreg 0x4000, r1
  41         shll r1
  42         assertreg 0x8000, r1
  43         shll r1
  44         assertreg 0x10000, r1
  45         shll r1
  46         assertreg 0x20000, r1
  47         shll r1
  48         assertreg 0x40000, r1
  49         shll r1
  50         assertreg 0x80000, r1
  51         shll r1
  52         assertreg 0x100000, r1
  53         shll r1
  54         assertreg 0x200000, r1
  55         shll r1
  56         assertreg 0x400000, r1
  57         shll r1
  58         assertreg 0x800000, r1
  59         shll r1
  60         assertreg 0x1000000, r1
  61         shll r1
  62         assertreg 0x2000000, r1
  63         shll r1
  64         assertreg 0x4000000, r1
  65         shll r1
  66         assertreg 0x8000000, r1
  67         shll r1
  68         assertreg 0x10000000, r1
  69         shll r1
  70         assertreg 0x20000000, r1
  71         shll r1
  72         assertreg 0x40000000, r1
  73         shll r1
  74         assertreg 0x80000000, r1
  75         shll r1
  76         assertreg 0, r1
  77         shll r1
  78         assertreg 0, r1
  79
  80         # another:
  81         mov #1, r1
  82         shll r1
  83         shll r1
  84         shll r1
  85         assertreg 8, r1
  86
  87         set_greg     0xa5a5a5a5, r1
  88         test_grs_a5a5
  89
  90         pass
  91         exit 0