sim/m32r/sem-switch.c

   1 /* Simulator instruction semantics for m32rbf.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Simulators.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #ifdef DEFINE_LABELS
  26
  27   /* The labels have the case they have because the enum of insn types
  28      is all uppercase and in the non-stdc case the insn symbol is built
  29      into the enum name.  */
  30
  31   static struct {
  32     int index;
  33     void *label;
  34   } labels[] = {
  35     { M32RBF_INSN_X_INVALID, && case_sem_INSN_X_INVALID },
  36     { M32RBF_INSN_X_AFTER, && case_sem_INSN_X_AFTER },
  37     { M32RBF_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE },
  38     { M32RBF_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN },
  39     { M32RBF_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN },
  40     { M32RBF_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN },
  41     { M32RBF_INSN_ADD, && case_sem_INSN_ADD },
  42     { M32RBF_INSN_ADD3, && case_sem_INSN_ADD3 },
  43     { M32RBF_INSN_AND, && case_sem_INSN_AND },
  44     { M32RBF_INSN_AND3, && case_sem_INSN_AND3 },
  45     { M32RBF_INSN_OR, && case_sem_INSN_OR },
  46     { M32RBF_INSN_OR3, && case_sem_INSN_OR3 },
  47     { M32RBF_INSN_XOR, && case_sem_INSN_XOR },
  48     { M32RBF_INSN_XOR3, && case_sem_INSN_XOR3 },
  49     { M32RBF_INSN_ADDI, && case_sem_INSN_ADDI },
  50     { M32RBF_INSN_ADDV, && case_sem_INSN_ADDV },
  51     { M32RBF_INSN_ADDV3, && case_sem_INSN_ADDV3 },
  52     { M32RBF_INSN_ADDX, && case_sem_INSN_ADDX },
  53     { M32RBF_INSN_BC8, && case_sem_INSN_BC8 },
  54     { M32RBF_INSN_BC24, && case_sem_INSN_BC24 },
  55     { M32RBF_INSN_BEQ, && case_sem_INSN_BEQ },
  56     { M32RBF_INSN_BEQZ, && case_sem_INSN_BEQZ },
  57     { M32RBF_INSN_BGEZ, && case_sem_INSN_BGEZ },
  58     { M32RBF_INSN_BGTZ, && case_sem_INSN_BGTZ },
  59     { M32RBF_INSN_BLEZ, && case_sem_INSN_BLEZ },
  60     { M32RBF_INSN_BLTZ, && case_sem_INSN_BLTZ },
  61     { M32RBF_INSN_BNEZ, && case_sem_INSN_BNEZ },
  62     { M32RBF_INSN_BL8, && case_sem_INSN_BL8 },
  63     { M32RBF_INSN_BL24, && case_sem_INSN_BL24 },
  64     { M32RBF_INSN_BNC8, && case_sem_INSN_BNC8 },
  65     { M32RBF_INSN_BNC24, && case_sem_INSN_BNC24 },
  66     { M32RBF_INSN_BNE, && case_sem_INSN_BNE },
  67     { M32RBF_INSN_BRA8, && case_sem_INSN_BRA8 },
  68     { M32RBF_INSN_BRA24, && case_sem_INSN_BRA24 },
  69     { M32RBF_INSN_CMP, && case_sem_INSN_CMP },
  70     { M32RBF_INSN_CMPI, && case_sem_INSN_CMPI },
  71     { M32RBF_INSN_CMPU, && case_sem_INSN_CMPU },
  72     { M32RBF_INSN_CMPUI, && case_sem_INSN_CMPUI },
  73     { M32RBF_INSN_DIV, && case_sem_INSN_DIV },
  74     { M32RBF_INSN_DIVU, && case_sem_INSN_DIVU },
  75     { M32RBF_INSN_REM, && case_sem_INSN_REM },
  76     { M32RBF_INSN_REMU, && case_sem_INSN_REMU },
  77     { M32RBF_INSN_JL, && case_sem_INSN_JL },
  78     { M32RBF_INSN_JMP, && case_sem_INSN_JMP },
  79     { M32RBF_INSN_LD, && case_sem_INSN_LD },
  80     { M32RBF_INSN_LD_D, && case_sem_INSN_LD_D },
  81     { M32RBF_INSN_LDB, && case_sem_INSN_LDB },
  82     { M32RBF_INSN_LDB_D, && case_sem_INSN_LDB_D },
  83     { M32RBF_INSN_LDH, && case_sem_INSN_LDH },
  84     { M32RBF_INSN_LDH_D, && case_sem_INSN_LDH_D },
  85     { M32RBF_INSN_LDUB, && case_sem_INSN_LDUB },
  86     { M32RBF_INSN_LDUB_D, && case_sem_INSN_LDUB_D },
  87     { M32RBF_INSN_LDUH, && case_sem_INSN_LDUH },
  88     { M32RBF_INSN_LDUH_D, && case_sem_INSN_LDUH_D },
  89     { M32RBF_INSN_LD_PLUS, && case_sem_INSN_LD_PLUS },
  90     { M32RBF_INSN_LD24, && case_sem_INSN_LD24 },
  91     { M32RBF_INSN_LDI8, && case_sem_INSN_LDI8 },
  92     { M32RBF_INSN_LDI16, && case_sem_INSN_LDI16 },
  93     { M32RBF_INSN_LOCK, && case_sem_INSN_LOCK },
  94     { M32RBF_INSN_MACHI, && case_sem_INSN_MACHI },
  95     { M32RBF_INSN_MACLO, && case_sem_INSN_MACLO },
  96     { M32RBF_INSN_MACWHI, && case_sem_INSN_MACWHI },
  97     { M32RBF_INSN_MACWLO, && case_sem_INSN_MACWLO },
  98     { M32RBF_INSN_MUL, && case_sem_INSN_MUL },
  99     { M32RBF_INSN_MULHI, && case_sem_INSN_MULHI },
 100     { M32RBF_INSN_MULLO, && case_sem_INSN_MULLO },
 101     { M32RBF_INSN_MULWHI, && case_sem_INSN_MULWHI },
 102     { M32RBF_INSN_MULWLO, && case_sem_INSN_MULWLO },
 103     { M32RBF_INSN_MV, && case_sem_INSN_MV },
 104     { M32RBF_INSN_MVFACHI, && case_sem_INSN_MVFACHI },
 105     { M32RBF_INSN_MVFACLO, && case_sem_INSN_MVFACLO },
 106     { M32RBF_INSN_MVFACMI, && case_sem_INSN_MVFACMI },
 107     { M32RBF_INSN_MVFC, && case_sem_INSN_MVFC },
 108     { M32RBF_INSN_MVTACHI, && case_sem_INSN_MVTACHI },
 109     { M32RBF_INSN_MVTACLO, && case_sem_INSN_MVTACLO },
 110     { M32RBF_INSN_MVTC, && case_sem_INSN_MVTC },
 111     { M32RBF_INSN_NEG, && case_sem_INSN_NEG },
 112     { M32RBF_INSN_NOP, && case_sem_INSN_NOP },
 113     { M32RBF_INSN_NOT, && case_sem_INSN_NOT },
 114     { M32RBF_INSN_RAC, && case_sem_INSN_RAC },
 115     { M32RBF_INSN_RACH, && case_sem_INSN_RACH },
 116     { M32RBF_INSN_RTE, && case_sem_INSN_RTE },
 117     { M32RBF_INSN_SETH, && case_sem_INSN_SETH },
 118     { M32RBF_INSN_SLL, && case_sem_INSN_SLL },
 119     { M32RBF_INSN_SLL3, && case_sem_INSN_SLL3 },
 120     { M32RBF_INSN_SLLI, && case_sem_INSN_SLLI },
 121     { M32RBF_INSN_SRA, && case_sem_INSN_SRA },
 122     { M32RBF_INSN_SRA3, && case_sem_INSN_SRA3 },
 123     { M32RBF_INSN_SRAI, && case_sem_INSN_SRAI },
 124     { M32RBF_INSN_SRL, && case_sem_INSN_SRL },
 125     { M32RBF_INSN_SRL3, && case_sem_INSN_SRL3 },
 126     { M32RBF_INSN_SRLI, && case_sem_INSN_SRLI },
 127     { M32RBF_INSN_ST, && case_sem_INSN_ST },
 128     { M32RBF_INSN_ST_D, && case_sem_INSN_ST_D },
 129     { M32RBF_INSN_STB, && case_sem_INSN_STB },
 130     { M32RBF_INSN_STB_D, && case_sem_INSN_STB_D },
 131     { M32RBF_INSN_STH, && case_sem_INSN_STH },
 132     { M32RBF_INSN_STH_D, && case_sem_INSN_STH_D },
 133     { M32RBF_INSN_ST_PLUS, && case_sem_INSN_ST_PLUS },
 134     { M32RBF_INSN_ST_MINUS, && case_sem_INSN_ST_MINUS },
 135     { M32RBF_INSN_SUB, && case_sem_INSN_SUB },
 136     { M32RBF_INSN_SUBV, && case_sem_INSN_SUBV },
 137     { M32RBF_INSN_SUBX, && case_sem_INSN_SUBX },
 138     { M32RBF_INSN_TRAP, && case_sem_INSN_TRAP },
 139     { M32RBF_INSN_UNLOCK, && case_sem_INSN_UNLOCK },
 140     { 0, 0 }
 141   };
 142   int i;
 143
 144   for (i = 0; labels[i].label != 0; ++i)
 145     {
 146 #if FAST_P
 147       CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label;
 148 #else
 149       CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label;
 150 #endif
 151     }
 152
 153 #undef DEFINE_LABELS
 154 #endif /* DEFINE_LABELS */
 155
 156 #ifdef DEFINE_SWITCH
 157
 158 /* If hyper-fast [well not unnecessarily slow] execution is selected, turn
 159    off frills like tracing and profiling.  */
 160 /* FIXME: A better way would be to have TRACE_RESULT check for something
 161    that can cause it to be optimized out.  Another way would be to emit
 162    special handlers into the instruction "stream".  */
 163
 164 #if FAST_P
 165 #undef TRACE_RESULT
 166 #define TRACE_RESULT(cpu, abuf, name, type, val)
 167 #endif
 168
 169 #undef GET_ATTR
 170 #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
 171
 172 {
 173
 174 #if WITH_SCACHE_PBB
 175
 176 /* Branch to next handler without going around main loop.  */
 177 #define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case
 178 SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
 179
 180 #else /* ! WITH_SCACHE_PBB */
 181
 182 #define NEXT(vpc) BREAK (sem)
 183 #ifdef __GNUC__
 184 #if FAST_P
 185   SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab)
 186 #else
 187   SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab)
 188 #endif
 189 #else
 190   SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num)
 191 #endif
 192
 193 #endif /* ! WITH_SCACHE_PBB */
 194
 195     {
 196
 197   CASE (sem, INSN_X_INVALID) : /* --invalid-- */
 198 {
 199   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 200   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 201 #define FLD(f) abuf->fields.fmt_empty.f
 202   int UNUSED written = 0;
 203   IADDR UNUSED pc = abuf->addr;
 204   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 205
 206   {
 207     /* Update the recorded pc in the cpu state struct.
 208        Only necessary for WITH_SCACHE case, but to avoid the
 209        conditional compilation ....  */
 210     SET_H_PC (pc);
 211     /* Virtual insns have zero size.  Overwrite vpc with address of next insn
 212        using the default-insn-bitsize spec.  When executing insns in parallel
 213        we may want to queue the fault and continue execution.  */
 214     vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 215     vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
 216   }
 217
 218 #undef FLD
 219 }
 220   NEXT (vpc);
 221
 222   CASE (sem, INSN_X_AFTER) : /* --after-- */
 223 {
 224   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 225   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 226 #define FLD(f) abuf->fields.fmt_empty.f
 227   int UNUSED written = 0;
 228   IADDR UNUSED pc = abuf->addr;
 229   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 230
 231   {
 232 #if WITH_SCACHE_PBB_M32RBF
 233     m32rbf_pbb_after (current_cpu, sem_arg);
 234 #endif
 235   }
 236
 237 #undef FLD
 238 }
 239   NEXT (vpc);
 240
 241   CASE (sem, INSN_X_BEFORE) : /* --before-- */
 242 {
 243   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 244   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 245 #define FLD(f) abuf->fields.fmt_empty.f
 246   int UNUSED written = 0;
 247   IADDR UNUSED pc = abuf->addr;
 248   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 249
 250   {
 251 #if WITH_SCACHE_PBB_M32RBF
 252     m32rbf_pbb_before (current_cpu, sem_arg);
 253 #endif
 254   }
 255
 256 #undef FLD
 257 }
 258   NEXT (vpc);
 259
 260   CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */
 261 {
 262   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 263   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 264 #define FLD(f) abuf->fields.fmt_empty.f
 265   int UNUSED written = 0;
 266   IADDR UNUSED pc = abuf->addr;
 267   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 268
 269   {
 270 #if WITH_SCACHE_PBB_M32RBF
 271 #ifdef DEFINE_SWITCH
 272     vpc = m32rbf_pbb_cti_chain (current_cpu, sem_arg,
 273                                pbb_br_type, pbb_br_npc);
 274     BREAK (sem);
 275 #else
 276     /* FIXME: Allow provision of explicit ifmt spec in insn spec.  */
 277     vpc = m32rbf_pbb_cti_chain (current_cpu, sem_arg,
 278                                CPU_PBB_BR_TYPE (current_cpu),
 279                                CPU_PBB_BR_NPC (current_cpu));
 280 #endif
 281 #endif
 282   }
 283
 284 #undef FLD
 285 }
 286   NEXT (vpc);
 287
 288   CASE (sem, INSN_X_CHAIN) : /* --chain-- */
 289 {
 290   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 291   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 292 #define FLD(f) abuf->fields.fmt_empty.f
 293   int UNUSED written = 0;
 294   IADDR UNUSED pc = abuf->addr;
 295   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 296
 297   {
 298 #if WITH_SCACHE_PBB_M32RBF
 299     vpc = m32rbf_pbb_chain (current_cpu, sem_arg);
 300 #ifdef DEFINE_SWITCH
 301     BREAK (sem);
 302 #endif
 303 #endif
 304   }
 305
 306 #undef FLD
 307 }
 308   NEXT (vpc);
 309
 310   CASE (sem, INSN_X_BEGIN) : /* --begin-- */
 311 {
 312   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 313   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 314 #define FLD(f) abuf->fields.fmt_empty.f
 315   int UNUSED written = 0;
 316   IADDR UNUSED pc = abuf->addr;
 317   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 318
 319   {
 320 #if WITH_SCACHE_PBB_M32RBF
 321 #ifdef DEFINE_SWITCH
 322     /* In the switch case FAST_P is a constant, allowing several optimizations
 323        in any called inline functions.  */
 324     vpc = m32rbf_pbb_begin (current_cpu, FAST_P);
 325 #else
 326     vpc = m32rbf_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
 327 #endif
 328 #endif
 329   }
 330
 331 #undef FLD
 332 }
 333   NEXT (vpc);
 334
 335   CASE (sem, INSN_ADD) : /* add $dr,$sr */
 336 {
 337   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 338   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 339 #define FLD(f) abuf->fields.sfmt_add.f
 340   int UNUSED written = 0;
 341   IADDR UNUSED pc = abuf->addr;
 342   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 343
 344   {
 345     SI opval = ADDSI (* FLD (i_dr), * FLD (i_sr));
 346     * FLD (i_dr) = opval;
 347     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
 348   }
 349
 350 #undef FLD
 351 }
 352   NEXT (vpc);
 353
 354   CASE (sem, INSN_ADD3) : /* add3 $dr,$sr,$hash$slo16 */
 355 {
 356   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 357   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 358 #define FLD(f) abuf->fields.sfmt_add3.f
 359   int UNUSED written = 0;
 360   IADDR UNUSED pc = abuf->addr;
 361   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 362
 363   {
 364     SI opval = ADDSI (* FLD (i_sr), FLD (f_simm16));
 365     * FLD (i_dr) = opval;
 366     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
 367   }
 368
 369 #undef FLD
 370 }
 371   NEXT (vpc);
 372
 373   CASE (sem, INSN_AND) : /* and $dr,$sr */
 374 {
 375   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 376   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 377 #define FLD(f) abuf->fields.sfmt_add.f
 378   int UNUSED written = 0;
 379   IADDR UNUSED pc = abuf->addr;
 380   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 381
 382   {
 383     SI opval = ANDSI (* FLD (i_dr), * FLD (i_sr));
 384     * FLD (i_dr) = opval;
 385     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
 386   }
 387
 388 #undef FLD
 389 }
 390   NEXT (vpc);
 391
 392   CASE (sem, INSN_AND3) : /* and3 $dr,$sr,$uimm16 */
 393 {
 394   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 395   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 396 #define FLD(f) abuf->fields.sfmt_and3.f
 397   int UNUSED written = 0;
 398   IADDR UNUSED pc = abuf->addr;
 399   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 400
 401   {
 402     SI opval = ANDSI (* FLD (i_sr), FLD (f_uimm16));
 403     * FLD (i_dr) = opval;
 404     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
 405   }
 406
 407 #undef FLD
 408 }
 409   NEXT (vpc);
 410
 411   CASE (sem, INSN_OR) : /* or $dr,$sr */
 412 {
 413   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 414   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 415 #define FLD(f) abuf->fields.sfmt_add.f
 416   int UNUSED written = 0;
 417   IADDR UNUSED pc = abuf->addr;
 418   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 419
 420   {
 421     SI opval = ORSI (* FLD (i_dr), * FLD (i_sr));
 422     * FLD (i_dr) = opval;
 423     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
 424   }
 425
 426 #undef FLD
 427 }
 428   NEXT (vpc);
 429
 430   CASE (sem, INSN_OR3) : /* or3 $dr,$sr,$hash$ulo16 */
 431 {
 432   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 433   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 434 #define FLD(f) abuf->fields.sfmt_and3.f
 435   int UNUSED written = 0;
 436   IADDR UNUSED pc = abuf->addr;
 437   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 438
 439   {
 440     SI opval = ORSI (* FLD (i_sr), FLD (f_uimm16));
 441     * FLD (i_dr) = opval;
 442     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
 443   }
 444
 445 #undef FLD
 446 }
 447   NEXT (vpc);
 448
 449   CASE (sem, INSN_XOR) : /* xor $dr,$sr */
 450 {
 451   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 452   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 453 #define FLD(f) abuf->fields.sfmt_add.f
 454   int UNUSED written = 0;
 455   IADDR UNUSED pc = abuf->addr;
 456   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 457
 458   {
 459     SI opval = XORSI (* FLD (i_dr), * FLD (i_sr));
 460     * FLD (i_dr) = opval;
 461     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
 462   }
 463
 464 #undef FLD
 465 }
 466   NEXT (vpc);
 467
 468   CASE (sem, INSN_XOR3) : /* xor3 $dr,$sr,$uimm16 */
 469 {
 470   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 471   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 472 #define FLD(f) abuf->fields.sfmt_and3.f
 473   int UNUSED written = 0;
 474   IADDR UNUSED pc = abuf->addr;
 475   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 476
 477   {
 478     SI opval = XORSI (* FLD (i_sr), FLD (f_uimm16));
 479     * FLD (i_dr) = opval;
 480     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
 481   }
 482
 483 #undef FLD
 484 }
 485   NEXT (vpc);
 486
 487   CASE (sem, INSN_ADDI) : /* addi $dr,$simm8 */
 488 {
 489   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 490   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 491 #define FLD(f) abuf->fields.sfmt_addi.f
 492   int UNUSED written = 0;
 493   IADDR UNUSED pc = abuf->addr;
 494   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 495
 496   {
 497     SI opval = ADDSI (* FLD (i_dr), FLD (f_simm8));
 498     * FLD (i_dr) = opval;
 499     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
 500   }
 501
 502 #undef FLD
 503 }
 504   NEXT (vpc);
 505
 506   CASE (sem, INSN_ADDV) : /* addv $dr,$sr */
 507 {
 508   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 509   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 510 #define FLD(f) abuf->fields.sfmt_add.f
 511   int UNUSED written = 0;
 512   IADDR UNUSED pc = abuf->addr;
 513   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 514
 515 {
 516   SI temp0;BI temp1;
 517   temp0 = ADDSI (* FLD (i_dr), * FLD (i_sr));
 518   temp1 = ADDOFSI (* FLD (i_dr), * FLD (i_sr), 0);
 519   {
 520     SI opval = temp0;
 521     * FLD (i_dr) = opval;
 522     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
 523   }
 524   {
 525     BI opval = temp1;
 526     CPU (h_cond) = opval;
 527     TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
 528   }
 529 }
 530
 531 #undef FLD
 532 }
 533   NEXT (vpc);
 534
 535   CASE (sem, INSN_ADDV3) : /* addv3 $dr,$sr,$simm16 */
 536 {
 537   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 538   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 539 #define FLD(f) abuf->fields.sfmt_add3.f
 540   int UNUSED written = 0;
 541   IADDR UNUSED pc = abuf->addr;
 542   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 543
 544 {
 545   SI temp0;BI temp1;
 546   temp0 = ADDSI (* FLD (i_sr), FLD (f_simm16));
 547   temp1 = ADDOFSI (* FLD (i_sr), FLD (f_simm16), 0);
 548   {
 549     SI opval = temp0;
 550     * FLD (i_dr) = opval;
 551     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
 552   }
 553   {
 554     BI opval = temp1;
 555     CPU (h_cond) = opval;
 556     TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
 557   }
 558 }
 559
 560 #undef FLD
 561 }
 562   NEXT (vpc);
 563
 564   CASE (sem, INSN_ADDX) : /* addx $dr,$sr */
 565 {
 566   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 567   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 568 #define FLD(f) abuf->fields.sfmt_add.f
 569   int UNUSED written = 0;
 570   IADDR UNUSED pc = abuf->addr;
 571   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 572
 573 {
 574   SI temp0;BI temp1;
 575   temp0 = ADDCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
 576   temp1 = ADDCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
 577   {
 578     SI opval = temp0;
 579     * FLD (i_dr) = opval;
 580     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
 581   }
 582   {
 583     BI opval = temp1;
 584     CPU (h_cond) = opval;
 585     TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
 586   }
 587 }
 588
 589 #undef FLD
 590 }
 591   NEXT (vpc);
 592
 593   CASE (sem, INSN_BC8) : /* bc.s $disp8 */
 594 {
 595   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 596   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 597 #define FLD(f) abuf->fields.sfmt_bl8.f
 598   int UNUSED written = 0;
 599   IADDR UNUSED pc = abuf->addr;
 600   SEM_BRANCH_INIT
 601   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 602
 603 if (CPU (h_cond)) {
 604   {
 605     USI opval = FLD (i_disp8);
 606     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
 607     written |= (1 << 2);
 608     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 609   }
 610 }
 611
 612   abuf->written = written;
 613   SEM_BRANCH_FINI (vpc);
 614 #undef FLD
 615 }
 616   NEXT (vpc);
 617
 618   CASE (sem, INSN_BC24) : /* bc.l $disp24 */
 619 {
 620   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 621   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 622 #define FLD(f) abuf->fields.sfmt_bl24.f
 623   int UNUSED written = 0;
 624   IADDR UNUSED pc = abuf->addr;
 625   SEM_BRANCH_INIT
 626   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 627
 628 if (CPU (h_cond)) {
 629   {
 630     USI opval = FLD (i_disp24);
 631     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
 632     written |= (1 << 2);
 633     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 634   }
 635 }
 636
 637   abuf->written = written;
 638   SEM_BRANCH_FINI (vpc);
 639 #undef FLD
 640 }
 641   NEXT (vpc);
 642
 643   CASE (sem, INSN_BEQ) : /* beq $src1,$src2,$disp16 */
 644 {
 645   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 646   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 647 #define FLD(f) abuf->fields.sfmt_beq.f
 648   int UNUSED written = 0;
 649   IADDR UNUSED pc = abuf->addr;
 650   SEM_BRANCH_INIT
 651   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 652
 653 if (EQSI (* FLD (i_src1), * FLD (i_src2))) {
 654   {
 655     USI opval = FLD (i_disp16);
 656     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
 657     written |= (1 << 3);
 658     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 659   }
 660 }
 661
 662   abuf->written = written;
 663   SEM_BRANCH_FINI (vpc);
 664 #undef FLD
 665 }
 666   NEXT (vpc);
 667
 668   CASE (sem, INSN_BEQZ) : /* beqz $src2,$disp16 */
 669 {
 670   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 671   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 672 #define FLD(f) abuf->fields.sfmt_beq.f
 673   int UNUSED written = 0;
 674   IADDR UNUSED pc = abuf->addr;
 675   SEM_BRANCH_INIT
 676   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 677
 678 if (EQSI (* FLD (i_src2), 0)) {
 679   {
 680     USI opval = FLD (i_disp16);
 681     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
 682     written |= (1 << 2);
 683     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 684   }
 685 }
 686
 687   abuf->written = written;
 688   SEM_BRANCH_FINI (vpc);
 689 #undef FLD
 690 }
 691   NEXT (vpc);
 692
 693   CASE (sem, INSN_BGEZ) : /* bgez $src2,$disp16 */
 694 {
 695   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 696   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 697 #define FLD(f) abuf->fields.sfmt_beq.f
 698   int UNUSED written = 0;
 699   IADDR UNUSED pc = abuf->addr;
 700   SEM_BRANCH_INIT
 701   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 702
 703 if (GESI (* FLD (i_src2), 0)) {
 704   {
 705     USI opval = FLD (i_disp16);
 706     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
 707     written |= (1 << 2);
 708     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 709   }
 710 }
 711
 712   abuf->written = written;
 713   SEM_BRANCH_FINI (vpc);
 714 #undef FLD
 715 }
 716   NEXT (vpc);
 717
 718   CASE (sem, INSN_BGTZ) : /* bgtz $src2,$disp16 */
 719 {
 720   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 721   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 722 #define FLD(f) abuf->fields.sfmt_beq.f
 723   int UNUSED written = 0;
 724   IADDR UNUSED pc = abuf->addr;
 725   SEM_BRANCH_INIT
 726   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 727
 728 if (GTSI (* FLD (i_src2), 0)) {
 729   {
 730     USI opval = FLD (i_disp16);
 731     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
 732     written |= (1 << 2);
 733     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 734   }
 735 }
 736
 737   abuf->written = written;
 738   SEM_BRANCH_FINI (vpc);
 739 #undef FLD
 740 }
 741   NEXT (vpc);
 742
 743   CASE (sem, INSN_BLEZ) : /* blez $src2,$disp16 */
 744 {
 745   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 746   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 747 #define FLD(f) abuf->fields.sfmt_beq.f
 748   int UNUSED written = 0;
 749   IADDR UNUSED pc = abuf->addr;
 750   SEM_BRANCH_INIT
 751   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 752
 753 if (LESI (* FLD (i_src2), 0)) {
 754   {
 755     USI opval = FLD (i_disp16);
 756     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
 757     written |= (1 << 2);
 758     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 759   }
 760 }
 761
 762   abuf->written = written;
 763   SEM_BRANCH_FINI (vpc);
 764 #undef FLD
 765 }
 766   NEXT (vpc);
 767
 768   CASE (sem, INSN_BLTZ) : /* bltz $src2,$disp16 */
 769 {
 770   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 771   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 772 #define FLD(f) abuf->fields.sfmt_beq.f
 773   int UNUSED written = 0;
 774   IADDR UNUSED pc = abuf->addr;
 775   SEM_BRANCH_INIT
 776   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 777
 778 if (LTSI (* FLD (i_src2), 0)) {
 779   {
 780     USI opval = FLD (i_disp16);
 781     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
 782     written |= (1 << 2);
 783     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 784   }
 785 }
 786
 787   abuf->written = written;
 788   SEM_BRANCH_FINI (vpc);
 789 #undef FLD
 790 }
 791   NEXT (vpc);
 792
 793   CASE (sem, INSN_BNEZ) : /* bnez $src2,$disp16 */
 794 {
 795   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 796   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 797 #define FLD(f) abuf->fields.sfmt_beq.f
 798   int UNUSED written = 0;
 799   IADDR UNUSED pc = abuf->addr;
 800   SEM_BRANCH_INIT
 801   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 802
 803 if (NESI (* FLD (i_src2), 0)) {
 804   {
 805     USI opval = FLD (i_disp16);
 806     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
 807     written |= (1 << 2);
 808     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 809   }
 810 }
 811
 812   abuf->written = written;
 813   SEM_BRANCH_FINI (vpc);
 814 #undef FLD
 815 }
 816   NEXT (vpc);
 817
 818   CASE (sem, INSN_BL8) : /* bl.s $disp8 */
 819 {
 820   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 821   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 822 #define FLD(f) abuf->fields.sfmt_bl8.f
 823   int UNUSED written = 0;
 824   IADDR UNUSED pc = abuf->addr;
 825   SEM_BRANCH_INIT
 826   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 827
 828 {
 829   {
 830     SI opval = ADDSI (ANDSI (pc, -4), 4);
 831     CPU (h_gr[((UINT) 14)]) = opval;
 832     TRACE_RESULT (current_cpu, abuf, "gr-14", 'x', opval);
 833   }
 834   {
 835     USI opval = FLD (i_disp8);
 836     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
 837     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 838   }
 839 }
 840
 841   SEM_BRANCH_FINI (vpc);
 842 #undef FLD
 843 }
 844   NEXT (vpc);
 845
 846   CASE (sem, INSN_BL24) : /* bl.l $disp24 */
 847 {
 848   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 849   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 850 #define FLD(f) abuf->fields.sfmt_bl24.f
 851   int UNUSED written = 0;
 852   IADDR UNUSED pc = abuf->addr;
 853   SEM_BRANCH_INIT
 854   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 855
 856 {
 857   {
 858     SI opval = ADDSI (pc, 4);
 859     CPU (h_gr[((UINT) 14)]) = opval;
 860     TRACE_RESULT (current_cpu, abuf, "gr-14", 'x', opval);
 861   }
 862   {
 863     USI opval = FLD (i_disp24);
 864     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
 865     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 866   }
 867 }
 868
 869   SEM_BRANCH_FINI (vpc);
 870 #undef FLD
 871 }
 872   NEXT (vpc);
 873
 874   CASE (sem, INSN_BNC8) : /* bnc.s $disp8 */
 875 {
 876   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 877   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 878 #define FLD(f) abuf->fields.sfmt_bl8.f
 879   int UNUSED written = 0;
 880   IADDR UNUSED pc = abuf->addr;
 881   SEM_BRANCH_INIT
 882   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 883
 884 if (NOTBI (CPU (h_cond))) {
 885   {
 886     USI opval = FLD (i_disp8);
 887     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
 888     written |= (1 << 2);
 889     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 890   }
 891 }
 892
 893   abuf->written = written;
 894   SEM_BRANCH_FINI (vpc);
 895 #undef FLD
 896 }
 897   NEXT (vpc);
 898
 899   CASE (sem, INSN_BNC24) : /* bnc.l $disp24 */
 900 {
 901   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 902   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 903 #define FLD(f) abuf->fields.sfmt_bl24.f
 904   int UNUSED written = 0;
 905   IADDR UNUSED pc = abuf->addr;
 906   SEM_BRANCH_INIT
 907   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 908
 909 if (NOTBI (CPU (h_cond))) {
 910   {
 911     USI opval = FLD (i_disp24);
 912     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
 913     written |= (1 << 2);
 914     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 915   }
 916 }
 917
 918   abuf->written = written;
 919   SEM_BRANCH_FINI (vpc);
 920 #undef FLD
 921 }
 922   NEXT (vpc);
 923
 924   CASE (sem, INSN_BNE) : /* bne $src1,$src2,$disp16 */
 925 {
 926   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 927   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 928 #define FLD(f) abuf->fields.sfmt_beq.f
 929   int UNUSED written = 0;
 930   IADDR UNUSED pc = abuf->addr;
 931   SEM_BRANCH_INIT
 932   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 933
 934 if (NESI (* FLD (i_src1), * FLD (i_src2))) {
 935   {
 936     USI opval = FLD (i_disp16);
 937     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
 938     written |= (1 << 3);
 939     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 940   }
 941 }
 942
 943   abuf->written = written;
 944   SEM_BRANCH_FINI (vpc);
 945 #undef FLD
 946 }
 947   NEXT (vpc);
 948
 949   CASE (sem, INSN_BRA8) : /* bra.s $disp8 */
 950 {
 951   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 952   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 953 #define FLD(f) abuf->fields.sfmt_bl8.f
 954   int UNUSED written = 0;
 955   IADDR UNUSED pc = abuf->addr;
 956   SEM_BRANCH_INIT
 957   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 958
 959   {
 960     USI opval = FLD (i_disp8);
 961     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
 962     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 963   }
 964
 965   SEM_BRANCH_FINI (vpc);
 966 #undef FLD
 967 }
 968   NEXT (vpc);
 969
 970   CASE (sem, INSN_BRA24) : /* bra.l $disp24 */
 971 {
 972   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 973   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 974 #define FLD(f) abuf->fields.sfmt_bl24.f
 975   int UNUSED written = 0;
 976   IADDR UNUSED pc = abuf->addr;
 977   SEM_BRANCH_INIT
 978   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 979
 980   {
 981     USI opval = FLD (i_disp24);
 982     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
 983     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 984   }
 985
 986   SEM_BRANCH_FINI (vpc);
 987 #undef FLD
 988 }
 989   NEXT (vpc);
 990
 991   CASE (sem, INSN_CMP) : /* cmp $src1,$src2 */
 992 {
 993   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 994   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 995 #define FLD(f) abuf->fields.sfmt_st_plus.f
 996   int UNUSED written = 0;
 997   IADDR UNUSED pc = abuf->addr;
 998   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 999
1000   {
1001     BI opval = LTSI (* FLD (i_src1), * FLD (i_src2));
1002     CPU (h_cond) = opval;
1003     TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
1004   }
1005
1006 #undef FLD
1007 }
1008   NEXT (vpc);
1009
1010   CASE (sem, INSN_CMPI) : /* cmpi $src2,$simm16 */
1011 {
1012   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1013   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1014 #define FLD(f) abuf->fields.sfmt_st_d.f
1015   int UNUSED written = 0;
1016   IADDR UNUSED pc = abuf->addr;
1017   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1018
1019   {
1020     BI opval = LTSI (* FLD (i_src2), FLD (f_simm16));
1021     CPU (h_cond) = opval;
1022     TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
1023   }
1024
1025 #undef FLD
1026 }
1027   NEXT (vpc);
1028
1029   CASE (sem, INSN_CMPU) : /* cmpu $src1,$src2 */
1030 {
1031   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1032   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1033 #define FLD(f) abuf->fields.sfmt_st_plus.f
1034   int UNUSED written = 0;
1035   IADDR UNUSED pc = abuf->addr;
1036   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1037
1038   {
1039     BI opval = LTUSI (* FLD (i_src1), * FLD (i_src2));
1040     CPU (h_cond) = opval;
1041     TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
1042   }
1043
1044 #undef FLD
1045 }
1046   NEXT (vpc);
1047
1048   CASE (sem, INSN_CMPUI) : /* cmpui $src2,$simm16 */
1049 {
1050   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1051   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1052 #define FLD(f) abuf->fields.sfmt_st_d.f
1053   int UNUSED written = 0;
1054   IADDR UNUSED pc = abuf->addr;
1055   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1056
1057   {
1058     BI opval = LTUSI (* FLD (i_src2), FLD (f_simm16));
1059     CPU (h_cond) = opval;
1060     TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
1061   }
1062
1063 #undef FLD
1064 }
1065   NEXT (vpc);
1066
1067   CASE (sem, INSN_DIV) : /* div $dr,$sr */
1068 {
1069   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1070   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1071 #define FLD(f) abuf->fields.sfmt_add.f
1072   int UNUSED written = 0;
1073   IADDR UNUSED pc = abuf->addr;
1074   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1075
1076 if (NESI (* FLD (i_sr), 0)) {
1077   {
1078     SI opval = DIVSI (* FLD (i_dr), * FLD (i_sr));
1079     * FLD (i_dr) = opval;
1080     written |= (1 << 2);
1081     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1082   }
1083 }
1084
1085   abuf->written = written;
1086 #undef FLD
1087 }
1088   NEXT (vpc);
1089
1090   CASE (sem, INSN_DIVU) : /* divu $dr,$sr */
1091 {
1092   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1093   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1094 #define FLD(f) abuf->fields.sfmt_add.f
1095   int UNUSED written = 0;
1096   IADDR UNUSED pc = abuf->addr;
1097   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1098
1099 if (NESI (* FLD (i_sr), 0)) {
1100   {
1101     SI opval = UDIVSI (* FLD (i_dr), * FLD (i_sr));
1102     * FLD (i_dr) = opval;
1103     written |= (1 << 2);
1104     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1105   }
1106 }
1107
1108   abuf->written = written;
1109 #undef FLD
1110 }
1111   NEXT (vpc);
1112
1113   CASE (sem, INSN_REM) : /* rem $dr,$sr */
1114 {
1115   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1116   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1117 #define FLD(f) abuf->fields.sfmt_add.f
1118   int UNUSED written = 0;
1119   IADDR UNUSED pc = abuf->addr;
1120   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1121
1122 if (NESI (* FLD (i_sr), 0)) {
1123   {
1124     SI opval = MODSI (* FLD (i_dr), * FLD (i_sr));
1125     * FLD (i_dr) = opval;
1126     written |= (1 << 2);
1127     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1128   }
1129 }
1130
1131   abuf->written = written;
1132 #undef FLD
1133 }
1134   NEXT (vpc);
1135
1136   CASE (sem, INSN_REMU) : /* remu $dr,$sr */
1137 {
1138   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1139   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1140 #define FLD(f) abuf->fields.sfmt_add.f
1141   int UNUSED written = 0;
1142   IADDR UNUSED pc = abuf->addr;
1143   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1144
1145 if (NESI (* FLD (i_sr), 0)) {
1146   {
1147     SI opval = UMODSI (* FLD (i_dr), * FLD (i_sr));
1148     * FLD (i_dr) = opval;
1149     written |= (1 << 2);
1150     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1151   }
1152 }
1153
1154   abuf->written = written;
1155 #undef FLD
1156 }
1157   NEXT (vpc);
1158
1159   CASE (sem, INSN_JL) : /* jl $sr */
1160 {
1161   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1162   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1163 #define FLD(f) abuf->fields.sfmt_jl.f
1164   int UNUSED written = 0;
1165   IADDR UNUSED pc = abuf->addr;
1166   SEM_BRANCH_INIT
1167   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1168
1169 {
1170   SI temp0;USI temp1;
1171   temp0 = ADDSI (ANDSI (pc, -4), 4);
1172   temp1 = ANDSI (* FLD (i_sr), -4);
1173   {
1174     SI opval = temp0;
1175     CPU (h_gr[((UINT) 14)]) = opval;
1176     TRACE_RESULT (current_cpu, abuf, "gr-14", 'x', opval);
1177   }
1178   {
1179     USI opval = temp1;
1180     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
1181     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
1182   }
1183 }
1184
1185   SEM_BRANCH_FINI (vpc);
1186 #undef FLD
1187 }
1188   NEXT (vpc);
1189
1190   CASE (sem, INSN_JMP) : /* jmp $sr */
1191 {
1192   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1193   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1194 #define FLD(f) abuf->fields.sfmt_mvtc.f
1195   int UNUSED written = 0;
1196   IADDR UNUSED pc = abuf->addr;
1197   SEM_BRANCH_INIT
1198   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1199
1200   {
1201     USI opval = ANDSI (* FLD (i_sr), -4);
1202     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
1203     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
1204   }
1205
1206   SEM_BRANCH_FINI (vpc);
1207 #undef FLD
1208 }
1209   NEXT (vpc);
1210
1211   CASE (sem, INSN_LD) : /* ld $dr,@$sr */
1212 {
1213   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1214   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1215 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1216   int UNUSED written = 0;
1217   IADDR UNUSED pc = abuf->addr;
1218   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1219
1220   {
1221     SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
1222     * FLD (i_dr) = opval;
1223     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1224   }
1225
1226 #undef FLD
1227 }
1228   NEXT (vpc);
1229
1230   CASE (sem, INSN_LD_D) : /* ld $dr,@($slo16,$sr) */
1231 {
1232   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1233   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1234 #define FLD(f) abuf->fields.sfmt_add3.f
1235   int UNUSED written = 0;
1236   IADDR UNUSED pc = abuf->addr;
1237   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1238
1239   {
1240     SI opval = GETMEMSI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)));
1241     * FLD (i_dr) = opval;
1242     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1243   }
1244
1245 #undef FLD
1246 }
1247   NEXT (vpc);
1248
1249   CASE (sem, INSN_LDB) : /* ldb $dr,@$sr */
1250 {
1251   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1252   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1253 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1254   int UNUSED written = 0;
1255   IADDR UNUSED pc = abuf->addr;
1256   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1257
1258   {
1259     SI opval = EXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));
1260     * FLD (i_dr) = opval;
1261     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1262   }
1263
1264 #undef FLD
1265 }
1266   NEXT (vpc);
1267
1268   CASE (sem, INSN_LDB_D) : /* ldb $dr,@($slo16,$sr) */
1269 {
1270   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1271   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1272 #define FLD(f) abuf->fields.sfmt_add3.f
1273   int UNUSED written = 0;
1274   IADDR UNUSED pc = abuf->addr;
1275   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1276
1277   {
1278     SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
1279     * FLD (i_dr) = opval;
1280     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1281   }
1282
1283 #undef FLD
1284 }
1285   NEXT (vpc);
1286
1287   CASE (sem, INSN_LDH) : /* ldh $dr,@$sr */
1288 {
1289   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1290   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1291 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1292   int UNUSED written = 0;
1293   IADDR UNUSED pc = abuf->addr;
1294   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1295
1296   {
1297     SI opval = EXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));
1298     * FLD (i_dr) = opval;
1299     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1300   }
1301
1302 #undef FLD
1303 }
1304   NEXT (vpc);
1305
1306   CASE (sem, INSN_LDH_D) : /* ldh $dr,@($slo16,$sr) */
1307 {
1308   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1309   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1310 #define FLD(f) abuf->fields.sfmt_add3.f
1311   int UNUSED written = 0;
1312   IADDR UNUSED pc = abuf->addr;
1313   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1314
1315   {
1316     SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
1317     * FLD (i_dr) = opval;
1318     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1319   }
1320
1321 #undef FLD
1322 }
1323   NEXT (vpc);
1324
1325   CASE (sem, INSN_LDUB) : /* ldub $dr,@$sr */
1326 {
1327   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1328   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1329 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1330   int UNUSED written = 0;
1331   IADDR UNUSED pc = abuf->addr;
1332   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1333
1334   {
1335     SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));
1336     * FLD (i_dr) = opval;
1337     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1338   }
1339
1340 #undef FLD
1341 }
1342   NEXT (vpc);
1343
1344   CASE (sem, INSN_LDUB_D) : /* ldub $dr,@($slo16,$sr) */
1345 {
1346   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1347   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1348 #define FLD(f) abuf->fields.sfmt_add3.f
1349   int UNUSED written = 0;
1350   IADDR UNUSED pc = abuf->addr;
1351   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1352
1353   {
1354     SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
1355     * FLD (i_dr) = opval;
1356     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1357   }
1358
1359 #undef FLD
1360 }
1361   NEXT (vpc);
1362
1363   CASE (sem, INSN_LDUH) : /* lduh $dr,@$sr */
1364 {
1365   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1366   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1367 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1368   int UNUSED written = 0;
1369   IADDR UNUSED pc = abuf->addr;
1370   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1371
1372   {
1373     SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));
1374     * FLD (i_dr) = opval;
1375     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1376   }
1377
1378 #undef FLD
1379 }
1380   NEXT (vpc);
1381
1382   CASE (sem, INSN_LDUH_D) : /* lduh $dr,@($slo16,$sr) */
1383 {
1384   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1385   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1386 #define FLD(f) abuf->fields.sfmt_add3.f
1387   int UNUSED written = 0;
1388   IADDR UNUSED pc = abuf->addr;
1389   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1390
1391   {
1392     SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
1393     * FLD (i_dr) = opval;
1394     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1395   }
1396
1397 #undef FLD
1398 }
1399   NEXT (vpc);
1400
1401   CASE (sem, INSN_LD_PLUS) : /* ld $dr,@$sr+ */
1402 {
1403   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1404   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1405 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1406   int UNUSED written = 0;
1407   IADDR UNUSED pc = abuf->addr;
1408   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1409
1410 {
1411   SI temp0;SI temp1;
1412   temp0 = GETMEMSI (current_cpu, pc, * FLD (i_sr));
1413   temp1 = ADDSI (* FLD (i_sr), 4);
1414   {
1415     SI opval = temp0;
1416     * FLD (i_dr) = opval;
1417     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1418   }
1419   {
1420     SI opval = temp1;
1421     * FLD (i_sr) = opval;
1422     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
1423   }
1424 }
1425
1426 #undef FLD
1427 }
1428   NEXT (vpc);
1429
1430   CASE (sem, INSN_LD24) : /* ld24 $dr,$uimm24 */
1431 {
1432   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1433   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1434 #define FLD(f) abuf->fields.sfmt_ld24.f
1435   int UNUSED written = 0;
1436   IADDR UNUSED pc = abuf->addr;
1437   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1438
1439   {
1440     SI opval = FLD (i_uimm24);
1441     * FLD (i_dr) = opval;
1442     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1443   }
1444
1445 #undef FLD
1446 }
1447   NEXT (vpc);
1448
1449   CASE (sem, INSN_LDI8) : /* ldi8 $dr,$simm8 */
1450 {
1451   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1452   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1453 #define FLD(f) abuf->fields.sfmt_addi.f
1454   int UNUSED written = 0;
1455   IADDR UNUSED pc = abuf->addr;
1456   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1457
1458   {
1459     SI opval = FLD (f_simm8);
1460     * FLD (i_dr) = opval;
1461     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1462   }
1463
1464 #undef FLD
1465 }
1466   NEXT (vpc);
1467
1468   CASE (sem, INSN_LDI16) : /* ldi16 $dr,$hash$slo16 */
1469 {
1470   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1471   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1472 #define FLD(f) abuf->fields.sfmt_add3.f
1473   int UNUSED written = 0;
1474   IADDR UNUSED pc = abuf->addr;
1475   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1476
1477   {
1478     SI opval = FLD (f_simm16);
1479     * FLD (i_dr) = opval;
1480     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1481   }
1482
1483 #undef FLD
1484 }
1485   NEXT (vpc);
1486
1487   CASE (sem, INSN_LOCK) : /* lock $dr,@$sr */
1488 {
1489   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1490   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1491 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1492   int UNUSED written = 0;
1493   IADDR UNUSED pc = abuf->addr;
1494   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1495
1496 {
1497   {
1498     BI opval = 1;
1499     CPU (h_lock) = opval;
1500     TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval);
1501   }
1502   {
1503     SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
1504     * FLD (i_dr) = opval;
1505     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1506   }
1507 }
1508
1509 #undef FLD
1510 }
1511   NEXT (vpc);
1512
1513   CASE (sem, INSN_MACHI) : /* machi $src1,$src2 */
1514 {
1515   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1516   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1517 #define FLD(f) abuf->fields.sfmt_st_plus.f
1518   int UNUSED written = 0;
1519   IADDR UNUSED pc = abuf->addr;
1520   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1521
1522   {
1523     DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUM (), MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))), 8), 8);
1524     SET_H_ACCUM (opval);
1525     TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1526   }
1527
1528 #undef FLD
1529 }
1530   NEXT (vpc);
1531
1532   CASE (sem, INSN_MACLO) : /* maclo $src1,$src2 */
1533 {
1534   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1535   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1536 #define FLD(f) abuf->fields.sfmt_st_plus.f
1537   int UNUSED written = 0;
1538   IADDR UNUSED pc = abuf->addr;
1539   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1540
1541   {
1542     DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUM (), MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))), 8), 8);
1543     SET_H_ACCUM (opval);
1544     TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1545   }
1546
1547 #undef FLD
1548 }
1549   NEXT (vpc);
1550
1551   CASE (sem, INSN_MACWHI) : /* macwhi $src1,$src2 */
1552 {
1553   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1554   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1555 #define FLD(f) abuf->fields.sfmt_st_plus.f
1556   int UNUSED written = 0;
1557   IADDR UNUSED pc = abuf->addr;
1558   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1559
1560   {
1561     DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUM (), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))), 8), 8);
1562     SET_H_ACCUM (opval);
1563     TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1564   }
1565
1566 #undef FLD
1567 }
1568   NEXT (vpc);
1569
1570   CASE (sem, INSN_MACWLO) : /* macwlo $src1,$src2 */
1571 {
1572   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1573   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1574 #define FLD(f) abuf->fields.sfmt_st_plus.f
1575   int UNUSED written = 0;
1576   IADDR UNUSED pc = abuf->addr;
1577   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1578
1579   {
1580     DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUM (), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))), 8), 8);
1581     SET_H_ACCUM (opval);
1582     TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1583   }
1584
1585 #undef FLD
1586 }
1587   NEXT (vpc);
1588
1589   CASE (sem, INSN_MUL) : /* mul $dr,$sr */
1590 {
1591   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1592   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1593 #define FLD(f) abuf->fields.sfmt_add.f
1594   int UNUSED written = 0;
1595   IADDR UNUSED pc = abuf->addr;
1596   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1597
1598   {
1599     SI opval = MULSI (* FLD (i_dr), * FLD (i_sr));
1600     * FLD (i_dr) = opval;
1601     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1602   }
1603
1604 #undef FLD
1605 }
1606   NEXT (vpc);
1607
1608   CASE (sem, INSN_MULHI) : /* mulhi $src1,$src2 */
1609 {
1610   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1611   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1612 #define FLD(f) abuf->fields.sfmt_st_plus.f
1613   int UNUSED written = 0;
1614   IADDR UNUSED pc = abuf->addr;
1615   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1616
1617   {
1618     DI opval = SRADI (SLLDI (MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))), 16), 16);
1619     SET_H_ACCUM (opval);
1620     TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1621   }
1622
1623 #undef FLD
1624 }
1625   NEXT (vpc);
1626
1627   CASE (sem, INSN_MULLO) : /* mullo $src1,$src2 */
1628 {
1629   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1630   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1631 #define FLD(f) abuf->fields.sfmt_st_plus.f
1632   int UNUSED written = 0;
1633   IADDR UNUSED pc = abuf->addr;
1634   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1635
1636   {
1637     DI opval = SRADI (SLLDI (MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 16), 16);
1638     SET_H_ACCUM (opval);
1639     TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1640   }
1641
1642 #undef FLD
1643 }
1644   NEXT (vpc);
1645
1646   CASE (sem, INSN_MULWHI) : /* mulwhi $src1,$src2 */
1647 {
1648   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1649   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1650 #define FLD(f) abuf->fields.sfmt_st_plus.f
1651   int UNUSED written = 0;
1652   IADDR UNUSED pc = abuf->addr;
1653   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1654
1655   {
1656     DI opval = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))), 8), 8);
1657     SET_H_ACCUM (opval);
1658     TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1659   }
1660
1661 #undef FLD
1662 }
1663   NEXT (vpc);
1664
1665   CASE (sem, INSN_MULWLO) : /* mulwlo $src1,$src2 */
1666 {
1667   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1668   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1669 #define FLD(f) abuf->fields.sfmt_st_plus.f
1670   int UNUSED written = 0;
1671   IADDR UNUSED pc = abuf->addr;
1672   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1673
1674   {
1675     DI opval = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 8), 8);
1676     SET_H_ACCUM (opval);
1677     TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1678   }
1679
1680 #undef FLD
1681 }
1682   NEXT (vpc);
1683
1684   CASE (sem, INSN_MV) : /* mv $dr,$sr */
1685 {
1686   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1687   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1688 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1689   int UNUSED written = 0;
1690   IADDR UNUSED pc = abuf->addr;
1691   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1692
1693   {
1694     SI opval = * FLD (i_sr);
1695     * FLD (i_dr) = opval;
1696     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1697   }
1698
1699 #undef FLD
1700 }
1701   NEXT (vpc);
1702
1703   CASE (sem, INSN_MVFACHI) : /* mvfachi $dr */
1704 {
1705   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1706   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1707 #define FLD(f) abuf->fields.sfmt_seth.f
1708   int UNUSED written = 0;
1709   IADDR UNUSED pc = abuf->addr;
1710   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1711
1712   {
1713     SI opval = TRUNCDISI (SRADI (GET_H_ACCUM (), 32));
1714     * FLD (i_dr) = opval;
1715     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1716   }
1717
1718 #undef FLD
1719 }
1720   NEXT (vpc);
1721
1722   CASE (sem, INSN_MVFACLO) : /* mvfaclo $dr */
1723 {
1724   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1725   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1726 #define FLD(f) abuf->fields.sfmt_seth.f
1727   int UNUSED written = 0;
1728   IADDR UNUSED pc = abuf->addr;
1729   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1730
1731   {
1732     SI opval = TRUNCDISI (GET_H_ACCUM ());
1733     * FLD (i_dr) = opval;
1734     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1735   }
1736
1737 #undef FLD
1738 }
1739   NEXT (vpc);
1740
1741   CASE (sem, INSN_MVFACMI) : /* mvfacmi $dr */
1742 {
1743   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1744   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1745 #define FLD(f) abuf->fields.sfmt_seth.f
1746   int UNUSED written = 0;
1747   IADDR UNUSED pc = abuf->addr;
1748   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1749
1750   {
1751     SI opval = TRUNCDISI (SRADI (GET_H_ACCUM (), 16));
1752     * FLD (i_dr) = opval;
1753     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1754   }
1755
1756 #undef FLD
1757 }
1758   NEXT (vpc);
1759
1760   CASE (sem, INSN_MVFC) : /* mvfc $dr,$scr */
1761 {
1762   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1763   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1764 #define FLD(f) abuf->fields.sfmt_mvfc.f
1765   int UNUSED written = 0;
1766   IADDR UNUSED pc = abuf->addr;
1767   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1768
1769   {
1770     SI opval = GET_H_CR (FLD (f_r2));
1771     * FLD (i_dr) = opval;
1772     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1773   }
1774
1775 #undef FLD
1776 }
1777   NEXT (vpc);
1778
1779   CASE (sem, INSN_MVTACHI) : /* mvtachi $src1 */
1780 {
1781   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1782   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1783 #define FLD(f) abuf->fields.sfmt_st_plus.f
1784   int UNUSED written = 0;
1785   IADDR UNUSED pc = abuf->addr;
1786   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1787
1788   {
1789     DI opval = ORDI (ANDDI (GET_H_ACCUM (), MAKEDI (0, 0xffffffff)), SLLDI (EXTSIDI (* FLD (i_src1)), 32));
1790     SET_H_ACCUM (opval);
1791     TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1792   }
1793
1794 #undef FLD
1795 }
1796   NEXT (vpc);
1797
1798   CASE (sem, INSN_MVTACLO) : /* mvtaclo $src1 */
1799 {
1800   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1801   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1802 #define FLD(f) abuf->fields.sfmt_st_plus.f
1803   int UNUSED written = 0;
1804   IADDR UNUSED pc = abuf->addr;
1805   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1806
1807   {
1808     DI opval = ORDI (ANDDI (GET_H_ACCUM (), MAKEDI (0xffffffff, 0)), ZEXTSIDI (* FLD (i_src1)));
1809     SET_H_ACCUM (opval);
1810     TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1811   }
1812
1813 #undef FLD
1814 }
1815   NEXT (vpc);
1816
1817   CASE (sem, INSN_MVTC) : /* mvtc $sr,$dcr */
1818 {
1819   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1820   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1821 #define FLD(f) abuf->fields.sfmt_mvtc.f
1822   int UNUSED written = 0;
1823   IADDR UNUSED pc = abuf->addr;
1824   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1825
1826   {
1827     USI opval = * FLD (i_sr);
1828     SET_H_CR (FLD (f_r1), opval);
1829     TRACE_RESULT (current_cpu, abuf, "dcr", 'x', opval);
1830   }
1831
1832 #undef FLD
1833 }
1834   NEXT (vpc);
1835
1836   CASE (sem, INSN_NEG) : /* neg $dr,$sr */
1837 {
1838   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1839   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1840 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1841   int UNUSED written = 0;
1842   IADDR UNUSED pc = abuf->addr;
1843   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1844
1845   {
1846     SI opval = NEGSI (* FLD (i_sr));
1847     * FLD (i_dr) = opval;
1848     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1849   }
1850
1851 #undef FLD
1852 }
1853   NEXT (vpc);
1854
1855   CASE (sem, INSN_NOP) : /* nop */
1856 {
1857   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1858   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1859 #define FLD(f) abuf->fields.fmt_empty.f
1860   int UNUSED written = 0;
1861   IADDR UNUSED pc = abuf->addr;
1862   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1863
1864 PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);
1865
1866 #undef FLD
1867 }
1868   NEXT (vpc);
1869
1870   CASE (sem, INSN_NOT) : /* not $dr,$sr */
1871 {
1872   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1873   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1874 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1875   int UNUSED written = 0;
1876   IADDR UNUSED pc = abuf->addr;
1877   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1878
1879   {
1880     SI opval = INVSI (* FLD (i_sr));
1881     * FLD (i_dr) = opval;
1882     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1883   }
1884
1885 #undef FLD
1886 }
1887   NEXT (vpc);
1888
1889   CASE (sem, INSN_RAC) : /* rac */
1890 {
1891   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1892   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1893 #define FLD(f) abuf->fields.fmt_empty.f
1894   int UNUSED written = 0;
1895   IADDR UNUSED pc = abuf->addr;
1896   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1897
1898 {
1899   DI tmp_tmp1;
1900   tmp_tmp1 = SLLDI (GET_H_ACCUM (), 1);
1901   tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 32768));
1902   {
1903     DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0xffff0000))) ? (MAKEDI (32767, 0xffff0000)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0xffff0000)));
1904     SET_H_ACCUM (opval);
1905     TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1906   }
1907 }
1908
1909 #undef FLD
1910 }
1911   NEXT (vpc);
1912
1913   CASE (sem, INSN_RACH) : /* rach */
1914 {
1915   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1916   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1917 #define FLD(f) abuf->fields.fmt_empty.f
1918   int UNUSED written = 0;
1919   IADDR UNUSED pc = abuf->addr;
1920   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1921
1922 {
1923   DI tmp_tmp1;
1924   tmp_tmp1 = ANDDI (GET_H_ACCUM (), MAKEDI (16777215, 0xffffffff));
1925 if (ANDIF (GEDI (tmp_tmp1, MAKEDI (16383, 0x80000000)), LEDI (tmp_tmp1, MAKEDI (8388607, 0xffffffff)))) {
1926   tmp_tmp1 = MAKEDI (16383, 0x80000000);
1927 } else {
1928 if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (16760832, 0)))) {
1929   tmp_tmp1 = MAKEDI (16760832, 0);
1930 } else {
1931   tmp_tmp1 = ANDDI (ADDDI (GET_H_ACCUM (), MAKEDI (0, 1073741824)), MAKEDI (0xffffffff, 0x80000000));
1932 }
1933 }
1934   tmp_tmp1 = SLLDI (tmp_tmp1, 1);
1935   {
1936     DI opval = SRADI (SLLDI (tmp_tmp1, 7), 7);
1937     SET_H_ACCUM (opval);
1938     TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1939   }
1940 }
1941
1942 #undef FLD
1943 }
1944   NEXT (vpc);
1945
1946   CASE (sem, INSN_RTE) : /* rte */
1947 {
1948   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1949   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1950 #define FLD(f) abuf->fields.fmt_empty.f
1951   int UNUSED written = 0;
1952   IADDR UNUSED pc = abuf->addr;
1953   SEM_BRANCH_INIT
1954   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1955
1956 {
1957   {
1958     USI opval = ANDSI (GET_H_CR (((UINT) 6)), -4);
1959     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
1960     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
1961   }
1962   {
1963     USI opval = GET_H_CR (((UINT) 14));
1964     SET_H_CR (((UINT) 6), opval);
1965     TRACE_RESULT (current_cpu, abuf, "cr-6", 'x', opval);
1966   }
1967   {
1968     UQI opval = CPU (h_bpsw);
1969     SET_H_PSW (opval);
1970     TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval);
1971   }
1972   {
1973     UQI opval = CPU (h_bbpsw);
1974     CPU (h_bpsw) = opval;
1975     TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval);
1976   }
1977 }
1978
1979   SEM_BRANCH_FINI (vpc);
1980 #undef FLD
1981 }
1982   NEXT (vpc);
1983
1984   CASE (sem, INSN_SETH) : /* seth $dr,$hash$hi16 */
1985 {
1986   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1987   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1988 #define FLD(f) abuf->fields.sfmt_seth.f
1989   int UNUSED written = 0;
1990   IADDR UNUSED pc = abuf->addr;
1991   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1992
1993   {
1994     SI opval = SLLSI (FLD (f_hi16), 16);
1995     * FLD (i_dr) = opval;
1996     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1997   }
1998
1999 #undef FLD
2000 }
2001   NEXT (vpc);
2002
2003   CASE (sem, INSN_SLL) : /* sll $dr,$sr */
2004 {
2005   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2006   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2007 #define FLD(f) abuf->fields.sfmt_add.f
2008   int UNUSED written = 0;
2009   IADDR UNUSED pc = abuf->addr;
2010   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2011
2012   {
2013     SI opval = SLLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
2014     * FLD (i_dr) = opval;
2015     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
2016   }
2017
2018 #undef FLD
2019 }
2020   NEXT (vpc);
2021
2022   CASE (sem, INSN_SLL3) : /* sll3 $dr,$sr,$simm16 */
2023 {
2024   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2025   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2026 #define FLD(f) abuf->fields.sfmt_add3.f
2027   int UNUSED written = 0;
2028   IADDR UNUSED pc = abuf->addr;
2029   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2030
2031   {
2032     SI opval = SLLSI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
2033     * FLD (i_dr) = opval;
2034     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
2035   }
2036
2037 #undef FLD
2038 }
2039   NEXT (vpc);
2040
2041   CASE (sem, INSN_SLLI) : /* slli $dr,$uimm5 */
2042 {
2043   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2044   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2045 #define FLD(f) abuf->fields.sfmt_slli.f
2046   int UNUSED written = 0;
2047   IADDR UNUSED pc = abuf->addr;
2048   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2049
2050   {
2051     SI opval = SLLSI (* FLD (i_dr), FLD (f_uimm5));
2052     * FLD (i_dr) = opval;
2053     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
2054   }
2055
2056 #undef FLD
2057 }
2058   NEXT (vpc);
2059
2060   CASE (sem, INSN_SRA) : /* sra $dr,$sr */
2061 {
2062   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2063   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2064 #define FLD(f) abuf->fields.sfmt_add.f
2065   int UNUSED written = 0;
2066   IADDR UNUSED pc = abuf->addr;
2067   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2068
2069   {
2070     SI opval = SRASI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
2071     * FLD (i_dr) = opval;
2072     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
2073   }
2074
2075 #undef FLD
2076 }
2077   NEXT (vpc);
2078
2079   CASE (sem, INSN_SRA3) : /* sra3 $dr,$sr,$simm16 */
2080 {
2081   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2082   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2083 #define FLD(f) abuf->fields.sfmt_add3.f
2084   int UNUSED written = 0;
2085   IADDR UNUSED pc = abuf->addr;
2086   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2087
2088   {
2089     SI opval = SRASI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
2090     * FLD (i_dr) = opval;
2091     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
2092   }
2093
2094 #undef FLD
2095 }
2096   NEXT (vpc);
2097
2098   CASE (sem, INSN_SRAI) : /* srai $dr,$uimm5 */
2099 {
2100   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2101   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2102 #define FLD(f) abuf->fields.sfmt_slli.f
2103   int UNUSED written = 0;
2104   IADDR UNUSED pc = abuf->addr;
2105   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2106
2107   {
2108     SI opval = SRASI (* FLD (i_dr), FLD (f_uimm5));
2109     * FLD (i_dr) = opval;
2110     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
2111   }
2112
2113 #undef FLD
2114 }
2115   NEXT (vpc);
2116
2117   CASE (sem, INSN_SRL) : /* srl $dr,$sr */
2118 {
2119   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2120   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2121 #define FLD(f) abuf->fields.sfmt_add.f
2122   int UNUSED written = 0;
2123   IADDR UNUSED pc = abuf->addr;
2124   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2125
2126   {
2127     SI opval = SRLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
2128     * FLD (i_dr) = opval;
2129     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
2130   }
2131
2132 #undef FLD
2133 }
2134   NEXT (vpc);
2135
2136   CASE (sem, INSN_SRL3) : /* srl3 $dr,$sr,$simm16 */
2137 {
2138   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2139   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2140 #define FLD(f) abuf->fields.sfmt_add3.f
2141   int UNUSED written = 0;
2142   IADDR UNUSED pc = abuf->addr;
2143   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2144
2145   {
2146     SI opval = SRLSI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
2147     * FLD (i_dr) = opval;
2148     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
2149   }
2150
2151 #undef FLD
2152 }
2153   NEXT (vpc);
2154
2155   CASE (sem, INSN_SRLI) : /* srli $dr,$uimm5 */
2156 {
2157   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2158   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2159 #define FLD(f) abuf->fields.sfmt_slli.f
2160   int UNUSED written = 0;
2161   IADDR UNUSED pc = abuf->addr;
2162   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2163
2164   {
2165     SI opval = SRLSI (* FLD (i_dr), FLD (f_uimm5));
2166     * FLD (i_dr) = opval;
2167     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
2168   }
2169
2170 #undef FLD
2171 }
2172   NEXT (vpc);
2173
2174   CASE (sem, INSN_ST) : /* st $src1,@$src2 */
2175 {
2176   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2177   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2178 #define FLD(f) abuf->fields.sfmt_st_plus.f
2179   int UNUSED written = 0;
2180   IADDR UNUSED pc = abuf->addr;
2181   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2182
2183   {
2184     SI opval = * FLD (i_src1);
2185     SETMEMSI (current_cpu, pc, * FLD (i_src2), opval);
2186     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2187   }
2188
2189 #undef FLD
2190 }
2191   NEXT (vpc);
2192
2193   CASE (sem, INSN_ST_D) : /* st $src1,@($slo16,$src2) */
2194 {
2195   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2196   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2197 #define FLD(f) abuf->fields.sfmt_st_d.f
2198   int UNUSED written = 0;
2199   IADDR UNUSED pc = abuf->addr;
2200   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2201
2202   {
2203     SI opval = * FLD (i_src1);
2204     SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
2205     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2206   }
2207
2208 #undef FLD
2209 }
2210   NEXT (vpc);
2211
2212   CASE (sem, INSN_STB) : /* stb $src1,@$src2 */
2213 {
2214   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2215   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2216 #define FLD(f) abuf->fields.sfmt_st_plus.f
2217   int UNUSED written = 0;
2218   IADDR UNUSED pc = abuf->addr;
2219   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2220
2221   {
2222     QI opval = * FLD (i_src1);
2223     SETMEMQI (current_cpu, pc, * FLD (i_src2), opval);
2224     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2225   }
2226
2227 #undef FLD
2228 }
2229   NEXT (vpc);
2230
2231   CASE (sem, INSN_STB_D) : /* stb $src1,@($slo16,$src2) */
2232 {
2233   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2234   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2235 #define FLD(f) abuf->fields.sfmt_st_d.f
2236   int UNUSED written = 0;
2237   IADDR UNUSED pc = abuf->addr;
2238   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2239
2240   {
2241     QI opval = * FLD (i_src1);
2242     SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
2243     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2244   }
2245
2246 #undef FLD
2247 }
2248   NEXT (vpc);
2249
2250   CASE (sem, INSN_STH) : /* sth $src1,@$src2 */
2251 {
2252   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2253   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2254 #define FLD(f) abuf->fields.sfmt_st_plus.f
2255   int UNUSED written = 0;
2256   IADDR UNUSED pc = abuf->addr;
2257   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2258
2259   {
2260     HI opval = * FLD (i_src1);
2261     SETMEMHI (current_cpu, pc, * FLD (i_src2), opval);
2262     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2263   }
2264
2265 #undef FLD
2266 }
2267   NEXT (vpc);
2268
2269   CASE (sem, INSN_STH_D) : /* sth $src1,@($slo16,$src2) */
2270 {
2271   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2272   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2273 #define FLD(f) abuf->fields.sfmt_st_d.f
2274   int UNUSED written = 0;
2275   IADDR UNUSED pc = abuf->addr;
2276   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2277
2278   {
2279     HI opval = * FLD (i_src1);
2280     SETMEMHI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
2281     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2282   }
2283
2284 #undef FLD
2285 }
2286   NEXT (vpc);
2287
2288   CASE (sem, INSN_ST_PLUS) : /* st $src1,@+$src2 */
2289 {
2290   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2291   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2292 #define FLD(f) abuf->fields.sfmt_st_plus.f
2293   int UNUSED written = 0;
2294   IADDR UNUSED pc = abuf->addr;
2295   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2296
2297 {
2298   SI tmp_new_src2;
2299   tmp_new_src2 = ADDSI (* FLD (i_src2), 4);
2300   {
2301     SI opval = * FLD (i_src1);
2302     SETMEMSI (current_cpu, pc, tmp_new_src2, opval);
2303     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2304   }
2305   {
2306     SI opval = tmp_new_src2;
2307     * FLD (i_src2) = opval;
2308     TRACE_RESULT (current_cpu, abuf, "src2", 'x', opval);
2309   }
2310 }
2311
2312 #undef FLD
2313 }
2314   NEXT (vpc);
2315
2316   CASE (sem, INSN_ST_MINUS) : /* st $src1,@-$src2 */
2317 {
2318   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2319   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2320 #define FLD(f) abuf->fields.sfmt_st_plus.f
2321   int UNUSED written = 0;
2322   IADDR UNUSED pc = abuf->addr;
2323   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2324
2325 {
2326   SI tmp_new_src2;
2327   tmp_new_src2 = SUBSI (* FLD (i_src2), 4);
2328   {
2329     SI opval = * FLD (i_src1);
2330     SETMEMSI (current_cpu, pc, tmp_new_src2, opval);
2331     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2332   }
2333   {
2334     SI opval = tmp_new_src2;
2335     * FLD (i_src2) = opval;
2336     TRACE_RESULT (current_cpu, abuf, "src2", 'x', opval);
2337   }
2338 }
2339
2340 #undef FLD
2341 }
2342   NEXT (vpc);
2343
2344   CASE (sem, INSN_SUB) : /* sub $dr,$sr */
2345 {
2346   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2347   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2348 #define FLD(f) abuf->fields.sfmt_add.f
2349   int UNUSED written = 0;
2350   IADDR UNUSED pc = abuf->addr;
2351   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2352
2353   {
2354     SI opval = SUBSI (* FLD (i_dr), * FLD (i_sr));
2355     * FLD (i_dr) = opval;
2356     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
2357   }
2358
2359 #undef FLD
2360 }
2361   NEXT (vpc);
2362
2363   CASE (sem, INSN_SUBV) : /* subv $dr,$sr */
2364 {
2365   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2366   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2367 #define FLD(f) abuf->fields.sfmt_add.f
2368   int UNUSED written = 0;
2369   IADDR UNUSED pc = abuf->addr;
2370   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2371
2372 {
2373   SI temp0;BI temp1;
2374   temp0 = SUBSI (* FLD (i_dr), * FLD (i_sr));
2375   temp1 = SUBOFSI (* FLD (i_dr), * FLD (i_sr), 0);
2376   {
2377     SI opval = temp0;
2378     * FLD (i_dr) = opval;
2379     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
2380   }
2381   {
2382     BI opval = temp1;
2383     CPU (h_cond) = opval;
2384     TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
2385   }
2386 }
2387
2388 #undef FLD
2389 }
2390   NEXT (vpc);
2391
2392   CASE (sem, INSN_SUBX) : /* subx $dr,$sr */
2393 {
2394   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2395   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2396 #define FLD(f) abuf->fields.sfmt_add.f
2397   int UNUSED written = 0;
2398   IADDR UNUSED pc = abuf->addr;
2399   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2400
2401 {
2402   SI temp0;BI temp1;
2403   temp0 = SUBCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
2404   temp1 = SUBCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
2405   {
2406     SI opval = temp0;
2407     * FLD (i_dr) = opval;
2408     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
2409   }
2410   {
2411     BI opval = temp1;
2412     CPU (h_cond) = opval;
2413     TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
2414   }
2415 }
2416
2417 #undef FLD
2418 }
2419   NEXT (vpc);
2420
2421   CASE (sem, INSN_TRAP) : /* trap $uimm4 */
2422 {
2423   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2424   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2425 #define FLD(f) abuf->fields.sfmt_trap.f
2426   int UNUSED written = 0;
2427   IADDR UNUSED pc = abuf->addr;
2428   SEM_BRANCH_INIT
2429   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2430
2431 {
2432   {
2433     USI opval = GET_H_CR (((UINT) 6));
2434     SET_H_CR (((UINT) 14), opval);
2435     TRACE_RESULT (current_cpu, abuf, "cr-14", 'x', opval);
2436   }
2437   {
2438     USI opval = ADDSI (pc, 4);
2439     SET_H_CR (((UINT) 6), opval);
2440     TRACE_RESULT (current_cpu, abuf, "cr-6", 'x', opval);
2441   }
2442   {
2443     UQI opval = CPU (h_bpsw);
2444     CPU (h_bbpsw) = opval;
2445     TRACE_RESULT (current_cpu, abuf, "bbpsw", 'x', opval);
2446   }
2447   {
2448     UQI opval = GET_H_PSW ();
2449     CPU (h_bpsw) = opval;
2450     TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval);
2451   }
2452   {
2453     UQI opval = ANDQI (GET_H_PSW (), 128);
2454     SET_H_PSW (opval);
2455     TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval);
2456   }
2457   {
2458     SI opval = m32r_trap (current_cpu, pc, FLD (f_uimm4));
2459     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
2460     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
2461   }
2462 }
2463
2464   SEM_BRANCH_FINI (vpc);
2465 #undef FLD
2466 }
2467   NEXT (vpc);
2468
2469   CASE (sem, INSN_UNLOCK) : /* unlock $src1,@$src2 */
2470 {
2471   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2472   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2473 #define FLD(f) abuf->fields.sfmt_st_plus.f
2474   int UNUSED written = 0;
2475   IADDR UNUSED pc = abuf->addr;
2476   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2477
2478 {
2479 if (CPU (h_lock)) {
2480   {
2481     SI opval = * FLD (i_src1);
2482     SETMEMSI (current_cpu, pc, * FLD (i_src2), opval);
2483     written |= (1 << 4);
2484     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2485   }
2486 }
2487   {
2488     BI opval = 0;
2489     CPU (h_lock) = opval;
2490     TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval);
2491   }
2492 }
2493
2494   abuf->written = written;
2495 #undef FLD
2496 }
2497   NEXT (vpc);
2498
2499
2500     }
2501   ENDSWITCH (sem) /* End of semantic switch.  */
2502
2503   /* At this point `vpc' contains the next insn to execute.  */
2504 }
2505
2506 #undef DEFINE_SWITCH
2507 #endif /* DEFINE_SWITCH */