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1 ; Fujitsu FR30 CPU description. -*- Scheme -*-
2 ; Copyright 2011 Free Software Foundation, Inc.
3 ;
4 ; Contributed by Red Hat Inc;
5 ;
6 ; This file is part of the GNU Binutils.
7 ;
8 ; This program is free software; you can redistribute it and/or modify
9 ; it under the terms of the GNU General Public License as published by
10 ; the Free Software Foundation; either version 3 of the License, or
11 ; (at your option) any later version.
12 ;
13 ; This program is distributed in the hope that it will be useful,
14 ; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ; GNU General Public License for more details.
17 ;
18 ; You should have received a copy of the GNU General Public License
19 ; along with this program; if not, write to the Free Software
20 ; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 ; MA 02110-1301, USA.
23 (define-rtl-version 0 8)
25 (include "simplify.inc")
27 ; define-arch must appear first
29 (define-arch
30 (name fr30) ; name of cpu family
31 (comment "Fujitsu FR30")
32 (default-alignment forced)
33 (insn-lsb0? #f)
34 (machs fr30)
35 (isas fr30)
36 )
38 (define-isa
39 (name fr30)
40 (base-insn-bitsize 16)
41 (decode-assist (0 1 2 3 4 5 6 7)) ; Initial bitnumbers to decode insns by.
42 (liw-insns 1) ; The fr30 fetches 1 insn at a time.
43 (parallel-insns 1) ; The fr30 executes 1 insn at a time.
44 )
46 (define-cpu
47 ; cpu names must be distinct from the architecture name and machine names.
48 ; The "b" suffix stands for "base" and is the convention.
49 ; The "f" suffix stands for "family" and is the convention.
50 (name fr30bf)
51 (comment "Fujitsu FR30 base family")
52 (endian big)
53 (word-bitsize 32)
54 )
56 (define-mach
57 (name fr30)
58 (comment "Generic FR30 cpu")
59 (cpu fr30bf)
60 )
61 \f
62 ; Model descriptions.
63 ;
64 (define-model
65 (name fr30-1) (comment "fr30-1") (attrs)
66 (mach fr30)
68 (pipeline all "" () ((fetch) (decode) (execute) (writeback)))
70 ; `state' is a list of variables for recording model state
71 (state
72 ; bit mask of h-gr registers loaded from memory by previous insn
73 (load-regs UINT)
74 ; bit mask of h-gr registers loaded from memory by current insn
75 (load-regs-pending UINT)
76 )
78 (unit u-exec "Execution Unit" ()
79 1 1 ; issue done
80 () ; state
81 ((Ri INT -1) (Rj INT -1)) ; inputs
82 ((Ri INT -1)) ; outputs
83 () ; profile action (default)
84 )
85 (unit u-cti "Branch Unit" ()
86 1 1 ; issue done
87 () ; state
88 ((Ri INT -1)) ; inputs
89 ((pc)) ; outputs
90 () ; profile action (default)
91 )
92 (unit u-load "Memory Load Unit" ()
93 1 1 ; issue done
94 () ; state
95 ((Rj INT -1)
96 ;(ld-mem AI)
97 ) ; inputs
98 ((Ri INT -1)) ; outputs
99 () ; profile action (default)
100 )
101 (unit u-store "Memory Store Unit" ()
102 1 1 ; issue done
103 () ; state
104 ((Ri INT -1) (Rj INT -1)) ; inputs
105 () ; ((st-mem AI)) ; outputs
106 () ; profile action (default)
107 )
108 (unit u-ldm "LDM Memory Load Unit" ()
109 1 1 ; issue done
110 () ; state
111 ((reglist INT)) ; inputs
112 () ; outputs
113 () ; profile action (default)
114 )
115 (unit u-stm "STM Memory Store Unit" ()
116 1 1 ; issue done
117 () ; state
118 ((reglist INT)) ; inputs
119 () ; outputs
120 () ; profile action (default)
121 )
122 )
123 \f
124 ; The instruction fetch/execute cycle.
125 ;
126 ; This is how to fetch and decode an instruction.
127 ; Leave it out for now
129 ; (define-extract (const SI 0))
131 ; This is how to execute a decoded instruction.
132 ; Leave it out for now
134 ; (define-execute (const SI 0))
135 \f
136 ; Instruction fields.
137 ;
138 ; Attributes:
139 ; PCREL-ADDR: pc relative value (for reloc and disassembly purposes)
140 ; ABS-ADDR: absolute address (for reloc and disassembly purposes?)
141 ; RESERVED: bits are not used to decode insn, must be all 0
143 (dnf f-op1 "1st 4 bits of opcode" () 0 4)
144 (dnf f-op2 "2nd 4 bits of opcode" () 4 4)
145 (dnf f-op3 "3rd 4 bits of opcode" () 8 4)
146 (dnf f-op4 "4th 4 bits of opcode" () 12 4)
147 (dnf f-op5 "5th bit of opcode" () 4 1)
148 (dnf f-cc "condition code" () 4 4)
149 (dnf f-ccc "coprocessor calc code" () 16 8)
150 (dnf f-Rj "register Rj" () 8 4)
151 (dnf f-Ri "register Ri" () 12 4)
152 (dnf f-Rs1 "register Rs" () 8 4)
153 (dnf f-Rs2 "register Rs" () 12 4)
154 (dnf f-Rjc "register Rj" () 24 4)
155 (dnf f-Ric "register Ri" () 28 4)
156 (dnf f-CRj "coprocessor register" () 24 4)
157 (dnf f-CRi "coprocessor register" () 28 4)
158 (dnf f-u4 "4 bit 0 extended" () 8 4)
159 (dnf f-u4c "4 bit 0 extended" () 12 4)
160 (df f-i4 "4 bit sign extended" () 8 4 INT #f #f)
161 (df f-m4 "4 bit minus extended" () 8 4 UINT
162 ; ??? This field takes a value in the range [-16,-1] but there
163 ; doesn't seem a way to tell CGEN that. Use an unsigned field and
164 ; disable range checks on insertion by masking. Restore the sign
165 ; on extraction. CGEN generated documentation for insns that use
166 ; this field will be wrong.
167 ((value pc) (and WI value (const #xf)))
168 ((value pc) (or WI value (const -16)))
169 )
170 (dnf f-u8 "8 bit unsigned" () 8 8)
171 (dnf f-i8 "8 bit unsigned" () 4 8)
173 (dnf f-i20-4 "upper 4 bits of i20" () 8 4)
174 (dnf f-i20-16 "lower 16 bits of i20" () 16 16)
175 (dnmf f-i20 "20 bit unsigned" () UINT
176 (f-i20-4 f-i20-16)
177 (sequence () ; insert
178 (set (ifield f-i20-4) (srl (ifield f-i20) (const 16)))
179 (set (ifield f-i20-16) (and (ifield f-i20) (const #xffff)))
180 )
181 (sequence () ; extract
182 (set (ifield f-i20) (or (sll (ifield f-i20-4) (const 16))
183 (ifield f-i20-16)))
184 )
185 )
187 (dnf f-i32 "32 bit immediate" (SIGN-OPT) 16 32)
189 (df f-udisp6 "6 bit unsigned offset" () 8 4 UINT
190 ((value pc) (srl UWI value (const 2)))
191 ((value pc) (sll UWI value (const 2)))
192 )
193 (df f-disp8 "8 bit signed offset" () 4 8 INT #f #f)
194 (df f-disp9 "9 bit signed offset" () 4 8 INT
195 ((value pc) (sra WI value (const 1)))
196 ((value pc) (sll WI value (const 1)))
197 )
198 (df f-disp10 "10 bit signed offset" () 4 8 INT
199 ((value pc) (sra WI value (const 2)))
200 ((value pc) (sll WI value (const 2)))
201 )
202 (df f-s10 "10 bit signed offset" () 8 8 INT
203 ((value pc) (sra WI value (const 2)))
204 ((value pc) (sll WI value (const 2)))
205 )
206 (df f-u10 "10 bit unsigned offset" () 8 8 UINT
207 ((value pc) (srl UWI value (const 2)))
208 ((value pc) (sll UWI value (const 2)))
209 )
210 (df f-rel9 "9 pc relative signed offset" (PCREL-ADDR) 8 8 INT
211 ((value pc) (sra WI (sub WI value (add WI pc (const 2))) (const 1)))
212 ((value pc) (add WI (sll WI value (const 1)) (add WI pc (const 2))))
213 )
214 (dnf f-dir8 "8 bit direct address" () 8 8)
215 (df f-dir9 "9 bit direct address" () 8 8 UINT
216 ((value pc) (srl UWI value (const 1)))
217 ((value pc) (sll UWI value (const 1)))
218 )
219 (df f-dir10 "10 bit direct address" () 8 8 UINT
220 ((value pc) (srl UWI value (const 2)))
221 ((value pc) (sll UWI value (const 2)))
222 )
223 (df f-rel12 "12 bit pc relative signed offset" (PCREL-ADDR) 5 11 INT
224 ((value pc) (sra WI (sub WI value (add WI pc (const 2))) (const 1)))
225 ((value pc) (add WI (sll WI value (const 1)) (add WI pc (const 2))))
226 )
228 (dnf f-reglist_hi_st "8 bit register mask for stm" () 8 8)
229 (dnf f-reglist_low_st "8 bit register mask for stm" () 8 8)
230 (dnf f-reglist_hi_ld "8 bit register mask for ldm" () 8 8)
231 (dnf f-reglist_low_ld "8 bit register mask for ldm" () 8 8)
232 \f
233 ; Enums.
235 ; insn-op1: bits 0-3
236 ; FIXME: should use die macro or some such
237 (define-normal-insn-enum insn-op1 "insn op1 enums" () OP1_ f-op1
238 ("0" "1" "2" "3" "4" "5" "6" "7"
239 "8" "9" "A" "B" "C" "D" "E" "F")
240 )
242 ; insn-op2: bits 4-7
243 ; FIXME: should use die macro or some such
244 (define-normal-insn-enum insn-op2 "insn op2 enums" () OP2_ f-op2
245 ("0" "1" "2" "3" "4" "5" "6" "7"
246 "8" "9" "A" "B" "C" "D" "E" "F")
247 )
249 ; insn-op3: bits 8-11
250 ; FIXME: should use die macro or some such
251 (define-normal-insn-enum insn-op3 "insn op3 enums" () OP3_ f-op3
252 ("0" "1" "2" "3" "4" "5" "6" "7"
253 "8" "9" "A" "B" "C" "D" "E" "F")
254 )
256 ; insn-op4: bits 12-15
257 ; FIXME: should use die macro or some such
258 (define-normal-insn-enum insn-op4 "insn op4 enums" () OP4_ f-op4
259 ("0")
260 )
262 ; insn-op5: bit 4 (5th bit origin 0)
263 ; FIXME: should use die macro or some such
264 (define-normal-insn-enum insn-op5 "insn op5 enums" () OP5_ f-op5
265 ("0" "1")
266 )
268 ; insn-cc: condition codes
269 ; FIXME: should use die macro or some such
270 (define-normal-insn-enum insn-cc "insn cc enums" () CC_ f-cc
271 ("ra" "no" "eq" "ne" "c" "nc" "n" "p" "v" "nv" "lt" "ge" "le" "gt" "ls" "hi")
272 )
273 \f
274 ; Hardware pieces.
275 ; These entries list the elements of the raw hardware.
276 ; They're also used to provide tables and other elements of the assembly
277 ; language.
279 (dnh h-pc "program counter" (PC PROFILE) (pc) () () ())
281 (define-keyword
282 (name gr-names)
283 (enum-prefix H-GR-)
284 (values (r0 0) (r1 1) (r2 2) (r3 3) (r4 4) (r5 5) (r6 6) (r7 7)
285 (r8 8) (r9 9) (r10 10) (r11 11) (r12 12) (r13 13) (r14 14) (r15 15)
286 (ac 13) (fp 14) (sp 15))
287 )
289 (define-hardware
290 (name h-gr)
291 (comment "general registers")
292 (attrs PROFILE CACHE-ADDR)
293 (type register WI (16))
294 (indices extern-keyword gr-names)
295 )
297 (define-keyword
298 (name cr-names)
299 (enum-prefix H-CR-)
300 (values (cr0 0) (cr1 1) (cr2 2) (cr3 3)
301 (cr4 4) (cr5 5) (cr6 6) (cr7 7)
302 (cr8 8) (cr9 9) (cr10 10) (cr11 11)
303 (cr12 12) (cr13 13) (cr14 14) (cr15 15))
304 )
306 (define-hardware
307 (name h-cr)
308 (comment "coprocessor registers")
309 (attrs)
310 (type register WI (16))
311 (indices extern-keyword cr-names)
312 )
314 (define-keyword
315 (name dr-names)
316 (enum-prefix H-DR-)
317 (values (tbr 0) (rp 1) (ssp 2) (usp 3) (mdh 4) (mdl 5))
318 )
320 (define-hardware
321 (name h-dr)
322 (comment "dedicated registers")
323 (type register WI (6))
324 (indices extern-keyword dr-names)
325 (get (index) (c-call WI "@cpu@_h_dr_get_handler" index))
326 (set (index newval) (c-call VOID "@cpu@_h_dr_set_handler" index newval))
327 )
329 (define-hardware
330 (name h-ps)
331 (comment "processor status")
332 (type register UWI)
333 (indices keyword "" ((ps 0)))
334 (get () (c-call UWI "@cpu@_h_ps_get_handler"))
335 (set (newval) (c-call VOID "@cpu@_h_ps_set_handler" newval))
336 )
338 (dnh h-r13 "General Register 13 explicitly required"
339 ()
340 (register WI)
341 (keyword "" ((r13 0)))
342 () ()
343 )
345 (dnh h-r14 "General Register 14 explicitly required"
346 ()
347 (register WI)
348 (keyword "" ((r14 0)))
349 () ()
350 )
352 (dnh h-r15 "General Register 15 explicitly required"
353 ()
354 (register WI)
355 (keyword "" ((r15 0)))
356 () ()
357 )
359 ; These bits are actually part of the PS register but are accessed more
360 ; often than the entire register, so define them directly. We can assemble
361 ; the PS register from its components when necessary.
363 (dsh h-nbit "negative bit" () (register BI))
364 (dsh h-zbit "zero bit" () (register BI))
365 (dsh h-vbit "overflow bit" () (register BI))
366 (dsh h-cbit "carry bit" () (register BI))
367 (dsh h-ibit "interrupt enable bit" () (register BI))
368 (define-hardware
369 (name h-sbit)
370 (comment "stack bit")
371 (type register BI)
372 (get () (c-call BI "@cpu@_h_sbit_get_handler"))
373 (set (newval) (c-call VOID "@cpu@_h_sbit_set_handler" newval))
374 )
375 (dsh h-tbit "trace trap bit" () (register BI))
376 (dsh h-d0bit "division 0 bit" () (register BI))
377 (dsh h-d1bit "division 1 bit" () (register BI))
379 ; These represent sub-registers within the program status register
381 (define-hardware
382 (name h-ccr)
383 (comment "condition code bits")
384 (type register UQI)
385 (get () (c-call UQI "@cpu@_h_ccr_get_handler"))
386 (set (newval) (c-call VOID "@cpu@_h_ccr_set_handler" newval))
387 )
388 (define-hardware
389 (name h-scr)
390 (comment "system condition bits")
391 (type register UQI)
392 (get () (c-call UQI "@cpu@_h_scr_get_handler"))
393 (set (newval) (c-call VOID "@cpu@_h_scr_set_handler" newval))
394 )
395 (define-hardware
396 (name h-ilm)
397 (comment "interrupt level mask")
398 (type register UQI)
399 (get () (c-call UQI "@cpu@_h_ilm_get_handler"))
400 (set (newval) (c-call VOID "@cpu@_h_ilm_set_handler" newval))
401 )
402 \f
403 ; Instruction Operands.
404 ; These entries provide a layer between the assembler and the raw hardware
405 ; description, and are used to refer to hardware elements in the semantic
406 ; code. Usually there's a bit of over-specification, but in more complicated
407 ; instruction sets there isn't.
409 ; FR30 specific operand attributes:
411 (define-attr
412 (for operand)
413 (type boolean)
414 (name HASH-PREFIX)
415 (comment "immediates have an optional '#' prefix")
416 )
418 ; ??? Convention says this should be o-sr, but then the insn definitions
419 ; should refer to o-sr which is clumsy. The "o-" could be implicit, but
420 ; then it should be implicit for all the symbols here, but then there would
421 ; be confusion between (f-)simm8 and (h-)simm8.
422 ; So for now the rule is exactly as it appears here.
424 (dnop Ri "destination register" () h-gr f-Ri)
425 (dnop Rj "source register" () h-gr f-Rj)
426 (dnop Ric "target register coproc insn" () h-gr f-Ric)
427 (dnop Rjc "source register coproc insn" () h-gr f-Rjc)
428 (dnop CRi "coprocessor register" () h-cr f-CRi)
429 (dnop CRj "coprocessor register" () h-cr f-CRj)
430 (dnop Rs1 "dedicated register" () h-dr f-Rs1)
431 (dnop Rs2 "dedicated register" () h-dr f-Rs2)
432 (dnop R13 "General Register 13" () h-r13 f-nil)
433 (dnop R14 "General Register 14" () h-r14 f-nil)
434 (dnop R15 "General Register 15" () h-r15 f-nil)
435 (dnop ps "Program Status register" () h-ps f-nil)
436 (dnop u4 "4 bit unsigned immediate" (HASH-PREFIX) h-uint f-u4)
437 (dnop u4c "4 bit unsigned immediate" (HASH-PREFIX) h-uint f-u4c)
438 (dnop u8 "8 bit unsigned immediate" (HASH-PREFIX) h-uint f-u8)
439 (dnop i8 "8 bit unsigned immediate" (HASH-PREFIX) h-uint f-i8)
440 (dnop udisp6 "6 bit unsigned immediate" (HASH-PREFIX) h-uint f-udisp6)
441 (dnop disp8 "8 bit signed immediate" (HASH-PREFIX) h-sint f-disp8)
442 (dnop disp9 "9 bit signed immediate" (HASH-PREFIX) h-sint f-disp9)
443 (dnop disp10 "10 bit signed immediate" (HASH-PREFIX) h-sint f-disp10)
445 (dnop s10 "10 bit signed immediate" (HASH-PREFIX) h-sint f-s10)
446 (dnop u10 "10 bit unsigned immediate" (HASH-PREFIX) h-uint f-u10)
447 (dnop i32 "32 bit immediate" (HASH-PREFIX) h-uint f-i32)
449 (define-operand
450 (name m4)
451 (comment "4 bit negative immediate")
452 (attrs HASH-PREFIX)
453 (type h-sint)
454 (index f-m4)
455 (handlers (print "m4"))
456 )
458 (define-operand
459 (name i20)
460 (comment "20 bit immediate")
461 (attrs HASH-PREFIX)
462 (type h-uint)
463 (index f-i20)
464 )
466 (dnop dir8 "8 bit direct address" () h-uint f-dir8)
467 (dnop dir9 "9 bit direct address" () h-uint f-dir9)
468 (dnop dir10 "10 bit direct address" () h-uint f-dir10)
470 (dnop label9 "9 bit pc relative address" () h-iaddr f-rel9)
471 (dnop label12 "12 bit pc relative address" () h-iaddr f-rel12)
473 (define-operand
474 (name reglist_low_ld)
475 (comment "8 bit low register mask for ldm")
476 (attrs)
477 (type h-uint)
478 (index f-reglist_low_ld)
479 (handlers (parse "low_register_list_ld")
480 (print "low_register_list_ld"))
481 )
483 (define-operand
484 (name reglist_hi_ld)
485 (comment "8 bit high register mask for ldm")
486 (attrs)
487 (type h-uint)
488 (index f-reglist_hi_ld)
489 (handlers (parse "hi_register_list_ld")
490 (print "hi_register_list_ld"))
491 )
493 (define-operand
494 (name reglist_low_st)
495 (comment "8 bit low register mask for stm")
496 (attrs)
497 (type h-uint)
498 (index f-reglist_low_st)
499 (handlers (parse "low_register_list_st")
500 (print "low_register_list_st"))
501 )
503 (define-operand
504 (name reglist_hi_st)
505 (comment "8 bit high register mask for stm")
506 (attrs)
507 (type h-uint)
508 (index f-reglist_hi_st)
509 (handlers (parse "hi_register_list_st")
510 (print "hi_register_list_st"))
511 )
513 (dnop cc "condition codes" () h-uint f-cc)
514 (dnop ccc "coprocessor calc" (HASH-PREFIX) h-uint f-ccc)
516 (dnop nbit "negative bit" (SEM-ONLY) h-nbit f-nil)
517 (dnop vbit "overflow bit" (SEM-ONLY) h-vbit f-nil)
518 (dnop zbit "zero bit" (SEM-ONLY) h-zbit f-nil)
519 (dnop cbit "carry bit" (SEM-ONLY) h-cbit f-nil)
520 (dnop ibit "interrupt bit" (SEM-ONLY) h-ibit f-nil)
521 (dnop sbit "stack bit" (SEM-ONLY) h-sbit f-nil)
522 (dnop tbit "trace trap bit" (SEM-ONLY) h-tbit f-nil)
523 (dnop d0bit "division 0 bit" (SEM-ONLY) h-d0bit f-nil)
524 (dnop d1bit "division 1 bit" (SEM-ONLY) h-d1bit f-nil)
526 (dnop ccr "condition code bits" (SEM-ONLY) h-ccr f-nil)
527 (dnop scr "system condition bits" (SEM-ONLY) h-scr f-nil)
528 (dnop ilm "interrupt level mask" (SEM-ONLY) h-ilm f-nil)
529 \f
530 ; Instruction definitions.
531 ;
532 ; Notes:
533 ; - dni is short for "define-normal-instruction"
535 ; FR30 specific insn attributes:
537 (define-attr
538 (for insn)
539 (type boolean)
540 (name NOT-IN-DELAY-SLOT)
541 (comment "insn can't go in delay slot")
542 )
544 ; Sets zbit and nbit based on the value of x
545 ;
546 (define-pmacro (set-z-and-n x)
547 (sequence ()
548 (set zbit (eq x (const 0)))
549 (set nbit (lt x (const 0))))
550 )
552 ; Binary integer instruction which sets status bits
553 ;
554 (define-pmacro (binary-int-op name insn comment opc1 opc2 op arg1 arg2)
555 (dni name
556 (.str insn " " comment)
557 ()
558 (.str insn " $" arg1 ",$" arg2)
559 (+ opc1 opc2 arg1 arg2)
560 (sequence ()
561 (set vbit ((.sym op -oflag) arg2 arg1 (const 0)))
562 (set cbit ((.sym op -cflag) arg2 arg1 (const 0)))
563 (set arg2 (op arg2 arg1))
564 (set-z-and-n arg2))
565 ()
566 )
567 )
569 ; Binary integer instruction which does *not* set status bits
570 ;
571 (define-pmacro (binary-int-op-n name insn comment opc1 opc2 op arg1 arg2)
572 (dni name
573 (.str insn " " comment)
574 ()
575 (.str insn " $" arg1 ",$" arg2)
576 (+ opc1 opc2 arg1 arg2)
577 (set arg2 (op arg2 arg1))
578 ()
579 )
580 )
582 ; Binary integer instruction with carry which sets status bits
583 ;
584 (define-pmacro (binary-int-op-c name insn comment opc1 opc2 op arg1 arg2)
585 (dni name
586 (.str insn " " comment)
587 ()
588 (.str insn " $" arg1 ",$" arg2)
589 (+ opc1 opc2 arg1 arg2)
590 (sequence ((WI tmp))
591 (set tmp ((.sym op c) arg2 arg1 cbit))
592 (set vbit ((.sym op -oflag) arg2 arg1 cbit))
593 (set cbit ((.sym op -cflag) arg2 arg1 cbit))
594 (set arg2 tmp)
595 (set-z-and-n arg2))
596 ()
597 )
598 )
600 (binary-int-op add add "reg/reg" OP1_A OP2_6 add Rj Ri)
601 (binary-int-op addi add "immed/reg" OP1_A OP2_4 add u4 Ri)
602 (binary-int-op add2 add2 "immed/reg" OP1_A OP2_5 add m4 Ri)
603 (binary-int-op-c addc addc "reg/reg" OP1_A OP2_7 add Rj Ri)
604 (binary-int-op-n addn addn "reg/reg" OP1_A OP2_2 add Rj Ri)
605 (binary-int-op-n addni addn "immed/reg" OP1_A OP2_0 add u4 Ri)
606 (binary-int-op-n addn2 addn2 "immed/reg" OP1_A OP2_1 add m4 Ri)
608 (binary-int-op sub sub "reg/reg" OP1_A OP2_C sub Rj Ri)
609 (binary-int-op-c subc subc "reg/reg" OP1_A OP2_D sub Rj Ri)
610 (binary-int-op-n subn subn "reg/reg" OP1_A OP2_E sub Rj Ri)
612 ; Integer compare instruction
613 ;
614 (define-pmacro (int-cmp name insn comment opc1 opc2 arg1 arg2)
615 (dni name
616 (.str insn " " comment)
617 ()
618 (.str insn " $" arg1 ",$" arg2)
619 (+ opc1 opc2 arg1 arg2)
620 (sequence ((WI tmp1))
621 (set vbit (sub-oflag arg2 arg1 (const 0)))
622 (set cbit (sub-cflag arg2 arg1 (const 0)))
623 (set tmp1 (sub arg2 arg1))
624 (set-z-and-n tmp1)
625 )
626 ()
627 )
628 )
630 (int-cmp cmp cmp "reg/reg" OP1_A OP2_A Rj Ri)
631 (int-cmp cmpi cmp "immed/reg" OP1_A OP2_8 u4 Ri)
632 (int-cmp cmp2 cmp2 "immed/reg" OP1_A OP2_9 m4 Ri)
634 ; Binary logical instruction
635 ;
636 (define-pmacro (binary-logical-op name insn comment opc1 opc2 op arg1 arg2)
637 (dni name
638 (.str insn " " comment)
639 ()
640 (.str insn " $" arg1 ",$" arg2)
641 (+ opc1 opc2 arg1 arg2)
642 (sequence ()
643 (set arg2 (op arg2 arg1))
644 (set-z-and-n arg2))
645 ()
646 )
647 )
649 (binary-logical-op and and "reg/reg" OP1_8 OP2_2 and Rj Ri)
650 (binary-logical-op or or "reg/reg" OP1_9 OP2_2 or Rj Ri)
651 (binary-logical-op eor eor "reg/reg" OP1_9 OP2_A xor Rj Ri)
653 (define-pmacro (les-units model) ; les: load-exec-store
654 (model (unit u-exec) (unit u-load) (unit u-store))
655 )
657 ; Binary logical instruction to memory
658 ;
659 (define-pmacro (binary-logical-op-m name insn comment opc1 opc2 mode op arg1 arg2)
660 (dni name
661 (.str insn " " comment)
662 (NOT-IN-DELAY-SLOT)
663 (.str insn " $" arg1 ",@$" arg2)
664 (+ opc1 opc2 arg1 arg2)
665 (sequence ((mode tmp))
666 (set mode tmp (op mode (mem mode arg2) arg1))
667 (set-z-and-n tmp)
668 (set mode (mem mode arg2) tmp))
669 ((les-units fr30-1))
670 )
671 )
673 (binary-logical-op-m andm and "reg/mem" OP1_8 OP2_4 WI and Rj Ri)
674 (binary-logical-op-m andh andh "reg/mem" OP1_8 OP2_5 HI and Rj Ri)
675 (binary-logical-op-m andb andb "reg/mem" OP1_8 OP2_6 QI and Rj Ri)
676 (binary-logical-op-m orm or "reg/mem" OP1_9 OP2_4 WI or Rj Ri)
677 (binary-logical-op-m orh orh "reg/mem" OP1_9 OP2_5 HI or Rj Ri)
678 (binary-logical-op-m orb orb "reg/mem" OP1_9 OP2_6 QI or Rj Ri)
679 (binary-logical-op-m eorm eor "reg/mem" OP1_9 OP2_C WI xor Rj Ri)
680 (binary-logical-op-m eorh eorh "reg/mem" OP1_9 OP2_D HI xor Rj Ri)
681 (binary-logical-op-m eorb eorb "reg/mem" OP1_9 OP2_E QI xor Rj Ri)
683 ; Binary logical instruction to low half of byte in memory
684 ;
685 (dni bandl
686 "bandl #u4,@Ri"
687 (NOT-IN-DELAY-SLOT)
688 "bandl $u4,@$Ri"
689 (+ OP1_8 OP2_0 u4 Ri)
690 (set QI (mem QI Ri)
691 (and QI
692 (or QI u4 (const #xf0))
693 (mem QI Ri)))
694 ((les-units fr30-1))
695 )
697 (dni borl
698 "borl #u4,@Ri"
699 (NOT-IN-DELAY-SLOT)
700 "borl $u4,@$Ri"
701 (+ OP1_9 OP2_0 u4 Ri)
702 (set QI (mem QI Ri) (or QI u4 (mem QI Ri)))
703 ((les-units fr30-1))
704 )
706 (dni beorl
707 "beorl #u4,@Ri"
708 (NOT-IN-DELAY-SLOT)
709 "beorl $u4,@$Ri"
710 (+ OP1_9 OP2_8 u4 Ri)
711 (set QI (mem QI Ri) (xor QI u4 (mem QI Ri)))
712 ((les-units fr30-1))
713 )
715 ; Binary logical instruction to high half of byte in memory
716 ;
717 (dni bandh
718 "bandh #u4,@Ri"
719 (NOT-IN-DELAY-SLOT)
720 "bandh $u4,@$Ri"
721 (+ OP1_8 OP2_1 u4 Ri)
722 (set QI (mem QI Ri)
723 (and QI
724 (or QI (sll QI u4 (const 4)) (const #x0f))
725 (mem QI Ri)))
726 ((les-units fr30-1))
727 )
729 (define-pmacro (binary-or-op-mh name insn opc1 opc2 op arg1 arg2)
730 (dni name
731 (.str name " #" arg1 ",@" args)
732 (NOT-IN-DELAY-SLOT)
733 (.str name " $" arg1 ",@$" arg2)
734 (+ opc1 opc2 arg1 arg2)
735 (set QI (mem QI arg2)
736 (insn QI
737 (sll QI arg1 (const 4))
738 (mem QI arg2)))
739 ((les-units fr30-1))
740 )
741 )
743 (binary-or-op-mh borh or OP1_9 OP2_1 or u4 Ri)
744 (binary-or-op-mh beorh xor OP1_9 OP2_9 xor u4 Ri)
746 (dni btstl
747 "btstl #u4,@Ri"
748 (NOT-IN-DELAY-SLOT)
749 "btstl $u4,@$Ri"
750 (+ OP1_8 OP2_8 u4 Ri)
751 (sequence ((QI tmp))
752 (set tmp (and QI u4 (mem QI Ri)))
753 (set zbit (eq tmp (const 0)))
754 (set nbit (const 0)))
755 ((fr30-1 (unit u-load) (unit u-exec (cycles 2))))
756 )
758 (dni btsth
759 "btsth #u4,@Ri"
760 (NOT-IN-DELAY-SLOT)
761 "btsth $u4,@$Ri"
762 (+ OP1_8 OP2_9 u4 Ri)
763 (sequence ((QI tmp))
764 (set tmp (and QI (sll QI u4 (const 4)) (mem QI Ri)))
765 (set zbit (eq tmp (const 0)))
766 (set nbit (lt tmp (const 0))))
767 ((fr30-1 (unit u-load) (unit u-exec (cycles 2))))
768 )
770 (dni mul
771 "mul Rj,Ri"
772 (NOT-IN-DELAY-SLOT)
773 "mul $Rj,$Ri"
774 (+ OP1_A OP2_F Rj Ri)
775 (sequence ((DI tmp))
776 (set tmp (mul DI (ext DI Rj) (ext DI Ri)))
777 (set (reg h-dr 5) (trunc WI tmp))
778 (set (reg h-dr 4) (trunc WI (srl tmp (const 32))))
779 (set nbit (lt (reg h-dr 5) (const 0)))
780 (set zbit (eq tmp (const DI 0)))
781 (set vbit (orif
782 (gt tmp (const DI #x7fffffff))
783 (lt tmp (neg (const DI #x80000000))))))
784 ((fr30-1 (unit u-exec (cycles 5))))
785 )
787 (dni mulu
788 "mulu Rj,Ri"
789 (NOT-IN-DELAY-SLOT)
790 "mulu $Rj,$Ri"
791 (+ OP1_A OP2_B Rj Ri)
792 (sequence ((DI tmp))
793 (set tmp (mul DI (zext DI Rj) (zext DI Ri)))
794 (set (reg h-dr 5) (trunc WI tmp))
795 (set (reg h-dr 4) (trunc WI (srl tmp (const 32))))
796 (set nbit (lt (reg h-dr 4) (const 0)))
797 (set zbit (eq (reg h-dr 5) (const 0)))
798 (set vbit (ne (reg h-dr 4) (const 0))))
799 ((fr30-1 (unit u-exec (cycles 5))))
800 )
802 (dni mulh
803 "mulh Rj,Ri"
804 (NOT-IN-DELAY-SLOT)
805 "mulh $Rj,$Ri"
806 (+ OP1_B OP2_F Rj Ri)
807 (sequence ()
808 (set (reg h-dr 5) (mul (trunc HI Rj) (trunc HI Ri)))
809 (set nbit (lt (reg h-dr 5) (const 0)))
810 (set zbit (ge (reg h-dr 5) (const 0))))
811 ((fr30-1 (unit u-exec (cycles 3))))
812 )
814 (dni muluh
815 "muluh Rj,Ri"
816 (NOT-IN-DELAY-SLOT)
817 "muluh $Rj,$Ri"
818 (+ OP1_B OP2_B Rj Ri)
819 (sequence ()
820 (set (reg h-dr 5) (mul (and Rj (const #xffff))
821 (and Ri (const #xffff))))
822 (set nbit (lt (reg h-dr 5) (const 0)))
823 (set zbit (ge (reg h-dr 5) (const 0))))
824 ((fr30-1 (unit u-exec (cycles 3))))
825 )
827 (dni div0s
828 "div0s Ri"
829 ()
830 "div0s $Ri"
831 (+ OP1_9 OP2_7 OP3_4 Ri)
832 (sequence ()
833 (set d0bit (lt (reg h-dr 5) (const 0)))
834 (set d1bit (xor d0bit (lt Ri (const 0))))
835 (if (ne d0bit (const 0))
836 (set (reg h-dr 4) (const #xffffffff))
837 (set (reg h-dr 4) (const 0))))
838 ()
839 )
841 (dni div0u
842 "div0u Ri"
843 ()
844 "div0u $Ri"
845 (+ OP1_9 OP2_7 OP3_5 Ri)
846 (sequence ()
847 (set d0bit (const 0))
848 (set d1bit (const 0))
849 (set (reg h-dr 4) (const 0)))
850 ()
851 )
853 (dni div1
854 "div1 Ri"
855 ()
856 "div1 $Ri"
857 (+ OP1_9 OP2_7 OP3_6 Ri)
858 (sequence ((WI tmp))
859 (set (reg h-dr 4) (sll (reg h-dr 4) (const 1)))
860 (if (lt (reg h-dr 5) (const 0))
861 (set (reg h-dr 4) (add (reg h-dr 4) (const 1))))
862 (set (reg h-dr 5) (sll (reg h-dr 5) (const 1)))
863 (if (eq d1bit (const 1))
864 (sequence ()
865 (set tmp (add (reg h-dr 4) Ri))
866 (set cbit (add-cflag (reg h-dr 4) Ri (const 0))))
867 (sequence ()
868 (set tmp (sub (reg h-dr 4) Ri))
869 (set cbit (sub-cflag (reg h-dr 4) Ri (const 0)))))
870 (if (not (xor (xor d0bit d1bit) cbit))
871 (sequence ()
872 (set (reg h-dr 4) tmp)
873 (set (reg h-dr 5) (or (reg h-dr 5) (const 1)))))
874 (set zbit (eq (reg h-dr 4) (const 0))))
875 ()
876 )
878 (dni div2
879 "div2 Ri"
880 ()
881 "div2 $Ri"
882 (+ OP1_9 OP2_7 OP3_7 Ri)
883 (sequence ((WI tmp))
884 (if (eq d1bit (const 1))
885 (sequence ()
886 (set tmp (add (reg h-dr 4) Ri))
887 (set cbit (add-cflag (reg h-dr 4) Ri (const 0))))
888 (sequence ()
889 (set tmp (sub (reg h-dr 4) Ri))
890 (set cbit (sub-cflag (reg h-dr 4) Ri (const 0)))))
891 (if (eq tmp (const 0))
892 (sequence ()
893 (set zbit (const 1))
894 (set (reg h-dr 4) (const 0)))
895 (set zbit (const 0))))
896 ()
897 )
899 (dni div3
900 "div3"
901 ()
902 "div3"
903 (+ OP1_9 OP2_F OP3_6 OP4_0)
904 (if (eq zbit (const 1))
905 (set (reg h-dr 5) (add (reg h-dr 5) (const 1))))
906 ()
907 )
909 (dni div4s
910 "div4s"
911 ()
912 "div4s"
913 (+ OP1_9 OP2_F OP3_7 OP4_0)
914 (if (eq d1bit (const 1))
915 (set (reg h-dr 5) (neg (reg h-dr 5))))
916 ()
917 )
919 (define-pmacro (leftshift-op name insn opc1 opc2 arg1 arg2 shift-expr)
920 (dni name
921 (.str insn " " arg1 "," arg2)
922 ()
923 (.str insn " $" arg1 ",$" arg2)
924 (+ opc1 opc2 arg1 arg2)
925 (sequence ((WI shift))
926 (set shift shift-expr)
927 (if (ne shift (const 0))
928 (sequence ()
929 (set cbit (ne (and arg2
930 (sll (const 1)
931 (sub (const 32) shift)))
932 (const 0)))
933 (set arg2 (sll arg2 shift)))
934 (set cbit (const 0)))
935 (set nbit (lt arg2 (const 0)))
936 (set zbit (eq arg2 (const 0))))
937 ()
938 )
939 )
940 (leftshift-op lsl lsl OP1_B OP2_6 Rj Ri (and Rj (const #x1f)))
941 (leftshift-op lsli lsl OP1_B OP2_4 u4 Ri u4)
942 (leftshift-op lsl2 lsl2 OP1_B OP2_5 u4 Ri (add u4 (const #x10)))
944 (define-pmacro (rightshift-op name insn opc1 opc2 op arg1 arg2 shift-expr)
945 (dni name
946 (.str insn " " arg1 "," arg2)
947 ()
948 (.str insn " $" arg1 ",$" arg2)
949 (+ opc1 opc2 arg1 arg2)
950 (sequence ((WI shift))
951 (set shift shift-expr)
952 (if (ne shift (const 0))
953 (sequence ()
954 (set cbit (ne (and arg2
955 (sll (const 1)
956 (sub shift (const 1))))
957 (const 0)))
958 (set arg2 (op arg2 shift)))
959 (set cbit (const 0)))
960 (set nbit (lt arg2 (const 0)))
961 (set zbit (eq arg2 (const 0))))
962 ()
963 )
964 )
965 (rightshift-op lsr lsr OP1_B OP2_2 srl Rj Ri (and Rj (const #x1f)))
966 (rightshift-op lsri lsr OP1_B OP2_0 srl u4 Ri u4)
967 (rightshift-op lsr2 lsr2 OP1_B OP2_1 srl u4 Ri (add u4 (const #x10)))
968 (rightshift-op asr asr OP1_B OP2_A sra Rj Ri (and Rj (const #x1f)))
969 (rightshift-op asri asr OP1_B OP2_8 sra u4 Ri u4)
970 (rightshift-op asr2 asr2 OP1_B OP2_9 sra u4 Ri (add u4 (const #x10)))
972 (dni ldi8
973 "load 8 bit unsigned immediate"
974 ()
975 "ldi:8 $i8,$Ri"
976 (+ OP1_C i8 Ri)
977 (set Ri i8)
978 ()
979 )
981 ; Typing ldi:8 in in emacs is a pain.
982 (dnmi ldi8m "ldi:8 without the colon"
983 (NO-DIS)
984 "ldi8 $i8,$Ri"
985 (emit ldi8 i8 Ri)
986 )
988 (dni ldi20
989 "load 20 bit unsigned immediate"
990 (NOT-IN-DELAY-SLOT)
991 "ldi:20 $i20,$Ri"
992 (+ OP1_9 OP2_B Ri i20)
993 (set Ri i20)
994 ((fr30-1 (unit u-exec (cycles 2))))
995 )
997 ; Typing ldi:20 in in emacs is a pain.
998 (dnmi ldi20m "ldi:20 without the colon"
999 (NO-DIS)
1000 "ldi20 $i20,$Ri"
1001 (emit ldi20 i20 Ri)
1002 )
1004 (dni ldi32
1005 "load 32 bit immediate"
1006 (NOT-IN-DELAY-SLOT)
1007 "ldi:32 $i32,$Ri"
1008 (+ OP1_9 OP2_F OP3_8 Ri i32)
1009 (set Ri i32)
1010 ((fr30-1 (unit u-exec (cycles 3))))
1011 )
1013 ; Typing ldi:32 in in emacs is a pain.
1014 (dnmi ldi32m "ldi:32 without the colon"
1015 (NO-DIS)
1016 "ldi32 $i32,$Ri"
1017 (emit ldi32 i32 Ri)
1018 )
1020 (define-pmacro (basic-ld name insn opc1 opc2 mode arg1 arg2)
1021 (dni name
1022 (.str name " @" arg1 "," arg2)
1023 ()
1024 (.str name " @$" arg1 ",$" arg2)
1025 (+ opc1 opc2 arg1 arg2)
1026 (set arg2 (mem mode arg1))
1027 ((fr30-1 (unit u-load)))
1028 )
1029 )
1031 (basic-ld ld ld OP1_0 OP2_4 WI Rj Ri)
1032 (basic-ld lduh lduh OP1_0 OP2_5 UHI Rj Ri)
1033 (basic-ld ldub ldub OP1_0 OP2_6 UQI Rj Ri)
1035 (define-pmacro (r13base-ld name insn opc1 opc2 mode arg1 arg2)
1036 (dni name
1037 (.str insn " @(R13," arg1 ")," arg2)
1038 ()
1039 (.str insn " @($R13,$" arg1 "),$" arg2)
1040 (+ opc1 opc2 arg1 arg2)
1041 (set arg2 (mem mode (add arg1 (reg h-gr 13))))
1042 ((fr30-1 (unit u-load)))
1043 )
1044 )
1046 (r13base-ld ldr13 ld OP1_0 OP2_0 WI Rj Ri)
1047 (r13base-ld ldr13uh lduh OP1_0 OP2_1 UHI Rj Ri)
1048 (r13base-ld ldr13ub ldub OP1_0 OP2_2 UQI Rj Ri)
1050 (define-pmacro (r14base-ld name insn opc1 mode arg1 arg2)
1051 (dni name
1052 (.str insn " @(R14," arg1 ")," arg2)
1053 ()
1054 (.str insn " @($R14,$" arg1 "),$" arg2)
1055 (+ opc1 arg1 arg2)
1056 (set arg2 (mem mode (add arg1 (reg h-gr 14))))
1057 ((fr30-1 (unit u-load)))
1058 )
1059 )
1061 (r14base-ld ldr14 ld OP1_2 WI disp10 Ri)
1062 (r14base-ld ldr14uh lduh OP1_4 UHI disp9 Ri)
1063 (r14base-ld ldr14ub ldub OP1_6 UQI disp8 Ri)
1065 (dni ldr15
1066 "ld @(R15,udisp6),Ri mem/reg"
1067 ()
1068 "ld @($R15,$udisp6),$Ri"
1069 (+ OP1_0 OP2_3 udisp6 Ri)
1070 (set Ri (mem WI (add udisp6 (reg h-gr 15))))
1071 ((fr30-1 (unit u-load)))
1072 )
1074 (dni ldr15gr
1075 "ld @R15+,Ri"
1076 ()
1077 "ld @$R15+,$Ri"
1078 (+ OP1_0 OP2_7 OP3_0 Ri)
1079 (sequence ()
1080 (set Ri (mem WI (reg h-gr 15)))
1081 (if (ne (ifield f-Ri) (const 15))
1082 (set (reg h-gr 15) (add (reg h-gr 15) (const 4)))))
1083 ((fr30-1 (unit u-load)))
1084 )
1086 ; This insn loads a value from where r15 points into the target register and
1087 ; then increments r15. If the target register is also r15, then the post
1088 ; increment is not performed.
1089 ;
1090 (dni ldr15dr
1091 "ld @R15+,Rs2"
1092 ()
1093 "ld @$R15+,$Rs2"
1094 (+ OP1_0 OP2_7 OP3_8 Rs2)
1095 ; This seems more straight forward, but doesn't work due to a problem in
1096 ; cgen. We're trying to not increment r15 if it is the target register.
1097 ; (sequence ()
1098 ; (set Rs2 (mem WI (reg h-gr 15)))
1099 ; (if (not (or (and (eq (ifield f-Rs2) (const 2))
1100 ; (eq sbit (const 0)))
1101 ; (and (eq (ifield f-Rs2) (const 3))
1102 ; (eq sbit (const 1)))))
1103 ; (set (reg h-gr 15) (add (reg h-gr 15) (const 4)))
1104 ; )
1105 ; )
1106 (sequence ((WI tmp))
1107 (set tmp (mem WI (reg h-gr 15))) ; save in case target is r15
1108 (set (reg h-gr 15) (add (reg h-gr 15) (const 4)))
1109 (set Rs2 tmp))
1110 ((fr30-1 (unit u-load)))
1111 )
1113 (dni ldr15ps
1114 "ld @R15+,ps mem/reg"
1115 (NOT-IN-DELAY-SLOT)
1116 "ld @$R15+,$ps"
1117 (+ OP1_0 OP2_7 OP3_9 OP4_0)
1118 (sequence ()
1119 (set ps (mem WI (reg h-gr 15)))
1120 (set (reg h-gr 15) (add (reg h-gr 15) (const 4))))
1121 ((fr30-1 (unit u-load)))
1122 )
1124 (define-pmacro (basic-st name insn opc1 opc2 mode arg1 arg2)
1125 (dni name
1126 (.str name " " arg1 ",@" arg2)
1127 ()
1128 (.str name " $" arg1 ",@$" arg2)
1129 (+ opc1 opc2 arg1 arg2)
1130 (set (mem mode arg2) arg1)
1131 ((fr30-1 (unit u-store)))
1132 )
1133 )
1135 (basic-st st st OP1_1 OP2_4 WI Ri Rj)
1136 (basic-st sth sth OP1_1 OP2_5 HI Ri Rj)
1137 (basic-st stb stb OP1_1 OP2_6 QI Ri Rj)
1139 (define-pmacro (r13base-st name insn opc1 opc2 mode arg1 arg2)
1140 (dni name
1141 (.str insn " " arg1 ",@(R13," arg2 ")")
1142 ()
1143 (.str insn " $" arg1 ",@($R13,$" arg2 ")")
1144 (+ opc1 opc2 arg1 arg2)
1145 (set (mem mode (add arg2 (reg h-gr 13))) arg1)
1146 ((fr30-1 (unit u-store)))
1147 )
1148 )
1150 (r13base-st str13 st OP1_1 OP2_0 WI Ri Rj)
1151 (r13base-st str13h sth OP1_1 OP2_1 HI Ri Rj)
1152 (r13base-st str13b stb OP1_1 OP2_2 QI Ri Rj)
1154 (define-pmacro (r14base-st name insn opc1 mode arg1 arg2)
1155 (dni name
1156 (.str insn " " arg1 ",@(R14," arg2 ")")
1157 ()
1158 (.str insn " $" arg1 ",@($R14,$" arg2 ")")
1159 (+ opc1 arg1 arg2)
1160 (set (mem mode (add arg2 (reg h-gr 14))) arg1)
1161 ((fr30-1 (unit u-store)))
1162 )
1163 )
1165 (r14base-st str14 st OP1_3 WI Ri disp10)
1166 (r14base-st str14h sth OP1_5 HI Ri disp9)
1167 (r14base-st str14b stb OP1_7 QI Ri disp8)
1169 (dni str15
1170 "st Ri,@(R15,udisp6) reg/mem"
1171 ()
1172 "st $Ri,@($R15,$udisp6)"
1173 (+ OP1_1 OP2_3 udisp6 Ri)
1174 (set (mem WI (add (reg h-gr 15) udisp6)) Ri)
1175 ((fr30-1 (unit u-store)))
1176 )
1178 ; These store insns predecrement r15 and then store the contents of the source
1179 ; register where r15 then points. If the source register is also r15, then the
1180 ; original value of r15 is stored.
1181 ;
1182 (dni str15gr
1183 "st Ri,@-R15 reg/mem"
1184 ()
1185 "st $Ri,@-$R15"
1186 (+ OP1_1 OP2_7 OP3_0 Ri)
1187 (sequence ((WI tmp))
1188 (set tmp Ri) ; save in case it's r15
1189 (set (reg h-gr 15) (sub (reg h-gr 15) (const 4)))
1190 (set (mem WI (reg h-gr 15)) tmp))
1191 ((fr30-1 (unit u-store)))
1192 )
1194 (dni str15dr
1195 "st Rs,@-R15 reg/mem"
1196 ()
1197 "st $Rs2,@-$R15"
1198 (+ OP1_1 OP2_7 OP3_8 Rs2)
1199 (sequence ((WI tmp))
1200 (set tmp Rs2) ; save in case it's r15
1201 (set (reg h-gr 15) (sub (reg h-gr 15) (const 4)))
1202 (set (mem WI (reg h-gr 15)) tmp))
1203 ((fr30-1 (unit u-store)))
1204 )
1206 (dni str15ps
1207 "st ps,@-R15 reg/mem"
1208 ()
1209 "st $ps,@-$R15"
1210 (+ OP1_1 OP2_7 OP3_9 OP4_0)
1211 (sequence ()
1212 (set (reg h-gr 15) (sub (reg h-gr 15) (const 4)))
1213 (set (mem WI (reg h-gr 15)) ps))
1214 ((fr30-1 (unit u-store)))
1215 )
1217 (define-pmacro (mov2gr name opc1 opc2 arg1 arg2)
1218 (dni name
1219 (.str "mov " arg1 "," arg2)
1220 ()
1221 (.str "mov $" arg1 ",$" arg2)
1222 (+ opc1 opc2 arg1 arg2)
1223 (set arg2 arg1)
1224 ()
1225 )
1226 )
1228 (mov2gr mov OP1_8 OP2_B Rj Ri)
1229 (mov2gr movdr OP1_B OP2_7 Rs1 Ri)
1231 (dni movps
1232 "mov ps,Ri reg/reg"
1233 ()
1234 "mov $ps,$Ri"
1235 (+ OP1_1 OP2_7 OP3_1 Ri)
1236 (set Ri ps)
1237 ()
1238 )
1240 (dni mov2dr
1241 "mov Ri,Rs reg/reg"
1242 ()
1243 "mov $Ri,$Rs1"
1244 (+ OP1_B OP2_3 Rs1 Ri)
1245 (set Rs1 Ri)
1246 ()
1247 )
1249 (dni mov2ps
1250 "mov Ri,ps reg/reg"
1251 ()
1252 "mov $Ri,$ps"
1253 (+ OP1_0 OP2_7 OP3_1 Ri)
1254 (set ps Ri)
1255 ()
1256 )
1258 (dni jmp
1259 "jmp with no delay slot"
1260 (NOT-IN-DELAY-SLOT)
1261 "jmp @$Ri"
1262 (+ OP1_9 OP2_7 OP3_0 Ri)
1263 (set pc Ri)
1264 ((fr30-1 (unit u-cti)))
1265 )
1267 (dni jmpd "jmp with delay slot"
1268 (NOT-IN-DELAY-SLOT)
1269 "jmp:d @$Ri"
1270 (+ OP1_9 OP2_F OP3_0 Ri)
1271 (delay (const 1)
1272 (set pc Ri))
1273 ((fr30-1 (unit u-cti)))
1274 )
1276 ; These versions which use registers must appear before the other
1277 ; versions which use relative addresses due to a problem in cgen
1278 ; - DB.
1279 (dni callr
1280 "call @Ri"
1281 (NOT-IN-DELAY-SLOT)
1282 "call @$Ri"
1283 (+ OP1_9 OP2_7 OP3_1 Ri)
1284 (sequence ()
1285 (set (reg h-dr 1) (add pc (const 2)))
1286 (set pc Ri))
1287 ((fr30-1 (unit u-cti)))
1288 )
1289 (dni callrd
1290 "call:d @Ri"
1291 (NOT-IN-DELAY-SLOT)
1292 "call:d @$Ri"
1293 (+ OP1_9 OP2_F OP3_1 Ri)
1294 (delay (const 1)
1295 (sequence ()
1296 (set (reg h-dr 1) (add pc (const 4)))
1297 (set pc Ri)))
1298 ((fr30-1 (unit u-cti)))
1299 )
1300 ; end of reordered insns
1302 (dni call
1303 "call relative to pc"
1304 (NOT-IN-DELAY-SLOT)
1305 "call $label12"
1306 (+ OP1_D OP5_0 label12)
1307 (sequence ()
1308 (set (reg h-dr 1) (add pc (const 2)))
1309 (set pc label12))
1310 ((fr30-1 (unit u-cti)))
1311 )
1312 (dni calld
1313 "call relative to pc"
1314 (NOT-IN-DELAY-SLOT)
1315 "call:d $label12"
1316 (+ OP1_D OP5_1 label12)
1317 (delay (const 1)
1318 (sequence ()
1319 (set (reg h-dr 1) (add pc (const 4)))
1320 (set pc label12)))
1321 ((fr30-1 (unit u-cti)))
1322 )
1324 (dni ret
1325 "return from subroutine"
1326 (NOT-IN-DELAY-SLOT)
1327 "ret"
1328 (+ OP1_9 OP2_7 OP3_2 OP4_0)
1329 (set pc (reg h-dr 1))
1330 ((fr30-1 (unit u-cti)))
1331 )
1333 (dni ret:d
1334 "return from subroutine with delay slot"
1335 (NOT-IN-DELAY-SLOT)
1336 "ret:d"
1337 (+ OP1_9 OP2_F OP3_2 OP4_0)
1338 (delay (const 1)
1339 (set pc (reg h-dr 1)))
1340 ((fr30-1 (unit u-cti)))
1341 )
1343 (dni int
1344 "interrupt"
1345 (NOT-IN-DELAY-SLOT)
1346 "int $u8"
1347 (+ OP1_1 OP2_F u8)
1348 (sequence ()
1349 ; This is defered to fr30_int because for the breakpoint case
1350 ; we want to change as little of the machine state as possible.
1351 ; Push PS onto the system stack
1352 ;(set (reg h-dr 2) (sub (reg h-dr 2) (const 4)))
1353 ;(set UWI (mem UWI (reg h-dr 2)) ps)
1354 ; Push the return address onto the system stack
1355 ;(set (reg h-dr 2) (sub (reg h-dr 2) (const 4)))
1356 ;(set UWI (mem UWI (reg h-dr 2)) (add pc (const 2)))
1357 ; Set status bits
1358 ;(set ibit (const 0))
1359 ;(set sbit (const 0))
1361 ; We still should indicate what is modified by this insn.
1362 (clobber (reg h-dr 2))
1363 (clobber ibit)
1364 (clobber sbit)
1365 ; ??? (clobber memory)?
1367 ; fr30_int handles operating vs user mode
1368 (set WI pc (c-call WI "fr30_int" pc u8))
1369 )
1370 ; This is more properly a cti, but branch stall calculation is different.
1371 ((fr30-1 (unit u-exec (cycles 6))))
1372 )
1374 (dni inte
1375 "interrupt for emulator"
1376 (NOT-IN-DELAY-SLOT)
1377 "inte"
1378 (+ OP1_9 OP2_F OP3_3 OP4_0)
1379 (sequence ()
1380 ; This is defered to fr30_inte because for the breakpoint case
1381 ; we want to change as little of the machine state as possible.
1382 ; Push PS onto the system stack
1383 ;(set (reg h-dr 2) (sub (reg h-dr 2) (const 4)))
1384 ;(set UWI (mem UWI (reg h-dr 2)) ps)
1385 ; Push the return address onto the system stack
1386 ;(set (reg h-dr 2) (sub (reg h-dr 2) (const 4)))
1387 ;(set UWI (mem UWI (reg h-dr 2)) (add pc (const 2)))
1388 ; Set status bits
1389 ;(set ibit (const 0))
1390 ;(set ilm (const 4))
1392 ; We still should indicate what is modified by this insn.
1393 (clobber (reg h-dr 2))
1394 (clobber ibit)
1395 (clobber ilm)
1396 ; ??? (clobber memory)?
1398 ; fr30_int handles operating vs user mode
1399 (set WI pc (c-call WI "fr30_inte" pc))
1400 )
1401 ; This is more properly a cti, but branch stall calculation is different.
1402 ((fr30-1 (unit u-exec (cycles 6))))
1403 )
1405 (dni reti
1406 "return from interrupt"
1407 (NOT-IN-DELAY-SLOT)
1408 "reti"
1409 (+ OP1_9 OP2_7 OP3_3 OP4_0)
1410 (if (eq sbit (const 0))
1411 (sequence ()
1412 ; Pop the return address from the system stack
1413 (set UWI pc (mem UWI (reg h-dr 2)))
1414 (set (reg h-dr 2) (add (reg h-dr 2) (const 4)))
1415 ; Pop PS from the system stack
1416 (set UWI ps (mem UWI (reg h-dr 2)))
1417 (set (reg h-dr 2) (add (reg h-dr 2) (const 4)))
1418 )
1419 (sequence ()
1420 ; Pop the return address from the user stack
1421 (set UWI pc (mem UWI (reg h-dr 3)))
1422 (set (reg h-dr 3) (add (reg h-dr 3) (const 4)))
1423 ; Pop PS from the user stack
1424 (set UWI ps (mem UWI (reg h-dr 3)))
1425 (set (reg h-dr 3) (add (reg h-dr 3) (const 4)))
1426 )
1427 )
1428 ; This is more properly a cti, but branch stall calculation is different.
1429 ((fr30-1 (unit u-exec (cycles 4))))
1430 )
1432 ; Conditional branches with and without delay slots
1433 ;
1434 (define-pmacro (cond-branch cc condition)
1435 (begin
1436 (dni (.sym b cc d)
1437 (.str (.sym b cc :d) " label9")
1438 (NOT-IN-DELAY-SLOT)
1439 (.str (.sym b cc :d) " $label9")
1440 (+ OP1_F (.sym CC_ cc) label9)
1441 (delay (const 1)
1442 (if condition (set pc label9)))
1443 ((fr30-1 (unit u-cti)))
1444 )
1445 (dni (.sym b cc)
1446 (.str (.sym b cc) " label9")
1447 (NOT-IN-DELAY-SLOT)
1448 (.str (.sym b cc) " $label9")
1449 (+ OP1_E (.sym CC_ cc) label9)
1450 (if condition (set pc label9))
1451 ((fr30-1 (unit u-cti)))
1452 )
1453 )
1454 )
1456 (cond-branch ra (const BI 1))
1457 (cond-branch no (const BI 0))
1458 (cond-branch eq zbit)
1459 (cond-branch ne (not zbit))
1460 (cond-branch c cbit)
1461 (cond-branch nc (not cbit))
1462 (cond-branch n nbit)
1463 (cond-branch p (not nbit))
1464 (cond-branch v vbit)
1465 (cond-branch nv (not vbit))
1466 (cond-branch lt (xor vbit nbit))
1467 (cond-branch ge (not (xor vbit nbit)))
1468 (cond-branch le (or (xor vbit nbit) zbit))
1469 (cond-branch gt (not (or (xor vbit nbit) zbit)))
1470 (cond-branch ls (or cbit zbit))
1471 (cond-branch hi (not (or cbit zbit)))
1473 (define-pmacro (dir2r13 name insn opc1 opc2 mode arg1)
1474 (dni name
1475 (.str insn " @" arg1 ",R13")
1476 ()
1477 (.str insn " @$" arg1 ",$R13")
1478 (+ opc1 opc2 arg1)
1479 (set (reg h-gr 13) (mem mode arg1))
1480 ((fr30-1 (unit u-load)))
1481 )
1482 )
1484 (define-pmacro (dir2r13-postinc name insn opc1 opc2 mode arg1 incr)
1485 (dni name
1486 (.str insn " @" arg1 ",@R13+")
1487 (NOT-IN-DELAY-SLOT)
1488 (.str insn " @$" arg1 ",@$R13+")
1489 (+ opc1 opc2 arg1)
1490 (sequence ()
1491 (set (mem mode (reg h-gr 13)) (mem mode arg1))
1492 (set (reg h-gr 13) (add (reg h-gr 13) incr)))
1493 ((fr30-1 (unit u-load) (unit u-store)))
1494 )
1495 )
1497 (define-pmacro (r132dir name insn opc1 opc2 mode arg1)
1498 (dni name
1499 (.str insn " R13,@" arg1)
1500 ()
1501 (.str insn " $R13,@$" arg1)
1502 (+ opc1 opc2 arg1)
1503 (set (mem mode arg1) (reg h-gr 13))
1504 ((fr30-1 (unit u-store)))
1505 )
1506 )
1508 (define-pmacro (r13-postinc2dir name insn opc1 opc2 mode arg1 incr)
1509 (dni name
1510 (.str insn " @R13+,@" arg1)
1511 (NOT-IN-DELAY-SLOT)
1512 (.str insn " @$R13+,@$" arg1)
1513 (+ opc1 opc2 arg1)
1514 (sequence ()
1515 (set (mem mode arg1) (mem mode (reg h-gr 13)))
1516 (set (reg h-gr 13) (add (reg h-gr 13) incr)))
1517 ((fr30-1 (unit u-load) (unit u-store)))
1518 )
1519 )
1521 ; These versions which move from reg to mem must appear before the other
1522 ; versions which use immediate addresses due to a problem in cgen
1523 ; - DB.
1524 (r132dir dmovr13 dmov OP1_1 OP2_8 WI dir10)
1525 (r132dir dmovr13h dmovh OP1_1 OP2_9 HI dir9)
1526 (r132dir dmovr13b dmovb OP1_1 OP2_A QI dir8)
1528 (r13-postinc2dir dmovr13pi dmov OP1_1 OP2_C WI dir10 (const 4))
1529 (r13-postinc2dir dmovr13pih dmovh OP1_1 OP2_D HI dir9 (const 2))
1530 (r13-postinc2dir dmovr13pib dmovb OP1_1 OP2_E QI dir8 (const 1))
1532 (dni dmovr15pi
1533 "dmov @R15+,@dir10"
1534 (NOT-IN-DELAY-SLOT)
1535 "dmov @$R15+,@$dir10"
1536 (+ OP1_1 OP2_B dir10)
1537 (sequence ()
1538 (set (mem WI dir10) (mem WI (reg h-gr 15)))
1539 (set (reg h-gr 15) (add (reg h-gr 15) (const 4))))
1540 ((fr30-1 (unit u-load) (unit u-store)))
1541 )
1542 ; End of reordered insns.
1544 (dir2r13 dmov2r13 dmov OP1_0 OP2_8 WI dir10)
1545 (dir2r13 dmov2r13h dmovh OP1_0 OP2_9 HI dir9)
1546 (dir2r13 dmov2r13b dmovb OP1_0 OP2_A QI dir8)
1548 (dir2r13-postinc dmov2r13pi dmov OP1_0 OP2_C WI dir10 (const 4))
1549 (dir2r13-postinc dmov2r13pih dmovh OP1_0 OP2_D HI dir9 (const 2))
1550 (dir2r13-postinc dmov2r13pib dmovb OP1_0 OP2_E QI dir8 (const 1))
1552 (dni dmov2r15pd
1553 "dmov @dir10,@-R15"
1554 (NOT-IN-DELAY-SLOT)
1555 "dmov @$dir10,@-$R15"
1556 (+ OP1_0 OP2_B dir10)
1557 (sequence ()
1558 (set (reg h-gr 15) (sub (reg h-gr 15) (const 4)))
1559 (set (mem WI (reg h-gr 15)) (mem WI dir10)))
1560 ((fr30-1 (unit u-load) (unit u-store)))
1561 )
1563 ; Leave these insns as stubs for now, except for the increment of $Ri
1564 ;
1565 (dni ldres
1566 "ldres @Ri+,#u4"
1567 ()
1568 "ldres @$Ri+,$u4"
1569 (+ OP1_B OP2_C u4 Ri)
1570 (set Ri (add Ri (const 4)))
1571 ()
1572 )
1574 (dni stres
1575 "stres #u4,@Ri+"
1576 ()
1577 "stres $u4,@$Ri+"
1578 (+ OP1_B OP2_D u4 Ri)
1579 (set Ri (add Ri (const 4)))
1580 ()
1581 )
1583 ; Leave the coprocessor insns as stubs for now.
1584 ;
1585 (define-pmacro (cop-stub name insn opc1 opc2 opc3 arg1 arg2)
1586 (dni name
1587 (.str insn " u4c,ccc,CRj," arg1 "," arg2)
1588 (NOT-IN-DELAY-SLOT)
1589 (.str insn " $u4c,$ccc,$" arg1 ",$" arg2)
1590 (+ opc1 opc2 opc3 u4c ccc arg1 arg2)
1591 (nop) ; STUB
1592 ()
1593 )
1594 )
1596 (cop-stub copop copop OP1_9 OP2_F OP3_C CRj CRi)
1597 (cop-stub copld copld OP1_9 OP2_F OP3_D Rjc CRi)
1598 (cop-stub copst copst OP1_9 OP2_F OP3_E CRj Ric)
1599 (cop-stub copsv copsv OP1_9 OP2_F OP3_F CRj Ric)
1601 (dni nop
1602 "nop"
1603 ()
1604 "nop"
1605 (+ OP1_9 OP2_F OP3_A OP4_0)
1606 (nop)
1607 ()
1608 )
1610 (dni andccr
1611 "andccr #u8"
1612 ()
1613 "andccr $u8"
1614 (+ OP1_8 OP2_3 u8)
1615 (set ccr (and ccr u8))
1616 ()
1617 )
1619 (dni orccr
1620 "orccr #u8"
1621 ()
1622 "orccr $u8"
1623 (+ OP1_9 OP2_3 u8)
1624 (set ccr (or ccr u8))
1625 ()
1626 )
1628 (dni stilm
1629 "stilm #u8"
1630 ()
1631 "stilm $u8"
1632 (+ OP1_8 OP2_7 u8)
1633 (set ilm (and u8 (const #x1f)))
1634 ()
1635 )
1637 (dni addsp
1638 "addsp #s10"
1639 ()
1640 "addsp $s10"
1641 (+ OP1_A OP2_3 s10)
1642 (set (reg h-gr 15) (add (reg h-gr 15) s10))
1643 ()
1644 )
1646 (define-pmacro (ext-op name opc1 opc2 opc3 op mode mask)
1647 (dni name
1648 (.str name " Ri")
1649 ()
1650 (.str name " $Ri")
1651 (+ opc1 opc2 opc3 Ri)
1652 (set Ri (op WI (and mode Ri mask)))
1653 ()
1654 )
1655 )
1657 (ext-op extsb OP1_9 OP2_7 OP3_8 ext QI (const #xff))
1658 (ext-op extub OP1_9 OP2_7 OP3_9 zext UQI (const #xff))
1659 (ext-op extsh OP1_9 OP2_7 OP3_A ext HI (const #xffff))
1660 (ext-op extuh OP1_9 OP2_7 OP3_B zext UHI (const #xffff))
1662 (dni ldm0
1663 "ldm0 (reglist_low_ld)"
1664 (NOT-IN-DELAY-SLOT)
1665 "ldm0 ($reglist_low_ld)"
1666 (+ OP1_8 OP2_C reglist_low_ld)
1667 (sequence ()
1668 (if (and reglist_low_ld (const #x1))
1669 (sequence ()
1670 (set (reg h-gr 0) (mem WI (reg h-gr 15)))
1671 (set (reg h-gr 15) (add (reg h-gr 15) (const 4)))))
1672 (if (and reglist_low_ld (const #x2))
1673 (sequence ()
1674 (set (reg h-gr 1) (mem WI (reg h-gr 15)))
1675 (set (reg h-gr 15) (add (reg h-gr 15) (const 4)))))
1676 (if (and reglist_low_ld (const #x4))
1677 (sequence ()
1678 (set (reg h-gr 2) (mem WI (reg h-gr 15)))
1679 (set (reg h-gr 15) (add (reg h-gr 15) (const 4)))))
1680 (if (and reglist_low_ld (const #x8))
1681 (sequence ()
1682 (set (reg h-gr 3) (mem WI (reg h-gr 15)))
1683 (set (reg h-gr 15) (add (reg h-gr 15) (const 4)))))
1684 (if (and reglist_low_ld (const #x10))
1685 (sequence ()
1686 (set (reg h-gr 4) (mem WI (reg h-gr 15)))
1687 (set (reg h-gr 15) (add (reg h-gr 15) (const 4)))))
1688 (if (and reglist_low_ld (const #x20))
1689 (sequence ()
1690 (set (reg h-gr 5) (mem WI (reg h-gr 15)))
1691 (set (reg h-gr 15) (add (reg h-gr 15) (const 4)))))
1692 (if (and reglist_low_ld (const #x40))
1693 (sequence ()
1694 (set (reg h-gr 6) (mem WI (reg h-gr 15)))
1695 (set (reg h-gr 15) (add (reg h-gr 15) (const 4)))))
1696 (if (and reglist_low_ld (const #x80))
1697 (sequence ()
1698 (set (reg h-gr 7) (mem WI (reg h-gr 15)))
1699 (set (reg h-gr 15) (add (reg h-gr 15) (const 4)))))
1700 )
1701 ((fr30-1 (unit u-ldm)))
1702 )
1704 (dni ldm1
1705 "ldm1 (reglist_hi_ld)"
1706 (NOT-IN-DELAY-SLOT)
1707 "ldm1 ($reglist_hi_ld)"
1708 (+ OP1_8 OP2_D reglist_hi_ld)
1709 (sequence ()
1710 (if (and reglist_hi_ld (const #x1))
1711 (sequence ()
1712 (set (reg h-gr 8) (mem WI (reg h-gr 15)))
1713 (set (reg h-gr 15) (add (reg h-gr 15) (const 4)))))
1714 (if (and reglist_hi_ld (const #x2))
1715 (sequence ()
1716 (set (reg h-gr 9) (mem WI (reg h-gr 15)))
1717 (set (reg h-gr 15) (add (reg h-gr 15) (const 4)))))
1718 (if (and reglist_hi_ld (const #x4))
1719 (sequence ()
1720 (set (reg h-gr 10) (mem WI (reg h-gr 15)))
1721 (set (reg h-gr 15) (add (reg h-gr 15) (const 4)))))
1722 (if (and reglist_hi_ld (const #x8))
1723 (sequence ()
1724 (set (reg h-gr 11) (mem WI (reg h-gr 15)))
1725 (set (reg h-gr 15) (add (reg h-gr 15) (const 4)))))
1726 (if (and reglist_hi_ld (const #x10))
1727 (sequence ()
1728 (set (reg h-gr 12) (mem WI (reg h-gr 15)))
1729 (set (reg h-gr 15) (add (reg h-gr 15) (const 4)))))
1730 (if (and reglist_hi_ld (const #x20))
1731 (sequence ()
1732 (set (reg h-gr 13) (mem WI (reg h-gr 15)))
1733 (set (reg h-gr 15) (add (reg h-gr 15) (const 4)))))
1734 (if (and reglist_hi_ld (const #x40))
1735 (sequence ()
1736 (set (reg h-gr 14) (mem WI (reg h-gr 15)))
1737 (set (reg h-gr 15) (add (reg h-gr 15) (const 4)))))
1738 (if (and reglist_hi_ld (const #x80))
1739 (set (reg h-gr 15) (mem WI (reg h-gr 15))))
1740 )
1741 ((fr30-1 (unit u-ldm)))
1742 )
1744 (dni stm0
1745 "stm0 (reglist_low_st)"
1746 (NOT-IN-DELAY-SLOT)
1747 "stm0 ($reglist_low_st)"
1748 (+ OP1_8 OP2_E reglist_low_st)
1749 (sequence ()
1750 (if (and reglist_low_st (const #x1))
1751 (sequence ()
1752 (set (reg h-gr 15) (sub (reg h-gr 15) (const 4)))
1753 (set (mem WI (reg h-gr 15)) (reg h-gr 7))))
1754 (if (and reglist_low_st (const #x2))
1755 (sequence ()
1756 (set (reg h-gr 15) (sub (reg h-gr 15) (const 4)))
1757 (set (mem WI (reg h-gr 15)) (reg h-gr 6))))
1758 (if (and reglist_low_st (const #x4))
1759 (sequence ()
1760 (set (reg h-gr 15) (sub (reg h-gr 15) (const 4)))
1761 (set (mem WI (reg h-gr 15)) (reg h-gr 5))))
1762 (if (and reglist_low_st (const #x8))
1763 (sequence ()
1764 (set (reg h-gr 15) (sub (reg h-gr 15) (const 4)))
1765 (set (mem WI (reg h-gr 15)) (reg h-gr 4))))
1766 (if (and reglist_low_st (const #x10))
1767 (sequence ()
1768 (set (reg h-gr 15) (sub (reg h-gr 15) (const 4)))
1769 (set (mem WI (reg h-gr 15)) (reg h-gr 3))))
1770 (if (and reglist_low_st (const #x20))
1771 (sequence ()
1772 (set (reg h-gr 15) (sub (reg h-gr 15) (const 4)))
1773 (set (mem WI (reg h-gr 15)) (reg h-gr 2))))
1774 (if (and reglist_low_st (const #x40))
1775 (sequence ()
1776 (set (reg h-gr 15) (sub (reg h-gr 15) (const 4)))
1777 (set (mem WI (reg h-gr 15)) (reg h-gr 1))))
1778 (if (and reglist_low_st (const #x80))
1779 (sequence ()
1780 (set (reg h-gr 15) (sub (reg h-gr 15) (const 4)))
1781 (set (mem WI (reg h-gr 15)) (reg h-gr 0))))
1782 )
1783 ((fr30-1 (unit u-stm)))
1784 )
1786 (dni stm1
1787 "stm1 (reglist_hi_st)"
1788 (NOT-IN-DELAY-SLOT)
1789 "stm1 ($reglist_hi_st)"
1790 (+ OP1_8 OP2_F reglist_hi_st)
1791 (sequence ()
1792 (if (and reglist_hi_st (const #x1))
1793 (sequence ((WI save-r15))
1794 (set save-r15 (reg h-gr 15))
1795 (set (reg h-gr 15) (sub (reg h-gr 15) (const 4)))
1796 (set (mem WI (reg h-gr 15)) save-r15)))
1797 (if (and reglist_hi_st (const #x2))
1798 (sequence ()
1799 (set (reg h-gr 15) (sub (reg h-gr 15) (const 4)))
1800 (set (mem WI (reg h-gr 15)) (reg h-gr 14))))
1801 (if (and reglist_hi_st (const #x4))
1802 (sequence ()
1803 (set (reg h-gr 15) (sub (reg h-gr 15) (const 4)))
1804 (set (mem WI (reg h-gr 15)) (reg h-gr 13))))
1805 (if (and reglist_hi_st (const #x8))
1806 (sequence ()
1807 (set (reg h-gr 15) (sub (reg h-gr 15) (const 4)))
1808 (set (mem WI (reg h-gr 15)) (reg h-gr 12))))
1809 (if (and reglist_hi_st (const #x10))
1810 (sequence ()
1811 (set (reg h-gr 15) (sub (reg h-gr 15) (const 4)))
1812 (set (mem WI (reg h-gr 15)) (reg h-gr 11))))
1813 (if (and reglist_hi_st (const #x20))
1814 (sequence ()
1815 (set (reg h-gr 15) (sub (reg h-gr 15) (const 4)))
1816 (set (mem WI (reg h-gr 15)) (reg h-gr 10))))
1817 (if (and reglist_hi_st (const #x40))
1818 (sequence ()
1819 (set (reg h-gr 15) (sub (reg h-gr 15) (const 4)))
1820 (set (mem WI (reg h-gr 15)) (reg h-gr 9))))
1821 (if (and reglist_hi_st (const #x80))
1822 (sequence ()
1823 (set (reg h-gr 15) (sub (reg h-gr 15) (const 4)))
1824 (set (mem WI (reg h-gr 15)) (reg h-gr 8))))
1825 )
1826 ((fr30-1 (unit u-stm)))
1827 )
1829 (dni enter
1830 "enter #u10"
1831 (NOT-IN-DELAY-SLOT)
1832 "enter $u10"
1833 (+ OP1_0 OP2_F u10)
1834 (sequence ((WI tmp))
1835 (set tmp (sub (reg h-gr 15) (const 4)))
1836 (set (mem WI tmp) (reg h-gr 14))
1837 (set (reg h-gr 14) tmp)
1838 (set (reg h-gr 15) (sub (reg h-gr 15) u10)))
1839 ((fr30-1 (unit u-exec (cycles 2))))
1840 )
1842 (dni leave
1843 "leave"
1844 ()
1845 "leave"
1846 (+ OP1_9 OP2_F OP3_9 OP4_0)
1847 (sequence ()
1848 (set (reg h-gr 15) (add (reg h-gr 14) (const 4)))
1849 (set (reg h-gr 14) (mem WI (sub (reg h-gr 15) (const 4)))))
1850 ()
1851 )
1853 (dni xchb
1854 "xchb @Rj,Ri"
1855 (NOT-IN-DELAY-SLOT)
1856 "xchb @$Rj,$Ri"
1857 (+ OP1_8 OP2_A Rj Ri)
1858 (sequence ((WI tmp))
1859 (set tmp Ri)
1860 (set Ri (mem UQI Rj))
1861 (set (mem UQI Rj) tmp))
1862 ((fr30-1 (unit u-load) (unit u-store)))
1863 )