sim/bfin/dv-bfin_emac.h

   1 /* Blackfin Ethernet Media Access Controller (EMAC) model.
   2
   3    Copyright (C) 2010-2020 Free Software Foundation, Inc.
   4    Contributed by Analog Devices, Inc.
   5
   6    This file is part of simulators.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 #ifndef DV_BFIN_EMAC_H
  22 #define DV_BFIN_EMAC_H
  23
  24 /* EMAC_OPMODE Masks */
  25 #define RE              (1 << 0)
  26 #define ASTP            (1 << 1)
  27 #define PR              (1 << 7)
  28 #define TE              (1 << 16)
  29
  30 /* EMAC_STAADD Masks */
  31 #define STABUSY         (1 << 0)
  32 #define STAOP           (1 << 1)
  33 #define STADISPRE       (1 << 2)
  34 #define STAIE           (1 << 3)
  35 #define REGAD_SHIFT     6
  36 #define REGAD_MASK      (0x1f << REGAD_SHIFT)
  37 #define REGAD(val)      (((val) & REGAD_MASK) >> REGAD_SHIFT)
  38 #define PHYAD_SHIFT     11
  39 #define PHYAD_MASK      (0x1f << PHYAD_SHIFT)
  40 #define PHYAD(val)      (((val) & PHYAD_MASK) >> PHYAD_SHIFT)
  41
  42 /* EMAC_SYSCTL Masks */
  43 #define PHYIE           (1 << 0)
  44 #define RXDWA           (1 << 1)
  45 #define RXCKS           (1 << 2)
  46 #define TXDWA           (1 << 4)
  47
  48 /* EMAC_RX_STAT Masks */
  49 #define RX_FRLEN        0x7ff
  50 #define RX_COMP         (1 << 12)
  51 #define RX_OK           (1 << 13)
  52 #define RX_ACCEPT       (1 << 31)
  53
  54 /* EMAC_TX_STAT Masks */
  55 #define TX_COMP         (1 << 0)
  56 #define TX_OK           (1 << 1)
  57
  58 #endif