sim/bfin/dv-bfin_evt.c

   1 /* Blackfin Event Vector Table (EVT) model.
   2
   3    Copyright (C) 2010-2020 Free Software Foundation, Inc.
   4    Contributed by Analog Devices, Inc.
   5
   6    This file is part of simulators.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 #include "config.h"
  22
  23 #include "sim-main.h"
  24 #include "devices.h"
  25 #include "dv-bfin_cec.h"
  26 #include "dv-bfin_evt.h"
  27
  28 struct bfin_evt
  29 {
  30   bu32 base;
  31
  32   /* Order after here is important -- matches hardware MMR layout.  */
  33   bu32 evt[16];
  34 };
  35 #define mmr_base()      offsetof(struct bfin_evt, evt[0])
  36 #define mmr_offset(mmr) (offsetof(struct bfin_evt, mmr) - mmr_base())
  37
  38 static const char * const mmr_names[] =
  39 {
  40   "EVT0", "EVT1", "EVT2", "EVT3", "EVT4", "EVT5", "EVT6", "EVT7", "EVT8",
  41   "EVT9", "EVT10", "EVT11", "EVT12", "EVT13", "EVT14", "EVT15",
  42 };
  43 #define mmr_name(off) mmr_names[(off) / 4]
  44
  45 static unsigned
  46 bfin_evt_io_write_buffer (struct hw *me, const void *source,
  47                           int space, address_word addr, unsigned nr_bytes)
  48 {
  49   struct bfin_evt *evt = hw_data (me);
  50   bu32 mmr_off;
  51   bu32 value;
  52
  53   /* Invalid access mode is higher priority than missing register.  */
  54   if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, true))
  55     return 0;
  56
  57   value = dv_load_4 (source);
  58   mmr_off = addr - evt->base;
  59
  60   HW_TRACE_WRITE ();
  61
  62   evt->evt[mmr_off / 4] = value;
  63
  64   return nr_bytes;
  65 }
  66
  67 static unsigned
  68 bfin_evt_io_read_buffer (struct hw *me, void *dest,
  69                          int space, address_word addr, unsigned nr_bytes)
  70 {
  71   struct bfin_evt *evt = hw_data (me);
  72   bu32 mmr_off;
  73   bu32 value;
  74
  75   /* Invalid access mode is higher priority than missing register.  */
  76   if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, false))
  77     return 0;
  78
  79   mmr_off = addr - evt->base;
  80
  81   HW_TRACE_READ ();
  82
  83   value = evt->evt[mmr_off / 4];
  84
  85   dv_store_4 (dest, value);
  86
  87   return nr_bytes;
  88 }
  89
  90 static void
  91 attach_bfin_evt_regs (struct hw *me, struct bfin_evt *evt)
  92 {
  93   address_word attach_address;
  94   int attach_space;
  95   unsigned attach_size;
  96   reg_property_spec reg;
  97
  98   if (hw_find_property (me, "reg") == NULL)
  99     hw_abort (me, "Missing \"reg\" property");
 100
 101   if (!hw_find_reg_array_property (me, "reg", 0, &reg))
 102     hw_abort (me, "\"reg\" property must contain three addr/size entries");
 103
 104   hw_unit_address_to_attach_address (hw_parent (me),
 105                                      &reg.address,
 106                                      &attach_space, &attach_address, me);
 107   hw_unit_size_to_attach_size (hw_parent (me), &reg.size, &attach_size, me);
 108
 109   if (attach_size != BFIN_COREMMR_EVT_SIZE)
 110     hw_abort (me, "\"reg\" size must be %#x", BFIN_COREMMR_EVT_SIZE);
 111
 112   hw_attach_address (hw_parent (me),
 113                      0, attach_space, attach_address, attach_size, me);
 114
 115   evt->base = attach_address;
 116 }
 117
 118 static void
 119 bfin_evt_finish (struct hw *me)
 120 {
 121   struct bfin_evt *evt;
 122
 123   evt = HW_ZALLOC (me, struct bfin_evt);
 124
 125   set_hw_data (me, evt);
 126   set_hw_io_read_buffer (me, bfin_evt_io_read_buffer);
 127   set_hw_io_write_buffer (me, bfin_evt_io_write_buffer);
 128
 129   attach_bfin_evt_regs (me, evt);
 130 }
 131
 132 const struct hw_descriptor dv_bfin_evt_descriptor[] =
 133 {
 134   {"bfin_evt", bfin_evt_finish,},
 135   {NULL, NULL},
 136 };
 137
 138 #define EVT_STATE(cpu) DV_STATE_CACHED (cpu, evt)
 139
 140 void
 141 cec_set_evt (SIM_CPU *cpu, int ivg, bu32 handler_addr)
 142 {
 143   if (ivg > IVG15 || ivg < 0)
 144     sim_io_error (CPU_STATE (cpu), "%s: ivg %i out of range !", __func__, ivg);
 145
 146   EVT_STATE (cpu)->evt[ivg] = handler_addr;
 147 }
 148
 149 bu32
 150 cec_get_evt (SIM_CPU *cpu, int ivg)
 151 {
 152   if (ivg > IVG15 || ivg < 0)
 153     sim_io_error (CPU_STATE (cpu), "%s: ivg %i out of range !", __func__, ivg);
 154
 155   return EVT_STATE (cpu)->evt[ivg];
 156 }
 157
 158 bu32
 159 cec_get_reset_evt (SIM_CPU *cpu)
 160 {
 161   /* XXX: This should tail into the model to get via BMODE pins.  */
 162   return 0xef000000;
 163 }