?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
gmp-utils: New API to simply use of GMP's integer/rational/float objects
[binutils-gdb.git] / sim / bfin / machs.c
blob0ca836da0ec15dbe8f8831036f405507b8588fc8
1 /* Simulator for Analog Devices Blackfin processors.
2
3 Copyright (C) 2005-2020 Free Software Foundation, Inc.
4 Contributed by Analog Devices, Inc. and Mike Frysinger.
5
6 This file is part of simulators.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20
21 #include "config.h"
22
23 #include "sim-main.h"
24 #include "gdb/sim-bfin.h"
25 #include "bfd.h"
26
27 #include "sim-hw.h"
28 #include "devices.h"
29 #include "dv-bfin_cec.h"
30 #include "dv-bfin_dmac.h"
31
32 static const SIM_MACH bfin_mach;
33
34 struct bfin_memory_layout {
35 address_word addr, len;
36 unsigned mask; /* see mapmask in sim_core_attach() */
37 };
38 struct bfin_dev_layout {
39 address_word base, len;
40 unsigned int dmac;
41 const char *dev;
42 };
43 struct bfin_dmac_layout {
44 address_word base;
45 unsigned int dma_count;
46 };
47 struct bfin_port_layout {
48 /* Which device this routes to (name/port). */
49 const char *dst, *dst_port;
50 /* Which device this routes from (name/port). */
51 const char *src, *src_port;
52 };
53 struct bfin_model_data {
54 bu32 chipid;
55 int model_num;
56 const struct bfin_memory_layout *mem;
57 size_t mem_count;
58 const struct bfin_dev_layout *dev;
59 size_t dev_count;
60 const struct bfin_dmac_layout *dmac;
61 size_t dmac_count;
62 const struct bfin_port_layout *port;
63 size_t port_count;
64 };
65
66 #define LAYOUT(_addr, _len, _mask) { .addr = _addr, .len = _len, .mask = access_##_mask, }
67 #define _DEVICE(_base, _len, _dev, _dmac) { .base = _base, .len = _len, .dev = _dev, .dmac = _dmac, }
68 #define DEVICE(_base, _len, _dev) _DEVICE(_base, _len, _dev, 0)
69 #define PORT(_dst, _dst_port, _src, _src_port) \
70 { \
71 .dst = _dst, \
72 .dst_port = _dst_port, \
73 .src = _src, \
74 .src_port = _src_port, \
75 }
76 #define SIC(_s, _ip, _d, _op) PORT("bfin_sic", "int"#_ip"@"#_s, _d, _op)
77
78 /* [1] Common sim code can't model exec-only memory.
79 http://sourceware.org/ml/gdb/2010-02/msg00047.html */
80
81 #define bf000_chipid 0
82 static const struct bfin_memory_layout bf000_mem[] = {};
83 static const struct bfin_dev_layout bf000_dev[] = {};
84 static const struct bfin_dmac_layout bf000_dmac[] = {};
85 static const struct bfin_port_layout bf000_port[] = {};
86
87 #define bf50x_chipid 0x2800
88 #define bf504_chipid bf50x_chipid
89 #define bf506_chipid bf50x_chipid
90 static const struct bfin_memory_layout bf50x_mem[] =
91 {
92 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
93 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
94 LAYOUT (0xFFC03200, 0x50, read_write), /* PORT_MUX stub */
95 LAYOUT (0xFFC03800, 0x100, read_write), /* RSI stub */
96 LAYOUT (0xFFC0328C, 0xC, read_write), /* Flash stub */
97 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
98 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
99 LAYOUT (0xFFA00000, 0x4000, read_write_exec), /* Inst A [1] */
100 LAYOUT (0xFFA04000, 0x4000, read_write_exec), /* Inst Cache [1] */
101 };
102 #define bf504_mem bf50x_mem
103 #define bf506_mem bf50x_mem
104 static const struct bfin_dev_layout bf50x_dev[] =
105 {
106 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
107 DEVICE (0xFFC00400, BFIN_MMR_UART2_SIZE, "bfin_uart2@0"),
108 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
109 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
110 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
111 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
112 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
113 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
114 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
115 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
116 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
117 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
118 DEVICE (0xFFC00A00, BF50X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
119 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
120 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
121 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
122 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
123 DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE, "bfin_uart2@1"),
124 DEVICE (0xFFC03400, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
125 };
126 #define bf504_dev bf50x_dev
127 #define bf506_dev bf50x_dev
128 static const struct bfin_dmac_layout bf50x_dmac[] =
129 {
130 { BFIN_MMR_DMAC0_BASE, 12, },
131 };
132 #define bf504_dmac bf50x_dmac
133 #define bf506_dmac bf50x_dmac
134 static const struct bfin_port_layout bf50x_port[] =
135 {
136 SIC (0, 0, "bfin_pll", "pll"),
137 /*SIC (0, 1, "bfin_dmac@0", "stat"),*/
138 SIC (0, 2, "bfin_ppi@0", "stat"),
139 SIC (0, 3, "bfin_sport@0", "stat"),
140 SIC (0, 4, "bfin_sport@1", "stat"),
141 SIC (0, 5, "bfin_uart2@0", "stat"),
142 SIC (0, 6, "bfin_uart2@1", "stat"),
143 SIC (0, 7, "bfin_spi@0", "stat"),
144 SIC (0, 8, "bfin_spi@1", "stat"),
145 SIC (0, 9, "bfin_can@0", "stat"),
146 SIC (0, 10, "bfin_rsi@0", "int0"),
147 /*SIC (0, 11, reserved),*/
148 SIC (0, 12, "bfin_counter@0", "stat"),
149 SIC (0, 13, "bfin_counter@1", "stat"),
150 SIC (0, 14, "bfin_dma@0", "di"),
151 SIC (0, 15, "bfin_dma@1", "di"),
152 SIC (0, 16, "bfin_dma@2", "di"),
153 SIC (0, 17, "bfin_dma@3", "di"),
154 SIC (0, 18, "bfin_dma@4", "di"),
155 SIC (0, 19, "bfin_dma@5", "di"),
156 SIC (0, 20, "bfin_dma@6", "di"),
157 SIC (0, 21, "bfin_dma@7", "di"),
158 SIC (0, 22, "bfin_dma@8", "di"),
159 SIC (0, 23, "bfin_dma@9", "di"),
160 SIC (0, 24, "bfin_dma@10", "di"),
161 SIC (0, 25, "bfin_dma@11", "di"),
162 SIC (0, 26, "bfin_can@0", "rx"),
163 SIC (0, 27, "bfin_can@0", "tx"),
164 SIC (0, 28, "bfin_twi@0", "stat"),
165 SIC (0, 29, "bfin_gpio@5", "mask_a"),
166 SIC (0, 30, "bfin_gpio@5", "mask_b"),
167 /*SIC (0, 31, reserved),*/
168 SIC (1, 0, "bfin_gptimer@0", "stat"),
169 SIC (1, 1, "bfin_gptimer@1", "stat"),
170 SIC (1, 2, "bfin_gptimer@2", "stat"),
171 SIC (1, 3, "bfin_gptimer@3", "stat"),
172 SIC (1, 4, "bfin_gptimer@4", "stat"),
173 SIC (1, 5, "bfin_gptimer@5", "stat"),
174 SIC (1, 6, "bfin_gptimer@6", "stat"),
175 SIC (1, 7, "bfin_gptimer@7", "stat"),
176 SIC (1, 8, "bfin_gpio@6", "mask_a"),
177 SIC (1, 9, "bfin_gpio@6", "mask_b"),
178 SIC (1, 10, "bfin_dma@256", "di"), /* mdma0 */
179 SIC (1, 10, "bfin_dma@257", "di"), /* mdma0 */
180 SIC (1, 11, "bfin_dma@258", "di"), /* mdma1 */
181 SIC (1, 11, "bfin_dma@259", "di"), /* mdma1 */
182 SIC (1, 12, "bfin_wdog@0", "gpi"),
183 SIC (1, 13, "bfin_gpio@7", "mask_a"),
184 SIC (1, 14, "bfin_gpio@7", "mask_b"),
185 SIC (1, 15, "bfin_acm@0", "stat"),
186 SIC (1, 16, "bfin_acm@1", "int"),
187 /*SIC (1, 17, reserved),*/
188 /*SIC (1, 18, reserved),*/
189 SIC (1, 19, "bfin_pwm@0", "trip"),
190 SIC (1, 20, "bfin_pwm@0", "sync"),
191 SIC (1, 21, "bfin_pwm@1", "trip"),
192 SIC (1, 22, "bfin_pwm@1", "sync"),
193 SIC (1, 23, "bfin_rsi@0", "int1"),
194 };
195 #define bf504_port bf50x_port
196 #define bf506_port bf50x_port
197
198 #define bf51x_chipid 0x27e8
199 #define bf512_chipid bf51x_chipid
200 #define bf514_chipid bf51x_chipid
201 #define bf516_chipid bf51x_chipid
202 #define bf518_chipid bf51x_chipid
203 static const struct bfin_memory_layout bf51x_mem[] =
204 {
205 LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
206 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
207 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
208 LAYOUT (0xFFC03200, 0x50, read_write), /* PORT_MUX stub */
209 LAYOUT (0xFFC03800, 0xD0, read_write), /* RSI stub */
210 LAYOUT (0xFFC03FE0, 0x20, read_write), /* RSI peripheral stub */
211 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
212 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
213 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
214 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
215 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
216 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
217 };
218 #define bf512_mem bf51x_mem
219 #define bf514_mem bf51x_mem
220 #define bf516_mem bf51x_mem
221 #define bf518_mem bf51x_mem
222 static const struct bfin_dev_layout bf512_dev[] =
223 {
224 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
225 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
226 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
227 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
228 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
229 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
230 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
231 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
232 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
233 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
234 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
235 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
236 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
237 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
238 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
239 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
240 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
241 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
242 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
243 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
244 DEVICE (0xFFC03400, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
245 DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"),
246 };
247 #define bf514_dev bf512_dev
248 static const struct bfin_dev_layout bf516_dev[] =
249 {
250 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
251 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
252 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
253 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
254 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
255 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
256 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
257 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
258 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
259 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
260 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
261 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
262 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
263 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
264 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
265 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
266 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
267 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
268 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
269 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
270 DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"),
271 DEVICE (0, 0x20, "bfin_emac/eth_phy"),
272 DEVICE (0xFFC03400, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
273 DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"),
274 };
275 #define bf518_dev bf516_dev
276 #define bf512_dmac bf50x_dmac
277 #define bf514_dmac bf50x_dmac
278 #define bf516_dmac bf50x_dmac
279 #define bf518_dmac bf50x_dmac
280 static const struct bfin_port_layout bf51x_port[] =
281 {
282 SIC (0, 0, "bfin_pll", "pll"),
283 /*SIC (0, 1, "bfin_dmac@0", "stat"),*/
284 SIC (0, 2, "bfin_dmar@0", "block"),
285 SIC (0, 3, "bfin_dmar@1", "block"),
286 SIC (0, 4, "bfin_dmar@0", "overflow"),
287 SIC (0, 5, "bfin_dmar@1", "overflow"),
288 SIC (0, 6, "bfin_ppi@0", "stat"),
289 SIC (0, 7, "bfin_emac", "stat"),
290 SIC (0, 8, "bfin_sport@0", "stat"),
291 SIC (0, 9, "bfin_sport@1", "stat"),
292 SIC (0, 10, "bfin_ptp", "stat"),
293 /*SIC (0, 11, reserved),*/
294 SIC (0, 12, "bfin_uart@0", "stat"),
295 SIC (0, 13, "bfin_uart@1", "stat"),
296 SIC (0, 14, "bfin_rtc", "rtc"),
297 SIC (0, 15, "bfin_dma@0", "di"),
298 SIC (0, 16, "bfin_dma@3", "di"),
299 SIC (0, 17, "bfin_dma@4", "di"),
300 SIC (0, 18, "bfin_dma@5", "di"),
301 SIC (0, 19, "bfin_dma@6", "di"),
302 SIC (0, 20, "bfin_twi@0", "stat"),
303 SIC (0, 21, "bfin_dma@7", "di"),
304 SIC (0, 22, "bfin_dma@8", "di"),
305 SIC (0, 23, "bfin_dma@9", "di"),
306 SIC (0, 24, "bfin_dma@10", "di"),
307 SIC (0, 25, "bfin_dma@11", "di"),
308 SIC (0, 26, "bfin_otp", "stat"),
309 SIC (0, 27, "bfin_counter@0", "stat"),
310 SIC (0, 28, "bfin_dma@1", "di"),
311 SIC (0, 29, "bfin_gpio@7", "mask_a"),
312 SIC (0, 30, "bfin_dma@2", "di"),
313 SIC (0, 31, "bfin_gpio@7", "mask_b"),
314 SIC (1, 0, "bfin_gptimer@0", "stat"),
315 SIC (1, 1, "bfin_gptimer@1", "stat"),
316 SIC (1, 2, "bfin_gptimer@2", "stat"),
317 SIC (1, 3, "bfin_gptimer@3", "stat"),
318 SIC (1, 4, "bfin_gptimer@4", "stat"),
319 SIC (1, 5, "bfin_gptimer@5", "stat"),
320 SIC (1, 6, "bfin_gptimer@6", "stat"),
321 SIC (1, 7, "bfin_gptimer@7", "stat"),
322 SIC (1, 8, "bfin_gpio@6", "mask_a"),
323 SIC (1, 9, "bfin_gpio@6", "mask_b"),
324 SIC (1, 10, "bfin_dma@256", "di"), /* mdma0 */
325 SIC (1, 10, "bfin_dma@257", "di"), /* mdma0 */
326 SIC (1, 11, "bfin_dma@258", "di"), /* mdma1 */
327 SIC (1, 11, "bfin_dma@259", "di"), /* mdma1 */
328 SIC (1, 12, "bfin_wdog@0", "gpi"),
329 SIC (1, 13, "bfin_gpio@5", "mask_a"),
330 SIC (1, 14, "bfin_gpio@5", "mask_b"),
331 SIC (1, 15, "bfin_spi@0", "stat"),
332 SIC (1, 16, "bfin_spi@1", "stat"),
333 /*SIC (1, 17, reserved),*/
334 /*SIC (1, 18, reserved),*/
335 SIC (1, 19, "bfin_rsi@0", "int0"),
336 SIC (1, 20, "bfin_rsi@0", "int1"),
337 SIC (1, 21, "bfin_pwm@0", "trip"),
338 SIC (1, 22, "bfin_pwm@0", "sync"),
339 SIC (1, 23, "bfin_ptp", "stat"),
340 };
341 #define bf512_port bf51x_port
342 #define bf514_port bf51x_port
343 #define bf516_port bf51x_port
344 #define bf518_port bf51x_port
345
346 #define bf522_chipid 0x27e4
347 #define bf523_chipid 0x27e0
348 #define bf524_chipid bf522_chipid
349 #define bf525_chipid bf523_chipid
350 #define bf526_chipid bf522_chipid
351 #define bf527_chipid bf523_chipid
352 static const struct bfin_memory_layout bf52x_mem[] =
353 {
354 LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
355 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
356 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
357 LAYOUT (0xFFC03200, 0x50, read_write), /* PORT_MUX stub */
358 LAYOUT (0xFFC03800, 0x500, read_write), /* MUSB stub */
359 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
360 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
361 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
362 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
363 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
364 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
365 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
366 };
367 #define bf522_mem bf52x_mem
368 #define bf523_mem bf52x_mem
369 #define bf524_mem bf52x_mem
370 #define bf525_mem bf52x_mem
371 #define bf526_mem bf52x_mem
372 #define bf527_mem bf52x_mem
373 static const struct bfin_dev_layout bf522_dev[] =
374 {
375 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
376 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
377 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
378 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
379 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
380 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
381 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
382 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
383 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
384 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
385 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
386 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
387 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
388 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
389 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
390 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
391 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
392 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
393 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
394 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
395 DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"),
396 DEVICE (0xFFC03700, BFIN_MMR_NFC_SIZE, "bfin_nfc"),
397 };
398 #define bf523_dev bf522_dev
399 #define bf524_dev bf522_dev
400 #define bf525_dev bf522_dev
401 static const struct bfin_dev_layout bf526_dev[] =
402 {
403 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
404 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
405 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
406 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
407 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
408 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
409 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
410 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
411 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
412 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
413 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
414 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
415 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
416 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
417 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
418 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
419 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
420 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
421 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
422 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
423 DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"),
424 DEVICE (0, 0x20, "bfin_emac/eth_phy"),
425 DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"),
426 DEVICE (0xFFC03700, BFIN_MMR_NFC_SIZE, "bfin_nfc"),
427 };
428 #define bf527_dev bf526_dev
429 #define bf522_dmac bf50x_dmac
430 #define bf523_dmac bf50x_dmac
431 #define bf524_dmac bf50x_dmac
432 #define bf525_dmac bf50x_dmac
433 #define bf526_dmac bf50x_dmac
434 #define bf527_dmac bf50x_dmac
435 static const struct bfin_port_layout bf52x_port[] =
436 {
437 SIC (0, 0, "bfin_pll", "pll"),
438 /*SIC (0, 1, "bfin_dmac@0", "stat"),*/
439 SIC (0, 2, "bfin_dmar@0", "block"),
440 SIC (0, 3, "bfin_dmar@1", "block"),
441 SIC (0, 4, "bfin_dmar@0", "overflow"),
442 SIC (0, 5, "bfin_dmar@1", "overflow"),
443 SIC (0, 6, "bfin_ppi@0", "stat"),
444 SIC (0, 7, "bfin_emac", "stat"),
445 SIC (0, 8, "bfin_sport@0", "stat"),
446 SIC (0, 9, "bfin_sport@1", "stat"),
447 /*SIC (0, 10, reserved),*/
448 /*SIC (0, 11, reserved),*/
449 SIC (0, 12, "bfin_uart@0", "stat"),
450 SIC (0, 13, "bfin_uart@1", "stat"),
451 SIC (0, 14, "bfin_rtc", "rtc"),
452 SIC (0, 15, "bfin_dma@0", "di"),
453 SIC (0, 16, "bfin_dma@3", "di"),
454 SIC (0, 17, "bfin_dma@4", "di"),
455 SIC (0, 18, "bfin_dma@5", "di"),
456 SIC (0, 19, "bfin_dma@6", "di"),
457 SIC (0, 20, "bfin_twi@0", "stat"),
458 SIC (0, 21, "bfin_dma@7", "di"),
459 SIC (0, 22, "bfin_dma@8", "di"),
460 SIC (0, 23, "bfin_dma@9", "di"),
461 SIC (0, 24, "bfin_dma@10", "di"),
462 SIC (0, 25, "bfin_dma@11", "di"),
463 SIC (0, 26, "bfin_otp", "stat"),
464 SIC (0, 27, "bfin_counter@0", "stat"),
465 SIC (0, 28, "bfin_dma@1", "di"),
466 SIC (0, 29, "bfin_gpio@7", "mask_a"),
467 SIC (0, 30, "bfin_dma@2", "di"),
468 SIC (0, 31, "bfin_gpio@7", "mask_b"),
469 SIC (1, 0, "bfin_gptimer@0", "stat"),
470 SIC (1, 1, "bfin_gptimer@1", "stat"),
471 SIC (1, 2, "bfin_gptimer@2", "stat"),
472 SIC (1, 3, "bfin_gptimer@3", "stat"),
473 SIC (1, 4, "bfin_gptimer@4", "stat"),
474 SIC (1, 5, "bfin_gptimer@5", "stat"),
475 SIC (1, 6, "bfin_gptimer@6", "stat"),
476 SIC (1, 7, "bfin_gptimer@7", "stat"),
477 SIC (1, 8, "bfin_gpio@6", "mask_a"),
478 SIC (1, 9, "bfin_gpio@6", "mask_b"),
479 SIC (1, 10, "bfin_dma@256", "di"), /* mdma0 */
480 SIC (1, 10, "bfin_dma@257", "di"), /* mdma0 */
481 SIC (1, 11, "bfin_dma@258", "di"), /* mdma1 */
482 SIC (1, 11, "bfin_dma@259", "di"), /* mdma1 */
483 SIC (1, 12, "bfin_wdog@0", "gpi"),
484 SIC (1, 13, "bfin_gpio@5", "mask_a"),
485 SIC (1, 14, "bfin_gpio@5", "mask_b"),
486 SIC (1, 15, "bfin_spi@0", "stat"),
487 SIC (1, 16, "bfin_nfc", "stat"),
488 SIC (1, 17, "bfin_hostdp", "stat"),
489 SIC (1, 18, "bfin_hostdp", "done"),
490 SIC (1, 20, "bfin_usb", "int0"),
491 SIC (1, 21, "bfin_usb", "int1"),
492 SIC (1, 22, "bfin_usb", "int2"),
493 };
494 #define bf522_port bf51x_port
495 #define bf523_port bf51x_port
496 #define bf524_port bf51x_port
497 #define bf525_port bf51x_port
498 #define bf526_port bf51x_port
499 #define bf527_port bf51x_port
500
501 #define bf531_chipid 0x27a5
502 #define bf532_chipid bf531_chipid
503 #define bf533_chipid bf531_chipid
504 static const struct bfin_memory_layout bf531_mem[] =
505 {
506 LAYOUT (0xFFC00640, 0xC, read_write), /* TIMER stub */
507 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
508 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
509 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
510 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
511 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
512 };
513 static const struct bfin_memory_layout bf532_mem[] =
514 {
515 LAYOUT (0xFFC00640, 0xC, read_write), /* TIMER stub */
516 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
517 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
518 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
519 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
520 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
521 LAYOUT (0xFFA0C000, 0x4000, read_write_exec), /* Inst C [1] */
522 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
523 };
524 static const struct bfin_memory_layout bf533_mem[] =
525 {
526 LAYOUT (0xFFC00640, 0xC, read_write), /* TIMER stub */
527 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
528 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
529 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
530 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
531 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
532 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
533 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
534 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
535 LAYOUT (0xFFA0C000, 0x4000, read_write_exec), /* Inst C [1] */
536 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
537 };
538 static const struct bfin_dev_layout bf533_dev[] =
539 {
540 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
541 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
542 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
543 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
544 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
545 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
546 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
547 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
548 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
549 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
550 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
551 };
552 #define bf531_dev bf533_dev
553 #define bf532_dev bf533_dev
554 static const struct bfin_dmac_layout bf533_dmac[] =
555 {
556 { BFIN_MMR_DMAC0_BASE, 8, },
557 };
558 #define bf531_dmac bf533_dmac
559 #define bf532_dmac bf533_dmac
560 static const struct bfin_port_layout bf533_port[] =
561 {
562 SIC (0, 0, "bfin_pll", "pll"),
563 /*SIC (0, 1, "bfin_dmac@0", "stat"),*/
564 SIC (0, 2, "bfin_ppi@0", "stat"),
565 SIC (0, 3, "bfin_sport@0", "stat"),
566 SIC (0, 4, "bfin_sport@1", "stat"),
567 SIC (0, 5, "bfin_spi@0", "stat"),
568 SIC (0, 6, "bfin_uart@0", "stat"),
569 SIC (0, 7, "bfin_rtc", "rtc"),
570 SIC (0, 8, "bfin_dma@0", "di"),
571 SIC (0, 9, "bfin_dma@1", "di"),
572 SIC (0, 10, "bfin_dma@2", "di"),
573 SIC (0, 11, "bfin_dma@3", "di"),
574 SIC (0, 12, "bfin_dma@4", "di"),
575 SIC (0, 13, "bfin_dma@5", "di"),
576 SIC (0, 14, "bfin_dma@6", "di"),
577 SIC (0, 15, "bfin_dma@7", "di"),
578 SIC (0, 16, "bfin_gptimer@0", "stat"),
579 SIC (0, 17, "bfin_gptimer@1", "stat"),
580 SIC (0, 18, "bfin_gptimer@2", "stat"),
581 SIC (0, 19, "bfin_gpio@5", "mask_a"),
582 SIC (0, 20, "bfin_gpio@5", "mask_b"),
583 SIC (0, 21, "bfin_dma@256", "di"), /* mdma0 */
584 SIC (0, 21, "bfin_dma@257", "di"), /* mdma0 */
585 SIC (0, 22, "bfin_dma@258", "di"), /* mdma */
586 SIC (0, 22, "bfin_dma@259", "di"), /* mdma1 */
587 SIC (0, 23, "bfin_wdog@0", "gpi"),
588 };
589 #define bf531_port bf533_port
590 #define bf532_port bf533_port
591
592 #define bf534_chipid 0x27c6
593 #define bf536_chipid 0x27c8
594 #define bf537_chipid bf536_chipid
595 static const struct bfin_memory_layout bf534_mem[] =
596 {
597 LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
598 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
599 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
600 LAYOUT (0xFFC03200, 0x10, read_write), /* PORT_MUX stub */
601 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
602 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
603 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
604 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
605 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
606 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
607 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
608 };
609 static const struct bfin_memory_layout bf536_mem[] =
610 {
611 LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
612 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
613 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
614 LAYOUT (0xFFC03200, 0x10, read_write), /* PORT_MUX stub */
615 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
616 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
617 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
618 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
619 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
620 };
621 static const struct bfin_memory_layout bf537_mem[] =
622 {
623 LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
624 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
625 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
626 LAYOUT (0xFFC03200, 0x10, read_write), /* PORT_MUX stub */
627 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
628 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
629 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
630 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
631 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
632 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
633 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
634 };
635 static const struct bfin_dev_layout bf534_dev[] =
636 {
637 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
638 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
639 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
640 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
641 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
642 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
643 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
644 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
645 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
646 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
647 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
648 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
649 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
650 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
651 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
652 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
653 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
654 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
655 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
656 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
657 DEVICE (0, 0, "glue-or@1"),
658 DEVICE (0, 0, "glue-or@1/interrupt-ranges 0 5"),
659 DEVICE (0, 0, "glue-or@2"),
660 DEVICE (0, 0, "glue-or@2/interrupt-ranges 0 8"),
661 DEVICE (0, 0, "glue-or@17"),
662 DEVICE (0, 0, "glue-or@17/interrupt-ranges 0 2"),
663 DEVICE (0, 0, "glue-or@18"),
664 DEVICE (0, 0, "glue-or@18/interrupt-ranges 0 2"),
665 DEVICE (0, 0, "glue-or@27"),
666 DEVICE (0, 0, "glue-or@27/interrupt-ranges 0 2"),
667 DEVICE (0, 0, "glue-or@31"),
668 DEVICE (0, 0, "glue-or@31/interrupt-ranges 0 2"),
669 };
670 static const struct bfin_dev_layout bf537_dev[] =
671 {
672 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
673 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
674 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
675 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
676 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
677 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
678 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
679 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
680 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
681 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
682 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
683 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
684 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
685 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
686 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
687 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
688 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
689 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
690 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
691 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
692 DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"),
693 DEVICE (0, 0x20, "bfin_emac/eth_phy"),
694 DEVICE (0, 0, "glue-or@1"),
695 DEVICE (0, 0, "glue-or@1/interrupt-ranges 0 5"),
696 DEVICE (0, 0, "glue-or@2"),
697 DEVICE (0, 0, "glue-or@2/interrupt-ranges 0 8"),
698 DEVICE (0, 0, "glue-or@17"),
699 DEVICE (0, 0, "glue-or@17/interrupt-ranges 0 2"),
700 DEVICE (0, 0, "glue-or@18"),
701 DEVICE (0, 0, "glue-or@18/interrupt-ranges 0 2"),
702 DEVICE (0, 0, "glue-or@27"),
703 DEVICE (0, 0, "glue-or@27/interrupt-ranges 0 2"),
704 DEVICE (0, 0, "glue-or@31"),
705 DEVICE (0, 0, "glue-or@31/interrupt-ranges 0 2"),
706 };
707 #define bf536_dev bf537_dev
708 #define bf534_dmac bf50x_dmac
709 #define bf536_dmac bf50x_dmac
710 #define bf537_dmac bf50x_dmac
711 static const struct bfin_port_layout bf537_port[] =
712 {
713 SIC (0, 0, "bfin_pll", "pll"),
714 SIC (0, 1, "glue-or@1", "int"),
715 /*PORT ("glue-or@1", "int", "bfin_dmac@0", "stat"),*/
716 PORT ("glue-or@1", "int", "bfin_dmar@0", "block"),
717 PORT ("glue-or@1", "int", "bfin_dmar@1", "block"),
718 PORT ("glue-or@1", "int", "bfin_dmar@0", "overflow"),
719 PORT ("glue-or@1", "int", "bfin_dmar@1", "overflow"),
720 SIC (0, 2, "glue-or@2", "int"),
721 PORT ("glue-or@2", "int", "bfin_can@0", "stat"),
722 PORT ("glue-or@2", "int", "bfin_emac", "stat"),
723 PORT ("glue-or@2", "int", "bfin_sport@0", "stat"),
724 PORT ("glue-or@2", "int", "bfin_sport@1", "stat"),
725 PORT ("glue-or@2", "int", "bfin_ppi@0", "stat"),
726 PORT ("glue-or@2", "int", "bfin_spi@0", "stat"),
727 PORT ("glue-or@2", "int", "bfin_uart@0", "stat"),
728 PORT ("glue-or@2", "int", "bfin_uart@1", "stat"),
729 SIC (0, 3, "bfin_rtc", "rtc"),
730 SIC (0, 4, "bfin_dma@0", "di"),
731 SIC (0, 5, "bfin_dma@3", "di"),
732 SIC (0, 6, "bfin_dma@4", "di"),
733 SIC (0, 7, "bfin_dma@5", "di"),
734 SIC (0, 8, "bfin_dma@6", "di"),
735 SIC (0, 9, "bfin_twi@0", "stat"),
736 SIC (0, 10, "bfin_dma@7", "di"),
737 SIC (0, 11, "bfin_dma@8", "di"),
738 SIC (0, 12, "bfin_dma@9", "di"),
739 SIC (0, 13, "bfin_dma@10", "di"),
740 SIC (0, 14, "bfin_dma@11", "di"),
741 SIC (0, 15, "bfin_can@0", "rx"),
742 SIC (0, 16, "bfin_can@0", "tx"),
743 SIC (0, 17, "glue-or@17", "int"),
744 PORT ("glue-or@17", "int", "bfin_dma@1", "di"),
745 PORT ("glue-or@17", "int", "bfin_gpio@7", "mask_a"),
746 SIC (0, 18, "glue-or@18", "int"),
747 PORT ("glue-or@18", "int", "bfin_dma@2", "di"),
748 PORT ("glue-or@18", "int", "bfin_gpio@7", "mask_b"),
749 SIC (0, 19, "bfin_gptimer@0", "stat"),
750 SIC (0, 20, "bfin_gptimer@1", "stat"),
751 SIC (0, 21, "bfin_gptimer@2", "stat"),
752 SIC (0, 22, "bfin_gptimer@3", "stat"),
753 SIC (0, 23, "bfin_gptimer@4", "stat"),
754 SIC (0, 24, "bfin_gptimer@5", "stat"),
755 SIC (0, 25, "bfin_gptimer@6", "stat"),
756 SIC (0, 26, "bfin_gptimer@7", "stat"),
757 SIC (0, 27, "glue-or@27", "int"),
758 PORT ("glue-or@27", "int", "bfin_gpio@5", "mask_a"),
759 PORT ("glue-or@27", "int", "bfin_gpio@6", "mask_a"),
760 SIC (0, 28, "bfin_gpio@6", "mask_b"),
761 SIC (0, 29, "bfin_dma@256", "di"), /* mdma0 */
762 SIC (0, 29, "bfin_dma@257", "di"), /* mdma0 */
763 SIC (0, 30, "bfin_dma@258", "di"), /* mdma1 */
764 SIC (0, 30, "bfin_dma@259", "di"), /* mdma1 */
765 SIC (0, 31, "glue-or@31", "int"),
766 PORT ("glue-or@31", "int", "bfin_wdog@0", "gpi"),
767 PORT ("glue-or@31", "int", "bfin_gpio@5", "mask_b"),
768 };
769 #define bf534_port bf537_port
770 #define bf536_port bf537_port
771
772 #define bf538_chipid 0x27c4
773 #define bf539_chipid bf538_chipid
774 static const struct bfin_memory_layout bf538_mem[] =
775 {
776 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
777 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
778 LAYOUT (0xFFC01500, 0x70, read_write), /* PORTC/D/E stub */
779 LAYOUT (0xFFC02500, 0x60, read_write), /* SPORT2 stub */
780 LAYOUT (0xFFC02600, 0x60, read_write), /* SPORT3 stub */
781 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
782 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
783 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
784 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
785 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
786 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
787 LAYOUT (0xFFA0C000, 0x4000, read_write_exec), /* Inst C [1] */
788 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
789 };
790 #define bf539_mem bf538_mem
791 static const struct bfin_dev_layout bf538_dev[] =
792 {
793 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
794 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
795 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
796 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
797 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
798 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
799 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
800 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
801 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
802 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
803 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
804 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
805 _DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1", 1),
806 _DEVICE (0xFFC02100, BFIN_MMR_UART_SIZE, "bfin_uart@2", 1),
807 DEVICE (0xFFC02200, BFIN_MMR_TWI_SIZE, "bfin_twi@1"),
808 _DEVICE (0xFFC02300, BFIN_MMR_SPI_SIZE, "bfin_spi@1", 1),
809 _DEVICE (0xFFC02400, BFIN_MMR_SPI_SIZE, "bfin_spi@2", 1),
810 };
811 #define bf539_dev bf538_dev
812 static const struct bfin_dmac_layout bf538_dmac[] =
813 {
814 { BFIN_MMR_DMAC0_BASE, 8, },
815 { BFIN_MMR_DMAC1_BASE, 12, },
816 };
817 #define bf539_dmac bf538_dmac
818 static const struct bfin_port_layout bf538_port[] =
819 {
820 SIC (0, 0, "bfin_pll", "pll"),
821 SIC (0, 1, "bfin_dmac@0", "stat"),
822 SIC (0, 2, "bfin_ppi@0", "stat"),
823 SIC (0, 3, "bfin_sport@0", "stat"),
824 SIC (0, 4, "bfin_sport@1", "stat"),
825 SIC (0, 5, "bfin_spi@0", "stat"),
826 SIC (0, 6, "bfin_uart@0", "stat"),
827 SIC (0, 7, "bfin_rtc", "rtc"),
828 SIC (0, 8, "bfin_dma@0", "di"),
829 SIC (0, 9, "bfin_dma@1", "di"),
830 SIC (0, 10, "bfin_dma@2", "di"),
831 SIC (0, 11, "bfin_dma@3", "di"),
832 SIC (0, 12, "bfin_dma@4", "di"),
833 SIC (0, 13, "bfin_dma@5", "di"),
834 SIC (0, 14, "bfin_dma@6", "di"),
835 SIC (0, 15, "bfin_dma@7", "di"),
836 SIC (0, 16, "bfin_gptimer@0", "stat"),
837 SIC (0, 17, "bfin_gptimer@1", "stat"),
838 SIC (0, 18, "bfin_gptimer@2", "stat"),
839 SIC (0, 19, "bfin_gpio@5", "mask_a"),
840 SIC (0, 20, "bfin_gpio@5", "mask_b"),
841 SIC (0, 21, "bfin_dma@256", "di"), /* mdma0 */
842 SIC (0, 21, "bfin_dma@257", "di"), /* mdma0 */
843 SIC (0, 22, "bfin_dma@258", "di"), /* mdma1 */
844 SIC (0, 22, "bfin_dma@259", "di"), /* mdma1 */
845 SIC (0, 23, "bfin_wdog@0", "gpi"),
846 SIC (0, 24, "bfin_dmac@1", "stat"),
847 SIC (0, 25, "bfin_sport@2", "stat"),
848 SIC (0, 26, "bfin_sport@3", "stat"),
849 /*SIC (0, 27, reserved),*/
850 SIC (0, 28, "bfin_spi@1", "stat"),
851 SIC (0, 29, "bfin_spi@2", "stat"),
852 SIC (0, 30, "bfin_uart@1", "stat"),
853 SIC (0, 31, "bfin_uart@2", "stat"),
854 SIC (1, 0, "bfin_can@0", "stat"),
855 SIC (1, 1, "bfin_dma@8", "di"),
856 SIC (1, 2, "bfin_dma@9", "di"),
857 SIC (1, 3, "bfin_dma@10", "di"),
858 SIC (1, 4, "bfin_dma@11", "di"),
859 SIC (1, 5, "bfin_dma@12", "di"),
860 SIC (1, 6, "bfin_dma@13", "di"),
861 SIC (1, 7, "bfin_dma@14", "di"),
862 SIC (1, 8, "bfin_dma@15", "di"),
863 SIC (1, 9, "bfin_dma@16", "di"),
864 SIC (1, 10, "bfin_dma@17", "di"),
865 SIC (1, 11, "bfin_dma@18", "di"),
866 SIC (1, 12, "bfin_dma@19", "di"),
867 SIC (1, 13, "bfin_twi@0", "stat"),
868 SIC (1, 14, "bfin_twi@1", "stat"),
869 SIC (1, 15, "bfin_can@0", "rx"),
870 SIC (1, 16, "bfin_can@0", "tx"),
871 SIC (1, 17, "bfin_dma@260", "di"), /* mdma2 */
872 SIC (1, 17, "bfin_dma@261", "di"), /* mdma2 */
873 SIC (1, 18, "bfin_dma@262", "di"), /* mdma3 */
874 SIC (1, 18, "bfin_dma@263", "di"), /* mdma3 */
875 };
876 #define bf539_port bf538_port
877
878 #define bf54x_chipid 0x27de
879 #define bf542_chipid bf54x_chipid
880 #define bf544_chipid bf54x_chipid
881 #define bf547_chipid bf54x_chipid
882 #define bf548_chipid bf54x_chipid
883 #define bf549_chipid bf54x_chipid
884 static const struct bfin_memory_layout bf54x_mem[] =
885 {
886 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub XXX: not on BF542/4 */
887 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
888 LAYOUT (0xFFC02500, 0x60, read_write), /* SPORT2 stub */
889 LAYOUT (0xFFC02600, 0x60, read_write), /* SPORT3 stub */
890 LAYOUT (0xFFC03800, 0x70, read_write), /* ATAPI stub */
891 LAYOUT (0xFFC03900, 0x100, read_write), /* RSI stub */
892 LAYOUT (0xFFC03C00, 0x500, read_write), /* MUSB stub */
893 LAYOUT (0xFEB00000, 0x20000, read_write_exec), /* L2 */
894 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
895 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
896 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
897 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
898 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
899 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
900 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
901 };
902 #define bf542_mem bf54x_mem
903 #define bf544_mem bf54x_mem
904 #define bf547_mem bf54x_mem
905 #define bf548_mem bf54x_mem
906 #define bf549_mem bf54x_mem
907 static const struct bfin_dev_layout bf542_dev[] =
908 {
909 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
910 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
911 DEVICE (0xFFC00400, BFIN_MMR_UART2_SIZE, "bfin_uart2@0"),
912 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
913 DEVICE (0xFFC00700, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
914 DEVICE (0xFFC00A00, BF54X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
915 DEVICE (0xFFC00A20, BFIN_MMR_EBIU_DDRC_SIZE, "bfin_ebiu_ddrc"),
916 _DEVICE (0xFFC01300, BFIN_MMR_EPPI_SIZE, "bfin_eppi@1", 1),
917 DEVICE (0xFFC01400, BFIN_MMR_PINT_SIZE, "bfin_pint@0"),
918 DEVICE (0xFFC01430, BFIN_MMR_PINT_SIZE, "bfin_pint@1"),
919 _DEVICE (0xFFC01460, BFIN_MMR_PINT_SIZE, "bfin_pint@2", 2),
920 _DEVICE (0xFFC01490, BFIN_MMR_PINT_SIZE, "bfin_pint@3", 2),
921 DEVICE (0xFFC014C0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@0"),
922 DEVICE (0xFFC014E0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@1"),
923 DEVICE (0xFFC01500, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@2"),
924 DEVICE (0xFFC01520, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@3"),
925 DEVICE (0xFFC01540, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@4"),
926 DEVICE (0xFFC01560, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@5"),
927 DEVICE (0xFFC01580, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@6"),
928 DEVICE (0xFFC015A0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@7"),
929 DEVICE (0xFFC015C0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@8"),
930 DEVICE (0xFFC015E0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@9"),
931 DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
932 DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
933 DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
934 DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
935 DEVICE (0xFFC01640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
936 DEVICE (0xFFC01650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
937 DEVICE (0xFFC01660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
938 DEVICE (0xFFC01670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
939 DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE, "bfin_uart2@1"),
940 _DEVICE (0xFFC02100, BFIN_MMR_UART2_SIZE, "bfin_uart2@2", 1),
941 DEVICE (0xFFC02300, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
942 _DEVICE (0xFFC02900, BFIN_MMR_EPPI_SIZE, "bfin_eppi@2", 1),
943 _DEVICE (0xFFC03100, BFIN_MMR_UART2_SIZE, "bfin_uart2@3", 1),
944 DEVICE (0xFFC03B00, BFIN_MMR_NFC_SIZE, "bfin_nfc"),
945 DEVICE (0xFFC04300, BFIN_MMR_OTP_SIZE, "bfin_otp"),
946 };
947 static const struct bfin_dev_layout bf544_dev[] =
948 {
949 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
950 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
951 DEVICE (0xFFC00400, BFIN_MMR_UART2_SIZE, "bfin_uart2@0"),
952 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
953 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@8"),
954 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@9"),
955 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@10"),
956 DEVICE (0xFFC00700, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
957 DEVICE (0xFFC00A00, BF54X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
958 DEVICE (0xFFC00A20, BFIN_MMR_EBIU_DDRC_SIZE, "bfin_ebiu_ddrc"),
959 _DEVICE (0xFFC01000, BFIN_MMR_EPPI_SIZE, "bfin_eppi@0", 1),
960 _DEVICE (0xFFC01300, BFIN_MMR_EPPI_SIZE, "bfin_eppi@1", 1),
961 DEVICE (0xFFC01400, BFIN_MMR_PINT_SIZE, "bfin_pint@0"),
962 DEVICE (0xFFC01430, BFIN_MMR_PINT_SIZE, "bfin_pint@1"),
963 _DEVICE (0xFFC01460, BFIN_MMR_PINT_SIZE, "bfin_pint@2", 2),
964 _DEVICE (0xFFC01490, BFIN_MMR_PINT_SIZE, "bfin_pint@3", 2),
965 DEVICE (0xFFC014C0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@0"),
966 DEVICE (0xFFC014E0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@1"),
967 DEVICE (0xFFC01500, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@2"),
968 DEVICE (0xFFC01520, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@3"),
969 DEVICE (0xFFC01540, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@4"),
970 DEVICE (0xFFC01560, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@5"),
971 DEVICE (0xFFC01580, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@6"),
972 DEVICE (0xFFC015A0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@7"),
973 DEVICE (0xFFC015C0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@8"),
974 DEVICE (0xFFC015E0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@9"),
975 DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
976 DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
977 DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
978 DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
979 DEVICE (0xFFC01640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
980 DEVICE (0xFFC01650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
981 DEVICE (0xFFC01660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
982 DEVICE (0xFFC01670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
983 DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE, "bfin_uart2@1"),
984 _DEVICE (0xFFC02100, BFIN_MMR_UART2_SIZE, "bfin_uart2@2", 1),
985 DEVICE (0xFFC02200, BFIN_MMR_TWI_SIZE, "bfin_twi@1"),
986 DEVICE (0xFFC02300, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
987 _DEVICE (0xFFC02900, BFIN_MMR_EPPI_SIZE, "bfin_eppi@2", 1),
988 _DEVICE (0xFFC03100, BFIN_MMR_UART2_SIZE, "bfin_uart2@3", 1),
989 DEVICE (0xFFC03B00, BFIN_MMR_NFC_SIZE, "bfin_nfc"),
990 DEVICE (0xFFC04300, BFIN_MMR_OTP_SIZE, "bfin_otp"),
991 };
992 static const struct bfin_dev_layout bf547_dev[] =
993 {
994 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
995 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
996 DEVICE (0xFFC00400, BFIN_MMR_UART2_SIZE, "bfin_uart2@0"),
997 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
998 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@8"),
999 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@9"),
1000 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@10"),
1001 DEVICE (0xFFC00700, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
1002 DEVICE (0xFFC00A00, BF54X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
1003 DEVICE (0xFFC00A20, BFIN_MMR_EBIU_DDRC_SIZE, "bfin_ebiu_ddrc"),
1004 _DEVICE (0xFFC01000, BFIN_MMR_EPPI_SIZE, "bfin_eppi@0", 1),
1005 _DEVICE (0xFFC01300, BFIN_MMR_EPPI_SIZE, "bfin_eppi@1", 1),
1006 DEVICE (0xFFC01400, BFIN_MMR_PINT_SIZE, "bfin_pint@0"),
1007 DEVICE (0xFFC01430, BFIN_MMR_PINT_SIZE, "bfin_pint@1"),
1008 _DEVICE (0xFFC01460, BFIN_MMR_PINT_SIZE, "bfin_pint@2", 2),
1009 _DEVICE (0xFFC01490, BFIN_MMR_PINT_SIZE, "bfin_pint@3", 2),
1010 DEVICE (0xFFC014C0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@0"),
1011 DEVICE (0xFFC014E0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@1"),
1012 DEVICE (0xFFC01500, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@2"),
1013 DEVICE (0xFFC01520, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@3"),
1014 DEVICE (0xFFC01540, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@4"),
1015 DEVICE (0xFFC01560, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@5"),
1016 DEVICE (0xFFC01580, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@6"),
1017 DEVICE (0xFFC015A0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@7"),
1018 DEVICE (0xFFC015C0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@8"),
1019 DEVICE (0xFFC015E0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@9"),
1020 DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
1021 DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
1022 DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
1023 DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
1024 DEVICE (0xFFC01640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
1025 DEVICE (0xFFC01650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
1026 DEVICE (0xFFC01660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
1027 DEVICE (0xFFC01670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
1028 DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE, "bfin_uart2@1"),
1029 _DEVICE (0xFFC02100, BFIN_MMR_UART2_SIZE, "bfin_uart2@2", 1),
1030 DEVICE (0xFFC02200, BFIN_MMR_TWI_SIZE, "bfin_twi@1"),
1031 DEVICE (0xFFC02300, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
1032 _DEVICE (0xFFC02400, BFIN_MMR_SPI_SIZE, "bfin_spi@2", 1),
1033 _DEVICE (0xFFC02900, BFIN_MMR_EPPI_SIZE, "bfin_eppi@2", 1),
1034 _DEVICE (0xFFC03100, BFIN_MMR_UART2_SIZE, "bfin_uart2@3", 1),
1035 DEVICE (0xFFC03B00, BFIN_MMR_NFC_SIZE, "bfin_nfc"),
1036 };
1037 #define bf548_dev bf547_dev
1038 #define bf549_dev bf547_dev
1039 static const struct bfin_dmac_layout bf54x_dmac[] =
1040 {
1041 { BFIN_MMR_DMAC0_BASE, 12, },
1042 { BFIN_MMR_DMAC1_BASE, 12, },
1043 };
1044 #define bf542_dmac bf54x_dmac
1045 #define bf544_dmac bf54x_dmac
1046 #define bf547_dmac bf54x_dmac
1047 #define bf548_dmac bf54x_dmac
1048 #define bf549_dmac bf54x_dmac
1049 #define PINT_PIQS(p, b, g) \
1050 PORT (p, "piq0@"#b, g, "p0"), \
1051 PORT (p, "piq1@"#b, g, "p1"), \
1052 PORT (p, "piq2@"#b, g, "p2"), \
1053 PORT (p, "piq3@"#b, g, "p3"), \
1054 PORT (p, "piq4@"#b, g, "p4"), \
1055 PORT (p, "piq5@"#b, g, "p5"), \
1056 PORT (p, "piq6@"#b, g, "p6"), \
1057 PORT (p, "piq7@"#b, g, "p7"), \
1058 PORT (p, "piq8@"#b, g, "p8"), \
1059 PORT (p, "piq9@"#b, g, "p9"), \
1060 PORT (p, "piq10@"#b, g, "p10"), \
1061 PORT (p, "piq11@"#b, g, "p11"), \
1062 PORT (p, "piq12@"#b, g, "p12"), \
1063 PORT (p, "piq13@"#b, g, "p13"), \
1064 PORT (p, "piq14@"#b, g, "p14"), \
1065 PORT (p, "piq15@"#b, g, "p15")
1066 static const struct bfin_port_layout bf54x_port[] =
1067 {
1068 SIC (0, 0, "bfin_pll", "pll"),
1069 SIC (0, 1, "bfin_dmac@0", "stat"),
1070 SIC (0, 2, "bfin_eppi@0", "stat"),
1071 SIC (0, 3, "bfin_sport@0", "stat"),
1072 SIC (0, 4, "bfin_sport@1", "stat"),
1073 SIC (0, 5, "bfin_spi@0", "stat"),
1074 SIC (0, 6, "bfin_uart2@0", "stat"),
1075 SIC (0, 7, "bfin_rtc", "rtc"),
1076 SIC (0, 8, "bfin_dma@12", "di"),
1077 SIC (0, 9, "bfin_dma@0", "di"),
1078 SIC (0, 10, "bfin_dma@1", "di"),
1079 SIC (0, 11, "bfin_dma@2", "di"),
1080 SIC (0, 12, "bfin_dma@3", "di"),
1081 SIC (0, 13, "bfin_dma@4", "di"),
1082 SIC (0, 14, "bfin_dma@6", "di"),
1083 SIC (0, 15, "bfin_dma@7", "di"),
1084 SIC (0, 16, "bfin_gptimer@8", "stat"),
1085 SIC (0, 17, "bfin_gptimer@9", "stat"),
1086 SIC (0, 18, "bfin_gptimer@10", "stat"),
1087 SIC (0, 19, "bfin_pint@0", "stat"),
1088 PINT_PIQS ("bfin_pint@0", 0, "bfin_gpio2@0"),
1089 PINT_PIQS ("bfin_pint@0", 1, "bfin_gpio2@1"),
1090 SIC (0, 20, "bfin_pint@1", "stat"),
1091 PINT_PIQS ("bfin_pint@1", 0, "bfin_gpio2@0"),
1092 PINT_PIQS ("bfin_pint@1", 1, "bfin_gpio2@1"),
1093 SIC (0, 21, "bfin_dma@256", "di"), /* mdma0 */
1094 SIC (0, 21, "bfin_dma@257", "di"), /* mdma0 */
1095 SIC (0, 22, "bfin_dma@258", "di"), /* mdma1 */
1096 SIC (0, 22, "bfin_dma@259", "di"), /* mdma1 */
1097 SIC (0, 23, "bfin_wdog@0", "gpi"),
1098 SIC (0, 24, "bfin_dmac@1", "stat"),
1099 SIC (0, 25, "bfin_sport@2", "stat"),
1100 SIC (0, 26, "bfin_sport@3", "stat"),
1101 SIC (0, 27, "bfin_mxvr", "data"),
1102 SIC (0, 28, "bfin_spi@1", "stat"),
1103 SIC (0, 29, "bfin_spi@2", "stat"),
1104 SIC (0, 30, "bfin_uart2@1", "stat"),
1105 SIC (0, 31, "bfin_uart2@2", "stat"),
1106 SIC (1, 0, "bfin_can@0", "stat"),
1107 SIC (1, 1, "bfin_dma@18", "di"),
1108 SIC (1, 2, "bfin_dma@19", "di"),
1109 SIC (1, 3, "bfin_dma@20", "di"),
1110 SIC (1, 4, "bfin_dma@21", "di"),
1111 SIC (1, 5, "bfin_dma@13", "di"),
1112 SIC (1, 6, "bfin_dma@14", "di"),
1113 SIC (1, 7, "bfin_dma@5", "di"),
1114 SIC (1, 8, "bfin_dma@23", "di"),
1115 SIC (1, 9, "bfin_dma@8", "di"),
1116 SIC (1, 10, "bfin_dma@9", "di"),
1117 SIC (1, 11, "bfin_dma@10", "di"),
1118 SIC (1, 12, "bfin_dma@11", "di"),
1119 SIC (1, 13, "bfin_twi@0", "stat"),
1120 SIC (1, 14, "bfin_twi@1", "stat"),
1121 SIC (1, 15, "bfin_can@0", "rx"),
1122 SIC (1, 16, "bfin_can@0", "tx"),
1123 SIC (1, 17, "bfin_dma@260", "di"), /* mdma2 */
1124 SIC (1, 17, "bfin_dma@261", "di"), /* mdma2 */
1125 SIC (1, 18, "bfin_dma@262", "di"), /* mdma3 */
1126 SIC (1, 18, "bfin_dma@263", "di"), /* mdma3 */
1127 SIC (1, 19, "bfin_mxvr", "stat"),
1128 SIC (1, 20, "bfin_mxvr", "message"),
1129 SIC (1, 21, "bfin_mxvr", "packet"),
1130 SIC (1, 22, "bfin_eppi@1", "stat"),
1131 SIC (1, 23, "bfin_eppi@2", "stat"),
1132 SIC (1, 24, "bfin_uart2@3", "stat"),
1133 SIC (1, 25, "bfin_hostdp", "stat"),
1134 /*SIC (1, 26, reserved),*/
1135 SIC (1, 27, "bfin_pixc", "stat"),
1136 SIC (1, 28, "bfin_nfc", "stat"),
1137 SIC (1, 29, "bfin_atapi", "stat"),
1138 SIC (1, 30, "bfin_can@1", "stat"),
1139 SIC (1, 31, "bfin_dmar@0", "block"),
1140 SIC (1, 31, "bfin_dmar@1", "block"),
1141 SIC (1, 31, "bfin_dmar@0", "overflow"),
1142 SIC (1, 31, "bfin_dmar@1", "overflow"),
1143 SIC (2, 0, "bfin_dma@15", "di"),
1144 SIC (2, 1, "bfin_dma@16", "di"),
1145 SIC (2, 2, "bfin_dma@17", "di"),
1146 SIC (2, 3, "bfin_dma@22", "di"),
1147 SIC (2, 4, "bfin_counter@0", "stat"),
1148 SIC (2, 5, "bfin_kpad@0", "stat"),
1149 SIC (2, 6, "bfin_can@1", "rx"),
1150 SIC (2, 7, "bfin_can@1", "tx"),
1151 SIC (2, 8, "bfin_sdh", "mask0"),
1152 SIC (2, 9, "bfin_sdh", "mask1"),
1153 /*SIC (2, 10, reserved),*/
1154 SIC (2, 11, "bfin_usb", "int0"),
1155 SIC (2, 12, "bfin_usb", "int1"),
1156 SIC (2, 13, "bfin_usb", "int2"),
1157 SIC (2, 14, "bfin_usb", "dma"),
1158 SIC (2, 15, "bfin_otp", "stat"),
1159 /*SIC (2, 16, reserved),*/
1160 /*SIC (2, 17, reserved),*/
1161 /*SIC (2, 18, reserved),*/
1162 /*SIC (2, 19, reserved),*/
1163 /*SIC (2, 20, reserved),*/
1164 /*SIC (2, 21, reserved),*/
1165 SIC (2, 22, "bfin_gptimer@0", "stat"),
1166 SIC (2, 23, "bfin_gptimer@1", "stat"),
1167 SIC (2, 24, "bfin_gptimer@2", "stat"),
1168 SIC (2, 25, "bfin_gptimer@3", "stat"),
1169 SIC (2, 26, "bfin_gptimer@4", "stat"),
1170 SIC (2, 27, "bfin_gptimer@5", "stat"),
1171 SIC (2, 28, "bfin_gptimer@6", "stat"),
1172 SIC (2, 29, "bfin_gptimer@7", "stat"),
1173 SIC (2, 30, "bfin_pint@2", "stat"),
1174 PINT_PIQS ("bfin_pint@2", 0, "bfin_gpio2@2"),
1175 PINT_PIQS ("bfin_pint@2", 1, "bfin_gpio2@3"),
1176 PINT_PIQS ("bfin_pint@2", 2, "bfin_gpio2@4"),
1177 PINT_PIQS ("bfin_pint@2", 3, "bfin_gpio2@5"),
1178 PINT_PIQS ("bfin_pint@2", 4, "bfin_gpio2@6"),
1179 PINT_PIQS ("bfin_pint@2", 5, "bfin_gpio2@7"),
1180 PINT_PIQS ("bfin_pint@2", 6, "bfin_gpio2@8"),
1181 PINT_PIQS ("bfin_pint@2", 7, "bfin_gpio2@9"),
1182 SIC (2, 31, "bfin_pint@3", "stat"),
1183 PINT_PIQS ("bfin_pint@3", 0, "bfin_gpio2@2"),
1184 PINT_PIQS ("bfin_pint@3", 1, "bfin_gpio2@3"),
1185 PINT_PIQS ("bfin_pint@3", 2, "bfin_gpio2@4"),
1186 PINT_PIQS ("bfin_pint@3", 3, "bfin_gpio2@5"),
1187 PINT_PIQS ("bfin_pint@3", 4, "bfin_gpio2@6"),
1188 PINT_PIQS ("bfin_pint@3", 5, "bfin_gpio2@7"),
1189 PINT_PIQS ("bfin_pint@3", 6, "bfin_gpio2@8"),
1190 PINT_PIQS ("bfin_pint@3", 7, "bfin_gpio2@9"),
1191 };
1192 #define bf542_port bf54x_port
1193 #define bf544_port bf54x_port
1194 #define bf547_port bf54x_port
1195 #define bf548_port bf54x_port
1196 #define bf549_port bf54x_port
1197
1198 /* This is only Core A of course ... */
1199 #define bf561_chipid 0x27bb
1200 static const struct bfin_memory_layout bf561_mem[] =
1201 {
1202 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
1203 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
1204 LAYOUT (0xFEB00000, 0x20000, read_write_exec), /* L2 */
1205 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
1206 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
1207 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
1208 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
1209 LAYOUT (0xFFA00000, 0x4000, read_write_exec), /* Inst A [1] */
1210 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
1211 };
1212 static const struct bfin_dev_layout bf561_dev[] =
1213 {
1214 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
1215 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
1216 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
1217 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
1218 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
1219 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
1220 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
1221 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
1222 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
1223 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
1224 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
1225 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
1226 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
1227 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
1228 _DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0", 1),
1229 DEVICE (0xFFC01200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@1"),
1230 _DEVICE (0xFFC01300, BFIN_MMR_PPI_SIZE, "bfin_ppi@1", 1),
1231 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
1232 DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@8"),
1233 DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@9"),
1234 DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@10"),
1235 DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@11"),
1236 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
1237 };
1238 static const struct bfin_dmac_layout bf561_dmac[] =
1239 {
1240 { BFIN_MMR_DMAC0_BASE, 12, },
1241 { BFIN_MMR_DMAC1_BASE, 12, },
1242 /* XXX: IMDMA: { 0xFFC01800, 4, }, */
1243 };
1244 static const struct bfin_port_layout bf561_port[] =
1245 {
1246 /* SIC0 */
1247 SIC (0, 0, "bfin_pll", "pll"),
1248 /*SIC (0, 1, "bfin_dmac@0", "stat"),*/
1249 /*SIC (0, 2, "bfin_dmac@1", "stat"),*/
1250 /*SIC (0, 3, "bfin_imdmac", "stat"),*/
1251 SIC (0, 4, "bfin_ppi@0", "stat"),
1252 SIC (0, 5, "bfin_ppi@1", "stat"),
1253 SIC (0, 6, "bfin_sport@0", "stat"),
1254 SIC (0, 7, "bfin_sport@1", "stat"),
1255 SIC (0, 8, "bfin_spi@0", "stat"),
1256 SIC (0, 9, "bfin_uart@0", "stat"),
1257 /*SIC (0, 10, reserved),*/
1258 SIC (0, 11, "bfin_dma@12", "di"),
1259 SIC (0, 12, "bfin_dma@13", "di"),
1260 SIC (0, 13, "bfin_dma@14", "di"),
1261 SIC (0, 14, "bfin_dma@15", "di"),
1262 SIC (0, 15, "bfin_dma@16", "di"),
1263 SIC (0, 16, "bfin_dma@17", "di"),
1264 SIC (0, 17, "bfin_dma@18", "di"),
1265 SIC (0, 18, "bfin_dma@19", "di"),
1266 SIC (0, 19, "bfin_dma@20", "di"),
1267 SIC (0, 20, "bfin_dma@21", "di"),
1268 SIC (0, 21, "bfin_dma@22", "di"),
1269 SIC (0, 22, "bfin_dma@23", "di"),
1270 SIC (0, 23, "bfin_dma@0", "di"),
1271 SIC (0, 24, "bfin_dma@1", "di"),
1272 SIC (0, 25, "bfin_dma@2", "di"),
1273 SIC (0, 26, "bfin_dma@3", "di"),
1274 SIC (0, 27, "bfin_dma@4", "di"),
1275 SIC (0, 28, "bfin_dma@5", "di"),
1276 SIC (0, 29, "bfin_dma@6", "di"),
1277 SIC (0, 30, "bfin_dma@7", "di"),
1278 SIC (0, 31, "bfin_dma@8", "di"),
1279 SIC (1, 0, "bfin_dma@9", "di"),
1280 SIC (1, 1, "bfin_dma@10", "di"),
1281 SIC (1, 2, "bfin_dma@11", "di"),
1282 SIC (1, 3, "bfin_gptimer@0", "stat"),
1283 SIC (1, 4, "bfin_gptimer@1", "stat"),
1284 SIC (1, 5, "bfin_gptimer@2", "stat"),
1285 SIC (1, 6, "bfin_gptimer@3", "stat"),
1286 SIC (1, 7, "bfin_gptimer@4", "stat"),
1287 SIC (1, 8, "bfin_gptimer@5", "stat"),
1288 SIC (1, 9, "bfin_gptimer@6", "stat"),
1289 SIC (1, 10, "bfin_gptimer@7", "stat"),
1290 SIC (1, 11, "bfin_gptimer@8", "stat"),
1291 SIC (1, 12, "bfin_gptimer@9", "stat"),
1292 SIC (1, 13, "bfin_gptimer@10", "stat"),
1293 SIC (1, 14, "bfin_gptimer@11", "stat"),
1294 SIC (1, 15, "bfin_gpio@5", "mask_a"),
1295 SIC (1, 16, "bfin_gpio@5", "mask_b"),
1296 SIC (1, 17, "bfin_gpio@6", "mask_a"),
1297 SIC (1, 18, "bfin_gpio@6", "mask_b"),
1298 SIC (1, 19, "bfin_gpio@7", "mask_a"),
1299 SIC (1, 20, "bfin_gpio@7", "mask_b"),
1300 SIC (1, 21, "bfin_dma@256", "di"), /* mdma0 */
1301 SIC (1, 21, "bfin_dma@257", "di"), /* mdma0 */
1302 SIC (1, 22, "bfin_dma@258", "di"), /* mdma1 */
1303 SIC (1, 22, "bfin_dma@259", "di"), /* mdma1 */
1304 SIC (1, 23, "bfin_dma@260", "di"), /* mdma2 */
1305 SIC (1, 23, "bfin_dma@261", "di"), /* mdma2 */
1306 SIC (1, 24, "bfin_dma@262", "di"), /* mdma3 */
1307 SIC (1, 24, "bfin_dma@263", "di"), /* mdma3 */
1308 SIC (1, 25, "bfin_imdma@0", "di"),
1309 SIC (1, 26, "bfin_imdma@1", "di"),
1310 SIC (1, 27, "bfin_wdog@0", "gpi"),
1311 SIC (1, 27, "bfin_wdog@1", "gpi"),
1312 /*SIC (1, 28, reserved),*/
1313 /*SIC (1, 29, reserved),*/
1314 SIC (1, 30, "bfin_sic", "sup_irq@0"),
1315 SIC (1, 31, "bfin_sic", "sup_irq@1"),
1316 };
1317
1318 #define bf592_chipid 0x20cb
1319 static const struct bfin_memory_layout bf592_mem[] =
1320 {
1321 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
1322 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
1323 LAYOUT (0xFF800000, 0x8000, read_write), /* Data A */
1324 LAYOUT (0xFFA00000, 0x4000, read_write_exec), /* Inst A [1] */
1325 LAYOUT (0xFFA04000, 0x4000, read_write_exec), /* Inst B [1] */
1326 };
1327 static const struct bfin_dev_layout bf592_dev[] =
1328 {
1329 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
1330 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
1331 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
1332 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
1333 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
1334 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
1335 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
1336 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
1337 DEVICE (0xFFC01300, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
1338 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
1339 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
1340 };
1341 static const struct bfin_dmac_layout bf592_dmac[] =
1342 {
1343 /* XXX: there are only 9 channels, but mdma code below assumes that they
1344 start right after the dma channels ... */
1345 { BFIN_MMR_DMAC0_BASE, 12, },
1346 };
1347 static const struct bfin_port_layout bf592_port[] =
1348 {
1349 SIC (0, 0, "bfin_pll", "pll"),
1350 /*SIC (0, 1, "bfin_dmac@0", "stat"),*/
1351 SIC (0, 2, "bfin_ppi@0", "stat"),
1352 SIC (0, 3, "bfin_sport@0", "stat"),
1353 SIC (0, 4, "bfin_sport@1", "stat"),
1354 SIC (0, 5, "bfin_spi@0", "stat"),
1355 SIC (0, 6, "bfin_spi@1", "stat"),
1356 SIC (0, 7, "bfin_uart@0", "stat"),
1357 SIC (0, 8, "bfin_dma@0", "di"),
1358 SIC (0, 9, "bfin_dma@1", "di"),
1359 SIC (0, 10, "bfin_dma@2", "di"),
1360 SIC (0, 11, "bfin_dma@3", "di"),
1361 SIC (0, 12, "bfin_dma@4", "di"),
1362 SIC (0, 13, "bfin_dma@5", "di"),
1363 SIC (0, 14, "bfin_dma@6", "di"),
1364 SIC (0, 15, "bfin_dma@7", "di"),
1365 SIC (0, 16, "bfin_dma@8", "di"),
1366 SIC (0, 17, "bfin_gpio@5", "mask_a"),
1367 SIC (0, 18, "bfin_gpio@5", "mask_b"),
1368 SIC (0, 19, "bfin_gptimer@0", "stat"),
1369 SIC (0, 20, "bfin_gptimer@1", "stat"),
1370 SIC (0, 21, "bfin_gptimer@2", "stat"),
1371 SIC (0, 22, "bfin_gpio@6", "mask_a"),
1372 SIC (0, 23, "bfin_gpio@6", "mask_b"),
1373 SIC (0, 24, "bfin_twi@0", "stat"),
1374 /* XXX: 25 - 28 are supposed to be reserved; see comment in machs.c:bf592_dmac[] */
1375 SIC (0, 25, "bfin_dma@9", "di"),
1376 SIC (0, 26, "bfin_dma@10", "di"),
1377 SIC (0, 27, "bfin_dma@11", "di"),
1378 SIC (0, 28, "bfin_dma@12", "di"),
1379 /*SIC (0, 25, reserved),*/
1380 /*SIC (0, 26, reserved),*/
1381 /*SIC (0, 27, reserved),*/
1382 /*SIC (0, 28, reserved),*/
1383 SIC (0, 29, "bfin_dma@256", "di"), /* mdma0 */
1384 SIC (0, 29, "bfin_dma@257", "di"), /* mdma0 */
1385 SIC (0, 30, "bfin_dma@258", "di"), /* mdma1 */
1386 SIC (0, 30, "bfin_dma@259", "di"), /* mdma1 */
1387 SIC (0, 31, "bfin_wdog", "gpi"),
1388 };
1389
1390 static const struct bfin_model_data bfin_model_data[] =
1391 {
1392 #define P(n) \
1393 [MODEL_BF##n] = { \
1394 bf##n##_chipid, n, \
1395 bf##n##_mem , ARRAY_SIZE (bf##n##_mem ), \
1396 bf##n##_dev , ARRAY_SIZE (bf##n##_dev ), \
1397 bf##n##_dmac, ARRAY_SIZE (bf##n##_dmac), \
1398 bf##n##_port, ARRAY_SIZE (bf##n##_port), \
1399 },
1400 #include "proc_list.def"
1401 #undef P
1402 };
1403
1404 #define CORE_DEVICE(dev, DEV) \
1405 DEVICE (BFIN_COREMMR_##DEV##_BASE, BFIN_COREMMR_##DEV##_SIZE, "bfin_"#dev)
1406 static const struct bfin_dev_layout bfin_core_dev[] =
1407 {
1408 CORE_DEVICE (cec, CEC),
1409 CORE_DEVICE (ctimer, CTIMER),
1410 CORE_DEVICE (evt, EVT),
1411 CORE_DEVICE (jtag, JTAG),
1412 CORE_DEVICE (mmu, MMU),
1413 CORE_DEVICE (pfmon, PFMON),
1414 CORE_DEVICE (trace, TRACE),
1415 CORE_DEVICE (wp, WP),
1416 };
1417
1418 static void
1419 dv_bfin_hw_port_parse (SIM_DESC sd, const struct bfin_model_data *mdata,
1420 const char *dev)
1421 {
1422 size_t i;
1423 const char *sdev;
1424
1425 sdev = strchr (dev, '/');
1426 if (sdev)
1427 ++sdev;
1428 else
1429 sdev = dev;
1430
1431 for (i = 0; i < mdata->port_count; ++i)
1432 {
1433 const struct bfin_port_layout *port = &mdata->port[i];
1434
1435 /* There might be more than one mapping. */
1436 if (!strcmp (sdev, port->src))
1437 sim_hw_parse (sd, "/core/%s > %s %s /core/%s", dev,
1438 port->src_port, port->dst_port, port->dst);
1439 }
1440 }
1441
1442 #define dv_bfin_hw_parse(sd, dv, DV) \
1443 do { \
1444 bu32 base = BFIN_MMR_##DV##_BASE; \
1445 bu32 size = BFIN_MMR_##DV##_SIZE; \
1446 sim_hw_parse (sd, "/core/bfin_"#dv"/reg %#x %i", base, size); \
1447 sim_hw_parse (sd, "/core/bfin_"#dv"/type %i", mdata->model_num); \
1448 dv_bfin_hw_port_parse (sd, mdata, "bfin_"#dv); \
1449 } while (0)
1450
1451 static void
1452 bfin_model_hw_tree_init (SIM_DESC sd, SIM_CPU *cpu)
1453 {
1454 const SIM_MODEL *model = CPU_MODEL (cpu);
1455 const struct bfin_model_data *mdata = CPU_MODEL_DATA (cpu);
1456 const struct bfin_board_data *board = STATE_BOARD_DATA (sd);
1457 int mnum = MODEL_NUM (model);
1458 unsigned i, j, dma_chan;
1459
1460 /* Map the core devices. */
1461 for (i = 0; i < ARRAY_SIZE (bfin_core_dev); ++i)
1462 {
1463 const struct bfin_dev_layout *dev = &bfin_core_dev[i];
1464 sim_hw_parse (sd, "/core/%s/reg %#x %i", dev->dev, dev->base, dev->len);
1465 }
1466 sim_hw_parse (sd, "/core/bfin_ctimer > ivtmr ivtmr /core/bfin_cec");
1467
1468 if (mnum == MODEL_BF000)
1469 goto done;
1470
1471 /* Map the system devices. */
1472 dv_bfin_hw_parse (sd, sic, SIC);
1473 for (i = 7; i < 16; ++i)
1474 sim_hw_parse (sd, "/core/bfin_sic > ivg%i ivg%i /core/bfin_cec", i, i);
1475
1476 dv_bfin_hw_parse (sd, pll, PLL);
1477
1478 dma_chan = 0;
1479 for (i = 0; i < mdata->dmac_count; ++i)
1480 {
1481 const struct bfin_dmac_layout *dmac = &mdata->dmac[i];
1482
1483 sim_hw_parse (sd, "/core/bfin_dmac@%u/type %i", i, mdata->model_num);
1484
1485 /* Hook up the non-mdma channels. */
1486 for (j = 0; j < dmac->dma_count; ++j)
1487 {
1488 char dev[64];
1489
1490 sprintf (dev, "bfin_dmac@%u/bfin_dma@%u", i, dma_chan);
1491 sim_hw_parse (sd, "/core/%s/reg %#x %i", dev,
1492 dmac->base + j * BFIN_MMR_DMA_SIZE, BFIN_MMR_DMA_SIZE);
1493 dv_bfin_hw_port_parse (sd, mdata, dev);
1494
1495 ++dma_chan;
1496 }
1497
1498 /* Hook up the mdma channels -- assume every DMAC has 4. */
1499 for (j = 0; j < 4; ++j)
1500 {
1501 char dev[64];
1502
1503 sprintf (dev, "bfin_dmac@%u/bfin_dma@%u", i, j + BFIN_DMAC_MDMA_BASE);
1504 sim_hw_parse (sd, "/core/%s/reg %#x %i", dev,
1505 dmac->base + (j + dmac->dma_count) * BFIN_MMR_DMA_SIZE,
1506 BFIN_MMR_DMA_SIZE);
1507 dv_bfin_hw_port_parse (sd, mdata, dev);
1508 }
1509 }
1510
1511 for (i = 0; i < mdata->dev_count; ++i)
1512 {
1513 const struct bfin_dev_layout *dev = &mdata->dev[i];
1514
1515 if (dev->len)
1516 {
1517 sim_hw_parse (sd, "/core/%s/reg %#x %i", dev->dev, dev->base, dev->len);
1518 sim_hw_parse (sd, "/core/%s/type %i", dev->dev, mdata->model_num);
1519 }
1520 else
1521 {
1522 sim_hw_parse (sd, "/core/%s", dev->dev);
1523 }
1524
1525 dv_bfin_hw_port_parse (sd, mdata, dev->dev);
1526 if (strchr (dev->dev, '/'))
1527 continue;
1528
1529 if (!strncmp (dev->dev, "bfin_uart", 9)
1530 || !strncmp (dev->dev, "bfin_emac", 9)
1531 || !strncmp (dev->dev, "bfin_sport", 10))
1532 {
1533 const char *sint = dev->dev + 5;
1534 sim_hw_parse (sd, "/core/%s > tx %s_tx /core/bfin_dmac@%u", dev->dev, sint, dev->dmac);
1535 sim_hw_parse (sd, "/core/%s > rx %s_rx /core/bfin_dmac@%u", dev->dev, sint, dev->dmac);
1536 }
1537 else if (!strncmp (dev->dev, "bfin_wdog", 9))
1538 {
1539 sim_hw_parse (sd, "/core/%s > reset rst /core/bfin_cec", dev->dev);
1540 sim_hw_parse (sd, "/core/%s > nmi nmi /core/bfin_cec", dev->dev);
1541 }
1542 }
1543
1544 done:
1545 /* Add any additional user board content. */
1546 if (board->hw_file)
1547 sim_do_commandf (sd, "hw-file %s", board->hw_file);
1548
1549 /* Trigger all the new devices' finish func. */
1550 hw_tree_finish (dv_get_device (cpu, "/"));
1551 }
1552
1553 #include "bfroms/all.h"
1554
1555 struct bfrom {
1556 bu32 addr, len, alias_len;
1557 int sirev;
1558 const char *buf;
1559 };
1560
1561 #define BFROMA(addr, rom, sirev, alias_len) \
1562 { addr, sizeof (bfrom_bf##rom##_0_##sirev), alias_len, \
1563 sirev, bfrom_bf##rom##_0_##sirev, }
1564 #define BFROM(rom, sirev, alias_len) BFROMA (0xef000000, rom, sirev, alias_len)
1565 #define BFROM_STUB { 0, 0, 0, 0, NULL, }
1566 static const struct bfrom bf50x_roms[] =
1567 {
1568 BFROM (50x, 0, 0x1000000),
1569 BFROM_STUB,
1570 };
1571 static const struct bfrom bf51x_roms[] =
1572 {
1573 BFROM (51x, 2, 0x1000000),
1574 BFROM (51x, 1, 0x1000000),
1575 BFROM (51x, 0, 0x1000000),
1576 BFROM_STUB,
1577 };
1578 static const struct bfrom bf526_roms[] =
1579 {
1580 BFROM (526, 2, 0x1000000),
1581 BFROM (526, 1, 0x1000000),
1582 BFROM (526, 0, 0x1000000),
1583 BFROM_STUB,
1584 };
1585 static const struct bfrom bf527_roms[] =
1586 {
1587 BFROM (527, 2, 0x1000000),
1588 BFROM (527, 1, 0x1000000),
1589 BFROM (527, 0, 0x1000000),
1590 BFROM_STUB,
1591 };
1592 static const struct bfrom bf533_roms[] =
1593 {
1594 BFROM (533, 6, 0x1000000),
1595 BFROM (533, 5, 0x1000000),
1596 BFROM (533, 4, 0x1000000),
1597 BFROM (533, 3, 0x1000000),
1598 BFROM (533, 2, 0x1000000),
1599 BFROM (533, 1, 0x1000000),
1600 BFROM_STUB,
1601 };
1602 static const struct bfrom bf537_roms[] =
1603 {
1604 BFROM (537, 3, 0x100000),
1605 BFROM (537, 2, 0x100000),
1606 BFROM (537, 1, 0x100000),
1607 BFROM (537, 0, 0x100000),
1608 BFROM_STUB,
1609 };
1610 static const struct bfrom bf538_roms[] =
1611 {
1612 BFROM (538, 5, 0x1000000),
1613 BFROM (538, 4, 0x1000000),
1614 BFROM (538, 3, 0x1000000),
1615 BFROM (538, 2, 0x1000000),
1616 BFROM (538, 1, 0x1000000),
1617 BFROM (538, 0, 0x1000000),
1618 BFROM_STUB,
1619 };
1620 static const struct bfrom bf54x_roms[] =
1621 {
1622 BFROM (54x, 4, 0x1000),
1623 BFROM (54x, 2, 0x1000),
1624 BFROM (54x, 1, 0x1000),
1625 BFROM (54x, 0, 0x1000),
1626 BFROMA (0xffa14000, 54x_l1, 4, 0x10000),
1627 BFROMA (0xffa14000, 54x_l1, 2, 0x10000),
1628 BFROMA (0xffa14000, 54x_l1, 1, 0x10000),
1629 BFROMA (0xffa14000, 54x_l1, 0, 0x10000),
1630 BFROM_STUB,
1631 };
1632 static const struct bfrom bf561_roms[] =
1633 {
1634 /* XXX: No idea what the actual wrap limit is here. */
1635 BFROM (561, 5, 0x1000),
1636 BFROM_STUB,
1637 };
1638 static const struct bfrom bf59x_roms[] =
1639 {
1640 BFROM (59x, 1, 0x1000000),
1641 BFROM (59x, 0, 0x1000000),
1642 BFROMA (0xffa10000, 59x_l1, 1, 0x10000),
1643 BFROM_STUB,
1644 };
1645
1646 static void
1647 bfin_model_map_bfrom (SIM_DESC sd, SIM_CPU *cpu)
1648 {
1649 const struct bfin_model_data *mdata = CPU_MODEL_DATA (cpu);
1650 const struct bfin_board_data *board = STATE_BOARD_DATA (sd);
1651 int mnum = mdata->model_num;
1652 const struct bfrom *bfrom;
1653 unsigned int sirev;
1654
1655 if (mnum >= 500 && mnum <= 509)
1656 bfrom = bf50x_roms;
1657 else if (mnum >= 510 && mnum <= 519)
1658 bfrom = bf51x_roms;
1659 else if (mnum >= 520 && mnum <= 529)
1660 bfrom = (mnum & 1) ? bf527_roms : bf526_roms;
1661 else if (mnum >= 531 && mnum <= 533)
1662 bfrom = bf533_roms;
1663 else if (mnum == 535)
1664 return; /* Stub. */
1665 else if (mnum >= 534 && mnum <= 537)
1666 bfrom = bf537_roms;
1667 else if (mnum >= 538 && mnum <= 539)
1668 bfrom = bf538_roms;
1669 else if (mnum >= 540 && mnum <= 549)
1670 bfrom = bf54x_roms;
1671 else if (mnum == 561)
1672 bfrom = bf561_roms;
1673 else if (mnum >= 590 && mnum <= 599)
1674 bfrom = bf59x_roms;
1675 else
1676 return;
1677
1678 if (board->sirev_valid)
1679 sirev = board->sirev;
1680 else
1681 sirev = bfrom->sirev;
1682 while (bfrom->buf)
1683 {
1684 /* Map all the ranges for this model/sirev. */
1685 if (bfrom->sirev == sirev)
1686 sim_core_attach (sd, NULL, 0, access_read_exec, 0, bfrom->addr,
1687 bfrom->alias_len ? : bfrom->len, bfrom->len, NULL,
1688 (char *)bfrom->buf);
1689 ++bfrom;
1690 }
1691 }
1692
1693 void
1694 bfin_model_cpu_init (SIM_DESC sd, SIM_CPU *cpu)
1695 {
1696 const SIM_MODEL *model = CPU_MODEL (cpu);
1697 const struct bfin_model_data *mdata = CPU_MODEL_DATA (cpu);
1698 int mnum = MODEL_NUM (model);
1699 size_t idx;
1700
1701 /* These memory maps are supposed to be cpu-specific, but the common sim
1702 code does not yet allow that (2nd arg is "cpu" rather than "NULL". */
1703 sim_core_attach (sd, NULL, 0, access_read_write, 0, BFIN_L1_SRAM_SCRATCH,
1704 BFIN_L1_SRAM_SCRATCH_SIZE, 0, NULL, NULL);
1705
1706 if (STATE_ENVIRONMENT (CPU_STATE (cpu)) != OPERATING_ENVIRONMENT)
1707 return;
1708
1709 if (mnum == MODEL_BF000)
1710 goto core_only;
1711
1712 /* Map in the on-chip memories (SRAMs). */
1713 mdata = &bfin_model_data[MODEL_NUM (model)];
1714 for (idx = 0; idx < mdata->mem_count; ++idx)
1715 {
1716 const struct bfin_memory_layout *mem = &mdata->mem[idx];
1717 sim_core_attach (sd, NULL, 0, mem->mask, 0, mem->addr,
1718 mem->len, 0, NULL, NULL);
1719 }
1720
1721 /* Map the on-chip ROMs. */
1722 bfin_model_map_bfrom (sd, cpu);
1723
1724 core_only:
1725 /* Finally, build up the tree for this cpu model. */
1726 bfin_model_hw_tree_init (sd, cpu);
1727 }
1728
1729 bu32
1730 bfin_model_get_chipid (SIM_DESC sd)
1731 {
1732 SIM_CPU *cpu = STATE_CPU (sd, 0);
1733 const struct bfin_model_data *mdata = CPU_MODEL_DATA (cpu);
1734 const struct bfin_board_data *board = STATE_BOARD_DATA (sd);
1735 return
1736 (board->sirev << 28) |
1737 (mdata->chipid << 12) |
1738 (((0xE5 << 1) | 1) & 0xFF);
1739 }
1740
1741 bu32
1742 bfin_model_get_dspid (SIM_DESC sd)
1743 {
1744 const struct bfin_board_data *board = STATE_BOARD_DATA (sd);
1745 return
1746 (0xE5 << 24) |
1747 (0x04 << 16) |
1748 (board->sirev);
1749 }
1750
1751 static void
1752 bfin_model_init (SIM_CPU *cpu)
1753 {
1754 CPU_MODEL_DATA (cpu) = (void *) &bfin_model_data[MODEL_NUM (CPU_MODEL (cpu))];
1755 }
1756
1757 static bu32
1758 bfin_extract_unsigned_integer (unsigned char *addr, int len)
1759 {
1760 bu32 retval;
1761 unsigned char * p;
1762 unsigned char * startaddr = (unsigned char *)addr;
1763 unsigned char * endaddr = startaddr + len;
1764
1765 retval = 0;
1766
1767 for (p = endaddr; p > startaddr;)
1768 retval = (retval << 8) | *--p;
1769
1770 return retval;
1771 }
1772
1773 static void
1774 bfin_store_unsigned_integer (unsigned char *addr, int len, bu32 val)
1775 {
1776 unsigned char *p;
1777 unsigned char *startaddr = addr;
1778 unsigned char *endaddr = startaddr + len;
1779
1780 for (p = startaddr; p < endaddr;)
1781 {
1782 *p++ = val & 0xff;
1783 val >>= 8;
1784 }
1785 }
1786
1787 static bu32 *
1788 bfin_get_reg (SIM_CPU *cpu, int rn)
1789 {
1790 switch (rn)
1791 {
1792 case SIM_BFIN_R0_REGNUM: return &DREG (0);
1793 case SIM_BFIN_R1_REGNUM: return &DREG (1);
1794 case SIM_BFIN_R2_REGNUM: return &DREG (2);
1795 case SIM_BFIN_R3_REGNUM: return &DREG (3);
1796 case SIM_BFIN_R4_REGNUM: return &DREG (4);
1797 case SIM_BFIN_R5_REGNUM: return &DREG (5);
1798 case SIM_BFIN_R6_REGNUM: return &DREG (6);
1799 case SIM_BFIN_R7_REGNUM: return &DREG (7);
1800 case SIM_BFIN_P0_REGNUM: return &PREG (0);
1801 case SIM_BFIN_P1_REGNUM: return &PREG (1);
1802 case SIM_BFIN_P2_REGNUM: return &PREG (2);
1803 case SIM_BFIN_P3_REGNUM: return &PREG (3);
1804 case SIM_BFIN_P4_REGNUM: return &PREG (4);
1805 case SIM_BFIN_P5_REGNUM: return &PREG (5);
1806 case SIM_BFIN_SP_REGNUM: return &SPREG;
1807 case SIM_BFIN_FP_REGNUM: return &FPREG;
1808 case SIM_BFIN_I0_REGNUM: return &IREG (0);
1809 case SIM_BFIN_I1_REGNUM: return &IREG (1);
1810 case SIM_BFIN_I2_REGNUM: return &IREG (2);
1811 case SIM_BFIN_I3_REGNUM: return &IREG (3);
1812 case SIM_BFIN_M0_REGNUM: return &MREG (0);
1813 case SIM_BFIN_M1_REGNUM: return &MREG (1);
1814 case SIM_BFIN_M2_REGNUM: return &MREG (2);
1815 case SIM_BFIN_M3_REGNUM: return &MREG (3);
1816 case SIM_BFIN_B0_REGNUM: return &BREG (0);
1817 case SIM_BFIN_B1_REGNUM: return &BREG (1);
1818 case SIM_BFIN_B2_REGNUM: return &BREG (2);
1819 case SIM_BFIN_B3_REGNUM: return &BREG (3);
1820 case SIM_BFIN_L0_REGNUM: return &LREG (0);
1821 case SIM_BFIN_L1_REGNUM: return &LREG (1);
1822 case SIM_BFIN_L2_REGNUM: return &LREG (2);
1823 case SIM_BFIN_L3_REGNUM: return &LREG (3);
1824 case SIM_BFIN_RETS_REGNUM: return &RETSREG;
1825 case SIM_BFIN_A0_DOT_X_REGNUM: return &AXREG (0);
1826 case SIM_BFIN_A0_DOT_W_REGNUM: return &AWREG (0);
1827 case SIM_BFIN_A1_DOT_X_REGNUM: return &AXREG (1);
1828 case SIM_BFIN_A1_DOT_W_REGNUM: return &AWREG (1);
1829 case SIM_BFIN_LC0_REGNUM: return &LCREG (0);
1830 case SIM_BFIN_LT0_REGNUM: return &LTREG (0);
1831 case SIM_BFIN_LB0_REGNUM: return &LBREG (0);
1832 case SIM_BFIN_LC1_REGNUM: return &LCREG (1);
1833 case SIM_BFIN_LT1_REGNUM: return &LTREG (1);
1834 case SIM_BFIN_LB1_REGNUM: return &LBREG (1);
1835 case SIM_BFIN_CYCLES_REGNUM: return &CYCLESREG;
1836 case SIM_BFIN_CYCLES2_REGNUM: return &CYCLES2REG;
1837 case SIM_BFIN_USP_REGNUM: return &USPREG;
1838 case SIM_BFIN_SEQSTAT_REGNUM: return &SEQSTATREG;
1839 case SIM_BFIN_SYSCFG_REGNUM: return &SYSCFGREG;
1840 case SIM_BFIN_RETI_REGNUM: return &RETIREG;
1841 case SIM_BFIN_RETX_REGNUM: return &RETXREG;
1842 case SIM_BFIN_RETN_REGNUM: return &RETNREG;
1843 case SIM_BFIN_RETE_REGNUM: return &RETEREG;
1844 case SIM_BFIN_PC_REGNUM: return &PCREG;
1845 default: return NULL;
1846 }
1847 }
1848
1849 static int
1850 bfin_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *buf, int len)
1851 {
1852 bu32 value, *reg;
1853
1854 reg = bfin_get_reg (cpu, rn);
1855 if (reg)
1856 value = *reg;
1857 else if (rn == SIM_BFIN_ASTAT_REGNUM)
1858 value = ASTAT;
1859 else if (rn == SIM_BFIN_CC_REGNUM)
1860 value = CCREG;
1861 else
1862 return -1;
1863
1864 /* Handle our KSP/USP shadowing in SP. While in supervisor mode, we
1865 have the normal SP/USP behavior. User mode is tricky though. */
1866 if (STATE_ENVIRONMENT (CPU_STATE (cpu)) == OPERATING_ENVIRONMENT
1867 && cec_is_user_mode (cpu))
1868 {
1869 if (rn == SIM_BFIN_SP_REGNUM)
1870 value = KSPREG;
1871 else if (rn == SIM_BFIN_USP_REGNUM)
1872 value = SPREG;
1873 }
1874
1875 bfin_store_unsigned_integer (buf, 4, value);
1876
1877 return 4;
1878 }
1879
1880 static int
1881 bfin_reg_store (SIM_CPU *cpu, int rn, unsigned char *buf, int len)
1882 {
1883 bu32 value, *reg;
1884
1885 value = bfin_extract_unsigned_integer (buf, 4);
1886 reg = bfin_get_reg (cpu, rn);
1887
1888 if (reg)
1889 /* XXX: Need register trace ? */
1890 *reg = value;
1891 else if (rn == SIM_BFIN_ASTAT_REGNUM)
1892 SET_ASTAT (value);
1893 else if (rn == SIM_BFIN_CC_REGNUM)
1894 SET_CCREG (value);
1895 else
1896 return -1;
1897
1898 return 4;
1899 }
1900
1901 static sim_cia
1902 bfin_pc_get (SIM_CPU *cpu)
1903 {
1904 return PCREG;
1905 }
1906
1907 static void
1908 bfin_pc_set (SIM_CPU *cpu, sim_cia newpc)
1909 {
1910 SET_PCREG (newpc);
1911 }
1912
1913 static const char *
1914 bfin_insn_name (SIM_CPU *cpu, int i)
1915 {
1916 static const char * const insn_name[] = {
1917 #define I(insn) #insn,
1918 #include "insn_list.def"
1919 #undef I
1920 };
1921 return insn_name[i];
1922 }
1923
1924 static void
1925 bfin_init_cpu (SIM_CPU *cpu)
1926 {
1927 CPU_REG_FETCH (cpu) = bfin_reg_fetch;
1928 CPU_REG_STORE (cpu) = bfin_reg_store;
1929 CPU_PC_FETCH (cpu) = bfin_pc_get;
1930 CPU_PC_STORE (cpu) = bfin_pc_set;
1931 CPU_MAX_INSNS (cpu) = BFIN_INSN_MAX;
1932 CPU_INSN_NAME (cpu) = bfin_insn_name;
1933 }
1934
1935 static void
1936 bfin_prepare_run (SIM_CPU *cpu)
1937 {
1938 }
1939
1940 static const SIM_MODEL bfin_models[] =
1941 {
1942 #define P(n) { "bf"#n, & bfin_mach, MODEL_BF##n, NULL, bfin_model_init },
1943 #include "proc_list.def"
1944 #undef P
1945 { 0, NULL, 0, NULL, NULL, }
1946 };
1947
1948 static const SIM_MACH_IMP_PROPERTIES bfin_imp_properties =
1949 {
1950 sizeof (SIM_CPU),
1951 0,
1952 };
1953
1954 static const SIM_MACH bfin_mach =
1955 {
1956 "bfin", "bfin", MACH_BFIN,
1957 32, 32, & bfin_models[0], & bfin_imp_properties,
1958 bfin_init_cpu,
1959 bfin_prepare_run
1960 };
1961
1962 const SIM_MACH *sim_machs[] =
1963 {
1964 & bfin_mach,
1965 NULL
1966 };
1967 \f
1968 /* Device option parsing. */
1969
1970 static DECLARE_OPTION_HANDLER (bfin_mach_option_handler);
1971
1972 enum {
1973 OPTION_MACH_SIREV = OPTION_START,
1974 OPTION_MACH_HW_BOARD_FILE,
1975 };
1976
1977 const OPTION bfin_mach_options[] =
1978 {
1979 { {"sirev", required_argument, NULL, OPTION_MACH_SIREV },
1980 '\0', "NUMBER", "Set CPU silicon revision",
1981 bfin_mach_option_handler, NULL },
1982
1983 { {"hw-board-file", required_argument, NULL, OPTION_MACH_HW_BOARD_FILE },
1984 '\0', "FILE", "Add the supplemental devices listed in the file",
1985 bfin_mach_option_handler, NULL },
1986
1987 { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL, NULL }
1988 };
1989
1990 static SIM_RC
1991 bfin_mach_option_handler (SIM_DESC sd, sim_cpu *current_cpu, int opt,
1992 char *arg, int is_command)
1993 {
1994 struct bfin_board_data *board = STATE_BOARD_DATA (sd);
1995
1996 switch (opt)
1997 {
1998 case OPTION_MACH_SIREV:
1999 board->sirev_valid = 1;
2000 /* Accept (and throw away) a leading "0." in the version. */
2001 if (!strncmp (arg, "0.", 2))
2002 arg += 2;
2003 board->sirev = atoi (arg);
2004 if (board->sirev > 0xf)
2005 {
2006 sim_io_eprintf (sd, "sirev '%s' needs to fit into 4 bits\n", arg);
2007 return SIM_RC_FAIL;
2008 }
2009 return SIM_RC_OK;
2010
2011 case OPTION_MACH_HW_BOARD_FILE:
2012 board->hw_file = xstrdup (arg);
2013 return SIM_RC_OK;
2014
2015 default:
2016 sim_io_eprintf (sd, "Unknown Blackfin option %d\n", opt);
2017 return SIM_RC_FAIL;
2018 }
2019 }
The GNU Binutils are a collection of binary tools.