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gmp-utils: New API to simply use of GMP's integer/rational/float objects
[binutils-gdb.git] / sim / cris / cris-desc.c
blob0194b6e7c513f86ab0f992a7b67e7eda32e83dd3
1 /* CPU data for cris.
2
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
4
5 Copyright 1996-2020 Free Software Foundation, Inc.
6
7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
8
9 This file is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
13
14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
18
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, see <http://www.gnu.org/licenses/>.
21
22 */
23
24 #include "sysdep.h"
25 #include <stdio.h>
26 #include <stdarg.h>
27 #include "ansidecl.h"
28 #include "bfd.h"
29 #include "symcat.h"
30 #include "cris-desc.h"
31 #include "cris-opc.h"
32 #include "opintl.h"
33 #include "libiberty.h"
34 #include "xregex.h"
35
36 /* Attributes. */
37
38 static const CGEN_ATTR_ENTRY bool_attr[] =
39 {
40 { "#f", 0 },
41 { "#t", 1 },
42 { 0, 0 }
43 };
44
45 static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
46 {
47 { "base", MACH_BASE },
48 { "crisv0", MACH_CRISV0 },
49 { "crisv3", MACH_CRISV3 },
50 { "crisv8", MACH_CRISV8 },
51 { "crisv10", MACH_CRISV10 },
52 { "crisv32", MACH_CRISV32 },
53 { "max", MACH_MAX },
54 { 0, 0 }
55 };
56
57 static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
58 {
59 { "cris", ISA_CRIS },
60 { "max", ISA_MAX },
61 { 0, 0 }
62 };
63
64 const CGEN_ATTR_TABLE cris_cgen_ifield_attr_table[] =
65 {
66 { "MACH", & MACH_attr[0], & MACH_attr[0] },
67 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
68 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
69 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
70 { "RESERVED", &bool_attr[0], &bool_attr[0] },
71 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
72 { "SIGNED", &bool_attr[0], &bool_attr[0] },
73 { 0, 0, 0 }
74 };
75
76 const CGEN_ATTR_TABLE cris_cgen_hardware_attr_table[] =
77 {
78 { "MACH", & MACH_attr[0], & MACH_attr[0] },
79 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
80 { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
81 { "PC", &bool_attr[0], &bool_attr[0] },
82 { "PROFILE", &bool_attr[0], &bool_attr[0] },
83 { 0, 0, 0 }
84 };
85
86 const CGEN_ATTR_TABLE cris_cgen_operand_attr_table[] =
87 {
88 { "MACH", & MACH_attr[0], & MACH_attr[0] },
89 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
90 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
91 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
92 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
93 { "SIGNED", &bool_attr[0], &bool_attr[0] },
94 { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
95 { "RELAX", &bool_attr[0], &bool_attr[0] },
96 { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
97 { 0, 0, 0 }
98 };
99
100 const CGEN_ATTR_TABLE cris_cgen_insn_attr_table[] =
101 {
102 { "MACH", & MACH_attr[0], & MACH_attr[0] },
103 { "ALIAS", &bool_attr[0], &bool_attr[0] },
104 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
105 { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
106 { "COND-CTI", &bool_attr[0], &bool_attr[0] },
107 { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
108 { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
109 { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
110 { "RELAXED", &bool_attr[0], &bool_attr[0] },
111 { "NO-DIS", &bool_attr[0], &bool_attr[0] },
112 { "PBB", &bool_attr[0], &bool_attr[0] },
113 { 0, 0, 0 }
114 };
115
116 /* Instruction set variants. */
117
118 static const CGEN_ISA cris_cgen_isa_table[] = {
119 { "cris", 16, 16, 16, 48 },
120 { 0, 0, 0, 0, 0 }
121 };
122
123 /* Machine variants. */
124
125 static const CGEN_MACH cris_cgen_mach_table[] = {
126 { "crisv0", "cris", MACH_CRISV0, 0 },
127 { "crisv3", "cris", MACH_CRISV3, 0 },
128 { "crisv8", "cris", MACH_CRISV8, 0 },
129 { "crisv10", "cris", MACH_CRISV10, 0 },
130 { "crisv32", "crisv32", MACH_CRISV32, 0 },
131 { 0, 0, 0, 0 }
132 };
133
134 static CGEN_KEYWORD_ENTRY cris_cgen_opval_gr_names_pcreg_entries[] =
135 {
136 { "PC", 15, {0, {{{0, 0}}}}, 0, 0 },
137 { "SP", 14, {0, {{{0, 0}}}}, 0, 0 },
138 { "R0", 0, {0, {{{0, 0}}}}, 0, 0 },
139 { "R1", 1, {0, {{{0, 0}}}}, 0, 0 },
140 { "R2", 2, {0, {{{0, 0}}}}, 0, 0 },
141 { "R3", 3, {0, {{{0, 0}}}}, 0, 0 },
142 { "R4", 4, {0, {{{0, 0}}}}, 0, 0 },
143 { "R5", 5, {0, {{{0, 0}}}}, 0, 0 },
144 { "R6", 6, {0, {{{0, 0}}}}, 0, 0 },
145 { "R7", 7, {0, {{{0, 0}}}}, 0, 0 },
146 { "R8", 8, {0, {{{0, 0}}}}, 0, 0 },
147 { "R9", 9, {0, {{{0, 0}}}}, 0, 0 },
148 { "R10", 10, {0, {{{0, 0}}}}, 0, 0 },
149 { "R11", 11, {0, {{{0, 0}}}}, 0, 0 },
150 { "R12", 12, {0, {{{0, 0}}}}, 0, 0 },
151 { "R13", 13, {0, {{{0, 0}}}}, 0, 0 },
152 { "R14", 14, {0, {{{0, 0}}}}, 0, 0 }
153 };
154
155 CGEN_KEYWORD cris_cgen_opval_gr_names_pcreg =
156 {
157 & cris_cgen_opval_gr_names_pcreg_entries[0],
158 17,
159 0, 0, 0, 0, ""
160 };
161
162 static CGEN_KEYWORD_ENTRY cris_cgen_opval_gr_names_acr_entries[] =
163 {
164 { "ACR", 15, {0, {{{0, 0}}}}, 0, 0 },
165 { "SP", 14, {0, {{{0, 0}}}}, 0, 0 },
166 { "R0", 0, {0, {{{0, 0}}}}, 0, 0 },
167 { "R1", 1, {0, {{{0, 0}}}}, 0, 0 },
168 { "R2", 2, {0, {{{0, 0}}}}, 0, 0 },
169 { "R3", 3, {0, {{{0, 0}}}}, 0, 0 },
170 { "R4", 4, {0, {{{0, 0}}}}, 0, 0 },
171 { "R5", 5, {0, {{{0, 0}}}}, 0, 0 },
172 { "R6", 6, {0, {{{0, 0}}}}, 0, 0 },
173 { "R7", 7, {0, {{{0, 0}}}}, 0, 0 },
174 { "R8", 8, {0, {{{0, 0}}}}, 0, 0 },
175 { "R9", 9, {0, {{{0, 0}}}}, 0, 0 },
176 { "R10", 10, {0, {{{0, 0}}}}, 0, 0 },
177 { "R11", 11, {0, {{{0, 0}}}}, 0, 0 },
178 { "R12", 12, {0, {{{0, 0}}}}, 0, 0 },
179 { "R13", 13, {0, {{{0, 0}}}}, 0, 0 },
180 { "R14", 14, {0, {{{0, 0}}}}, 0, 0 }
181 };
182
183 CGEN_KEYWORD cris_cgen_opval_gr_names_acr =
184 {
185 & cris_cgen_opval_gr_names_acr_entries[0],
186 17,
187 0, 0, 0, 0, ""
188 };
189
190 static CGEN_KEYWORD_ENTRY cris_cgen_opval_gr_names_v32_entries[] =
191 {
192 { "ACR", 15, {0, {{{0, 0}}}}, 0, 0 },
193 { "SP", 14, {0, {{{0, 0}}}}, 0, 0 },
194 { "R0", 0, {0, {{{0, 0}}}}, 0, 0 },
195 { "R1", 1, {0, {{{0, 0}}}}, 0, 0 },
196 { "R2", 2, {0, {{{0, 0}}}}, 0, 0 },
197 { "R3", 3, {0, {{{0, 0}}}}, 0, 0 },
198 { "R4", 4, {0, {{{0, 0}}}}, 0, 0 },
199 { "R5", 5, {0, {{{0, 0}}}}, 0, 0 },
200 { "R6", 6, {0, {{{0, 0}}}}, 0, 0 },
201 { "R7", 7, {0, {{{0, 0}}}}, 0, 0 },
202 { "R8", 8, {0, {{{0, 0}}}}, 0, 0 },
203 { "R9", 9, {0, {{{0, 0}}}}, 0, 0 },
204 { "R10", 10, {0, {{{0, 0}}}}, 0, 0 },
205 { "R11", 11, {0, {{{0, 0}}}}, 0, 0 },
206 { "R12", 12, {0, {{{0, 0}}}}, 0, 0 },
207 { "R13", 13, {0, {{{0, 0}}}}, 0, 0 },
208 { "R14", 14, {0, {{{0, 0}}}}, 0, 0 }
209 };
210
211 CGEN_KEYWORD cris_cgen_opval_gr_names_v32 =
212 {
213 & cris_cgen_opval_gr_names_v32_entries[0],
214 17,
215 0, 0, 0, 0, ""
216 };
217
218 static CGEN_KEYWORD_ENTRY cris_cgen_opval_p_names_v10_entries[] =
219 {
220 { "CCR", 5, {0, {{{0, 0}}}}, 0, 0 },
221 { "MOF", 7, {0, {{{0, 0}}}}, 0, 0 },
222 { "IBR", 9, {0, {{{0, 0}}}}, 0, 0 },
223 { "IRP", 10, {0, {{{0, 0}}}}, 0, 0 },
224 { "BAR", 12, {0, {{{0, 0}}}}, 0, 0 },
225 { "DCCR", 13, {0, {{{0, 0}}}}, 0, 0 },
226 { "BRP", 14, {0, {{{0, 0}}}}, 0, 0 },
227 { "USP", 15, {0, {{{0, 0}}}}, 0, 0 },
228 { "VR", 1, {0, {{{0, 0}}}}, 0, 0 },
229 { "SRP", 11, {0, {{{0, 0}}}}, 0, 0 },
230 { "P0", 0, {0, {{{0, 0}}}}, 0, 0 },
231 { "P1", 1, {0, {{{0, 0}}}}, 0, 0 },
232 { "P2", 2, {0, {{{0, 0}}}}, 0, 0 },
233 { "P3", 3, {0, {{{0, 0}}}}, 0, 0 },
234 { "P4", 4, {0, {{{0, 0}}}}, 0, 0 },
235 { "P5", 5, {0, {{{0, 0}}}}, 0, 0 },
236 { "P6", 6, {0, {{{0, 0}}}}, 0, 0 },
237 { "P7", 7, {0, {{{0, 0}}}}, 0, 0 },
238 { "P8", 8, {0, {{{0, 0}}}}, 0, 0 },
239 { "P9", 9, {0, {{{0, 0}}}}, 0, 0 },
240 { "P10", 10, {0, {{{0, 0}}}}, 0, 0 },
241 { "P11", 11, {0, {{{0, 0}}}}, 0, 0 },
242 { "P12", 12, {0, {{{0, 0}}}}, 0, 0 },
243 { "P13", 13, {0, {{{0, 0}}}}, 0, 0 },
244 { "P14", 14, {0, {{{0, 0}}}}, 0, 0 }
245 };
246
247 CGEN_KEYWORD cris_cgen_opval_p_names_v10 =
248 {
249 & cris_cgen_opval_p_names_v10_entries[0],
250 25,
251 0, 0, 0, 0, ""
252 };
253
254 static CGEN_KEYWORD_ENTRY cris_cgen_opval_p_names_v32_entries[] =
255 {
256 { "BZ", 0, {0, {{{0, 0}}}}, 0, 0 },
257 { "PID", 2, {0, {{{0, 0}}}}, 0, 0 },
258 { "SRS", 3, {0, {{{0, 0}}}}, 0, 0 },
259 { "WZ", 4, {0, {{{0, 0}}}}, 0, 0 },
260 { "EXS", 5, {0, {{{0, 0}}}}, 0, 0 },
261 { "EDA", 6, {0, {{{0, 0}}}}, 0, 0 },
262 { "MOF", 7, {0, {{{0, 0}}}}, 0, 0 },
263 { "DZ", 8, {0, {{{0, 0}}}}, 0, 0 },
264 { "EBP", 9, {0, {{{0, 0}}}}, 0, 0 },
265 { "ERP", 10, {0, {{{0, 0}}}}, 0, 0 },
266 { "NRP", 12, {0, {{{0, 0}}}}, 0, 0 },
267 { "CCS", 13, {0, {{{0, 0}}}}, 0, 0 },
268 { "USP", 14, {0, {{{0, 0}}}}, 0, 0 },
269 { "SPC", 15, {0, {{{0, 0}}}}, 0, 0 },
270 { "VR", 1, {0, {{{0, 0}}}}, 0, 0 },
271 { "SRP", 11, {0, {{{0, 0}}}}, 0, 0 },
272 { "P0", 0, {0, {{{0, 0}}}}, 0, 0 },
273 { "P1", 1, {0, {{{0, 0}}}}, 0, 0 },
274 { "P2", 2, {0, {{{0, 0}}}}, 0, 0 },
275 { "P3", 3, {0, {{{0, 0}}}}, 0, 0 },
276 { "P4", 4, {0, {{{0, 0}}}}, 0, 0 },
277 { "P5", 5, {0, {{{0, 0}}}}, 0, 0 },
278 { "P6", 6, {0, {{{0, 0}}}}, 0, 0 },
279 { "P7", 7, {0, {{{0, 0}}}}, 0, 0 },
280 { "P8", 8, {0, {{{0, 0}}}}, 0, 0 },
281 { "P9", 9, {0, {{{0, 0}}}}, 0, 0 },
282 { "P10", 10, {0, {{{0, 0}}}}, 0, 0 },
283 { "P11", 11, {0, {{{0, 0}}}}, 0, 0 },
284 { "P12", 12, {0, {{{0, 0}}}}, 0, 0 },
285 { "P13", 13, {0, {{{0, 0}}}}, 0, 0 },
286 { "P14", 14, {0, {{{0, 0}}}}, 0, 0 }
287 };
288
289 CGEN_KEYWORD cris_cgen_opval_p_names_v32 =
290 {
291 & cris_cgen_opval_p_names_v32_entries[0],
292 31,
293 0, 0, 0, 0, ""
294 };
295
296 static CGEN_KEYWORD_ENTRY cris_cgen_opval_p_names_v32_x_entries[] =
297 {
298 { "BZ", 0, {0, {{{0, 0}}}}, 0, 0 },
299 { "PID", 2, {0, {{{0, 0}}}}, 0, 0 },
300 { "SRS", 3, {0, {{{0, 0}}}}, 0, 0 },
301 { "WZ", 4, {0, {{{0, 0}}}}, 0, 0 },
302 { "EXS", 5, {0, {{{0, 0}}}}, 0, 0 },
303 { "EDA", 6, {0, {{{0, 0}}}}, 0, 0 },
304 { "MOF", 7, {0, {{{0, 0}}}}, 0, 0 },
305 { "DZ", 8, {0, {{{0, 0}}}}, 0, 0 },
306 { "EBP", 9, {0, {{{0, 0}}}}, 0, 0 },
307 { "ERP", 10, {0, {{{0, 0}}}}, 0, 0 },
308 { "NRP", 12, {0, {{{0, 0}}}}, 0, 0 },
309 { "CCS", 13, {0, {{{0, 0}}}}, 0, 0 },
310 { "USP", 14, {0, {{{0, 0}}}}, 0, 0 },
311 { "SPC", 15, {0, {{{0, 0}}}}, 0, 0 },
312 { "VR", 1, {0, {{{0, 0}}}}, 0, 0 },
313 { "SRP", 11, {0, {{{0, 0}}}}, 0, 0 },
314 { "P0", 0, {0, {{{0, 0}}}}, 0, 0 },
315 { "P1", 1, {0, {{{0, 0}}}}, 0, 0 },
316 { "P2", 2, {0, {{{0, 0}}}}, 0, 0 },
317 { "P3", 3, {0, {{{0, 0}}}}, 0, 0 },
318 { "P4", 4, {0, {{{0, 0}}}}, 0, 0 },
319 { "P5", 5, {0, {{{0, 0}}}}, 0, 0 },
320 { "P6", 6, {0, {{{0, 0}}}}, 0, 0 },
321 { "P7", 7, {0, {{{0, 0}}}}, 0, 0 },
322 { "P8", 8, {0, {{{0, 0}}}}, 0, 0 },
323 { "P9", 9, {0, {{{0, 0}}}}, 0, 0 },
324 { "P10", 10, {0, {{{0, 0}}}}, 0, 0 },
325 { "P11", 11, {0, {{{0, 0}}}}, 0, 0 },
326 { "P12", 12, {0, {{{0, 0}}}}, 0, 0 },
327 { "P13", 13, {0, {{{0, 0}}}}, 0, 0 },
328 { "P14", 14, {0, {{{0, 0}}}}, 0, 0 }
329 };
330
331 CGEN_KEYWORD cris_cgen_opval_p_names_v32_x =
332 {
333 & cris_cgen_opval_p_names_v32_x_entries[0],
334 31,
335 0, 0, 0, 0, ""
336 };
337
338 static CGEN_KEYWORD_ENTRY cris_cgen_opval_h_inc_entries[] =
339 {
340 { "", 0, {0, {{{0, 0}}}}, 0, 0 },
341 { "+", 1, {0, {{{0, 0}}}}, 0, 0 }
342 };
343
344 CGEN_KEYWORD cris_cgen_opval_h_inc =
345 {
346 & cris_cgen_opval_h_inc_entries[0],
347 2,
348 0, 0, 0, 0, ""
349 };
350
351 static CGEN_KEYWORD_ENTRY cris_cgen_opval_h_ccode_entries[] =
352 {
353 { "cc", 0, {0, {{{0, 0}}}}, 0, 0 },
354 { "cs", 1, {0, {{{0, 0}}}}, 0, 0 },
355 { "ne", 2, {0, {{{0, 0}}}}, 0, 0 },
356 { "eq", 3, {0, {{{0, 0}}}}, 0, 0 },
357 { "vc", 4, {0, {{{0, 0}}}}, 0, 0 },
358 { "vs", 5, {0, {{{0, 0}}}}, 0, 0 },
359 { "pl", 6, {0, {{{0, 0}}}}, 0, 0 },
360 { "mi", 7, {0, {{{0, 0}}}}, 0, 0 },
361 { "ls", 8, {0, {{{0, 0}}}}, 0, 0 },
362 { "hi", 9, {0, {{{0, 0}}}}, 0, 0 },
363 { "ge", 10, {0, {{{0, 0}}}}, 0, 0 },
364 { "lt", 11, {0, {{{0, 0}}}}, 0, 0 },
365 { "gt", 12, {0, {{{0, 0}}}}, 0, 0 },
366 { "le", 13, {0, {{{0, 0}}}}, 0, 0 },
367 { "a", 14, {0, {{{0, 0}}}}, 0, 0 },
368 { "wf", 15, {0, {{{0, 0}}}}, 0, 0 }
369 };
370
371 CGEN_KEYWORD cris_cgen_opval_h_ccode =
372 {
373 & cris_cgen_opval_h_ccode_entries[0],
374 16,
375 0, 0, 0, 0, ""
376 };
377
378 static CGEN_KEYWORD_ENTRY cris_cgen_opval_h_swap_entries[] =
379 {
380 { " ", 0, {0, {{{0, 0}}}}, 0, 0 },
381 { "r", 1, {0, {{{0, 0}}}}, 0, 0 },
382 { "b", 2, {0, {{{0, 0}}}}, 0, 0 },
383 { "br", 3, {0, {{{0, 0}}}}, 0, 0 },
384 { "w", 4, {0, {{{0, 0}}}}, 0, 0 },
385 { "wr", 5, {0, {{{0, 0}}}}, 0, 0 },
386 { "wb", 6, {0, {{{0, 0}}}}, 0, 0 },
387 { "wbr", 7, {0, {{{0, 0}}}}, 0, 0 },
388 { "n", 8, {0, {{{0, 0}}}}, 0, 0 },
389 { "nr", 9, {0, {{{0, 0}}}}, 0, 0 },
390 { "nb", 10, {0, {{{0, 0}}}}, 0, 0 },
391 { "nbr", 11, {0, {{{0, 0}}}}, 0, 0 },
392 { "nw", 12, {0, {{{0, 0}}}}, 0, 0 },
393 { "nwr", 13, {0, {{{0, 0}}}}, 0, 0 },
394 { "nwb", 14, {0, {{{0, 0}}}}, 0, 0 },
395 { "nwbr", 15, {0, {{{0, 0}}}}, 0, 0 }
396 };
397
398 CGEN_KEYWORD cris_cgen_opval_h_swap =
399 {
400 & cris_cgen_opval_h_swap_entries[0],
401 16,
402 0, 0, 0, 0, ""
403 };
404
405 static CGEN_KEYWORD_ENTRY cris_cgen_opval_h_flagbits_entries[] =
406 {
407 { "_", 0, {0, {{{0, 0}}}}, 0, 0 },
408 { "c", 1, {0, {{{0, 0}}}}, 0, 0 },
409 { "v", 2, {0, {{{0, 0}}}}, 0, 0 },
410 { "cv", 3, {0, {{{0, 0}}}}, 0, 0 },
411 { "z", 4, {0, {{{0, 0}}}}, 0, 0 },
412 { "cz", 5, {0, {{{0, 0}}}}, 0, 0 },
413 { "vz", 6, {0, {{{0, 0}}}}, 0, 0 },
414 { "cvz", 7, {0, {{{0, 0}}}}, 0, 0 },
415 { "n", 8, {0, {{{0, 0}}}}, 0, 0 },
416 { "cn", 9, {0, {{{0, 0}}}}, 0, 0 },
417 { "vn", 10, {0, {{{0, 0}}}}, 0, 0 },
418 { "cvn", 11, {0, {{{0, 0}}}}, 0, 0 },
419 { "zn", 12, {0, {{{0, 0}}}}, 0, 0 },
420 { "czn", 13, {0, {{{0, 0}}}}, 0, 0 },
421 { "vzn", 14, {0, {{{0, 0}}}}, 0, 0 },
422 { "cvzn", 15, {0, {{{0, 0}}}}, 0, 0 },
423 { "x", 16, {0, {{{0, 0}}}}, 0, 0 },
424 { "cx", 17, {0, {{{0, 0}}}}, 0, 0 },
425 { "vx", 18, {0, {{{0, 0}}}}, 0, 0 },
426 { "cvx", 19, {0, {{{0, 0}}}}, 0, 0 },
427 { "zx", 20, {0, {{{0, 0}}}}, 0, 0 },
428 { "czx", 21, {0, {{{0, 0}}}}, 0, 0 },
429 { "vzx", 22, {0, {{{0, 0}}}}, 0, 0 },
430 { "cvzx", 23, {0, {{{0, 0}}}}, 0, 0 },
431 { "nx", 24, {0, {{{0, 0}}}}, 0, 0 },
432 { "cnx", 25, {0, {{{0, 0}}}}, 0, 0 },
433 { "vnx", 26, {0, {{{0, 0}}}}, 0, 0 },
434 { "cvnx", 27, {0, {{{0, 0}}}}, 0, 0 },
435 { "znx", 28, {0, {{{0, 0}}}}, 0, 0 },
436 { "cznx", 29, {0, {{{0, 0}}}}, 0, 0 },
437 { "vznx", 30, {0, {{{0, 0}}}}, 0, 0 },
438 { "cvznx", 31, {0, {{{0, 0}}}}, 0, 0 },
439 { "i", 32, {0, {{{0, 0}}}}, 0, 0 },
440 { "ci", 33, {0, {{{0, 0}}}}, 0, 0 },
441 { "vi", 34, {0, {{{0, 0}}}}, 0, 0 },
442 { "cvi", 35, {0, {{{0, 0}}}}, 0, 0 },
443 { "zi", 36, {0, {{{0, 0}}}}, 0, 0 },
444 { "czi", 37, {0, {{{0, 0}}}}, 0, 0 },
445 { "vzi", 38, {0, {{{0, 0}}}}, 0, 0 },
446 { "cvzi", 39, {0, {{{0, 0}}}}, 0, 0 },
447 { "ni", 40, {0, {{{0, 0}}}}, 0, 0 },
448 { "cni", 41, {0, {{{0, 0}}}}, 0, 0 },
449 { "vni", 42, {0, {{{0, 0}}}}, 0, 0 },
450 { "cvni", 43, {0, {{{0, 0}}}}, 0, 0 },
451 { "zni", 44, {0, {{{0, 0}}}}, 0, 0 },
452 { "czni", 45, {0, {{{0, 0}}}}, 0, 0 },
453 { "vzni", 46, {0, {{{0, 0}}}}, 0, 0 },
454 { "cvzni", 47, {0, {{{0, 0}}}}, 0, 0 },
455 { "xi", 48, {0, {{{0, 0}}}}, 0, 0 },
456 { "cxi", 49, {0, {{{0, 0}}}}, 0, 0 },
457 { "vxi", 50, {0, {{{0, 0}}}}, 0, 0 },
458 { "cvxi", 51, {0, {{{0, 0}}}}, 0, 0 },
459 { "zxi", 52, {0, {{{0, 0}}}}, 0, 0 },
460 { "czxi", 53, {0, {{{0, 0}}}}, 0, 0 },
461 { "vzxi", 54, {0, {{{0, 0}}}}, 0, 0 },
462 { "cvzxi", 55, {0, {{{0, 0}}}}, 0, 0 },
463 { "nxi", 56, {0, {{{0, 0}}}}, 0, 0 },
464 { "cnxi", 57, {0, {{{0, 0}}}}, 0, 0 },
465 { "vnxi", 58, {0, {{{0, 0}}}}, 0, 0 },
466 { "cvnxi", 59, {0, {{{0, 0}}}}, 0, 0 },
467 { "znxi", 60, {0, {{{0, 0}}}}, 0, 0 },
468 { "cznxi", 61, {0, {{{0, 0}}}}, 0, 0 },
469 { "vznxi", 62, {0, {{{0, 0}}}}, 0, 0 },
470 { "cvznxi", 63, {0, {{{0, 0}}}}, 0, 0 },
471 { "u", 64, {0, {{{0, 0}}}}, 0, 0 },
472 { "cu", 65, {0, {{{0, 0}}}}, 0, 0 },
473 { "vu", 66, {0, {{{0, 0}}}}, 0, 0 },
474 { "cvu", 67, {0, {{{0, 0}}}}, 0, 0 },
475 { "zu", 68, {0, {{{0, 0}}}}, 0, 0 },
476 { "czu", 69, {0, {{{0, 0}}}}, 0, 0 },
477 { "vzu", 70, {0, {{{0, 0}}}}, 0, 0 },
478 { "cvzu", 71, {0, {{{0, 0}}}}, 0, 0 },
479 { "nu", 72, {0, {{{0, 0}}}}, 0, 0 },
480 { "cnu", 73, {0, {{{0, 0}}}}, 0, 0 },
481 { "vnu", 74, {0, {{{0, 0}}}}, 0, 0 },
482 { "cvnu", 75, {0, {{{0, 0}}}}, 0, 0 },
483 { "znu", 76, {0, {{{0, 0}}}}, 0, 0 },
484 { "cznu", 77, {0, {{{0, 0}}}}, 0, 0 },
485 { "vznu", 78, {0, {{{0, 0}}}}, 0, 0 },
486 { "cvznu", 79, {0, {{{0, 0}}}}, 0, 0 },
487 { "xu", 80, {0, {{{0, 0}}}}, 0, 0 },
488 { "cxu", 81, {0, {{{0, 0}}}}, 0, 0 },
489 { "vxu", 82, {0, {{{0, 0}}}}, 0, 0 },
490 { "cvxu", 83, {0, {{{0, 0}}}}, 0, 0 },
491 { "zxu", 84, {0, {{{0, 0}}}}, 0, 0 },
492 { "czxu", 85, {0, {{{0, 0}}}}, 0, 0 },
493 { "vzxu", 86, {0, {{{0, 0}}}}, 0, 0 },
494 { "cvzxu", 87, {0, {{{0, 0}}}}, 0, 0 },
495 { "nxu", 88, {0, {{{0, 0}}}}, 0, 0 },
496 { "cnxu", 89, {0, {{{0, 0}}}}, 0, 0 },
497 { "vnxu", 90, {0, {{{0, 0}}}}, 0, 0 },
498 { "cvnxu", 91, {0, {{{0, 0}}}}, 0, 0 },
499 { "znxu", 92, {0, {{{0, 0}}}}, 0, 0 },
500 { "cznxu", 93, {0, {{{0, 0}}}}, 0, 0 },
501 { "vznxu", 94, {0, {{{0, 0}}}}, 0, 0 },
502 { "cvznxu", 95, {0, {{{0, 0}}}}, 0, 0 },
503 { "iu", 96, {0, {{{0, 0}}}}, 0, 0 },
504 { "ciu", 97, {0, {{{0, 0}}}}, 0, 0 },
505 { "viu", 98, {0, {{{0, 0}}}}, 0, 0 },
506 { "cviu", 99, {0, {{{0, 0}}}}, 0, 0 },
507 { "ziu", 100, {0, {{{0, 0}}}}, 0, 0 },
508 { "cziu", 101, {0, {{{0, 0}}}}, 0, 0 },
509 { "vziu", 102, {0, {{{0, 0}}}}, 0, 0 },
510 { "cvziu", 103, {0, {{{0, 0}}}}, 0, 0 },
511 { "niu", 104, {0, {{{0, 0}}}}, 0, 0 },
512 { "cniu", 105, {0, {{{0, 0}}}}, 0, 0 },
513 { "vniu", 106, {0, {{{0, 0}}}}, 0, 0 },
514 { "cvniu", 107, {0, {{{0, 0}}}}, 0, 0 },
515 { "zniu", 108, {0, {{{0, 0}}}}, 0, 0 },
516 { "czniu", 109, {0, {{{0, 0}}}}, 0, 0 },
517 { "vzniu", 110, {0, {{{0, 0}}}}, 0, 0 },
518 { "cvzniu", 111, {0, {{{0, 0}}}}, 0, 0 },
519 { "xiu", 112, {0, {{{0, 0}}}}, 0, 0 },
520 { "cxiu", 113, {0, {{{0, 0}}}}, 0, 0 },
521 { "vxiu", 114, {0, {{{0, 0}}}}, 0, 0 },
522 { "cvxiu", 115, {0, {{{0, 0}}}}, 0, 0 },
523 { "zxiu", 116, {0, {{{0, 0}}}}, 0, 0 },
524 { "czxiu", 117, {0, {{{0, 0}}}}, 0, 0 },
525 { "vzxiu", 118, {0, {{{0, 0}}}}, 0, 0 },
526 { "cvzxiu", 119, {0, {{{0, 0}}}}, 0, 0 },
527 { "nxiu", 120, {0, {{{0, 0}}}}, 0, 0 },
528 { "cnxiu", 121, {0, {{{0, 0}}}}, 0, 0 },
529 { "vnxiu", 122, {0, {{{0, 0}}}}, 0, 0 },
530 { "cvnxiu", 123, {0, {{{0, 0}}}}, 0, 0 },
531 { "znxiu", 124, {0, {{{0, 0}}}}, 0, 0 },
532 { "cznxiu", 125, {0, {{{0, 0}}}}, 0, 0 },
533 { "vznxiu", 126, {0, {{{0, 0}}}}, 0, 0 },
534 { "cvznxiu", 127, {0, {{{0, 0}}}}, 0, 0 },
535 { "p", 128, {0, {{{0, 0}}}}, 0, 0 },
536 { "cp", 129, {0, {{{0, 0}}}}, 0, 0 },
537 { "vp", 130, {0, {{{0, 0}}}}, 0, 0 },
538 { "cvp", 131, {0, {{{0, 0}}}}, 0, 0 },
539 { "zp", 132, {0, {{{0, 0}}}}, 0, 0 },
540 { "czp", 133, {0, {{{0, 0}}}}, 0, 0 },
541 { "vzp", 134, {0, {{{0, 0}}}}, 0, 0 },
542 { "cvzp", 135, {0, {{{0, 0}}}}, 0, 0 },
543 { "np", 136, {0, {{{0, 0}}}}, 0, 0 },
544 { "cnp", 137, {0, {{{0, 0}}}}, 0, 0 },
545 { "vnp", 138, {0, {{{0, 0}}}}, 0, 0 },
546 { "cvnp", 139, {0, {{{0, 0}}}}, 0, 0 },
547 { "znp", 140, {0, {{{0, 0}}}}, 0, 0 },
548 { "cznp", 141, {0, {{{0, 0}}}}, 0, 0 },
549 { "vznp", 142, {0, {{{0, 0}}}}, 0, 0 },
550 { "cvznp", 143, {0, {{{0, 0}}}}, 0, 0 },
551 { "xp", 144, {0, {{{0, 0}}}}, 0, 0 },
552 { "cxp", 145, {0, {{{0, 0}}}}, 0, 0 },
553 { "vxp", 146, {0, {{{0, 0}}}}, 0, 0 },
554 { "cvxp", 147, {0, {{{0, 0}}}}, 0, 0 },
555 { "zxp", 148, {0, {{{0, 0}}}}, 0, 0 },
556 { "czxp", 149, {0, {{{0, 0}}}}, 0, 0 },
557 { "vzxp", 150, {0, {{{0, 0}}}}, 0, 0 },
558 { "cvzxp", 151, {0, {{{0, 0}}}}, 0, 0 },
559 { "nxp", 152, {0, {{{0, 0}}}}, 0, 0 },
560 { "cnxp", 153, {0, {{{0, 0}}}}, 0, 0 },
561 { "vnxp", 154, {0, {{{0, 0}}}}, 0, 0 },
562 { "cvnxp", 155, {0, {{{0, 0}}}}, 0, 0 },
563 { "znxp", 156, {0, {{{0, 0}}}}, 0, 0 },
564 { "cznxp", 157, {0, {{{0, 0}}}}, 0, 0 },
565 { "vznxp", 158, {0, {{{0, 0}}}}, 0, 0 },
566 { "cvznxp", 159, {0, {{{0, 0}}}}, 0, 0 },
567 { "ip", 160, {0, {{{0, 0}}}}, 0, 0 },
568 { "cip", 161, {0, {{{0, 0}}}}, 0, 0 },
569 { "vip", 162, {0, {{{0, 0}}}}, 0, 0 },
570 { "cvip", 163, {0, {{{0, 0}}}}, 0, 0 },
571 { "zip", 164, {0, {{{0, 0}}}}, 0, 0 },
572 { "czip", 165, {0, {{{0, 0}}}}, 0, 0 },
573 { "vzip", 166, {0, {{{0, 0}}}}, 0, 0 },
574 { "cvzip", 167, {0, {{{0, 0}}}}, 0, 0 },
575 { "nip", 168, {0, {{{0, 0}}}}, 0, 0 },
576 { "cnip", 169, {0, {{{0, 0}}}}, 0, 0 },
577 { "vnip", 170, {0, {{{0, 0}}}}, 0, 0 },
578 { "cvnip", 171, {0, {{{0, 0}}}}, 0, 0 },
579 { "znip", 172, {0, {{{0, 0}}}}, 0, 0 },
580 { "cznip", 173, {0, {{{0, 0}}}}, 0, 0 },
581 { "vznip", 174, {0, {{{0, 0}}}}, 0, 0 },
582 { "cvznip", 175, {0, {{{0, 0}}}}, 0, 0 },
583 { "xip", 176, {0, {{{0, 0}}}}, 0, 0 },
584 { "cxip", 177, {0, {{{0, 0}}}}, 0, 0 },
585 { "vxip", 178, {0, {{{0, 0}}}}, 0, 0 },
586 { "cvxip", 179, {0, {{{0, 0}}}}, 0, 0 },
587 { "zxip", 180, {0, {{{0, 0}}}}, 0, 0 },
588 { "czxip", 181, {0, {{{0, 0}}}}, 0, 0 },
589 { "vzxip", 182, {0, {{{0, 0}}}}, 0, 0 },
590 { "cvzxip", 183, {0, {{{0, 0}}}}, 0, 0 },
591 { "nxip", 184, {0, {{{0, 0}}}}, 0, 0 },
592 { "cnxip", 185, {0, {{{0, 0}}}}, 0, 0 },
593 { "vnxip", 186, {0, {{{0, 0}}}}, 0, 0 },
594 { "cvnxip", 187, {0, {{{0, 0}}}}, 0, 0 },
595 { "znxip", 188, {0, {{{0, 0}}}}, 0, 0 },
596 { "cznxip", 189, {0, {{{0, 0}}}}, 0, 0 },
597 { "vznxip", 190, {0, {{{0, 0}}}}, 0, 0 },
598 { "cvznxip", 191, {0, {{{0, 0}}}}, 0, 0 },
599 { "up", 192, {0, {{{0, 0}}}}, 0, 0 },
600 { "cup", 193, {0, {{{0, 0}}}}, 0, 0 },
601 { "vup", 194, {0, {{{0, 0}}}}, 0, 0 },
602 { "cvup", 195, {0, {{{0, 0}}}}, 0, 0 },
603 { "zup", 196, {0, {{{0, 0}}}}, 0, 0 },
604 { "czup", 197, {0, {{{0, 0}}}}, 0, 0 },
605 { "vzup", 198, {0, {{{0, 0}}}}, 0, 0 },
606 { "cvzup", 199, {0, {{{0, 0}}}}, 0, 0 },
607 { "nup", 200, {0, {{{0, 0}}}}, 0, 0 },
608 { "cnup", 201, {0, {{{0, 0}}}}, 0, 0 },
609 { "vnup", 202, {0, {{{0, 0}}}}, 0, 0 },
610 { "cvnup", 203, {0, {{{0, 0}}}}, 0, 0 },
611 { "znup", 204, {0, {{{0, 0}}}}, 0, 0 },
612 { "cznup", 205, {0, {{{0, 0}}}}, 0, 0 },
613 { "vznup", 206, {0, {{{0, 0}}}}, 0, 0 },
614 { "cvznup", 207, {0, {{{0, 0}}}}, 0, 0 },
615 { "xup", 208, {0, {{{0, 0}}}}, 0, 0 },
616 { "cxup", 209, {0, {{{0, 0}}}}, 0, 0 },
617 { "vxup", 210, {0, {{{0, 0}}}}, 0, 0 },
618 { "cvxup", 211, {0, {{{0, 0}}}}, 0, 0 },
619 { "zxup", 212, {0, {{{0, 0}}}}, 0, 0 },
620 { "czxup", 213, {0, {{{0, 0}}}}, 0, 0 },
621 { "vzxup", 214, {0, {{{0, 0}}}}, 0, 0 },
622 { "cvzxup", 215, {0, {{{0, 0}}}}, 0, 0 },
623 { "nxup", 216, {0, {{{0, 0}}}}, 0, 0 },
624 { "cnxup", 217, {0, {{{0, 0}}}}, 0, 0 },
625 { "vnxup", 218, {0, {{{0, 0}}}}, 0, 0 },
626 { "cvnxup", 219, {0, {{{0, 0}}}}, 0, 0 },
627 { "znxup", 220, {0, {{{0, 0}}}}, 0, 0 },
628 { "cznxup", 221, {0, {{{0, 0}}}}, 0, 0 },
629 { "vznxup", 222, {0, {{{0, 0}}}}, 0, 0 },
630 { "cvznxup", 223, {0, {{{0, 0}}}}, 0, 0 },
631 { "iup", 224, {0, {{{0, 0}}}}, 0, 0 },
632 { "ciup", 225, {0, {{{0, 0}}}}, 0, 0 },
633 { "viup", 226, {0, {{{0, 0}}}}, 0, 0 },
634 { "cviup", 227, {0, {{{0, 0}}}}, 0, 0 },
635 { "ziup", 228, {0, {{{0, 0}}}}, 0, 0 },
636 { "cziup", 229, {0, {{{0, 0}}}}, 0, 0 },
637 { "vziup", 230, {0, {{{0, 0}}}}, 0, 0 },
638 { "cvziup", 231, {0, {{{0, 0}}}}, 0, 0 },
639 { "niup", 232, {0, {{{0, 0}}}}, 0, 0 },
640 { "cniup", 233, {0, {{{0, 0}}}}, 0, 0 },
641 { "vniup", 234, {0, {{{0, 0}}}}, 0, 0 },
642 { "cvniup", 235, {0, {{{0, 0}}}}, 0, 0 },
643 { "zniup", 236, {0, {{{0, 0}}}}, 0, 0 },
644 { "czniup", 237, {0, {{{0, 0}}}}, 0, 0 },
645 { "vzniup", 238, {0, {{{0, 0}}}}, 0, 0 },
646 { "cvzniup", 239, {0, {{{0, 0}}}}, 0, 0 },
647 { "xiup", 240, {0, {{{0, 0}}}}, 0, 0 },
648 { "cxiup", 241, {0, {{{0, 0}}}}, 0, 0 },
649 { "vxiup", 242, {0, {{{0, 0}}}}, 0, 0 },
650 { "cvxiup", 243, {0, {{{0, 0}}}}, 0, 0 },
651 { "zxiup", 244, {0, {{{0, 0}}}}, 0, 0 },
652 { "czxiup", 245, {0, {{{0, 0}}}}, 0, 0 },
653 { "vzxiup", 246, {0, {{{0, 0}}}}, 0, 0 },
654 { "cvzxiup", 247, {0, {{{0, 0}}}}, 0, 0 },
655 { "nxiup", 248, {0, {{{0, 0}}}}, 0, 0 },
656 { "cnxiup", 249, {0, {{{0, 0}}}}, 0, 0 },
657 { "vnxiup", 250, {0, {{{0, 0}}}}, 0, 0 },
658 { "cvnxiup", 251, {0, {{{0, 0}}}}, 0, 0 },
659 { "znxiup", 252, {0, {{{0, 0}}}}, 0, 0 },
660 { "cznxiup", 253, {0, {{{0, 0}}}}, 0, 0 },
661 { "vznxiup", 254, {0, {{{0, 0}}}}, 0, 0 },
662 { "cvznxiup", 255, {0, {{{0, 0}}}}, 0, 0 }
663 };
664
665 CGEN_KEYWORD cris_cgen_opval_h_flagbits =
666 {
667 & cris_cgen_opval_h_flagbits_entries[0],
668 256,
669 0, 0, 0, 0, ""
670 };
671
672 static CGEN_KEYWORD_ENTRY cris_cgen_opval_h_supr_entries[] =
673 {
674 { "S0", 0, {0, {{{0, 0}}}}, 0, 0 },
675 { "S1", 1, {0, {{{0, 0}}}}, 0, 0 },
676 { "S2", 2, {0, {{{0, 0}}}}, 0, 0 },
677 { "S3", 3, {0, {{{0, 0}}}}, 0, 0 },
678 { "S4", 4, {0, {{{0, 0}}}}, 0, 0 },
679 { "S5", 5, {0, {{{0, 0}}}}, 0, 0 },
680 { "S6", 6, {0, {{{0, 0}}}}, 0, 0 },
681 { "S7", 7, {0, {{{0, 0}}}}, 0, 0 },
682 { "S8", 8, {0, {{{0, 0}}}}, 0, 0 },
683 { "S9", 9, {0, {{{0, 0}}}}, 0, 0 },
684 { "S10", 10, {0, {{{0, 0}}}}, 0, 0 },
685 { "S11", 11, {0, {{{0, 0}}}}, 0, 0 },
686 { "S12", 12, {0, {{{0, 0}}}}, 0, 0 },
687 { "S13", 13, {0, {{{0, 0}}}}, 0, 0 },
688 { "S14", 14, {0, {{{0, 0}}}}, 0, 0 },
689 { "S15", 15, {0, {{{0, 0}}}}, 0, 0 }
690 };
691
692 CGEN_KEYWORD cris_cgen_opval_h_supr =
693 {
694 & cris_cgen_opval_h_supr_entries[0],
695 16,
696 0, 0, 0, 0, ""
697 };
698
699
700 /* The hardware table. */
701
702 #define A(a) (1 << CGEN_HW_##a)
703
704 const CGEN_HW_ENTRY cris_cgen_hw_table[] =
705 {
706 { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
707 { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
708 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
709 { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
710 { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
711 { "h-inc", HW_H_INC, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_h_inc, { 0, { { { (1<<MACH_BASE), 0 } } } } },
712 { "h-ccode", HW_H_CCODE, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_h_ccode, { 0, { { { (1<<MACH_BASE), 0 } } } } },
713 { "h-swap", HW_H_SWAP, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_h_swap, { 0, { { { (1<<MACH_BASE), 0 } } } } },
714 { "h-flagbits", HW_H_FLAGBITS, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_h_flagbits, { 0, { { { (1<<MACH_BASE), 0 } } } } },
715 { "h-v32-v32", HW_H_V32, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV32), 0 } } } } },
716 { "h-v32-non-v32", HW_H_V32, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } },
717 { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
718 { "h-gr", HW_H_GR, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
719 { "h-gr-pc", HW_H_GR_X, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_gr_names_pcreg, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } },
720 { "h-gr-real-pc", HW_H_GR_REAL_PC, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_gr_names_pcreg, { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } },
721 { "h-raw-gr-pc", HW_H_RAW_GR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } },
722 { "h-gr-acr", HW_H_GR_X, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_gr_names_acr, { 0, { { { (1<<MACH_CRISV32), 0 } } } } },
723 { "h-raw-gr-acr", HW_H_RAW_GR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV32), 0 } } } } },
724 { "h-sr", HW_H_SR, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
725 { "h-sr-v0", HW_H_SR_X, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_p_names_v10, { 0, { { { (1<<MACH_CRISV0), 0 } } } } },
726 { "h-sr-v3", HW_H_SR_X, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_p_names_v10, { 0, { { { (1<<MACH_CRISV3), 0 } } } } },
727 { "h-sr-v8", HW_H_SR_X, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_p_names_v10, { 0, { { { (1<<MACH_CRISV8), 0 } } } } },
728 { "h-sr-v10", HW_H_SR_X, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_p_names_v10, { 0, { { { (1<<MACH_CRISV10), 0 } } } } },
729 { "h-sr-v32", HW_H_SR_X, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_p_names_v32, { 0, { { { (1<<MACH_CRISV32), 0 } } } } },
730 { "h-supr", HW_H_SUPR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV32), 0 } } } } },
731 { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
732 { "h-cbit-move", HW_H_CBIT_MOVE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
733 { "h-cbit-move-v32", HW_H_CBIT_MOVE_X, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV32), 0 } } } } },
734 { "h-cbit-move-pre-v32", HW_H_CBIT_MOVE_X, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } },
735 { "h-vbit", HW_H_VBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
736 { "h-vbit-move", HW_H_VBIT_MOVE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
737 { "h-vbit-move-v32", HW_H_VBIT_MOVE_X, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV32), 0 } } } } },
738 { "h-vbit-move-pre-v32", HW_H_VBIT_MOVE_X, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } },
739 { "h-zbit", HW_H_ZBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
740 { "h-zbit-move", HW_H_ZBIT_MOVE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
741 { "h-zbit-move-v32", HW_H_ZBIT_MOVE_X, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV32), 0 } } } } },
742 { "h-zbit-move-pre-v32", HW_H_ZBIT_MOVE_X, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } },
743 { "h-nbit", HW_H_NBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
744 { "h-nbit-move", HW_H_NBIT_MOVE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
745 { "h-nbit-move-v32", HW_H_NBIT_MOVE_X, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV32), 0 } } } } },
746 { "h-nbit-move-pre-v32", HW_H_NBIT_MOVE_X, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } },
747 { "h-xbit", HW_H_XBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
748 { "h-ibit", HW_H_IBIT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
749 { "h-ibit-pre-v32", HW_H_IBIT_X, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } },
750 { "h-pbit", HW_H_PBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_CRISV10)|(1<<MACH_CRISV32), 0 } } } } },
751 { "h-rbit", HW_H_RBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_CRISV32), 0 } } } } },
752 { "h-ubit", HW_H_UBIT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
753 { "h-ubit-pre-v32", HW_H_UBIT_X, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_CRISV10), 0 } } } } },
754 { "h-gbit", HW_H_GBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_CRISV32), 0 } } } } },
755 { "h-kernel-sp", HW_H_KERNEL_SP, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_CRISV32), 0 } } } } },
756 { "h-ubit-v32", HW_H_UBIT_X, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_CRISV32), 0 } } } } },
757 { "h-ibit-v32", HW_H_IBIT_X, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_CRISV32), 0 } } } } },
758 { "h-mbit", HW_H_MBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_CRISV32), 0 } } } } },
759 { "h-qbit", HW_H_QBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_CRISV32), 0 } } } } },
760 { "h-sbit", HW_H_SBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_CRISV32), 0 } } } } },
761 { "h-insn-prefixed-p", HW_H_INSN_PREFIXED_P, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
762 { "h-insn-prefixed-p-pre-v32", HW_H_INSN_PREFIXED_P_X, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } },
763 { "h-insn-prefixed-p-v32", HW_H_INSN_PREFIXED_P_X, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV32), 0 } } } } },
764 { "h-prefixreg-pre-v32", HW_H_PREFIXREG, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } },
765 { "h-prefixreg-v32", HW_H_PREFIXREG, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV32), 0 } } } } },
766 { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
767 };
768
769 #undef A
770
771
772 /* The instruction field table. */
773
774 #define A(a) (1 << CGEN_IFLD_##a)
775
776 const CGEN_IFLD cris_cgen_ifld_table[] =
777 {
778 { CRIS_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
779 { CRIS_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
780 { CRIS_F_OPERAND1, "f-operand1", 0, 16, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
781 { CRIS_F_SIZE, "f-size", 0, 16, 5, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
782 { CRIS_F_OPCODE, "f-opcode", 0, 16, 9, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
783 { CRIS_F_MODE, "f-mode", 0, 16, 11, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
784 { CRIS_F_OPERAND2, "f-operand2", 0, 16, 15, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
785 { CRIS_F_MEMMODE, "f-memmode", 0, 16, 10, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
786 { CRIS_F_MEMBIT, "f-membit", 0, 16, 11, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
787 { CRIS_F_B5, "f-b5", 0, 16, 5, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
788 { CRIS_F_OPCODE_HI, "f-opcode-hi", 0, 16, 9, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
789 { CRIS_F_DSTSRC, "f-dstsrc", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
790 { CRIS_F_U6, "f-u6", 0, 16, 5, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } },
791 { CRIS_F_S6, "f-s6", 0, 16, 5, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } },
792 { CRIS_F_U5, "f-u5", 0, 16, 4, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } },
793 { CRIS_F_U4, "f-u4", 0, 16, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
794 { CRIS_F_S8, "f-s8", 0, 16, 7, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
795 { CRIS_F_DISP9_HI, "f-disp9-hi", 0, 16, 0, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
796 { CRIS_F_DISP9_LO, "f-disp9-lo", 0, 16, 7, 7, { 0, { { { (1<<MACH_BASE), 0 } } } } },
797 { CRIS_F_DISP9, "f-disp9", 0, 0, 0, 0,{ 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
798 { CRIS_F_QO, "f-qo", 0, 16, 3, 4, { 0|A(PCREL_ADDR), { { { (1<<MACH_CRISV32), 0 } } } } },
799 { CRIS_F_INDIR_PC__BYTE, "f-indir-pc+-byte", 16, 16, 15, 16, { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } },
800 { CRIS_F_INDIR_PC__WORD, "f-indir-pc+-word", 16, 16, 15, 16, { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } },
801 { CRIS_F_INDIR_PC__WORD_PCREL, "f-indir-pc+-word-pcrel", 16, 16, 15, 16, { 0|A(SIGN_OPT)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
802 { CRIS_F_INDIR_PC__DWORD, "f-indir-pc+-dword", 16, 32, 31, 32, { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } },
803 { CRIS_F_INDIR_PC__DWORD_PCREL, "f-indir-pc+-dword-pcrel", 16, 32, 31, 32, { 0|A(PCREL_ADDR)|A(SIGN_OPT), { { { (1<<MACH_CRISV32), 0 } } } } },
804 { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
805 };
806
807 #undef A
808
809
810
811 /* multi ifield declarations */
812
813 const CGEN_MAYBE_MULTI_IFLD CRIS_F_DSTSRC_MULTI_IFIELD [];
814 const CGEN_MAYBE_MULTI_IFLD CRIS_F_DISP9_MULTI_IFIELD [];
815
816
817 /* multi ifield definitions */
818
819 const CGEN_MAYBE_MULTI_IFLD CRIS_F_DSTSRC_MULTI_IFIELD [] =
820 {
821 { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
822 { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_OPERAND1] } },
823 { 0, { (const PTR) 0 } }
824 };
825 const CGEN_MAYBE_MULTI_IFLD CRIS_F_DISP9_MULTI_IFIELD [] =
826 {
827 { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_DISP9_HI] } },
828 { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_DISP9_LO] } },
829 { 0, { (const PTR) 0 } }
830 };
831
832 /* The operand table. */
833
834 #define A(a) (1 << CGEN_OPERAND_##a)
835 #define OPERAND(op) CRIS_OPERAND_##op
836
837 const CGEN_OPERAND cris_cgen_operand_table[] =
838 {
839 /* pc: program counter */
840 { "pc", CRIS_OPERAND_PC, HW_H_PC, 0, 0,
841 { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_NIL] } },
842 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
843 /* cbit: */
844 { "cbit", CRIS_OPERAND_CBIT, HW_H_CBIT, 0, 0,
845 { 0, { (const PTR) 0 } },
846 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
847 /* cbit-move: cbit for pre-V32, nothing for newer */
848 { "cbit-move", CRIS_OPERAND_CBIT_MOVE, HW_H_CBIT_MOVE, 0, 0,
849 { 0, { (const PTR) 0 } },
850 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
851 /* vbit: */
852 { "vbit", CRIS_OPERAND_VBIT, HW_H_VBIT, 0, 0,
853 { 0, { (const PTR) 0 } },
854 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
855 /* vbit-move: vbit for pre-V32, nothing for newer */
856 { "vbit-move", CRIS_OPERAND_VBIT_MOVE, HW_H_VBIT_MOVE, 0, 0,
857 { 0, { (const PTR) 0 } },
858 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
859 /* zbit: */
860 { "zbit", CRIS_OPERAND_ZBIT, HW_H_ZBIT, 0, 0,
861 { 0, { (const PTR) 0 } },
862 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
863 /* zbit-move: zbit for pre-V32, nothing for newer */
864 { "zbit-move", CRIS_OPERAND_ZBIT_MOVE, HW_H_ZBIT_MOVE, 0, 0,
865 { 0, { (const PTR) 0 } },
866 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
867 /* nbit: */
868 { "nbit", CRIS_OPERAND_NBIT, HW_H_NBIT, 0, 0,
869 { 0, { (const PTR) 0 } },
870 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
871 /* nbit-move: nbit for pre-V32, nothing for newer */
872 { "nbit-move", CRIS_OPERAND_NBIT_MOVE, HW_H_NBIT_MOVE, 0, 0,
873 { 0, { (const PTR) 0 } },
874 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
875 /* xbit: */
876 { "xbit", CRIS_OPERAND_XBIT, HW_H_XBIT, 0, 0,
877 { 0, { (const PTR) 0 } },
878 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
879 /* ibit: */
880 { "ibit", CRIS_OPERAND_IBIT, HW_H_IBIT, 0, 0,
881 { 0, { (const PTR) 0 } },
882 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
883 /* ubit: */
884 { "ubit", CRIS_OPERAND_UBIT, HW_H_UBIT, 0, 0,
885 { 0, { (const PTR) 0 } },
886 { 0|A(SEM_ONLY), { { { (1<<MACH_CRISV10)|(1<<MACH_CRISV32), 0 } } } } },
887 /* pbit: */
888 { "pbit", CRIS_OPERAND_PBIT, HW_H_PBIT, 0, 0,
889 { 0, { (const PTR) 0 } },
890 { 0|A(SEM_ONLY), { { { (1<<MACH_CRISV10)|(1<<MACH_CRISV32), 0 } } } } },
891 /* rbit: carry bit for MCP+restore-P flag bit */
892 { "rbit", CRIS_OPERAND_RBIT, HW_H_RBIT, 0, 0,
893 { 0, { (const PTR) 0 } },
894 { 0|A(SEM_ONLY), { { { (1<<MACH_CRISV32), 0 } } } } },
895 /* sbit: */
896 { "sbit", CRIS_OPERAND_SBIT, HW_H_SBIT, 0, 0,
897 { 0, { (const PTR) 0 } },
898 { 0|A(SEM_ONLY), { { { (1<<MACH_CRISV32), 0 } } } } },
899 /* mbit: */
900 { "mbit", CRIS_OPERAND_MBIT, HW_H_MBIT, 0, 0,
901 { 0, { (const PTR) 0 } },
902 { 0|A(SEM_ONLY), { { { (1<<MACH_CRISV32), 0 } } } } },
903 /* qbit: */
904 { "qbit", CRIS_OPERAND_QBIT, HW_H_QBIT, 0, 0,
905 { 0, { (const PTR) 0 } },
906 { 0|A(SEM_ONLY), { { { (1<<MACH_CRISV32), 0 } } } } },
907 /* prefix-set: Instruction-prefixed flag */
908 { "prefix-set", CRIS_OPERAND_PREFIX_SET, HW_H_INSN_PREFIXED_P, 0, 0,
909 { 0, { (const PTR) 0 } },
910 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
911 /* prefixreg: Prefix address */
912 { "prefixreg", CRIS_OPERAND_PREFIXREG, HW_H_PREFIXREG, 0, 0,
913 { 0, { (const PTR) 0 } },
914 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
915 /* Rs: Source general register */
916 { "Rs", CRIS_OPERAND_RS, HW_H_GR, 3, 4,
917 { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_OPERAND1] } },
918 { 0, { { { (1<<MACH_BASE), 0 } } } } },
919 /* inc: Incrementness of indirect operand */
920 { "inc", CRIS_OPERAND_INC, HW_H_INC, 10, 1,
921 { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_MEMMODE] } },
922 { 0, { { { (1<<MACH_BASE), 0 } } } } },
923 /* Ps: Source special register */
924 { "Ps", CRIS_OPERAND_PS, HW_H_SR, 15, 4,
925 { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
926 { 0, { { { (1<<MACH_BASE), 0 } } } } },
927 /* Ss: Source support register */
928 { "Ss", CRIS_OPERAND_SS, HW_H_SUPR, 15, 4,
929 { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
930 { 0, { { { (1<<MACH_CRISV32), 0 } } } } },
931 /* Sd: Destination support register */
932 { "Sd", CRIS_OPERAND_SD, HW_H_SUPR, 15, 4,
933 { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
934 { 0, { { { (1<<MACH_CRISV32), 0 } } } } },
935 /* i: Quick signed 6-bit */
936 { "i", CRIS_OPERAND_I, HW_H_SINT, 5, 6,
937 { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_S6] } },
938 { 0, { { { (1<<MACH_BASE), 0 } } } } },
939 /* j: Quick unsigned 6-bit */
940 { "j", CRIS_OPERAND_J, HW_H_UINT, 5, 6,
941 { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_U6] } },
942 { 0, { { { (1<<MACH_BASE), 0 } } } } },
943 /* c: Quick unsigned 5-bit */
944 { "c", CRIS_OPERAND_C, HW_H_UINT, 4, 5,
945 { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_U5] } },
946 { 0, { { { (1<<MACH_BASE), 0 } } } } },
947 /* qo: Quick unsigned 4-bit, PC-relative */
948 { "qo", CRIS_OPERAND_QO, HW_H_ADDR, 3, 4,
949 { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_QO] } },
950 { 0|A(PCREL_ADDR), { { { (1<<MACH_CRISV32), 0 } } } } },
951 /* Rd: Destination general register */
952 { "Rd", CRIS_OPERAND_RD, HW_H_GR, 15, 4,
953 { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
954 { 0, { { { (1<<MACH_BASE), 0 } } } } },
955 /* sconst8: Signed byte [PC+] */
956 { "sconst8", CRIS_OPERAND_SCONST8, HW_H_SINT, 15, 16,
957 { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_INDIR_PC__BYTE] } },
958 { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } },
959 /* uconst8: Unsigned byte [PC+] */
960 { "uconst8", CRIS_OPERAND_UCONST8, HW_H_UINT, 15, 16,
961 { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_INDIR_PC__BYTE] } },
962 { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } },
963 /* sconst16: Signed word [PC+] */
964 { "sconst16", CRIS_OPERAND_SCONST16, HW_H_SINT, 15, 16,
965 { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_INDIR_PC__WORD] } },
966 { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } },
967 /* uconst16: Unsigned word [PC+] */
968 { "uconst16", CRIS_OPERAND_UCONST16, HW_H_UINT, 15, 16,
969 { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_INDIR_PC__WORD] } },
970 { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } },
971 /* const32: Dword [PC+] */
972 { "const32", CRIS_OPERAND_CONST32, HW_H_UINT, 31, 32,
973 { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_INDIR_PC__DWORD] } },
974 { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } },
975 /* const32-pcrel: Dword [PC+] */
976 { "const32-pcrel", CRIS_OPERAND_CONST32_PCREL, HW_H_ADDR, 31, 32,
977 { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_INDIR_PC__DWORD_PCREL] } },
978 { 0|A(PCREL_ADDR)|A(SIGN_OPT), { { { (1<<MACH_CRISV32), 0 } } } } },
979 /* Pd: Destination special register */
980 { "Pd", CRIS_OPERAND_PD, HW_H_SR, 15, 4,
981 { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
982 { 0, { { { (1<<MACH_BASE), 0 } } } } },
983 /* o: Signed 8-bit */
984 { "o", CRIS_OPERAND_O, HW_H_SINT, 7, 8,
985 { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_S8] } },
986 { 0, { { { (1<<MACH_BASE), 0 } } } } },
987 /* o-pcrel: 9-bit signed immediate PC-rel */
988 { "o-pcrel", CRIS_OPERAND_O_PCREL, HW_H_IADDR, 0, 8,
989 { 2, { (const PTR) &CRIS_F_DISP9_MULTI_IFIELD[0] } },
990 { 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
991 /* o-word-pcrel: 16-bit signed immediate PC-rel */
992 { "o-word-pcrel", CRIS_OPERAND_O_WORD_PCREL, HW_H_IADDR, 15, 16,
993 { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_INDIR_PC__WORD_PCREL] } },
994 { 0|A(SIGN_OPT)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
995 /* cc: Condition codes */
996 { "cc", CRIS_OPERAND_CC, HW_H_CCODE, 15, 4,
997 { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
998 { 0, { { { (1<<MACH_BASE), 0 } } } } },
999 /* n: Quick unsigned 4-bit */
1000 { "n", CRIS_OPERAND_N, HW_H_UINT, 3, 4,
1001 { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_U4] } },
1002 { 0, { { { (1<<MACH_BASE), 0 } } } } },
1003 /* swapoption: Swap option */
1004 { "swapoption", CRIS_OPERAND_SWAPOPTION, HW_H_SWAP, 15, 4,
1005 { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
1006 { 0, { { { (1<<MACH_BASE), 0 } } } } },
1007 /* list-of-flags: Flag bits as operand */
1008 { "list-of-flags", CRIS_OPERAND_LIST_OF_FLAGS, HW_H_FLAGBITS, 3, 8,
1009 { 2, { (const PTR) &CRIS_F_DSTSRC_MULTI_IFIELD[0] } },
1010 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
1011 /* sentinel */
1012 { 0, 0, 0, 0, 0,
1013 { 0, { (const PTR) 0 } },
1014 { 0, { { { (1<<MACH_BASE), 0 } } } } }
1015 };
1016
1017 #undef A
1018
1019
1020 /* The instruction table. */
1021
1022 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
1023 #define A(a) (1 << CGEN_INSN_##a)
1024
1025 static const CGEN_IBASE cris_cgen_insn_table[MAX_INSNS] =
1026 {
1027 /* Special null first entry.
1028 A `num' value of zero is thus invalid.
1029 Also, the special `invalid' insn resides here. */
1030 { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
1031 /* nop */
1032 {
1033 CRIS_INSN_NOP, "nop", "nop", 16,
1034 { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } }
1035 },
1036 /* move.b move.m ${Rs},${Rd} */
1037 {
1038 CRIS_INSN_MOVE_B_R, "move.b-r", "move.b", 16,
1039 { 0, { { { (1<<MACH_BASE), 0 } } } }
1040 },
1041 /* move.w move.m ${Rs},${Rd} */
1042 {
1043 CRIS_INSN_MOVE_W_R, "move.w-r", "move.w", 16,
1044 { 0, { { { (1<<MACH_BASE), 0 } } } }
1045 },
1046 /* move.d move.m ${Rs},${Rd} */
1047 {
1048 CRIS_INSN_MOVE_D_R, "move.d-r", "move.d", 16,
1049 { 0, { { { (1<<MACH_BASE), 0 } } } }
1050 },
1051 /* move.d PC,${Rd} */
1052 {
1053 CRIS_INSN_MOVEPCR, "movepcr", "move.d", 16,
1054 { 0|A(UNCOND_CTI), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } }
1055 },
1056 /* moveq $i,$Rd */
1057 {
1058 CRIS_INSN_MOVEQ, "moveq", "moveq", 16,
1059 { 0, { { { (1<<MACH_BASE), 0 } } } }
1060 },
1061 /* movs.b movs.m ${Rs},${Rd} */
1062 {
1063 CRIS_INSN_MOVS_B_R, "movs.b-r", "movs.b", 16,
1064 { 0, { { { (1<<MACH_BASE), 0 } } } }
1065 },
1066 /* movs.w movs.m ${Rs},${Rd} */
1067 {
1068 CRIS_INSN_MOVS_W_R, "movs.w-r", "movs.w", 16,
1069 { 0, { { { (1<<MACH_BASE), 0 } } } }
1070 },
1071 /* movu.b movu.m ${Rs},${Rd} */
1072 {
1073 CRIS_INSN_MOVU_B_R, "movu.b-r", "movu.b", 16,
1074 { 0, { { { (1<<MACH_BASE), 0 } } } }
1075 },
1076 /* movu.w movu.m ${Rs},${Rd} */
1077 {
1078 CRIS_INSN_MOVU_W_R, "movu.w-r", "movu.w", 16,
1079 { 0, { { { (1<<MACH_BASE), 0 } } } }
1080 },
1081 /* move.b ${sconst8},${Rd} */
1082 {
1083 CRIS_INSN_MOVECBR, "movecbr", "move.b", 32,
1084 { 0, { { { (1<<MACH_BASE), 0 } } } }
1085 },
1086 /* move.w ${sconst16},${Rd} */
1087 {
1088 CRIS_INSN_MOVECWR, "movecwr", "move.w", 32,
1089 { 0, { { { (1<<MACH_BASE), 0 } } } }
1090 },
1091 /* move.d ${const32},${Rd} */
1092 {
1093 CRIS_INSN_MOVECDR, "movecdr", "move.d", 48,
1094 { 0, { { { (1<<MACH_BASE), 0 } } } }
1095 },
1096 /* movs.b ${sconst8},${Rd} */
1097 {
1098 CRIS_INSN_MOVSCBR, "movscbr", "movs.b", 32,
1099 { 0, { { { (1<<MACH_BASE), 0 } } } }
1100 },
1101 /* movs.w ${sconst16},${Rd} */
1102 {
1103 CRIS_INSN_MOVSCWR, "movscwr", "movs.w", 32,
1104 { 0, { { { (1<<MACH_BASE), 0 } } } }
1105 },
1106 /* movu.b ${uconst8},${Rd} */
1107 {
1108 CRIS_INSN_MOVUCBR, "movucbr", "movu.b", 32,
1109 { 0, { { { (1<<MACH_BASE), 0 } } } }
1110 },
1111 /* movu.w ${uconst16},${Rd} */
1112 {
1113 CRIS_INSN_MOVUCWR, "movucwr", "movu.w", 32,
1114 { 0, { { { (1<<MACH_BASE), 0 } } } }
1115 },
1116 /* addq $j,$Rd */
1117 {
1118 CRIS_INSN_ADDQ, "addq", "addq", 16,
1119 { 0, { { { (1<<MACH_BASE), 0 } } } }
1120 },
1121 /* subq $j,$Rd */
1122 {
1123 CRIS_INSN_SUBQ, "subq", "subq", 16,
1124 { 0, { { { (1<<MACH_BASE), 0 } } } }
1125 },
1126 /* cmp-r.b $Rs,$Rd */
1127 {
1128 CRIS_INSN_CMP_R_B_R, "cmp-r.b-r", "cmp-r.b", 16,
1129 { 0, { { { (1<<MACH_BASE), 0 } } } }
1130 },
1131 /* cmp-r.w $Rs,$Rd */
1132 {
1133 CRIS_INSN_CMP_R_W_R, "cmp-r.w-r", "cmp-r.w", 16,
1134 { 0, { { { (1<<MACH_BASE), 0 } } } }
1135 },
1136 /* cmp-r.d $Rs,$Rd */
1137 {
1138 CRIS_INSN_CMP_R_D_R, "cmp-r.d-r", "cmp-r.d", 16,
1139 { 0, { { { (1<<MACH_BASE), 0 } } } }
1140 },
1141 /* cmp-m.b [${Rs}${inc}],${Rd} */
1142 {
1143 CRIS_INSN_CMP_M_B_M, "cmp-m.b-m", "cmp-m.b", 16,
1144 { 0, { { { (1<<MACH_BASE), 0 } } } }
1145 },
1146 /* cmp-m.w [${Rs}${inc}],${Rd} */
1147 {
1148 CRIS_INSN_CMP_M_W_M, "cmp-m.w-m", "cmp-m.w", 16,
1149 { 0, { { { (1<<MACH_BASE), 0 } } } }
1150 },
1151 /* cmp-m.d [${Rs}${inc}],${Rd} */
1152 {
1153 CRIS_INSN_CMP_M_D_M, "cmp-m.d-m", "cmp-m.d", 16,
1154 { 0, { { { (1<<MACH_BASE), 0 } } } }
1155 },
1156 /* cmp.b $sconst8,$Rd */
1157 {
1158 CRIS_INSN_CMPCBR, "cmpcbr", "cmp.b", 32,
1159 { 0, { { { (1<<MACH_BASE), 0 } } } }
1160 },
1161 /* cmp.w $sconst16,$Rd */
1162 {
1163 CRIS_INSN_CMPCWR, "cmpcwr", "cmp.w", 32,
1164 { 0, { { { (1<<MACH_BASE), 0 } } } }
1165 },
1166 /* cmp.d $const32,$Rd */
1167 {
1168 CRIS_INSN_CMPCDR, "cmpcdr", "cmp.d", 48,
1169 { 0, { { { (1<<MACH_BASE), 0 } } } }
1170 },
1171 /* cmpq $i,$Rd */
1172 {
1173 CRIS_INSN_CMPQ, "cmpq", "cmpq", 16,
1174 { 0, { { { (1<<MACH_BASE), 0 } } } }
1175 },
1176 /* cmps-m.b [${Rs}${inc}],$Rd */
1177 {
1178 CRIS_INSN_CMPS_M_B_M, "cmps-m.b-m", "cmps-m.b", 16,
1179 { 0, { { { (1<<MACH_BASE), 0 } } } }
1180 },
1181 /* cmps-m.w [${Rs}${inc}],$Rd */
1182 {
1183 CRIS_INSN_CMPS_M_W_M, "cmps-m.w-m", "cmps-m.w", 16,
1184 { 0, { { { (1<<MACH_BASE), 0 } } } }
1185 },
1186 /* [${Rs}${inc}],$Rd */
1187 {
1188 CRIS_INSN_CMPSCBR, "cmpscbr", "[", 32,
1189 { 0, { { { (1<<MACH_BASE), 0 } } } }
1190 },
1191 /* [${Rs}${inc}],$Rd */
1192 {
1193 CRIS_INSN_CMPSCWR, "cmpscwr", "[", 32,
1194 { 0, { { { (1<<MACH_BASE), 0 } } } }
1195 },
1196 /* cmpu-m.b [${Rs}${inc}],$Rd */
1197 {
1198 CRIS_INSN_CMPU_M_B_M, "cmpu-m.b-m", "cmpu-m.b", 16,
1199 { 0, { { { (1<<MACH_BASE), 0 } } } }
1200 },
1201 /* cmpu-m.w [${Rs}${inc}],$Rd */
1202 {
1203 CRIS_INSN_CMPU_M_W_M, "cmpu-m.w-m", "cmpu-m.w", 16,
1204 { 0, { { { (1<<MACH_BASE), 0 } } } }
1205 },
1206 /* [${Rs}${inc}],$Rd */
1207 {
1208 CRIS_INSN_CMPUCBR, "cmpucbr", "[", 32,
1209 { 0, { { { (1<<MACH_BASE), 0 } } } }
1210 },
1211 /* [${Rs}${inc}],$Rd */
1212 {
1213 CRIS_INSN_CMPUCWR, "cmpucwr", "[", 32,
1214 { 0, { { { (1<<MACH_BASE), 0 } } } }
1215 },
1216 /* move-m.b [${Rs}${inc}],${Rd} */
1217 {
1218 CRIS_INSN_MOVE_M_B_M, "move-m.b-m", "move-m.b", 16,
1219 { 0, { { { (1<<MACH_BASE), 0 } } } }
1220 },
1221 /* move-m.w [${Rs}${inc}],${Rd} */
1222 {
1223 CRIS_INSN_MOVE_M_W_M, "move-m.w-m", "move-m.w", 16,
1224 { 0, { { { (1<<MACH_BASE), 0 } } } }
1225 },
1226 /* move-m.d [${Rs}${inc}],${Rd} */
1227 {
1228 CRIS_INSN_MOVE_M_D_M, "move-m.d-m", "move-m.d", 16,
1229 { 0, { { { (1<<MACH_BASE), 0 } } } }
1230 },
1231 /* movs-m.b [${Rs}${inc}],${Rd} */
1232 {
1233 CRIS_INSN_MOVS_M_B_M, "movs-m.b-m", "movs-m.b", 16,
1234 { 0, { { { (1<<MACH_BASE), 0 } } } }
1235 },
1236 /* movs-m.w [${Rs}${inc}],${Rd} */
1237 {
1238 CRIS_INSN_MOVS_M_W_M, "movs-m.w-m", "movs-m.w", 16,
1239 { 0, { { { (1<<MACH_BASE), 0 } } } }
1240 },
1241 /* movu-m.b [${Rs}${inc}],${Rd} */
1242 {
1243 CRIS_INSN_MOVU_M_B_M, "movu-m.b-m", "movu-m.b", 16,
1244 { 0, { { { (1<<MACH_BASE), 0 } } } }
1245 },
1246 /* movu-m.w [${Rs}${inc}],${Rd} */
1247 {
1248 CRIS_INSN_MOVU_M_W_M, "movu-m.w-m", "movu-m.w", 16,
1249 { 0, { { { (1<<MACH_BASE), 0 } } } }
1250 },
1251 /* move ${Rs},${Pd} */
1252 {
1253 CRIS_INSN_MOVE_R_SPRV0, "move-r-sprv0", "move", 16,
1254 { 0, { { { (1<<MACH_CRISV0), 0 } } } }
1255 },
1256 /* move ${Rs},${Pd} */
1257 {
1258 CRIS_INSN_MOVE_R_SPRV3, "move-r-sprv3", "move", 16,
1259 { 0, { { { (1<<MACH_CRISV3), 0 } } } }
1260 },
1261 /* move ${Rs},${Pd} */
1262 {
1263 CRIS_INSN_MOVE_R_SPRV8, "move-r-sprv8", "move", 16,
1264 { 0, { { { (1<<MACH_CRISV8), 0 } } } }
1265 },
1266 /* move ${Rs},${Pd} */
1267 {
1268 CRIS_INSN_MOVE_R_SPRV10, "move-r-sprv10", "move", 16,
1269 { 0, { { { (1<<MACH_CRISV10), 0 } } } }
1270 },
1271 /* move ${Rs},${Pd} */
1272 {
1273 CRIS_INSN_MOVE_R_SPRV32, "move-r-sprv32", "move", 16,
1274 { 0, { { { (1<<MACH_CRISV32), 0 } } } }
1275 },
1276 /* move ${Ps},${Rd-sfield} */
1277 {
1278 CRIS_INSN_MOVE_SPR_RV0, "move-spr-rv0", "move", 16,
1279 { 0, { { { (1<<MACH_CRISV0), 0 } } } }
1280 },
1281 /* move ${Ps},${Rd-sfield} */
1282 {
1283 CRIS_INSN_MOVE_SPR_RV3, "move-spr-rv3", "move", 16,
1284 { 0, { { { (1<<MACH_CRISV3), 0 } } } }
1285 },
1286 /* move ${Ps},${Rd-sfield} */
1287 {
1288 CRIS_INSN_MOVE_SPR_RV8, "move-spr-rv8", "move", 16,
1289 { 0, { { { (1<<MACH_CRISV8), 0 } } } }
1290 },
1291 /* move ${Ps},${Rd-sfield} */
1292 {
1293 CRIS_INSN_MOVE_SPR_RV10, "move-spr-rv10", "move", 16,
1294 { 0, { { { (1<<MACH_CRISV10), 0 } } } }
1295 },
1296 /* move ${Ps},${Rd-sfield} */
1297 {
1298 CRIS_INSN_MOVE_SPR_RV32, "move-spr-rv32", "move", 16,
1299 { 0, { { { (1<<MACH_CRISV32), 0 } } } }
1300 },
1301 /* ret/reti/retb */
1302 {
1303 CRIS_INSN_RET_TYPE, "ret-type", "ret/reti/retb", 16,
1304 { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } }
1305 },
1306 /* move [${Rs}${inc}],${Pd} */
1307 {
1308 CRIS_INSN_MOVE_M_SPRV0, "move-m-sprv0", "move", 16,
1309 { 0, { { { (1<<MACH_CRISV0), 0 } } } }
1310 },
1311 /* move [${Rs}${inc}],${Pd} */
1312 {
1313 CRIS_INSN_MOVE_M_SPRV3, "move-m-sprv3", "move", 16,
1314 { 0, { { { (1<<MACH_CRISV3), 0 } } } }
1315 },
1316 /* move [${Rs}${inc}],${Pd} */
1317 {
1318 CRIS_INSN_MOVE_M_SPRV8, "move-m-sprv8", "move", 16,
1319 { 0, { { { (1<<MACH_CRISV8), 0 } } } }
1320 },
1321 /* move [${Rs}${inc}],${Pd} */
1322 {
1323 CRIS_INSN_MOVE_M_SPRV10, "move-m-sprv10", "move", 16,
1324 { 0, { { { (1<<MACH_CRISV10), 0 } } } }
1325 },
1326 /* move [${Rs}${inc}],${Pd} */
1327 {
1328 CRIS_INSN_MOVE_M_SPRV32, "move-m-sprv32", "move", 16,
1329 { 0, { { { (1<<MACH_CRISV32), 0 } } } }
1330 },
1331 /* move ${sconst16},${Pd} */
1332 {
1333 CRIS_INSN_MOVE_C_SPRV0_P5, "move-c-sprv0-p5", "move", 32,
1334 { 0, { { { (1<<MACH_CRISV0), 0 } } } }
1335 },
1336 /* move ${const32},${Pd} */
1337 {
1338 CRIS_INSN_MOVE_C_SPRV0_P9, "move-c-sprv0-p9", "move", 48,
1339 { 0, { { { (1<<MACH_CRISV0), 0 } } } }
1340 },
1341 /* move ${const32},${Pd} */
1342 {
1343 CRIS_INSN_MOVE_C_SPRV0_P10, "move-c-sprv0-p10", "move", 48,
1344 { 0, { { { (1<<MACH_CRISV0), 0 } } } }
1345 },
1346 /* move ${const32},${Pd} */
1347 {
1348 CRIS_INSN_MOVE_C_SPRV0_P11, "move-c-sprv0-p11", "move", 48,
1349 { 0, { { { (1<<MACH_CRISV0), 0 } } } }
1350 },
1351 /* move ${const32},${Pd} */
1352 {
1353 CRIS_INSN_MOVE_C_SPRV0_P12, "move-c-sprv0-p12", "move", 48,
1354 { 0, { { { (1<<MACH_CRISV0), 0 } } } }
1355 },
1356 /* move ${const32},${Pd} */
1357 {
1358 CRIS_INSN_MOVE_C_SPRV0_P13, "move-c-sprv0-p13", "move", 48,
1359 { 0, { { { (1<<MACH_CRISV0), 0 } } } }
1360 },
1361 /* move ${sconst16},${Pd} */
1362 {
1363 CRIS_INSN_MOVE_C_SPRV0_P6, "move-c-sprv0-p6", "move", 32,
1364 { 0, { { { (1<<MACH_CRISV0), 0 } } } }
1365 },
1366 /* move ${sconst16},${Pd} */
1367 {
1368 CRIS_INSN_MOVE_C_SPRV0_P7, "move-c-sprv0-p7", "move", 32,
1369 { 0, { { { (1<<MACH_CRISV0), 0 } } } }
1370 },
1371 /* move ${sconst16},${Pd} */
1372 {
1373 CRIS_INSN_MOVE_C_SPRV3_P5, "move-c-sprv3-p5", "move", 32,
1374 { 0, { { { (1<<MACH_CRISV3), 0 } } } }
1375 },
1376 /* move ${const32},${Pd} */
1377 {
1378 CRIS_INSN_MOVE_C_SPRV3_P9, "move-c-sprv3-p9", "move", 48,
1379 { 0, { { { (1<<MACH_CRISV3), 0 } } } }
1380 },
1381 /* move ${const32},${Pd} */
1382 {
1383 CRIS_INSN_MOVE_C_SPRV3_P10, "move-c-sprv3-p10", "move", 48,
1384 { 0, { { { (1<<MACH_CRISV3), 0 } } } }
1385 },
1386 /* move ${const32},${Pd} */
1387 {
1388 CRIS_INSN_MOVE_C_SPRV3_P11, "move-c-sprv3-p11", "move", 48,
1389 { 0, { { { (1<<MACH_CRISV3), 0 } } } }
1390 },
1391 /* move ${const32},${Pd} */
1392 {
1393 CRIS_INSN_MOVE_C_SPRV3_P12, "move-c-sprv3-p12", "move", 48,
1394 { 0, { { { (1<<MACH_CRISV3), 0 } } } }
1395 },
1396 /* move ${const32},${Pd} */
1397 {
1398 CRIS_INSN_MOVE_C_SPRV3_P13, "move-c-sprv3-p13", "move", 48,
1399 { 0, { { { (1<<MACH_CRISV3), 0 } } } }
1400 },
1401 /* move ${sconst16},${Pd} */
1402 {
1403 CRIS_INSN_MOVE_C_SPRV3_P6, "move-c-sprv3-p6", "move", 32,
1404 { 0, { { { (1<<MACH_CRISV3), 0 } } } }
1405 },
1406 /* move ${sconst16},${Pd} */
1407 {
1408 CRIS_INSN_MOVE_C_SPRV3_P7, "move-c-sprv3-p7", "move", 32,
1409 { 0, { { { (1<<MACH_CRISV3), 0 } } } }
1410 },
1411 /* move ${const32},${Pd} */
1412 {
1413 CRIS_INSN_MOVE_C_SPRV3_P14, "move-c-sprv3-p14", "move", 48,
1414 { 0, { { { (1<<MACH_CRISV3), 0 } } } }
1415 },
1416 /* move ${sconst16},${Pd} */
1417 {
1418 CRIS_INSN_MOVE_C_SPRV8_P5, "move-c-sprv8-p5", "move", 32,
1419 { 0, { { { (1<<MACH_CRISV8), 0 } } } }
1420 },
1421 /* move ${const32},${Pd} */
1422 {
1423 CRIS_INSN_MOVE_C_SPRV8_P9, "move-c-sprv8-p9", "move", 48,
1424 { 0, { { { (1<<MACH_CRISV8), 0 } } } }
1425 },
1426 /* move ${const32},${Pd} */
1427 {
1428 CRIS_INSN_MOVE_C_SPRV8_P10, "move-c-sprv8-p10", "move", 48,
1429 { 0, { { { (1<<MACH_CRISV8), 0 } } } }
1430 },
1431 /* move ${const32},${Pd} */
1432 {
1433 CRIS_INSN_MOVE_C_SPRV8_P11, "move-c-sprv8-p11", "move", 48,
1434 { 0, { { { (1<<MACH_CRISV8), 0 } } } }
1435 },
1436 /* move ${const32},${Pd} */
1437 {
1438 CRIS_INSN_MOVE_C_SPRV8_P12, "move-c-sprv8-p12", "move", 48,
1439 { 0, { { { (1<<MACH_CRISV8), 0 } } } }
1440 },
1441 /* move ${const32},${Pd} */
1442 {
1443 CRIS_INSN_MOVE_C_SPRV8_P13, "move-c-sprv8-p13", "move", 48,
1444 { 0, { { { (1<<MACH_CRISV8), 0 } } } }
1445 },
1446 /* move ${const32},${Pd} */
1447 {
1448 CRIS_INSN_MOVE_C_SPRV8_P14, "move-c-sprv8-p14", "move", 48,
1449 { 0, { { { (1<<MACH_CRISV8), 0 } } } }
1450 },
1451 /* move ${sconst16},${Pd} */
1452 {
1453 CRIS_INSN_MOVE_C_SPRV10_P5, "move-c-sprv10-p5", "move", 32,
1454 { 0, { { { (1<<MACH_CRISV10), 0 } } } }
1455 },
1456 /* move ${const32},${Pd} */
1457 {
1458 CRIS_INSN_MOVE_C_SPRV10_P9, "move-c-sprv10-p9", "move", 48,
1459 { 0, { { { (1<<MACH_CRISV10), 0 } } } }
1460 },
1461 /* move ${const32},${Pd} */
1462 {
1463 CRIS_INSN_MOVE_C_SPRV10_P10, "move-c-sprv10-p10", "move", 48,
1464 { 0, { { { (1<<MACH_CRISV10), 0 } } } }
1465 },
1466 /* move ${const32},${Pd} */
1467 {
1468 CRIS_INSN_MOVE_C_SPRV10_P11, "move-c-sprv10-p11", "move", 48,
1469 { 0, { { { (1<<MACH_CRISV10), 0 } } } }
1470 },
1471 /* move ${const32},${Pd} */
1472 {
1473 CRIS_INSN_MOVE_C_SPRV10_P12, "move-c-sprv10-p12", "move", 48,
1474 { 0, { { { (1<<MACH_CRISV10), 0 } } } }
1475 },
1476 /* move ${const32},${Pd} */
1477 {
1478 CRIS_INSN_MOVE_C_SPRV10_P13, "move-c-sprv10-p13", "move", 48,
1479 { 0, { { { (1<<MACH_CRISV10), 0 } } } }
1480 },
1481 /* move ${const32},${Pd} */
1482 {
1483 CRIS_INSN_MOVE_C_SPRV10_P7, "move-c-sprv10-p7", "move", 48,
1484 { 0, { { { (1<<MACH_CRISV10), 0 } } } }
1485 },
1486 /* move ${const32},${Pd} */
1487 {
1488 CRIS_INSN_MOVE_C_SPRV10_P14, "move-c-sprv10-p14", "move", 48,
1489 { 0, { { { (1<<MACH_CRISV10), 0 } } } }
1490 },
1491 /* move ${const32},${Pd} */
1492 {
1493 CRIS_INSN_MOVE_C_SPRV10_P15, "move-c-sprv10-p15", "move", 48,
1494 { 0, { { { (1<<MACH_CRISV10), 0 } } } }
1495 },
1496 /* move ${const32},${Pd} */
1497 {
1498 CRIS_INSN_MOVE_C_SPRV32_P2, "move-c-sprv32-p2", "move", 48,
1499 { 0, { { { (1<<MACH_CRISV32), 0 } } } }
1500 },
1501 /* move ${const32},${Pd} */
1502 {
1503 CRIS_INSN_MOVE_C_SPRV32_P3, "move-c-sprv32-p3", "move", 48,
1504 { 0, { { { (1<<MACH_CRISV32), 0 } } } }
1505 },
1506 /* move ${const32},${Pd} */
1507 {
1508 CRIS_INSN_MOVE_C_SPRV32_P5, "move-c-sprv32-p5", "move", 48,
1509 { 0, { { { (1<<MACH_CRISV32), 0 } } } }
1510 },
1511 /* move ${const32},${Pd} */
1512 {
1513 CRIS_INSN_MOVE_C_SPRV32_P6, "move-c-sprv32-p6", "move", 48,
1514 { 0, { { { (1<<MACH_CRISV32), 0 } } } }
1515 },
1516 /* move ${const32},${Pd} */
1517 {
1518 CRIS_INSN_MOVE_C_SPRV32_P7, "move-c-sprv32-p7", "move", 48,
1519 { 0, { { { (1<<MACH_CRISV32), 0 } } } }
1520 },
1521 /* move ${const32},${Pd} */
1522 {
1523 CRIS_INSN_MOVE_C_SPRV32_P9, "move-c-sprv32-p9", "move", 48,
1524 { 0, { { { (1<<MACH_CRISV32), 0 } } } }
1525 },
1526 /* move ${const32},${Pd} */
1527 {
1528 CRIS_INSN_MOVE_C_SPRV32_P10, "move-c-sprv32-p10", "move", 48,
1529 { 0, { { { (1<<MACH_CRISV32), 0 } } } }
1530 },
1531 /* move ${const32},${Pd} */
1532 {
1533 CRIS_INSN_MOVE_C_SPRV32_P11, "move-c-sprv32-p11", "move", 48,
1534 { 0, { { { (1<<MACH_CRISV32), 0 } } } }
1535 },
1536 /* move ${const32},${Pd} */
1537 {
1538 CRIS_INSN_MOVE_C_SPRV32_P12, "move-c-sprv32-p12", "move", 48,
1539 { 0, { { { (1<<MACH_CRISV32), 0 } } } }
1540 },
1541 /* move ${const32},${Pd} */
1542 {
1543 CRIS_INSN_MOVE_C_SPRV32_P13, "move-c-sprv32-p13", "move", 48,
1544 { 0, { { { (1<<MACH_CRISV32), 0 } } } }
1545 },
1546 /* move ${const32},${Pd} */
1547 {
1548 CRIS_INSN_MOVE_C_SPRV32_P14, "move-c-sprv32-p14", "move", 48,
1549 { 0, { { { (1<<MACH_CRISV32), 0 } } } }
1550 },
1551 /* move ${const32},${Pd} */
1552 {
1553 CRIS_INSN_MOVE_C_SPRV32_P15, "move-c-sprv32-p15", "move", 48,
1554 { 0, { { { (1<<MACH_CRISV32), 0 } } } }
1555 },
1556 /* move ${Ps},[${Rd-sfield}${inc}] */
1557 {
1558 CRIS_INSN_MOVE_SPR_MV0, "move-spr-mv0", "move", 16,
1559 { 0, { { { (1<<MACH_CRISV0), 0 } } } }
1560 },
1561 /* move ${Ps},[${Rd-sfield}${inc}] */
1562 {
1563 CRIS_INSN_MOVE_SPR_MV3, "move-spr-mv3", "move", 16,
1564 { 0, { { { (1<<MACH_CRISV3), 0 } } } }
1565 },
1566 /* move ${Ps},[${Rd-sfield}${inc}] */
1567 {
1568 CRIS_INSN_MOVE_SPR_MV8, "move-spr-mv8", "move", 16,
1569 { 0, { { { (1<<MACH_CRISV8), 0 } } } }
1570 },
1571 /* move ${Ps},[${Rd-sfield}${inc}] */
1572 {
1573 CRIS_INSN_MOVE_SPR_MV10, "move-spr-mv10", "move", 16,
1574 { 0, { { { (1<<MACH_CRISV10), 0 } } } }
1575 },
1576 /* move ${Ps},[${Rd-sfield}${inc}] */
1577 {
1578 CRIS_INSN_MOVE_SPR_MV32, "move-spr-mv32", "move", 16,
1579 { 0, { { { (1<<MACH_CRISV32), 0 } } } }
1580 },
1581 /* sbfs [${Rd-sfield}${inc}] */
1582 {
1583 CRIS_INSN_SBFS, "sbfs", "sbfs", 16,
1584 { 0, { { { (1<<MACH_CRISV10), 0 } } } }
1585 },
1586 /* move ${Ss},${Rd-sfield} */
1587 {
1588 CRIS_INSN_MOVE_SS_R, "move-ss-r", "move", 16,
1589 { 0, { { { (1<<MACH_CRISV32), 0 } } } }
1590 },
1591 /* move ${Rs},${Sd} */
1592 {
1593 CRIS_INSN_MOVE_R_SS, "move-r-ss", "move", 16,
1594 { 0, { { { (1<<MACH_CRISV32), 0 } } } }
1595 },
1596 /* movem ${Rs-dfield},[${Rd-sfield}${inc}] */
1597 {
1598 CRIS_INSN_MOVEM_R_M, "movem-r-m", "movem", 16,
1599 { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } }
1600 },
1601 /* movem ${Rs-dfield},[${Rd-sfield}${inc}] */
1602 {
1603 CRIS_INSN_MOVEM_R_M_V32, "movem-r-m-v32", "movem", 16,
1604 { 0, { { { (1<<MACH_CRISV32), 0 } } } }
1605 },
1606 /* movem [${Rs}${inc}],${Rd} */
1607 {
1608 CRIS_INSN_MOVEM_M_R, "movem-m-r", "movem", 16,
1609 { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } }
1610 },
1611 /* movem [${Rs}${inc}],${Rd} */
1612 {
1613 CRIS_INSN_MOVEM_M_PC, "movem-m-pc", "movem", 16,
1614 { 0|A(UNCOND_CTI), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } }
1615 },
1616 /* movem [${Rs}${inc}],${Rd} */
1617 {
1618 CRIS_INSN_MOVEM_M_R_V32, "movem-m-r-v32", "movem", 16,
1619 { 0, { { { (1<<MACH_CRISV32), 0 } } } }
1620 },
1621 /* add.b $Rs,$Rd */
1622 {
1623 CRIS_INSN_ADD_B_R, "add.b-r", "add.b", 16,
1624 { 0, { { { (1<<MACH_BASE), 0 } } } }
1625 },
1626 /* add.w $Rs,$Rd */
1627 {
1628 CRIS_INSN_ADD_W_R, "add.w-r", "add.w", 16,
1629 { 0, { { { (1<<MACH_BASE), 0 } } } }
1630 },
1631 /* add.d $Rs,$Rd */
1632 {
1633 CRIS_INSN_ADD_D_R, "add.d-r", "add.d", 16,
1634 { 0, { { { (1<<MACH_BASE), 0 } } } }
1635 },
1636 /* add-m.b [${Rs}${inc}],${Rd} */
1637 {
1638 CRIS_INSN_ADD_M_B_M, "add-m.b-m", "add-m.b", 16,
1639 { 0, { { { (1<<MACH_BASE), 0 } } } }
1640 },
1641 /* add-m.w [${Rs}${inc}],${Rd} */
1642 {
1643 CRIS_INSN_ADD_M_W_M, "add-m.w-m", "add-m.w", 16,
1644 { 0, { { { (1<<MACH_BASE), 0 } } } }
1645 },
1646 /* add-m.d [${Rs}${inc}],${Rd} */
1647 {
1648 CRIS_INSN_ADD_M_D_M, "add-m.d-m", "add-m.d", 16,
1649 { 0, { { { (1<<MACH_BASE), 0 } } } }
1650 },
1651 /* add.b ${sconst8}],${Rd} */
1652 {
1653 CRIS_INSN_ADDCBR, "addcbr", "add.b", 32,
1654 { 0, { { { (1<<MACH_BASE), 0 } } } }
1655 },
1656 /* add.w ${sconst16}],${Rd} */
1657 {
1658 CRIS_INSN_ADDCWR, "addcwr", "add.w", 32,
1659 { 0, { { { (1<<MACH_BASE), 0 } } } }
1660 },
1661 /* add.d ${const32}],${Rd} */
1662 {
1663 CRIS_INSN_ADDCDR, "addcdr", "add.d", 48,
1664 { 0, { { { (1<<MACH_BASE), 0 } } } }
1665 },
1666 /* add.d ${sconst32},PC */
1667 {
1668 CRIS_INSN_ADDCPC, "addcpc", "add.d", 48,
1669 { 0|A(UNCOND_CTI), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } }
1670 },
1671 /* adds.b $Rs,$Rd */
1672 {
1673 CRIS_INSN_ADDS_B_R, "adds.b-r", "adds.b", 16,
1674 { 0, { { { (1<<MACH_BASE), 0 } } } }
1675 },
1676 /* adds.w $Rs,$Rd */
1677 {
1678 CRIS_INSN_ADDS_W_R, "adds.w-r", "adds.w", 16,
1679 { 0, { { { (1<<MACH_BASE), 0 } } } }
1680 },
1681 /* adds-m.b [${Rs}${inc}],$Rd */
1682 {
1683 CRIS_INSN_ADDS_M_B_M, "adds-m.b-m", "adds-m.b", 16,
1684 { 0, { { { (1<<MACH_BASE), 0 } } } }
1685 },
1686 /* adds-m.w [${Rs}${inc}],$Rd */
1687 {
1688 CRIS_INSN_ADDS_M_W_M, "adds-m.w-m", "adds-m.w", 16,
1689 { 0, { { { (1<<MACH_BASE), 0 } } } }
1690 },
1691 /* [${Rs}${inc}],$Rd */
1692 {
1693 CRIS_INSN_ADDSCBR, "addscbr", "[", 32,
1694 { 0, { { { (1<<MACH_BASE), 0 } } } }
1695 },
1696 /* [${Rs}${inc}],$Rd */
1697 {
1698 CRIS_INSN_ADDSCWR, "addscwr", "[", 32,
1699 { 0, { { { (1<<MACH_BASE), 0 } } } }
1700 },
1701 /* adds.w [PC],PC */
1702 {
1703 CRIS_INSN_ADDSPCPC, "addspcpc", "adds.w", 16,
1704 { 0|A(UNCOND_CTI), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } }
1705 },
1706 /* addu.b $Rs,$Rd */
1707 {
1708 CRIS_INSN_ADDU_B_R, "addu.b-r", "addu.b", 16,
1709 { 0, { { { (1<<MACH_BASE), 0 } } } }
1710 },
1711 /* addu.w $Rs,$Rd */
1712 {
1713 CRIS_INSN_ADDU_W_R, "addu.w-r", "addu.w", 16,
1714 { 0, { { { (1<<MACH_BASE), 0 } } } }
1715 },
1716 /* addu-m.b [${Rs}${inc}],$Rd */
1717 {
1718 CRIS_INSN_ADDU_M_B_M, "addu-m.b-m", "addu-m.b", 16,
1719 { 0, { { { (1<<MACH_BASE), 0 } } } }
1720 },
1721 /* addu-m.w [${Rs}${inc}],$Rd */
1722 {
1723 CRIS_INSN_ADDU_M_W_M, "addu-m.w-m", "addu-m.w", 16,
1724 { 0, { { { (1<<MACH_BASE), 0 } } } }
1725 },
1726 /* [${Rs}${inc}],$Rd */
1727 {
1728 CRIS_INSN_ADDUCBR, "adducbr", "[", 32,
1729 { 0, { { { (1<<MACH_BASE), 0 } } } }
1730 },
1731 /* [${Rs}${inc}],$Rd */
1732 {
1733 CRIS_INSN_ADDUCWR, "adducwr", "[", 32,
1734 { 0, { { { (1<<MACH_BASE), 0 } } } }
1735 },
1736 /* sub.b $Rs,$Rd */
1737 {
1738 CRIS_INSN_SUB_B_R, "sub.b-r", "sub.b", 16,
1739 { 0, { { { (1<<MACH_BASE), 0 } } } }
1740 },
1741 /* sub.w $Rs,$Rd */
1742 {
1743 CRIS_INSN_SUB_W_R, "sub.w-r", "sub.w", 16,
1744 { 0, { { { (1<<MACH_BASE), 0 } } } }
1745 },
1746 /* sub.d $Rs,$Rd */
1747 {
1748 CRIS_INSN_SUB_D_R, "sub.d-r", "sub.d", 16,
1749 { 0, { { { (1<<MACH_BASE), 0 } } } }
1750 },
1751 /* sub-m.b [${Rs}${inc}],${Rd} */
1752 {
1753 CRIS_INSN_SUB_M_B_M, "sub-m.b-m", "sub-m.b", 16,
1754 { 0, { { { (1<<MACH_BASE), 0 } } } }
1755 },
1756 /* sub-m.w [${Rs}${inc}],${Rd} */
1757 {
1758 CRIS_INSN_SUB_M_W_M, "sub-m.w-m", "sub-m.w", 16,
1759 { 0, { { { (1<<MACH_BASE), 0 } } } }
1760 },
1761 /* sub-m.d [${Rs}${inc}],${Rd} */
1762 {
1763 CRIS_INSN_SUB_M_D_M, "sub-m.d-m", "sub-m.d", 16,
1764 { 0, { { { (1<<MACH_BASE), 0 } } } }
1765 },
1766 /* sub.b ${sconst8}],${Rd} */
1767 {
1768 CRIS_INSN_SUBCBR, "subcbr", "sub.b", 32,
1769 { 0, { { { (1<<MACH_BASE), 0 } } } }
1770 },
1771 /* sub.w ${sconst16}],${Rd} */
1772 {
1773 CRIS_INSN_SUBCWR, "subcwr", "sub.w", 32,
1774 { 0, { { { (1<<MACH_BASE), 0 } } } }
1775 },
1776 /* sub.d ${const32}],${Rd} */
1777 {
1778 CRIS_INSN_SUBCDR, "subcdr", "sub.d", 48,
1779 { 0, { { { (1<<MACH_BASE), 0 } } } }
1780 },
1781 /* subs.b $Rs,$Rd */
1782 {
1783 CRIS_INSN_SUBS_B_R, "subs.b-r", "subs.b", 16,
1784 { 0, { { { (1<<MACH_BASE), 0 } } } }
1785 },
1786 /* subs.w $Rs,$Rd */
1787 {
1788 CRIS_INSN_SUBS_W_R, "subs.w-r", "subs.w", 16,
1789 { 0, { { { (1<<MACH_BASE), 0 } } } }
1790 },
1791 /* subs-m.b [${Rs}${inc}],$Rd */
1792 {
1793 CRIS_INSN_SUBS_M_B_M, "subs-m.b-m", "subs-m.b", 16,
1794 { 0, { { { (1<<MACH_BASE), 0 } } } }
1795 },
1796 /* subs-m.w [${Rs}${inc}],$Rd */
1797 {
1798 CRIS_INSN_SUBS_M_W_M, "subs-m.w-m", "subs-m.w", 16,
1799 { 0, { { { (1<<MACH_BASE), 0 } } } }
1800 },
1801 /* [${Rs}${inc}],$Rd */
1802 {
1803 CRIS_INSN_SUBSCBR, "subscbr", "[", 32,
1804 { 0, { { { (1<<MACH_BASE), 0 } } } }
1805 },
1806 /* [${Rs}${inc}],$Rd */
1807 {
1808 CRIS_INSN_SUBSCWR, "subscwr", "[", 32,
1809 { 0, { { { (1<<MACH_BASE), 0 } } } }
1810 },
1811 /* subu.b $Rs,$Rd */
1812 {
1813 CRIS_INSN_SUBU_B_R, "subu.b-r", "subu.b", 16,
1814 { 0, { { { (1<<MACH_BASE), 0 } } } }
1815 },
1816 /* subu.w $Rs,$Rd */
1817 {
1818 CRIS_INSN_SUBU_W_R, "subu.w-r", "subu.w", 16,
1819 { 0, { { { (1<<MACH_BASE), 0 } } } }
1820 },
1821 /* subu-m.b [${Rs}${inc}],$Rd */
1822 {
1823 CRIS_INSN_SUBU_M_B_M, "subu-m.b-m", "subu-m.b", 16,
1824 { 0, { { { (1<<MACH_BASE), 0 } } } }
1825 },
1826 /* subu-m.w [${Rs}${inc}],$Rd */
1827 {
1828 CRIS_INSN_SUBU_M_W_M, "subu-m.w-m", "subu-m.w", 16,
1829 { 0, { { { (1<<MACH_BASE), 0 } } } }
1830 },
1831 /* [${Rs}${inc}],$Rd */
1832 {
1833 CRIS_INSN_SUBUCBR, "subucbr", "[", 32,
1834 { 0, { { { (1<<MACH_BASE), 0 } } } }
1835 },
1836 /* [${Rs}${inc}],$Rd */
1837 {
1838 CRIS_INSN_SUBUCWR, "subucwr", "[", 32,
1839 { 0, { { { (1<<MACH_BASE), 0 } } } }
1840 },
1841 /* addc $Rs,$Rd */
1842 {
1843 CRIS_INSN_ADDC_R, "addc-r", "addc", 16,
1844 { 0, { { { (1<<MACH_CRISV32), 0 } } } }
1845 },
1846 /* addc [${Rs}${inc}],${Rd} */
1847 {
1848 CRIS_INSN_ADDC_M, "addc-m", "addc", 16,
1849 { 0, { { { (1<<MACH_CRISV32), 0 } } } }
1850 },
1851 /* addc ${const32},${Rd} */
1852 {
1853 CRIS_INSN_ADDC_C, "addc-c", "addc", 48,
1854 { 0, { { { (1<<MACH_CRISV32), 0 } } } }
1855 },
1856 /* lapc.d ${const32-pcrel},${Rd} */
1857 {
1858 CRIS_INSN_LAPC_D, "lapc-d", "lapc.d", 48,
1859 { 0, { { { (1<<MACH_CRISV32), 0 } } } }
1860 },
1861 /* lapcq ${qo},${Rd} */
1862 {
1863 CRIS_INSN_LAPCQ, "lapcq", "lapcq", 16,
1864 { 0, { { { (1<<MACH_CRISV32), 0 } } } }
1865 },
1866 /* addi.b ${Rs-dfield}.m,${Rd-sfield} */
1867 {
1868 CRIS_INSN_ADDI_B_R, "addi.b-r", "addi.b", 16,
1869 { 0, { { { (1<<MACH_BASE), 0 } } } }
1870 },
1871 /* addi.w ${Rs-dfield}.m,${Rd-sfield} */
1872 {
1873 CRIS_INSN_ADDI_W_R, "addi.w-r", "addi.w", 16,
1874 { 0, { { { (1<<MACH_BASE), 0 } } } }
1875 },
1876 /* addi.d ${Rs-dfield}.m,${Rd-sfield} */
1877 {
1878 CRIS_INSN_ADDI_D_R, "addi.d-r", "addi.d", 16,
1879 { 0, { { { (1<<MACH_BASE), 0 } } } }
1880 },
1881 /* neg.b $Rs,$Rd */
1882 {
1883 CRIS_INSN_NEG_B_R, "neg.b-r", "neg.b", 16,
1884 { 0, { { { (1<<MACH_BASE), 0 } } } }
1885 },
1886 /* neg.w $Rs,$Rd */
1887 {
1888 CRIS_INSN_NEG_W_R, "neg.w-r", "neg.w", 16,
1889 { 0, { { { (1<<MACH_BASE), 0 } } } }
1890 },
1891 /* neg.d $Rs,$Rd */
1892 {
1893 CRIS_INSN_NEG_D_R, "neg.d-r", "neg.d", 16,
1894 { 0, { { { (1<<MACH_BASE), 0 } } } }
1895 },
1896 /* test-m.b [${Rs}${inc}] */
1897 {
1898 CRIS_INSN_TEST_M_B_M, "test-m.b-m", "test-m.b", 16,
1899 { 0, { { { (1<<MACH_BASE), 0 } } } }
1900 },
1901 /* test-m.w [${Rs}${inc}] */
1902 {
1903 CRIS_INSN_TEST_M_W_M, "test-m.w-m", "test-m.w", 16,
1904 { 0, { { { (1<<MACH_BASE), 0 } } } }
1905 },
1906 /* test-m.d [${Rs}${inc}] */
1907 {
1908 CRIS_INSN_TEST_M_D_M, "test-m.d-m", "test-m.d", 16,
1909 { 0, { { { (1<<MACH_BASE), 0 } } } }
1910 },
1911 /* move-r-m.b ${Rs-dfield},[${Rd-sfield}${inc}] */
1912 {
1913 CRIS_INSN_MOVE_R_M_B_M, "move-r-m.b-m", "move-r-m.b", 16,
1914 { 0, { { { (1<<MACH_BASE), 0 } } } }
1915 },
1916 /* move-r-m.w ${Rs-dfield},[${Rd-sfield}${inc}] */
1917 {
1918 CRIS_INSN_MOVE_R_M_W_M, "move-r-m.w-m", "move-r-m.w", 16,
1919 { 0, { { { (1<<MACH_BASE), 0 } } } }
1920 },
1921 /* move-r-m.d ${Rs-dfield},[${Rd-sfield}${inc}] */
1922 {
1923 CRIS_INSN_MOVE_R_M_D_M, "move-r-m.d-m", "move-r-m.d", 16,
1924 { 0, { { { (1<<MACH_BASE), 0 } } } }
1925 },
1926 /* muls.b $Rs,$Rd */
1927 {
1928 CRIS_INSN_MULS_B, "muls.b", "muls.b", 16,
1929 { 0, { { { (1<<MACH_CRISV10)|(1<<MACH_CRISV32), 0 } } } }
1930 },
1931 /* muls.w $Rs,$Rd */
1932 {
1933 CRIS_INSN_MULS_W, "muls.w", "muls.w", 16,
1934 { 0, { { { (1<<MACH_CRISV10)|(1<<MACH_CRISV32), 0 } } } }
1935 },
1936 /* muls.d $Rs,$Rd */
1937 {
1938 CRIS_INSN_MULS_D, "muls.d", "muls.d", 16,
1939 { 0, { { { (1<<MACH_CRISV10)|(1<<MACH_CRISV32), 0 } } } }
1940 },
1941 /* mulu.b $Rs,$Rd */
1942 {
1943 CRIS_INSN_MULU_B, "mulu.b", "mulu.b", 16,
1944 { 0, { { { (1<<MACH_CRISV10)|(1<<MACH_CRISV32), 0 } } } }
1945 },
1946 /* mulu.w $Rs,$Rd */
1947 {
1948 CRIS_INSN_MULU_W, "mulu.w", "mulu.w", 16,
1949 { 0, { { { (1<<MACH_CRISV10)|(1<<MACH_CRISV32), 0 } } } }
1950 },
1951 /* mulu.d $Rs,$Rd */
1952 {
1953 CRIS_INSN_MULU_D, "mulu.d", "mulu.d", 16,
1954 { 0, { { { (1<<MACH_CRISV10)|(1<<MACH_CRISV32), 0 } } } }
1955 },
1956 /* mcp $Ps,$Rd */
1957 {
1958 CRIS_INSN_MCP, "mcp", "mcp", 16,
1959 { 0, { { { (1<<MACH_CRISV32), 0 } } } }
1960 },
1961 /* mstep $Rs,$Rd */
1962 {
1963 CRIS_INSN_MSTEP, "mstep", "mstep", 16,
1964 { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } }
1965 },
1966 /* dstep $Rs,$Rd */
1967 {
1968 CRIS_INSN_DSTEP, "dstep", "dstep", 16,
1969 { 0, { { { (1<<MACH_BASE), 0 } } } }
1970 },
1971 /* abs $Rs,$Rd */
1972 {
1973 CRIS_INSN_ABS, "abs", "abs", 16,
1974 { 0, { { { (1<<MACH_BASE), 0 } } } }
1975 },
1976 /* and.b $Rs,$Rd */
1977 {
1978 CRIS_INSN_AND_B_R, "and.b-r", "and.b", 16,
1979 { 0, { { { (1<<MACH_BASE), 0 } } } }
1980 },
1981 /* and.w $Rs,$Rd */
1982 {
1983 CRIS_INSN_AND_W_R, "and.w-r", "and.w", 16,
1984 { 0, { { { (1<<MACH_BASE), 0 } } } }
1985 },
1986 /* and.d $Rs,$Rd */
1987 {
1988 CRIS_INSN_AND_D_R, "and.d-r", "and.d", 16,
1989 { 0, { { { (1<<MACH_BASE), 0 } } } }
1990 },
1991 /* and-m.b [${Rs}${inc}],${Rd} */
1992 {
1993 CRIS_INSN_AND_M_B_M, "and-m.b-m", "and-m.b", 16,
1994 { 0, { { { (1<<MACH_BASE), 0 } } } }
1995 },
1996 /* and-m.w [${Rs}${inc}],${Rd} */
1997 {
1998 CRIS_INSN_AND_M_W_M, "and-m.w-m", "and-m.w", 16,
1999 { 0, { { { (1<<MACH_BASE), 0 } } } }
2000 },
2001 /* and-m.d [${Rs}${inc}],${Rd} */
2002 {
2003 CRIS_INSN_AND_M_D_M, "and-m.d-m", "and-m.d", 16,
2004 { 0, { { { (1<<MACH_BASE), 0 } } } }
2005 },
2006 /* and.b ${sconst8}],${Rd} */
2007 {
2008 CRIS_INSN_ANDCBR, "andcbr", "and.b", 32,
2009 { 0, { { { (1<<MACH_BASE), 0 } } } }
2010 },
2011 /* and.w ${sconst16}],${Rd} */
2012 {
2013 CRIS_INSN_ANDCWR, "andcwr", "and.w", 32,
2014 { 0, { { { (1<<MACH_BASE), 0 } } } }
2015 },
2016 /* and.d ${const32}],${Rd} */
2017 {
2018 CRIS_INSN_ANDCDR, "andcdr", "and.d", 48,
2019 { 0, { { { (1<<MACH_BASE), 0 } } } }
2020 },
2021 /* andq $i,$Rd */
2022 {
2023 CRIS_INSN_ANDQ, "andq", "andq", 16,
2024 { 0, { { { (1<<MACH_BASE), 0 } } } }
2025 },
2026 /* orr.b $Rs,$Rd */
2027 {
2028 CRIS_INSN_ORR_B_R, "orr.b-r", "orr.b", 16,
2029 { 0, { { { (1<<MACH_BASE), 0 } } } }
2030 },
2031 /* orr.w $Rs,$Rd */
2032 {
2033 CRIS_INSN_ORR_W_R, "orr.w-r", "orr.w", 16,
2034 { 0, { { { (1<<MACH_BASE), 0 } } } }
2035 },
2036 /* orr.d $Rs,$Rd */
2037 {
2038 CRIS_INSN_ORR_D_R, "orr.d-r", "orr.d", 16,
2039 { 0, { { { (1<<MACH_BASE), 0 } } } }
2040 },
2041 /* or-m.b [${Rs}${inc}],${Rd} */
2042 {
2043 CRIS_INSN_OR_M_B_M, "or-m.b-m", "or-m.b", 16,
2044 { 0, { { { (1<<MACH_BASE), 0 } } } }
2045 },
2046 /* or-m.w [${Rs}${inc}],${Rd} */
2047 {
2048 CRIS_INSN_OR_M_W_M, "or-m.w-m", "or-m.w", 16,
2049 { 0, { { { (1<<MACH_BASE), 0 } } } }
2050 },
2051 /* or-m.d [${Rs}${inc}],${Rd} */
2052 {
2053 CRIS_INSN_OR_M_D_M, "or-m.d-m", "or-m.d", 16,
2054 { 0, { { { (1<<MACH_BASE), 0 } } } }
2055 },
2056 /* or.b ${sconst8}],${Rd} */
2057 {
2058 CRIS_INSN_ORCBR, "orcbr", "or.b", 32,
2059 { 0, { { { (1<<MACH_BASE), 0 } } } }
2060 },
2061 /* or.w ${sconst16}],${Rd} */
2062 {
2063 CRIS_INSN_ORCWR, "orcwr", "or.w", 32,
2064 { 0, { { { (1<<MACH_BASE), 0 } } } }
2065 },
2066 /* or.d ${const32}],${Rd} */
2067 {
2068 CRIS_INSN_ORCDR, "orcdr", "or.d", 48,
2069 { 0, { { { (1<<MACH_BASE), 0 } } } }
2070 },
2071 /* orq $i,$Rd */
2072 {
2073 CRIS_INSN_ORQ, "orq", "orq", 16,
2074 { 0, { { { (1<<MACH_BASE), 0 } } } }
2075 },
2076 /* xor $Rs,$Rd */
2077 {
2078 CRIS_INSN_XOR, "xor", "xor", 16,
2079 { 0, { { { (1<<MACH_BASE), 0 } } } }
2080 },
2081 /* not ${Rs} */
2082 {
2083 CRIS_INSN_NOT, "not", "not", 16,
2084 { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3), 0 } } } }
2085 },
2086 /* swap${swapoption} ${Rs} */
2087 {
2088 CRIS_INSN_SWAP, "swap", "swap", 16,
2089 { 0, { { { (1<<MACH_CRISV8)|(1<<MACH_CRISV10)|(1<<MACH_CRISV32), 0 } } } }
2090 },
2091 /* asrr.b $Rs,$Rd */
2092 {
2093 CRIS_INSN_ASRR_B_R, "asrr.b-r", "asrr.b", 16,
2094 { 0, { { { (1<<MACH_BASE), 0 } } } }
2095 },
2096 /* asrr.w $Rs,$Rd */
2097 {
2098 CRIS_INSN_ASRR_W_R, "asrr.w-r", "asrr.w", 16,
2099 { 0, { { { (1<<MACH_BASE), 0 } } } }
2100 },
2101 /* asrr.d $Rs,$Rd */
2102 {
2103 CRIS_INSN_ASRR_D_R, "asrr.d-r", "asrr.d", 16,
2104 { 0, { { { (1<<MACH_BASE), 0 } } } }
2105 },
2106 /* asrq $c,${Rd} */
2107 {
2108 CRIS_INSN_ASRQ, "asrq", "asrq", 16,
2109 { 0, { { { (1<<MACH_BASE), 0 } } } }
2110 },
2111 /* lsrr.b $Rs,$Rd */
2112 {
2113 CRIS_INSN_LSRR_B_R, "lsrr.b-r", "lsrr.b", 16,
2114 { 0, { { { (1<<MACH_BASE), 0 } } } }
2115 },
2116 /* lsrr.w $Rs,$Rd */
2117 {
2118 CRIS_INSN_LSRR_W_R, "lsrr.w-r", "lsrr.w", 16,
2119 { 0, { { { (1<<MACH_BASE), 0 } } } }
2120 },
2121 /* lsrr.d $Rs,$Rd */
2122 {
2123 CRIS_INSN_LSRR_D_R, "lsrr.d-r", "lsrr.d", 16,
2124 { 0, { { { (1<<MACH_BASE), 0 } } } }
2125 },
2126 /* lsrq $c,${Rd} */
2127 {
2128 CRIS_INSN_LSRQ, "lsrq", "lsrq", 16,
2129 { 0, { { { (1<<MACH_BASE), 0 } } } }
2130 },
2131 /* lslr.b $Rs,$Rd */
2132 {
2133 CRIS_INSN_LSLR_B_R, "lslr.b-r", "lslr.b", 16,
2134 { 0, { { { (1<<MACH_BASE), 0 } } } }
2135 },
2136 /* lslr.w $Rs,$Rd */
2137 {
2138 CRIS_INSN_LSLR_W_R, "lslr.w-r", "lslr.w", 16,
2139 { 0, { { { (1<<MACH_BASE), 0 } } } }
2140 },
2141 /* lslr.d $Rs,$Rd */
2142 {
2143 CRIS_INSN_LSLR_D_R, "lslr.d-r", "lslr.d", 16,
2144 { 0, { { { (1<<MACH_BASE), 0 } } } }
2145 },
2146 /* lslq $c,${Rd} */
2147 {
2148 CRIS_INSN_LSLQ, "lslq", "lslq", 16,
2149 { 0, { { { (1<<MACH_BASE), 0 } } } }
2150 },
2151 /* $Rs,$Rd */
2152 {
2153 CRIS_INSN_BTST, "btst", "", 16,
2154 { 0, { { { (1<<MACH_BASE), 0 } } } }
2155 },
2156 /* btstq $c,${Rd} */
2157 {
2158 CRIS_INSN_BTSTQ, "btstq", "btstq", 16,
2159 { 0, { { { (1<<MACH_BASE), 0 } } } }
2160 },
2161 /* setf ${list-of-flags} */
2162 {
2163 CRIS_INSN_SETF, "setf", "setf", 16,
2164 { 0, { { { (1<<MACH_BASE), 0 } } } }
2165 },
2166 /* clearf ${list-of-flags} */
2167 {
2168 CRIS_INSN_CLEARF, "clearf", "clearf", 16,
2169 { 0, { { { (1<<MACH_BASE), 0 } } } }
2170 },
2171 /* rfe */
2172 {
2173 CRIS_INSN_RFE, "rfe", "rfe", 16,
2174 { 0, { { { (1<<MACH_CRISV32), 0 } } } }
2175 },
2176 /* sfe */
2177 {
2178 CRIS_INSN_SFE, "sfe", "sfe", 16,
2179 { 0, { { { (1<<MACH_CRISV32), 0 } } } }
2180 },
2181 /* rfg */
2182 {
2183 CRIS_INSN_RFG, "rfg", "rfg", 16,
2184 { 0, { { { (1<<MACH_CRISV32), 0 } } } }
2185 },
2186 /* rfn */
2187 {
2188 CRIS_INSN_RFN, "rfn", "rfn", 16,
2189 { 0, { { { (1<<MACH_CRISV32), 0 } } } }
2190 },
2191 /* halt */
2192 {
2193 CRIS_INSN_HALT, "halt", "halt", 16,
2194 { 0|A(UNCOND_CTI), { { { (1<<MACH_CRISV32), 0 } } } }
2195 },
2196 /* b${cc} ${o-pcrel} */
2197 {
2198 CRIS_INSN_BCC_B, "bcc-b", "b", 16,
2199 { 0|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
2200 },
2201 /* ba ${o-pcrel} */
2202 {
2203 CRIS_INSN_BA_B, "ba-b", "ba", 16,
2204 { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
2205 },
2206 /* b${cc} ${o-word-pcrel} */
2207 {
2208 CRIS_INSN_BCC_W, "bcc-w", "b", 32,
2209 { 0|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
2210 },
2211 /* ba ${o-word-pcrel} */
2212 {
2213 CRIS_INSN_BA_W, "ba-w", "ba", 32,
2214 { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
2215 },
2216 /* jas ${Rs},${Pd} */
2217 {
2218 CRIS_INSN_JAS_R, "jas-r", "jas", 16,
2219 { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_CRISV32), 0 } } } }
2220 },
2221 /* jump/jsr/jir ${Rs} */
2222 {
2223 CRIS_INSN_JUMP_R, "jump-r", "jump/jsr/jir", 16,
2224 { 0|A(UNCOND_CTI), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } }
2225 },
2226 /* jas ${const32},${Pd} */
2227 {
2228 CRIS_INSN_JAS_C, "jas-c", "jas", 48,
2229 { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_CRISV32), 0 } } } }
2230 },
2231 /* jump/jsr/jir [${Rs}${inc}] */
2232 {
2233 CRIS_INSN_JUMP_M, "jump-m", "jump/jsr/jir", 16,
2234 { 0|A(UNCOND_CTI), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } }
2235 },
2236 /* jump/jsr/jir ${const32} */
2237 {
2238 CRIS_INSN_JUMP_C, "jump-c", "jump/jsr/jir", 48,
2239 { 0|A(UNCOND_CTI), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } }
2240 },
2241 /* jump ${Ps} */
2242 {
2243 CRIS_INSN_JUMP_P, "jump-p", "jump", 16,
2244 { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_CRISV32), 0 } } } }
2245 },
2246 /* bas ${const32},${Pd} */
2247 {
2248 CRIS_INSN_BAS_C, "bas-c", "bas", 48,
2249 { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_CRISV32), 0 } } } }
2250 },
2251 /* jasc ${Rs},${Pd} */
2252 {
2253 CRIS_INSN_JASC_R, "jasc-r", "jasc", 16,
2254 { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_CRISV32), 0 } } } }
2255 },
2256 /* jasc ${const32},${Pd} */
2257 {
2258 CRIS_INSN_JASC_C, "jasc-c", "jasc", 48,
2259 { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_CRISV32), 0 } } } }
2260 },
2261 /* basc ${const32},${Pd} */
2262 {
2263 CRIS_INSN_BASC_C, "basc-c", "basc", 48,
2264 { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_CRISV32), 0 } } } }
2265 },
2266 /* break $n */
2267 {
2268 CRIS_INSN_BREAK, "break", "break", 16,
2269 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
2270 },
2271 /* bound-r.b ${Rs},${Rd} */
2272 {
2273 CRIS_INSN_BOUND_R_B_R, "bound-r.b-r", "bound-r.b", 16,
2274 { 0, { { { (1<<MACH_BASE), 0 } } } }
2275 },
2276 /* bound-r.w ${Rs},${Rd} */
2277 {
2278 CRIS_INSN_BOUND_R_W_R, "bound-r.w-r", "bound-r.w", 16,
2279 { 0, { { { (1<<MACH_BASE), 0 } } } }
2280 },
2281 /* bound-r.d ${Rs},${Rd} */
2282 {
2283 CRIS_INSN_BOUND_R_D_R, "bound-r.d-r", "bound-r.d", 16,
2284 { 0, { { { (1<<MACH_BASE), 0 } } } }
2285 },
2286 /* bound-m.b [${Rs}${inc}],${Rd} */
2287 {
2288 CRIS_INSN_BOUND_M_B_M, "bound-m.b-m", "bound-m.b", 16,
2289 { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } }
2290 },
2291 /* bound-m.w [${Rs}${inc}],${Rd} */
2292 {
2293 CRIS_INSN_BOUND_M_W_M, "bound-m.w-m", "bound-m.w", 16,
2294 { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } }
2295 },
2296 /* bound-m.d [${Rs}${inc}],${Rd} */
2297 {
2298 CRIS_INSN_BOUND_M_D_M, "bound-m.d-m", "bound-m.d", 16,
2299 { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } }
2300 },
2301 /* bound.b [PC+],${Rd} */
2302 {
2303 CRIS_INSN_BOUND_CB, "bound-cb", "bound.b", 32,
2304 { 0, { { { (1<<MACH_BASE), 0 } } } }
2305 },
2306 /* bound.w [PC+],${Rd} */
2307 {
2308 CRIS_INSN_BOUND_CW, "bound-cw", "bound.w", 32,
2309 { 0, { { { (1<<MACH_BASE), 0 } } } }
2310 },
2311 /* bound.d [PC+],${Rd} */
2312 {
2313 CRIS_INSN_BOUND_CD, "bound-cd", "bound.d", 48,
2314 { 0, { { { (1<<MACH_BASE), 0 } } } }
2315 },
2316 /* s${cc} ${Rd-sfield} */
2317 {
2318 CRIS_INSN_SCC, "scc", "s", 16,
2319 { 0, { { { (1<<MACH_BASE), 0 } } } }
2320 },
2321 /* lz ${Rs},${Rd} */
2322 {
2323 CRIS_INSN_LZ, "lz", "lz", 16,
2324 { 0, { { { (1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10)|(1<<MACH_CRISV32), 0 } } } }
2325 },
2326 /* addoq $o,$Rs,ACR */
2327 {
2328 CRIS_INSN_ADDOQ, "addoq", "addoq", 16,
2329 { 0, { { { (1<<MACH_BASE), 0 } } } }
2330 },
2331 /* bdapq $o,PC */
2332 {
2333 CRIS_INSN_BDAPQPC, "bdapqpc", "bdapq", 16,
2334 { 0|A(UNCOND_CTI), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } }
2335 },
2336 /* bdap ${sconst32},PC */
2337 {
2338 CRIS_INSN_BDAP_32_PC, "bdap-32-pc", "bdap", 48,
2339 { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } }
2340 },
2341 /* move [PC+],P0 */
2342 {
2343 CRIS_INSN_MOVE_M_PCPLUS_P0, "move-m-pcplus-p0", "move", 16,
2344 { 0|A(COND_CTI), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } }
2345 },
2346 /* move [SP+],P8 */
2347 {
2348 CRIS_INSN_MOVE_M_SPPLUS_P8, "move-m-spplus-p8", "move", 16,
2349 { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } }
2350 },
2351 /* addo-m.b [${Rs}${inc}],$Rd,ACR */
2352 {
2353 CRIS_INSN_ADDO_M_B_M, "addo-m.b-m", "addo-m.b", 16,
2354 { 0, { { { (1<<MACH_BASE), 0 } } } }
2355 },
2356 /* addo-m.w [${Rs}${inc}],$Rd,ACR */
2357 {
2358 CRIS_INSN_ADDO_M_W_M, "addo-m.w-m", "addo-m.w", 16,
2359 { 0, { { { (1<<MACH_BASE), 0 } } } }
2360 },
2361 /* addo-m.d [${Rs}${inc}],$Rd,ACR */
2362 {
2363 CRIS_INSN_ADDO_M_D_M, "addo-m.d-m", "addo-m.d", 16,
2364 { 0, { { { (1<<MACH_BASE), 0 } } } }
2365 },
2366 /* addo.b [PC+],$Rd,ACR */
2367 {
2368 CRIS_INSN_ADDO_CB, "addo-cb", "addo.b", 32,
2369 { 0, { { { (1<<MACH_BASE), 0 } } } }
2370 },
2371 /* addo.w [PC+],$Rd,ACR */
2372 {
2373 CRIS_INSN_ADDO_CW, "addo-cw", "addo.w", 32,
2374 { 0, { { { (1<<MACH_BASE), 0 } } } }
2375 },
2376 /* addo.d [PC+],$Rd,ACR */
2377 {
2378 CRIS_INSN_ADDO_CD, "addo-cd", "addo.d", 48,
2379 { 0, { { { (1<<MACH_BASE), 0 } } } }
2380 },
2381 /* dip [${Rs}${inc}] */
2382 {
2383 CRIS_INSN_DIP_M, "dip-m", "dip", 16,
2384 { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } }
2385 },
2386 /* dip [PC+] */
2387 {
2388 CRIS_INSN_DIP_C, "dip-c", "dip", 48,
2389 { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } }
2390 },
2391 /* addi-acr.b ${Rs-dfield}.m,${Rd-sfield},ACR */
2392 {
2393 CRIS_INSN_ADDI_ACR_B_R, "addi-acr.b-r", "addi-acr.b", 16,
2394 { 0, { { { (1<<MACH_BASE), 0 } } } }
2395 },
2396 /* addi-acr.w ${Rs-dfield}.m,${Rd-sfield},ACR */
2397 {
2398 CRIS_INSN_ADDI_ACR_W_R, "addi-acr.w-r", "addi-acr.w", 16,
2399 { 0, { { { (1<<MACH_BASE), 0 } } } }
2400 },
2401 /* addi-acr.d ${Rs-dfield}.m,${Rd-sfield},ACR */
2402 {
2403 CRIS_INSN_ADDI_ACR_D_R, "addi-acr.d-r", "addi-acr.d", 16,
2404 { 0, { { { (1<<MACH_BASE), 0 } } } }
2405 },
2406 /* biap-pc.b ${Rs-dfield}.m,PC */
2407 {
2408 CRIS_INSN_BIAP_PC_B_R, "biap-pc.b-r", "biap-pc.b", 16,
2409 { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } }
2410 },
2411 /* biap-pc.w ${Rs-dfield}.m,PC */
2412 {
2413 CRIS_INSN_BIAP_PC_W_R, "biap-pc.w-r", "biap-pc.w", 16,
2414 { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } }
2415 },
2416 /* biap-pc.d ${Rs-dfield}.m,PC */
2417 {
2418 CRIS_INSN_BIAP_PC_D_R, "biap-pc.d-r", "biap-pc.d", 16,
2419 { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } }
2420 },
2421 /* fidxi [$Rs] */
2422 {
2423 CRIS_INSN_FIDXI, "fidxi", "fidxi", 16,
2424 { 0|A(UNCOND_CTI), { { { (1<<MACH_CRISV32), 0 } } } }
2425 },
2426 /* fidxi [$Rs] */
2427 {
2428 CRIS_INSN_FTAGI, "ftagi", "fidxi", 16,
2429 { 0|A(UNCOND_CTI), { { { (1<<MACH_CRISV32), 0 } } } }
2430 },
2431 /* fidxd [$Rs] */
2432 {
2433 CRIS_INSN_FIDXD, "fidxd", "fidxd", 16,
2434 { 0|A(UNCOND_CTI), { { { (1<<MACH_CRISV32), 0 } } } }
2435 },
2436 /* ftagd [$Rs] */
2437 {
2438 CRIS_INSN_FTAGD, "ftagd", "ftagd", 16,
2439 { 0|A(UNCOND_CTI), { { { (1<<MACH_CRISV32), 0 } } } }
2440 },
2441 };
2442
2443 #undef OP
2444 #undef A
2445
2446 /* Initialize anything needed to be done once, before any cpu_open call. */
2447
2448 static void
2449 init_tables (void)
2450 {
2451 }
2452
2453 static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
2454 static void build_hw_table (CGEN_CPU_TABLE *);
2455 static void build_ifield_table (CGEN_CPU_TABLE *);
2456 static void build_operand_table (CGEN_CPU_TABLE *);
2457 static void build_insn_table (CGEN_CPU_TABLE *);
2458 static void cris_cgen_rebuild_tables (CGEN_CPU_TABLE *);
2459
2460 /* Subroutine of cris_cgen_cpu_open to look up a mach via its bfd name. */
2461
2462 static const CGEN_MACH *
2463 lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
2464 {
2465 while (table->name)
2466 {
2467 if (strcmp (name, table->bfd_name) == 0)
2468 return table;
2469 ++table;
2470 }
2471 abort ();
2472 }
2473
2474 /* Subroutine of cris_cgen_cpu_open to build the hardware table. */
2475
2476 static void
2477 build_hw_table (CGEN_CPU_TABLE *cd)
2478 {
2479 int i;
2480 int machs = cd->machs;
2481 const CGEN_HW_ENTRY *init = & cris_cgen_hw_table[0];
2482 /* MAX_HW is only an upper bound on the number of selected entries.
2483 However each entry is indexed by it's enum so there can be holes in
2484 the table. */
2485 const CGEN_HW_ENTRY **selected =
2486 (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
2487
2488 cd->hw_table.init_entries = init;
2489 cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
2490 memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
2491 /* ??? For now we just use machs to determine which ones we want. */
2492 for (i = 0; init[i].name != NULL; ++i)
2493 if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
2494 & machs)
2495 selected[init[i].type] = &init[i];
2496 cd->hw_table.entries = selected;
2497 cd->hw_table.num_entries = MAX_HW;
2498 }
2499
2500 /* Subroutine of cris_cgen_cpu_open to build the hardware table. */
2501
2502 static void
2503 build_ifield_table (CGEN_CPU_TABLE *cd)
2504 {
2505 cd->ifld_table = & cris_cgen_ifld_table[0];
2506 }
2507
2508 /* Subroutine of cris_cgen_cpu_open to build the hardware table. */
2509
2510 static void
2511 build_operand_table (CGEN_CPU_TABLE *cd)
2512 {
2513 int i;
2514 int machs = cd->machs;
2515 const CGEN_OPERAND *init = & cris_cgen_operand_table[0];
2516 /* MAX_OPERANDS is only an upper bound on the number of selected entries.
2517 However each entry is indexed by it's enum so there can be holes in
2518 the table. */
2519 const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
2520
2521 cd->operand_table.init_entries = init;
2522 cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
2523 memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
2524 /* ??? For now we just use mach to determine which ones we want. */
2525 for (i = 0; init[i].name != NULL; ++i)
2526 if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
2527 & machs)
2528 selected[init[i].type] = &init[i];
2529 cd->operand_table.entries = selected;
2530 cd->operand_table.num_entries = MAX_OPERANDS;
2531 }
2532
2533 /* Subroutine of cris_cgen_cpu_open to build the hardware table.
2534 ??? This could leave out insns not supported by the specified mach/isa,
2535 but that would cause errors like "foo only supported by bar" to become
2536 "unknown insn", so for now we include all insns and require the app to
2537 do the checking later.
2538 ??? On the other hand, parsing of such insns may require their hardware or
2539 operand elements to be in the table [which they mightn't be]. */
2540
2541 static void
2542 build_insn_table (CGEN_CPU_TABLE *cd)
2543 {
2544 int i;
2545 const CGEN_IBASE *ib = & cris_cgen_insn_table[0];
2546 CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
2547
2548 memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
2549 for (i = 0; i < MAX_INSNS; ++i)
2550 insns[i].base = &ib[i];
2551 cd->insn_table.init_entries = insns;
2552 cd->insn_table.entry_size = sizeof (CGEN_IBASE);
2553 cd->insn_table.num_init_entries = MAX_INSNS;
2554 }
2555
2556 /* Subroutine of cris_cgen_cpu_open to rebuild the tables. */
2557
2558 static void
2559 cris_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
2560 {
2561 int i;
2562 CGEN_BITSET *isas = cd->isas;
2563 unsigned int machs = cd->machs;
2564
2565 cd->int_insn_p = CGEN_INT_INSN_P;
2566
2567 /* Data derived from the isa spec. */
2568 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
2569 cd->default_insn_bitsize = UNSET;
2570 cd->base_insn_bitsize = UNSET;
2571 cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */
2572 cd->max_insn_bitsize = 0;
2573 for (i = 0; i < MAX_ISAS; ++i)
2574 if (cgen_bitset_contains (isas, i))
2575 {
2576 const CGEN_ISA *isa = & cris_cgen_isa_table[i];
2577
2578 /* Default insn sizes of all selected isas must be
2579 equal or we set the result to 0, meaning "unknown". */
2580 if (cd->default_insn_bitsize == UNSET)
2581 cd->default_insn_bitsize = isa->default_insn_bitsize;
2582 else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
2583 ; /* This is ok. */
2584 else
2585 cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
2586
2587 /* Base insn sizes of all selected isas must be equal
2588 or we set the result to 0, meaning "unknown". */
2589 if (cd->base_insn_bitsize == UNSET)
2590 cd->base_insn_bitsize = isa->base_insn_bitsize;
2591 else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
2592 ; /* This is ok. */
2593 else
2594 cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
2595
2596 /* Set min,max insn sizes. */
2597 if (isa->min_insn_bitsize < cd->min_insn_bitsize)
2598 cd->min_insn_bitsize = isa->min_insn_bitsize;
2599 if (isa->max_insn_bitsize > cd->max_insn_bitsize)
2600 cd->max_insn_bitsize = isa->max_insn_bitsize;
2601 }
2602
2603 /* Data derived from the mach spec. */
2604 for (i = 0; i < MAX_MACHS; ++i)
2605 if (((1 << i) & machs) != 0)
2606 {
2607 const CGEN_MACH *mach = & cris_cgen_mach_table[i];
2608
2609 if (mach->insn_chunk_bitsize != 0)
2610 {
2611 if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
2612 {
2613 fprintf (stderr, "cris_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
2614 cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
2615 abort ();
2616 }
2617
2618 cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
2619 }
2620 }
2621
2622 /* Determine which hw elements are used by MACH. */
2623 build_hw_table (cd);
2624
2625 /* Build the ifield table. */
2626 build_ifield_table (cd);
2627
2628 /* Determine which operands are used by MACH/ISA. */
2629 build_operand_table (cd);
2630
2631 /* Build the instruction table. */
2632 build_insn_table (cd);
2633 }
2634
2635 /* Initialize a cpu table and return a descriptor.
2636 It's much like opening a file, and must be the first function called.
2637 The arguments are a set of (type/value) pairs, terminated with
2638 CGEN_CPU_OPEN_END.
2639
2640 Currently supported values:
2641 CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr
2642 CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr
2643 CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
2644 CGEN_CPU_OPEN_ENDIAN: specify endian choice
2645 CGEN_CPU_OPEN_END: terminates arguments
2646
2647 ??? Simultaneous multiple isas might not make sense, but it's not (yet)
2648 precluded. */
2649
2650 CGEN_CPU_DESC
2651 cris_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
2652 {
2653 CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
2654 static int init_p;
2655 CGEN_BITSET *isas = 0; /* 0 = "unspecified" */
2656 unsigned int machs = 0; /* 0 = "unspecified" */
2657 enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
2658 va_list ap;
2659
2660 if (! init_p)
2661 {
2662 init_tables ();
2663 init_p = 1;
2664 }
2665
2666 memset (cd, 0, sizeof (*cd));
2667
2668 va_start (ap, arg_type);
2669 while (arg_type != CGEN_CPU_OPEN_END)
2670 {
2671 switch (arg_type)
2672 {
2673 case CGEN_CPU_OPEN_ISAS :
2674 isas = va_arg (ap, CGEN_BITSET *);
2675 break;
2676 case CGEN_CPU_OPEN_MACHS :
2677 machs = va_arg (ap, unsigned int);
2678 break;
2679 case CGEN_CPU_OPEN_BFDMACH :
2680 {
2681 const char *name = va_arg (ap, const char *);
2682 const CGEN_MACH *mach =
2683 lookup_mach_via_bfd_name (cris_cgen_mach_table, name);
2684
2685 machs |= 1 << mach->num;
2686 break;
2687 }
2688 case CGEN_CPU_OPEN_ENDIAN :
2689 endian = va_arg (ap, enum cgen_endian);
2690 break;
2691 default :
2692 fprintf (stderr, "cris_cgen_cpu_open: unsupported argument `%d'\n",
2693 arg_type);
2694 abort (); /* ??? return NULL? */
2695 }
2696 arg_type = va_arg (ap, enum cgen_cpu_open_arg);
2697 }
2698 va_end (ap);
2699
2700 /* Mach unspecified means "all". */
2701 if (machs == 0)
2702 machs = (1 << MAX_MACHS) - 1;
2703 /* Base mach is always selected. */
2704 machs |= 1;
2705 if (endian == CGEN_ENDIAN_UNKNOWN)
2706 {
2707 /* ??? If target has only one, could have a default. */
2708 fprintf (stderr, "cris_cgen_cpu_open: no endianness specified\n");
2709 abort ();
2710 }
2711
2712 cd->isas = cgen_bitset_copy (isas);
2713 cd->machs = machs;
2714 cd->endian = endian;
2715 /* FIXME: for the sparc case we can determine insn-endianness statically.
2716 The worry here is where both data and insn endian can be independently
2717 chosen, in which case this function will need another argument.
2718 Actually, will want to allow for more arguments in the future anyway. */
2719 cd->insn_endian = endian;
2720
2721 /* Table (re)builder. */
2722 cd->rebuild_tables = cris_cgen_rebuild_tables;
2723 cris_cgen_rebuild_tables (cd);
2724
2725 /* Default to not allowing signed overflow. */
2726 cd->signed_overflow_ok_p = 0;
2727
2728 return (CGEN_CPU_DESC) cd;
2729 }
2730
2731 /* Cover fn to cris_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
2732 MACH_NAME is the bfd name of the mach. */
2733
2734 CGEN_CPU_DESC
2735 cris_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
2736 {
2737 return cris_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
2738 CGEN_CPU_OPEN_ENDIAN, endian,
2739 CGEN_CPU_OPEN_END);
2740 }
2741
2742 /* Close a cpu table.
2743 ??? This can live in a machine independent file, but there's currently
2744 no place to put this file (there's no libcgen). libopcodes is the wrong
2745 place as some simulator ports use this but they don't use libopcodes. */
2746
2747 void
2748 cris_cgen_cpu_close (CGEN_CPU_DESC cd)
2749 {
2750 unsigned int i;
2751 const CGEN_INSN *insns;
2752
2753 if (cd->macro_insn_table.init_entries)
2754 {
2755 insns = cd->macro_insn_table.init_entries;
2756 for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
2757 if (CGEN_INSN_RX ((insns)))
2758 regfree (CGEN_INSN_RX (insns));
2759 }
2760
2761 if (cd->insn_table.init_entries)
2762 {
2763 insns = cd->insn_table.init_entries;
2764 for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
2765 if (CGEN_INSN_RX (insns))
2766 regfree (CGEN_INSN_RX (insns));
2767 }
2768
2769 if (cd->macro_insn_table.init_entries)
2770 free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
2771
2772 if (cd->insn_table.init_entries)
2773 free ((CGEN_INSN *) cd->insn_table.init_entries);
2774
2775 if (cd->hw_table.entries)
2776 free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
2777
2778 if (cd->operand_table.entries)
2779 free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
2780
2781 free (cd);
2782 }
2783
The GNU Binutils are a collection of binary tools.