sim/lm32/dv-lm32uart.c

   1 /*  Lattice Mico32 UART model.
   2     Contributed by Jon Beniston <jon@beniston.com>
   3
   4    Copyright (C) 2009-2020 Free Software Foundation, Inc.
   5
   6    This file is part of GDB.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 #include "sim-main.h"
  22 #include "hw-main.h"
  23 #include "sim-assert.h"
  24
  25 #include <stdio.h>
  26 #include <sys/time.h>
  27
  28 struct lm32uart
  29 {
  30   unsigned base;                /* Base address of this UART.  */
  31   unsigned limit;               /* Limit address of this UART.  */
  32   unsigned char rbr;
  33   unsigned char thr;
  34   unsigned char ier;
  35   unsigned char iir;
  36   unsigned char lcr;
  37   unsigned char mcr;
  38   unsigned char lsr;
  39   unsigned char msr;
  40   unsigned char div;
  41   struct hw_event *event;
  42 };
  43
  44 /* UART registers.  */
  45
  46 #define LM32_UART_RBR           0x0
  47 #define LM32_UART_THR           0x0
  48 #define LM32_UART_IER           0x4
  49 #define LM32_UART_IIR           0x8
  50 #define LM32_UART_LCR           0xc
  51 #define LM32_UART_MCR           0x10
  52 #define LM32_UART_LSR           0x14
  53 #define LM32_UART_MSR           0x18
  54 #define LM32_UART_DIV           0x1c
  55
  56 #define LM32_UART_IER_RX_INT    0x1
  57 #define LM32_UART_IER_TX_INT    0x2
  58
  59 #define MICOUART_IIR_TXRDY      0x2
  60 #define MICOUART_IIR_RXRDY      0x4
  61
  62 #define LM32_UART_LSR_RX_RDY    0x01
  63 #define LM32_UART_LSR_TX_RDY    0x20
  64
  65 #define LM32_UART_LCR_WLS_MASK  0x3
  66 #define LM32_UART_LCR_WLS_5     0x0
  67 #define LM32_UART_LCR_WLS_6     0x1
  68 #define LM32_UART_LCR_WLS_7     0x2
  69 #define LM32_UART_LCR_WLS_8     0x3
  70
  71 /* UART ports.  */
  72
  73 enum
  74 {
  75   INT_PORT
  76 };
  77
  78 static const struct hw_port_descriptor lm32uart_ports[] = {
  79   {"int", INT_PORT, 0, output_port},
  80   {}
  81 };
  82
  83 static void
  84 do_uart_tx_event (struct hw *me, void *data)
  85 {
  86   struct lm32uart *uart = hw_data (me);
  87   char c;
  88
  89   /* Generate interrupt when transmission is complete.  */
  90   if (uart->ier & LM32_UART_IER_TX_INT)
  91     {
  92       /* Generate interrupt */
  93       hw_port_event (me, INT_PORT, 1);
  94     }
  95
  96   /* Indicate which interrupt has occured.  */
  97   uart->iir = MICOUART_IIR_TXRDY;
  98
  99   /* Indicate THR is empty.  */
 100   uart->lsr |= LM32_UART_LSR_TX_RDY;
 101
 102   /* Output the character in the THR.  */
 103   c = (char) uart->thr;
 104
 105   /* WLS field in LCR register specifies the number of bits to output.  */
 106   switch (uart->lcr & LM32_UART_LCR_WLS_MASK)
 107     {
 108     case LM32_UART_LCR_WLS_5:
 109       c &= 0x1f;
 110       break;
 111     case LM32_UART_LCR_WLS_6:
 112       c &= 0x3f;
 113       break;
 114     case LM32_UART_LCR_WLS_7:
 115       c &= 0x7f;
 116       break;
 117     }
 118   printf ("%c", c);
 119 }
 120
 121 static unsigned
 122 lm32uart_io_write_buffer (struct hw *me,
 123                           const void *source,
 124                           int space, unsigned_word base, unsigned nr_bytes)
 125 {
 126   struct lm32uart *uart = hw_data (me);
 127   int uart_reg;
 128   const unsigned char *source_bytes = source;
 129   int value = 0;
 130
 131   HW_TRACE ((me, "write to 0x%08lx length %d with 0x%x", (long) base,
 132              (int) nr_bytes, value));
 133
 134   if (nr_bytes == 4)
 135     value = (source_bytes[0] << 24)
 136       | (source_bytes[1] << 16) | (source_bytes[2] << 8) | (source_bytes[3]);
 137   else
 138     hw_abort (me, "write of unsupported number of bytes: %d.", nr_bytes);
 139
 140   uart_reg = base - uart->base;
 141
 142   switch (uart_reg)
 143     {
 144     case LM32_UART_THR:
 145       /* Buffer the character to output.  */
 146       uart->thr = value;
 147
 148       /* Indicate the THR is full.  */
 149       uart->lsr &= ~LM32_UART_LSR_TX_RDY;
 150
 151       /* deassert interrupt when IER is loaded.  */
 152       uart->iir &= ~MICOUART_IIR_TXRDY;
 153
 154       /* schedule an event to output the character.  */
 155       hw_event_queue_schedule (me, 1, do_uart_tx_event, 0);
 156
 157       break;
 158     case LM32_UART_IER:
 159       uart->ier = value;
 160       if ((value & LM32_UART_IER_TX_INT)
 161           && (uart->lsr & LM32_UART_LSR_TX_RDY))
 162         {
 163           /* hw_event_queue_schedule (me, 1, do_uart_tx_event, 0); */
 164           uart->lsr |= LM32_UART_LSR_TX_RDY;
 165           uart->iir |= MICOUART_IIR_TXRDY;
 166           hw_port_event (me, INT_PORT, 1);
 167         }
 168       else if ((value & LM32_UART_IER_TX_INT) == 0)
 169         {
 170           hw_port_event (me, INT_PORT, 0);
 171         }
 172       break;
 173     case LM32_UART_IIR:
 174       uart->iir = value;
 175       break;
 176     case LM32_UART_LCR:
 177       uart->lcr = value;
 178       break;
 179     case LM32_UART_MCR:
 180       uart->mcr = value;
 181       break;
 182     case LM32_UART_LSR:
 183       uart->lsr = value;
 184       break;
 185     case LM32_UART_MSR:
 186       uart->msr = value;
 187       break;
 188     case LM32_UART_DIV:
 189       uart->div = value;
 190       break;
 191     default:
 192       hw_abort (me, "write to invalid register address: 0x%x.", uart_reg);
 193     }
 194
 195   return nr_bytes;
 196 }
 197
 198 static unsigned
 199 lm32uart_io_read_buffer (struct hw *me,
 200                          void *dest,
 201                          int space, unsigned_word base, unsigned nr_bytes)
 202 {
 203   struct lm32uart *uart = hw_data (me);
 204   int uart_reg;
 205   int value;
 206   unsigned char *dest_bytes = dest;
 207   fd_set fd;
 208   struct timeval tv;
 209
 210   HW_TRACE ((me, "read 0x%08lx length %d", (long) base, (int) nr_bytes));
 211
 212   uart_reg = base - uart->base;
 213
 214   switch (uart_reg)
 215     {
 216     case LM32_UART_RBR:
 217       value = getchar ();
 218       uart->lsr &= ~LM32_UART_LSR_RX_RDY;
 219       break;
 220     case LM32_UART_IER:
 221       value = uart->ier;
 222       break;
 223     case LM32_UART_IIR:
 224       value = uart->iir;
 225       break;
 226     case LM32_UART_LCR:
 227       value = uart->lcr;
 228       break;
 229     case LM32_UART_MCR:
 230       value = uart->mcr;
 231       break;
 232     case LM32_UART_LSR:
 233       /* Check to see if any data waiting in stdin.  */
 234       FD_ZERO (&fd);
 235       FD_SET (fileno (stdin), &fd);
 236       tv.tv_sec = 0;
 237       tv.tv_usec = 1;
 238       if (select (fileno (stdin) + 1, &fd, NULL, NULL, &tv))
 239         uart->lsr |= LM32_UART_LSR_RX_RDY;
 240       value = uart->lsr;
 241       break;
 242     case LM32_UART_MSR:
 243       value = uart->msr;
 244       break;
 245     case LM32_UART_DIV:
 246       value = uart->div;
 247       break;
 248     default:
 249       hw_abort (me, "read from invalid register address: 0x%x.", uart_reg);
 250     }
 251
 252   if (nr_bytes == 4)
 253     {
 254       dest_bytes[0] = value >> 24;
 255       dest_bytes[1] = value >> 16;
 256       dest_bytes[2] = value >> 8;
 257       dest_bytes[3] = value;
 258     }
 259   else
 260     hw_abort (me, "read of unsupported number of bytes: %d", nr_bytes);
 261
 262   return nr_bytes;
 263 }
 264
 265 static void
 266 attach_lm32uart_regs (struct hw *me, struct lm32uart *uart)
 267 {
 268   unsigned_word attach_address;
 269   int attach_space;
 270   unsigned attach_size;
 271   reg_property_spec reg;
 272
 273   if (hw_find_property (me, "reg") == NULL)
 274     hw_abort (me, "Missing \"reg\" property");
 275   if (!hw_find_reg_array_property (me, "reg", 0, &reg))
 276     hw_abort (me, "\"reg\" property must contain three addr/size entries");
 277   hw_unit_address_to_attach_address (hw_parent (me),
 278                                      &reg.address,
 279                                      &attach_space, &attach_address, me);
 280   uart->base = attach_address;
 281   hw_unit_size_to_attach_size (hw_parent (me), &reg.size, &attach_size, me);
 282   uart->limit = attach_address + (attach_size - 1);
 283   hw_attach_address (hw_parent (me),
 284                      0, attach_space, attach_address, attach_size, me);
 285 }
 286
 287 static void
 288 lm32uart_finish (struct hw *me)
 289 {
 290   struct lm32uart *uart;
 291   int i;
 292
 293   uart = HW_ZALLOC (me, struct lm32uart);
 294   set_hw_data (me, uart);
 295   set_hw_io_read_buffer (me, lm32uart_io_read_buffer);
 296   set_hw_io_write_buffer (me, lm32uart_io_write_buffer);
 297   set_hw_ports (me, lm32uart_ports);
 298
 299   /* Attach ourself to our parent bus.  */
 300   attach_lm32uart_regs (me, uart);
 301
 302   /* Initialize the UART.  */
 303   uart->rbr = 0;
 304   uart->thr = 0;
 305   uart->ier = 0;
 306   uart->iir = 0;
 307   uart->lcr = 0;
 308   uart->mcr = 0;
 309   uart->lsr = LM32_UART_LSR_TX_RDY;
 310   uart->msr = 0;
 311   uart->div = 0;                /* By setting to zero, characters are output immediately.  */
 312 }
 313
 314 const struct hw_descriptor dv_lm32uart_descriptor[] = {
 315   {"lm32uart", lm32uart_finish,},
 316   {NULL},
 317 };