opcodes/arm-dis.c

   1 /* Instruction printing code for the ARM
   2    Copyright (C) 1994-2019 Free Software Foundation, Inc.
   3    Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
   4    Modification by James G. Smith (jsmith@cygnus.co.uk)
   5
   6    This file is part of libopcodes.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23 #include "sysdep.h"
  24
  25 #include "disassemble.h"
  26 #include "opcode/arm.h"
  27 #include "opintl.h"
  28 #include "safe-ctype.h"
  29 #include "libiberty.h"
  30 #include "floatformat.h"
  31
  32 /* FIXME: This shouldn't be done here.  */
  33 #include "coff/internal.h"
  34 #include "libcoff.h"
  35 #include "bfd.h"
  36 #include "elf-bfd.h"
  37 #include "elf/internal.h"
  38 #include "elf/arm.h"
  39 #include "mach-o.h"
  40
  41 /* FIXME: Belongs in global header.  */
  42 #ifndef strneq
  43 #define strneq(a,b,n)   (strncmp ((a), (b), (n)) == 0)
  44 #endif
  45
  46 /* Cached mapping symbol state.  */
  47 enum map_type
  48 {
  49   MAP_ARM,
  50   MAP_THUMB,
  51   MAP_DATA
  52 };
  53
  54 struct arm_private_data
  55 {
  56   /* The features to use when disassembling optional instructions.  */
  57   arm_feature_set features;
  58
  59   /* Track the last type (although this doesn't seem to be useful) */
  60   enum map_type last_type;
  61
  62   /* Tracking symbol table information */
  63   int last_mapping_sym;
  64
  65   /* The end range of the current range being disassembled.  */
  66   bfd_vma last_stop_offset;
  67   bfd_vma last_mapping_addr;
  68 };
  69
  70 struct opcode32
  71 {
  72   arm_feature_set arch;         /* Architecture defining this insn.  */
  73   unsigned long value;          /* If arch is 0 then value is a sentinel.  */
  74   unsigned long mask;           /* Recognise insn if (op & mask) == value.  */
  75   const char *  assembler;      /* How to disassemble this insn.  */
  76 };
  77
  78 enum isa {
  79   ANY,
  80   T32,
  81   ARM
  82 };
  83
  84
  85 /* Shared (between Arm and Thumb mode) opcode.  */
  86 struct sopcode32
  87 {
  88   enum isa isa;                 /* Execution mode instruction availability.  */
  89   arm_feature_set arch;         /* Architecture defining this insn.  */
  90   unsigned long value;          /* If arch is 0 then value is a sentinel.  */
  91   unsigned long mask;           /* Recognise insn if (op & mask) == value.  */
  92   const char *  assembler;      /* How to disassemble this insn.  */
  93 };
  94
  95 struct opcode16
  96 {
  97   arm_feature_set arch;         /* Architecture defining this insn.  */
  98   unsigned short value, mask;   /* Recognise insn if (op & mask) == value.  */
  99   const char *assembler;        /* How to disassemble this insn.  */
 100 };
 101
 102 /* print_insn_coprocessor recognizes the following format control codes:
 103
 104    %%                   %
 105
 106    %c                   print condition code (always bits 28-31 in ARM mode)
 107    %q                   print shifter argument
 108    %u                   print condition code (unconditional in ARM mode,
 109                           UNPREDICTABLE if not AL in Thumb)
 110    %A                   print address for ldc/stc/ldf/stf instruction
 111    %B                   print vstm/vldm register list
 112    %C                   print vscclrm register list
 113    %I                   print cirrus signed shift immediate: bits 0..3|4..6
 114    %J                   print register for VLDR instruction
 115    %K                   print address for VLDR instruction
 116    %F                   print the COUNT field of a LFM/SFM instruction.
 117    %P                   print floating point precision in arithmetic insn
 118    %Q                   print floating point precision in ldf/stf insn
 119    %R                   print floating point rounding mode
 120
 121    %<bitfield>c         print as a condition code (for vsel)
 122    %<bitfield>r         print as an ARM register
 123    %<bitfield>R         as %<>r but r15 is UNPREDICTABLE
 124    %<bitfield>ru        as %<>r but each u register must be unique.
 125    %<bitfield>d         print the bitfield in decimal
 126    %<bitfield>k         print immediate for VFPv3 conversion instruction
 127    %<bitfield>x         print the bitfield in hex
 128    %<bitfield>X         print the bitfield as 1 hex digit without leading "0x"
 129    %<bitfield>f         print a floating point constant if >7 else a
 130                         floating point register
 131    %<bitfield>w         print as an iWMMXt width field - [bhwd]ss/us
 132    %<bitfield>g         print as an iWMMXt 64-bit register
 133    %<bitfield>G         print as an iWMMXt general purpose or control register
 134    %<bitfield>D         print as a NEON D register
 135    %<bitfield>Q         print as a NEON Q register
 136    %<bitfield>V         print as a NEON D or Q register
 137    %<bitfield>E         print a quarter-float immediate value
 138
 139    %y<code>             print a single precision VFP reg.
 140                           Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
 141    %z<code>             print a double precision VFP reg
 142                           Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
 143
 144    %<bitfield>'c        print specified char iff bitfield is all ones
 145    %<bitfield>`c        print specified char iff bitfield is all zeroes
 146    %<bitfield>?ab...    select from array of values in big endian order
 147
 148    %L                   print as an iWMMXt N/M width field.
 149    %Z                   print the Immediate of a WSHUFH instruction.
 150    %l                   like 'A' except use byte offsets for 'B' & 'H'
 151                         versions.
 152    %i                   print 5-bit immediate in bits 8,3..0
 153                         (print "32" when 0)
 154    %r                   print register offset address for wldt/wstr instruction.  */
 155
 156 enum opcode_sentinel_enum
 157 {
 158   SENTINEL_IWMMXT_START = 1,
 159   SENTINEL_IWMMXT_END,
 160   SENTINEL_GENERIC_START
 161 } opcode_sentinels;
 162
 163 #define UNDEFINED_INSTRUCTION      "\t\t; <UNDEFINED> instruction: %0-31x"
 164 #define UNKNOWN_INSTRUCTION_32BIT  "\t\t; <UNDEFINED> instruction: %08x"
 165 #define UNKNOWN_INSTRUCTION_16BIT  "\t\t; <UNDEFINED> instruction: %04x"
 166 #define UNPREDICTABLE_INSTRUCTION  "\t; <UNPREDICTABLE>"
 167
 168 /* Common coprocessor opcodes shared between Arm and Thumb-2.  */
 169
 170 static const struct sopcode32 coprocessor_opcodes[] =
 171 {
 172   /* XScale instructions.  */
 173   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 174     0x0e200010, 0x0fff0ff0,
 175     "mia%c\tacc0, %0-3r, %12-15r"},
 176   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 177     0x0e280010, 0x0fff0ff0,
 178     "miaph%c\tacc0, %0-3r, %12-15r"},
 179   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 180     0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
 181   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 182     0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
 183   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 184     0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
 185
 186   /* Intel Wireless MMX technology instructions.  */
 187   {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
 188   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
 189     0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
 190   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 191     0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
 192   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 193     0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
 194   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 195     0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
 196   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 197     0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
 198   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 199     0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
 200   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 201     0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
 202   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 203     0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
 204   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 205     0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
 206   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 207     0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
 208   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 209     0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
 210   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 211     0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
 212   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 213     0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
 214   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 215     0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
 216   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 217     0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
 218   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 219     0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
 220   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 221     0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
 222   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 223     0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 224   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 225     0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
 226   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 227     0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
 228   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 229     0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
 230   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 231     0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
 232   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 233     0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
 234   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 235     0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
 236   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 237     0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
 238   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 239     0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 240   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 241     0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 242   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 243     0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
 244   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 245     0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
 246   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 247     0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
 248   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 249     0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
 250   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 251     0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
 252   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 253     0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
 254   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 255     0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 256   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 257     0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
 258   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 259     0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 260   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 261     0x0e800120, 0x0f800ff0,
 262     "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 263   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 264     0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 265   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 266     0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
 267   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 268     0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
 269   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 270     0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
 271   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 272     0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
 273   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 274     0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
 275   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 276     0x0e8000a0, 0x0f800ff0,
 277     "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 278   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 279     0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
 280   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 281     0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
 282   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 283     0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
 284   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 285     0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 286   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 287     0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
 288   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 289     0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 290   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 291     0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
 292   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 293     0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
 294   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 295     0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
 296   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 297     0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
 298   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 299     0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 300   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 301     0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 302   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 303     0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
 304   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 305     0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 306   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 307     0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 308   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 309     0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
 310   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 311     0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 312   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 313     0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 314   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 315     0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
 316   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 317     0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
 318   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 319     0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
 320   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 321     0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 322   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 323     0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
 324   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 325     0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 326   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 327     0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
 328   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 329     0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
 330   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 331     0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
 332   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 333     0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
 334   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 335     0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 336   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 337     0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 338   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 339     0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
 340   {ANY, ARM_FEATURE_CORE_LOW (0),
 341     SENTINEL_IWMMXT_END, 0, "" },
 342
 343   /* Floating point coprocessor (FPA) instructions.  */
 344   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 345     0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 346   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 347     0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 348   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 349     0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 350   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 351     0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 352   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 353     0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 354   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 355     0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 356   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 357     0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
 358   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 359     0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
 360   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 361     0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 362   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 363     0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
 364   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 365     0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
 366   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 367     0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
 368   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 369     0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
 370   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 371     0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
 372   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 373     0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
 374   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 375     0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
 376   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 377     0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
 378   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 379     0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
 380   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 381     0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
 382   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 383     0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
 384   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 385     0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
 386   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 387     0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
 388   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 389     0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
 390   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 391     0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
 392   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 393     0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
 394   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 395     0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
 396   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 397     0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
 398   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 399     0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
 400   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 401     0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
 402   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 403     0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
 404   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 405     0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
 406   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 407     0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
 408   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 409     0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
 410   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 411     0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
 412   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 413     0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
 414   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 415     0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
 416   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 417     0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
 418   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 419     0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
 420   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 421     0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
 422   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 423     0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
 424   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 425     0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
 426   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
 427     0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
 428   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
 429     0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
 430
 431   /* Armv8.1-M Mainline instructions.  */
 432   {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
 433     0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
 434   {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
 435     0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
 436
 437   /* ARMv8-M Mainline Security Extensions instructions.  */
 438   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
 439     0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
 440   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
 441     0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
 442
 443   /* Register load/store.  */
 444   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 445     0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
 446   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 447     0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
 448   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 449     0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
 450   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 451     0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
 452   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 453     0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
 454   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 455     0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
 456   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 457     0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
 458   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 459     0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
 460   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 461     0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
 462   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 463     0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
 464   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 465     0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
 466   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 467     0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
 468   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 469     0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
 470   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 471     0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
 472   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 473     0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
 474   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 475     0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
 476   {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
 477     0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
 478   {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
 479     0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
 480
 481   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 482     0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
 483   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 484     0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
 485   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 486     0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
 487   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 488     0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
 489
 490   /* Data transfer between ARM and NEON registers.  */
 491   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 492     0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
 493   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 494     0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
 495   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 496     0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
 497   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 498     0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
 499   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 500     0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
 501   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 502     0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
 503   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 504     0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
 505   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 506     0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
 507   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 508     0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
 509   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 510     0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
 511   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 512     0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
 513   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 514     0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
 515   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 516     0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
 517   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 518     0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
 519   /* Half-precision conversion instructions.  */
 520   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 521     0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
 522   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 523     0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
 524   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
 525     0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
 526   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
 527     0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
 528
 529   /* Floating point coprocessor (VFP) instructions.  */
 530   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 531     0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
 532   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 533     0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
 534   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 535     0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
 536   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 537     0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
 538   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 539     0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
 540   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 541     0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
 542   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 543     0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
 544   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 545     0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
 546   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 547     0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
 548   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 549     0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
 550   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 551     0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
 552   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 553     0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
 554   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 555     0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
 556   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 557     0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
 558   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 559     0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
 560   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 561     0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
 562   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 563     0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
 564   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 565     0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
 566   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 567     0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
 568   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 569     0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
 570   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 571     0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
 572   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 573     0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
 574   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 575     0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
 576   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 577     0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
 578   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 579     0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
 580   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 581     0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
 582   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 583     0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
 584   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 585     0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
 586   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 587     0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
 588   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 589     0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
 590   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 591     0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
 592   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 593     0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
 594   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 595     0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
 596   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 597     0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
 598   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 599     0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
 600   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 601     0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
 602   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 603     0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
 604   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 605     0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
 606   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 607     0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
 608   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
 609     0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
 610   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
 611     0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
 612   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 613     0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
 614   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 615     0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
 616   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
 617     0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
 618   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
 619     0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
 620   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 621     0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
 622   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
 623     0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
 624   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
 625     0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
 626   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
 627     0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
 628   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
 629     0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
 630   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
 631     0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
 632   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 633     0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
 634   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 635     0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
 636   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 637     0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
 638   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 639     0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
 640   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 641     0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
 642   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 643     0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
 644   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 645     0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
 646   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 647     0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
 648   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 649     0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
 650   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 651     0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
 652   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 653     0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
 654   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 655     0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
 656   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 657     0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
 658   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 659     0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
 660   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 661     0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
 662   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 663     0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
 664   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 665     0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
 666   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 667     0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
 668
 669   /* Cirrus coprocessor instructions.  */
 670   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 671     0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
 672   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 673     0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
 674   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 675     0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
 676   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 677     0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
 678   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 679     0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
 680   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 681     0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
 682   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 683     0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
 684   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 685     0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
 686   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 687     0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
 688   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 689     0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
 690   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 691     0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
 692   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 693     0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
 694   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 695     0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
 696   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 697     0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
 698   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 699     0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
 700   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 701     0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
 702   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 703     0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
 704   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 705     0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
 706   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 707     0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
 708   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 709     0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
 710   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 711     0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
 712   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 713     0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
 714   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 715     0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
 716   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 717     0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
 718   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 719     0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
 720   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 721     0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
 722   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 723     0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
 724   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 725     0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
 726   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 727     0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
 728   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 729     0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
 730   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 731     0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
 732   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 733     0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
 734   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 735     0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
 736   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 737     0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
 738   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 739     0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
 740   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 741     0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
 742   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 743     0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
 744   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 745     0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
 746   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 747     0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
 748   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 749     0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
 750   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 751     0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
 752   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 753     0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
 754   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 755     0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
 756   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 757     0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
 758   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 759     0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
 760   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 761     0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
 762   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 763     0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
 764   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 765     0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
 766   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 767     0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
 768   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 769     0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
 770   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 771     0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
 772   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 773     0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
 774   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 775     0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
 776   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 777     0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
 778   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 779     0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
 780   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 781     0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
 782   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 783     0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
 784   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 785     0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
 786   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 787     0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
 788   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 789     0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
 790   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 791     0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
 792   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 793     0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
 794   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 795     0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
 796   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 797     0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
 798   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 799     0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
 800   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 801     0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
 802   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 803     0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
 804   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 805     0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
 806   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 807     0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
 808   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 809     0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
 810   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 811     0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
 812   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 813     0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
 814   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 815     0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 816   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 817     0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
 818   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 819     0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 820   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 821     0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
 822   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 823     0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 824   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 825     0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
 826   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 827     0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 828   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 829     0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 830   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 831     0x0e000600, 0x0ff00f10,
 832     "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 833   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 834     0x0e100600, 0x0ff00f10,
 835     "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 836   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 837     0x0e200600, 0x0ff00f10,
 838     "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
 839   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 840     0x0e300600, 0x0ff00f10,
 841     "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
 842
 843   /* VFP Fused multiply add instructions.  */
 844   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 845     0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
 846   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 847     0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
 848   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 849     0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
 850   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 851     0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
 852   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 853     0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
 854   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 855     0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
 856   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 857     0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
 858   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 859     0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
 860
 861   /* FP v5.  */
 862   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 863     0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
 864   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 865     0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
 866   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 867     0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
 868   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 869     0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
 870   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 871     0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
 872   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 873     0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
 874   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 875     0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
 876   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 877     0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
 878   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 879     0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
 880   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 881     0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
 882   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 883     0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
 884   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 885     0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
 886
 887   /* Generic coprocessor instructions.  */
 888   {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
 889   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
 890     0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
 891   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
 892     0x0c500000, 0x0ff00000,
 893     "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
 894   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 895     0x0e000000, 0x0f000010,
 896     "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
 897   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 898     0x0e10f010, 0x0f10f010,
 899     "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
 900   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 901     0x0e100010, 0x0f100010,
 902     "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
 903   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 904     0x0e000010, 0x0f100010,
 905     "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
 906   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 907     0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
 908   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 909     0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
 910
 911   /* V6 coprocessor instructions.  */
 912   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
 913     0xfc500000, 0xfff00000,
 914     "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
 915   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
 916     0xfc400000, 0xfff00000,
 917     "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
 918
 919   /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8.  */
 920   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 921     0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
 922   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 923     0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
 924   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 925     0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
 926   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 927     0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
 928   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 929     0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
 930   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 931     0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
 932   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 933     0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
 934   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 935     0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
 936   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 937     0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
 938   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 939     0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
 940
 941   /* Dot Product instructions in the space of coprocessor 13.  */
 942   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
 943     0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
 944   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
 945     0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
 946
 947   /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8.  */
 948   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
 949     0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
 950   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
 951     0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
 952   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
 953     0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
 954   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
 955     0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
 956   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
 957     0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
 958   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
 959     0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
 960   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
 961     0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
 962   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
 963     0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
 964
 965   /* V5 coprocessor instructions.  */
 966   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
 967     0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
 968   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
 969     0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
 970   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
 971     0xfe000000, 0xff000010,
 972     "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
 973   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
 974     0xfe000010, 0xff100010,
 975     "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
 976   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
 977     0xfe100010, 0xff100010,
 978     "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
 979
 980   /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
 981      cp_num: bit <11:8> == 0b1001.
 982      cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE.  */
 983   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 984     0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
 985   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 986     0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
 987   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 988     0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
 989   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 990     0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
 991   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 992     0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
 993   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 994     0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
 995   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 996     0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
 997   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 998     0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
 999   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1000     0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
1001   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1002     0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
1003   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1004     0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
1005   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1006     0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
1007   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1008     0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
1009   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1010     0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
1011   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1012     0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
1013   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1014     0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
1015   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1016     0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
1017   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1018     0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
1019   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1020     0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
1021   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1022     0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
1023   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1024     0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
1025   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1026     0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
1027   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1028     0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
1029   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1030     0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
1031   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1032     0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
1033   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1034     0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
1035   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1036     0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
1037   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1038     0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
1039   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1040     0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
1041   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1042     0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
1043   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1044     0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
1045   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1046     0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
1047   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1048     0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
1049   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1050     0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
1051   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1052     0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1053
1054   /* ARMv8.3 javascript conversion instruction.  */
1055   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1056     0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1057
1058   {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1059 };
1060
1061 /* Neon opcode table:  This does not encode the top byte -- that is
1062    checked by the print_insn_neon routine, as it depends on whether we are
1063    doing thumb32 or arm32 disassembly.  */
1064
1065 /* print_insn_neon recognizes the following format control codes:
1066
1067    %%                   %
1068
1069    %c                   print condition code
1070    %u                   print condition code (unconditional in ARM mode,
1071                           UNPREDICTABLE if not AL in Thumb)
1072    %A                   print v{st,ld}[1234] operands
1073    %B                   print v{st,ld}[1234] any one operands
1074    %C                   print v{st,ld}[1234] single->all operands
1075    %D                   print scalar
1076    %E                   print vmov, vmvn, vorr, vbic encoded constant
1077    %F                   print vtbl,vtbx register list
1078
1079    %<bitfield>r         print as an ARM register
1080    %<bitfield>d         print the bitfield in decimal
1081    %<bitfield>e         print the 2^N - bitfield in decimal
1082    %<bitfield>D         print as a NEON D register
1083    %<bitfield>Q         print as a NEON Q register
1084    %<bitfield>R         print as a NEON D or Q register
1085    %<bitfield>Sn        print byte scaled width limited by n
1086    %<bitfield>Tn        print short scaled width limited by n
1087    %<bitfield>Un        print long scaled width limited by n
1088
1089    %<bitfield>'c        print specified char iff bitfield is all ones
1090    %<bitfield>`c        print specified char iff bitfield is all zeroes
1091    %<bitfield>?ab...    select from array of values in big endian order.  */
1092
1093 static const struct opcode32 neon_opcodes[] =
1094 {
1095   /* Extract.  */
1096   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1097     0xf2b00840, 0xffb00850,
1098     "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1099   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1100     0xf2b00000, 0xffb00810,
1101     "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1102
1103   /* Move data element to all lanes.  */
1104   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1105     0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1106   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1107     0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1108   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1109     0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
1110
1111   /* Table lookup.  */
1112   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1113     0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1114   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1115     0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1116
1117   /* Half-precision conversions.  */
1118   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1119     0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1120   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1121     0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
1122
1123   /* NEON fused multiply add instructions.  */
1124   {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1125     0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1126   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1127     0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1128   {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1129     0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1130   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1131     0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1132
1133   /* Two registers, miscellaneous.  */
1134   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1135     0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
1136   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1137     0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
1138   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1139     0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
1140   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1141     0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
1142   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1143     0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1144   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1145     0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1146   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1147     0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1148   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1149     0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1150   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1151     0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1152   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1153     0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1154   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1155     0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1156   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1157     0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1158   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1159     0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1160   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1161     0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1162   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1163     0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1164   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1165     0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1166   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1167     0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1168   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1169     0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1170   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1171     0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1172   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1173     0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1174   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1175     0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1176   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1177     0xf3b20300, 0xffb30fd0,
1178     "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1179   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1180     0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1181   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1182     0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1183   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1184     0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1185   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1186     0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1187   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1188     0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1189   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1190     0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1191   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1192     0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1193   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1194     0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1195   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1196     0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1197   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1198     0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1199   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1200     0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1201   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1202     0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1203   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1204     0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1205   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1206     0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1207   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1208     0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1209   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1210     0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1211   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1212     0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1213   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1214     0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1215   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1216     0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1217   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1218     0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1219   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1220     0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1221   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1222     0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1223   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1224     0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1225   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1226     0xf3bb0600, 0xffbf0e10,
1227     "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
1228   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1229     0xf3b70600, 0xffbf0e10,
1230     "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
1231
1232   /* Three registers of the same length.  */
1233   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1234     0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1235   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1236     0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1237   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1238     0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1239   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1240     0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1241   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1242     0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1243   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1244     0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1245   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1246     0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1247   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1248     0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1249   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1250     0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1251   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1252     0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1253   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1254     0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1255   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1256     0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1257   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1258     0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1259   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1260     0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1261   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1262     0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1263   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1264     0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1265   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1266     0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1267   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1268     0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1269   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1270     0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1271   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1272     0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1273   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1274     0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1275   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1276     0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1277   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1278     0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1279   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1280     0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1281   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1282     0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1283   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1284     0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1285   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1286     0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1287   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1288     0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1289   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1290     0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1291   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1292     0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1293   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1294     0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1295   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1296     0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1297   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1298     0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1299   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1300     0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1301   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1302     0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1303   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1304     0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1305   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1306     0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1307   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1308     0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1309   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1310     0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1311   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1312     0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1313   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1314     0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1315   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1316     0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1317   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1318     0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1319   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1320     0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1321   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1322     0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1323   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1324     0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1325   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1326     0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1327   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1328     0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1329   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1330     0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1331   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1332     0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1333   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1334     0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1335   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1336     0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1337   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1338     0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1339   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1340     0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1341   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1342     0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1343   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1344     0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1345   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1346     0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1347   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1348     0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1349   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1350     0xf2000b00, 0xff800f10,
1351     "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1352   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1353     0xf2000b10, 0xff800f10,
1354     "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1355   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1356     0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1357   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1358     0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1359   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1360     0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1361   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1362     0xf3000b00, 0xff800f10,
1363     "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1364   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1365     0xf2000000, 0xfe800f10,
1366     "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1367   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1368     0xf2000010, 0xfe800f10,
1369     "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1370   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1371     0xf2000100, 0xfe800f10,
1372     "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1373   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1374     0xf2000200, 0xfe800f10,
1375     "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1376   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1377     0xf2000210, 0xfe800f10,
1378     "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1379   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1380     0xf2000300, 0xfe800f10,
1381     "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1382   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1383     0xf2000310, 0xfe800f10,
1384     "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1385   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1386     0xf2000400, 0xfe800f10,
1387     "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1388   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1389     0xf2000410, 0xfe800f10,
1390     "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1391   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1392     0xf2000500, 0xfe800f10,
1393     "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1394   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1395     0xf2000510, 0xfe800f10,
1396     "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1397   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1398     0xf2000600, 0xfe800f10,
1399     "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1400   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1401     0xf2000610, 0xfe800f10,
1402     "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1403   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1404     0xf2000700, 0xfe800f10,
1405     "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1406   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1407     0xf2000710, 0xfe800f10,
1408     "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1409   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1410     0xf2000910, 0xfe800f10,
1411     "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1412   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1413     0xf2000a00, 0xfe800f10,
1414     "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1415   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1416     0xf2000a10, 0xfe800f10,
1417     "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1418   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1419     0xf3000b10, 0xff800f10,
1420     "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1421   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1422     0xf3000c10, 0xff800f10,
1423     "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1424
1425   /* One register and an immediate value.  */
1426   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1427     0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1428   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1429     0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1430   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1431     0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1432   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1433     0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1434   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1435     0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1436   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1437     0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1438   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1439     0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1440   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1441     0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1442   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1443     0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1444   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1445     0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1446   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1447     0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1448   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1449     0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1450   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1451     0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
1452
1453   /* Two registers and a shift amount.  */
1454   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1455     0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1456   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1457     0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1458   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1459     0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1460   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1461     0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1462   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1463     0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1464   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1465     0xf2880950, 0xfeb80fd0,
1466     "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1467   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1468     0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1469   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1470     0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1471   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1472     0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1473   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1474     0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1475   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1476     0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1477   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1478     0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1479   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1480     0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1481   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1482     0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1483   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1484     0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1485   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1486     0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1487   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1488     0xf2900950, 0xfeb00fd0,
1489     "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1490   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1491     0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1492   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1493     0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1494   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1495     0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1496   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1497     0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1498   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1499     0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1500   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1501     0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1502   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1503     0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1504   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1505     0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1506   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1507     0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1508   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1509     0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1510   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1511     0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1512   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1513     0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1514   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1515     0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1516   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1517     0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1518   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1519     0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1520   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1521     0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1522   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1523     0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1524   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1525     0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1526   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1527     0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1528   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1529     0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1530   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1531     0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1532   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1533     0xf2a00950, 0xfea00fd0,
1534     "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1535   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1536     0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1537   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1538     0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1539   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1540     0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1541   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1542     0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1543   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1544     0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1545   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1546     0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1547   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1548     0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1549   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1550     0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1551   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1552     0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1553   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1554     0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1555   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1556     0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1557   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1558     0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1559   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1560     0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1561   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1562     0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1563   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1564     0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1565   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1566     0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1567   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1568     0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1569   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1570     0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1571   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1572     0xf2a00e10, 0xfea00e90,
1573     "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
1574   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1575     0xf2a00c10, 0xfea00e90,
1576     "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
1577
1578   /* Three registers of different lengths.  */
1579   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1580     0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1581   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1582     0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1583   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1584     0xf2800400, 0xff800f50,
1585     "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1586   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1587     0xf2800600, 0xff800f50,
1588     "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1589   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1590     0xf2800900, 0xff800f50,
1591     "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1592   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1593     0xf2800b00, 0xff800f50,
1594     "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1595   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1596     0xf2800d00, 0xff800f50,
1597     "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1598   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1599     0xf3800400, 0xff800f50,
1600     "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1601   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1602     0xf3800600, 0xff800f50,
1603     "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1604   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1605     0xf2800000, 0xfe800f50,
1606     "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1607   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1608     0xf2800100, 0xfe800f50,
1609     "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1610   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1611     0xf2800200, 0xfe800f50,
1612     "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1613   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1614     0xf2800300, 0xfe800f50,
1615     "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1616   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1617     0xf2800500, 0xfe800f50,
1618     "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1619   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1620     0xf2800700, 0xfe800f50,
1621     "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1622   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1623     0xf2800800, 0xfe800f50,
1624     "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1625   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1626     0xf2800a00, 0xfe800f50,
1627     "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1628   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1629     0xf2800c00, 0xfe800f50,
1630     "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1631
1632   /* Two registers and a scalar.  */
1633   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1634     0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1635   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1636     0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1637   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1638     0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
1639   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1640     0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1641   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1642     0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1643   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1644     0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1645   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1646     0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
1647   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1648     0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1649   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1650     0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1651   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1652     0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1653   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1654     0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
1655   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1656     0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1657   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1658     0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1659   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1660     0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1661   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1662     0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1663   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1664     0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1665   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1666     0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1667   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1668     0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1669   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1670     0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1671   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1672     0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1673   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1674     0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1675   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1676     0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1677   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1678     0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1679   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1680     0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1681   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1682     0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1683   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1684     0xf2800240, 0xfe800f50,
1685     "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1686   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1687     0xf2800640, 0xfe800f50,
1688     "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1689   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1690     0xf2800a40, 0xfe800f50,
1691     "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1692   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1693     0xf2800e40, 0xff800f50,
1694    "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1695   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1696     0xf2800f40, 0xff800f50,
1697    "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1698   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1699     0xf3800e40, 0xff800f50,
1700    "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1701   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1702     0xf3800f40, 0xff800f50,
1703    "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1704   },
1705
1706   /* Element and structure load/store.  */
1707   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1708     0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1709   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1710     0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1711   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1712     0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1713   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1714     0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1715   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1716     0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1717   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1718     0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1719   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1720     0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1721   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1722     0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1723   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1724     0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1725   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1726     0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1727   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1728     0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1729   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1730     0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1731   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1732     0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1733   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1734     0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1735   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1736     0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1737   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1738     0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1739   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1740     0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1741   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1742     0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1743   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1744     0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1745
1746   {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
1747 };
1748
1749 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb.  All three are partially
1750    ordered: they must be searched linearly from the top to obtain a correct
1751    match.  */
1752
1753 /* print_insn_arm recognizes the following format control codes:
1754
1755    %%                   %
1756
1757    %a                   print address for ldr/str instruction
1758    %s                   print address for ldr/str halfword/signextend instruction
1759    %S                   like %s but allow UNPREDICTABLE addressing
1760    %b                   print branch destination
1761    %c                   print condition code (always bits 28-31)
1762    %m                   print register mask for ldm/stm instruction
1763    %o                   print operand2 (immediate or register + shift)
1764    %p                   print 'p' iff bits 12-15 are 15
1765    %t                   print 't' iff bit 21 set and bit 24 clear
1766    %B                   print arm BLX(1) destination
1767    %C                   print the PSR sub type.
1768    %U                   print barrier type.
1769    %P                   print address for pli instruction.
1770
1771    %<bitfield>r         print as an ARM register
1772    %<bitfield>T         print as an ARM register + 1
1773    %<bitfield>R         as %r but r15 is UNPREDICTABLE
1774    %<bitfield>{r|R}u    as %{r|R} but if matches the other %u field then is UNPREDICTABLE
1775    %<bitfield>{r|R}U    as %{r|R} but if matches the other %U field then is UNPREDICTABLE
1776    %<bitfield>d         print the bitfield in decimal
1777    %<bitfield>W         print the bitfield plus one in decimal
1778    %<bitfield>x         print the bitfield in hex
1779    %<bitfield>X         print the bitfield as 1 hex digit without leading "0x"
1780
1781    %<bitfield>'c        print specified char iff bitfield is all ones
1782    %<bitfield>`c        print specified char iff bitfield is all zeroes
1783    %<bitfield>?ab...    select from array of values in big endian order
1784
1785    %e                   print arm SMI operand (bits 0..7,8..19).
1786    %E                   print the LSB and WIDTH fields of a BFI or BFC instruction.
1787    %V                   print the 16-bit immediate field of a MOVT or MOVW instruction.
1788    %R                   print the SPSR/CPSR or banked register of an MRS.  */
1789
1790 static const struct opcode32 arm_opcodes[] =
1791 {
1792   /* ARM instructions.  */
1793   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1794     0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
1795   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1796     0xe7f000f0, 0xfff000f0, "udf\t#%e"},
1797
1798   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
1799     0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
1800   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1801     0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
1802   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1803     0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1804   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
1805     0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
1806   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1807     0x00800090, 0x0fa000f0,
1808     "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1809   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1810     0x00a00090, 0x0fa000f0,
1811     "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1812
1813   /* V8.2 RAS extension instructions.  */
1814   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
1815     0xe320f010, 0xffffffff, "esb"},
1816
1817   /* V8 instructions.  */
1818   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1819     0x0320f005, 0x0fffffff, "sevl"},
1820   /* Defined in V8 but is in NOP space so available to all arch.  */
1821   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1822     0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
1823   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
1824     0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
1825   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1826     0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
1827   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1828     0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
1829   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1830     0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
1831   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1832     0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
1833   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1834     0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
1835   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1836     0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
1837   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1838     0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
1839   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1840     0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
1841   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1842     0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
1843   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1844     0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
1845   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1846     0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
1847   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1848     0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
1849   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1850     0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
1851   /* CRC32 instructions.  */
1852   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1853     0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
1854   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1855     0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
1856   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1857     0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
1858   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1859     0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
1860   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1861     0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
1862   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1863     0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
1864
1865   /* Privileged Access Never extension instructions.  */
1866   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
1867     0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
1868
1869   /* Virtualization Extension instructions.  */
1870   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
1871   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
1872
1873   /* Integer Divide Extension instructions.  */
1874   {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1875     0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
1876   {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1877     0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
1878
1879   /* MP Extension instructions.  */
1880   {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
1881
1882   /* Speculation Barriers.  */
1883   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
1884   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
1885   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
1886
1887   /* V7 instructions.  */
1888   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
1889   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
1890   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
1891   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
1892   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
1893   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
1894   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
1895    {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
1896     0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
1897
1898   /* ARM V6T2 instructions.  */
1899   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1900     0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
1901   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1902     0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
1903   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1904     0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1905   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1906     0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
1907
1908   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1909     0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
1910   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1911     0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
1912
1913   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
1914     0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
1915   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
1916     0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
1917   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1918     0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
1919   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1920     0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
1921
1922   /* ARM Security extension instructions.  */
1923   {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
1924     0x01600070, 0x0ff000f0, "smc%c\t%e"},
1925
1926   /* ARM V6K instructions.  */
1927   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1928     0xf57ff01f, 0xffffffff, "clrex"},
1929   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1930     0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
1931   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1932     0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
1933   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1934     0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
1935   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1936     0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
1937   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1938     0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
1939   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1940     0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
1941
1942   /* ARMv8.5-A instructions.  */
1943   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
1944
1945   /* ARM V6K NOP hints.  */
1946   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1947     0x0320f001, 0x0fffffff, "yield%c"},
1948   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1949     0x0320f002, 0x0fffffff, "wfe%c"},
1950   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1951     0x0320f003, 0x0fffffff, "wfi%c"},
1952   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1953     0x0320f004, 0x0fffffff, "sev%c"},
1954   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1955     0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
1956
1957   /* ARM V6 instructions.  */
1958   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1959     0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
1960   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1961     0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
1962   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1963     0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
1964   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1965     0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
1966   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1967     0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
1968   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1969     0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
1970   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1971     0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
1972   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1973     0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
1974   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1975     0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
1976   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1977     0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
1978   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1979     0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
1980   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1981     0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
1982   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1983     0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
1984   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1985     0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
1986   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1987     0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
1988   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1989     0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
1990   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1991     0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
1992   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1993     0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
1994   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1995     0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
1996   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1997     0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
1998   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1999     0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
2000   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2001     0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
2002   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2003     0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
2004   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2005     0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
2006   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2007     0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
2008   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2009     0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
2010   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2011     0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
2012   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2013     0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
2014   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2015     0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
2016   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2017     0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
2018   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2019     0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
2020   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2021     0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
2022   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2023     0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
2024   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2025     0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
2026   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2027     0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
2028   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2029     0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
2030   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2031     0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
2032   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2033     0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
2034   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2035     0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
2036   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2037     0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
2038   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2039     0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
2040   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2041     0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
2042   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2043     0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
2044   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2045     0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
2046   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2047     0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
2048   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2049     0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
2050   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2051     0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
2052   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2053     0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
2054   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2055     0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
2056   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2057     0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
2058   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2059     0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
2060   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2061     0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
2062   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2063     0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
2064   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2065     0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
2066   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2067     0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
2068   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2069     0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
2070   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2071     0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
2072   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2073     0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
2074   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2075     0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
2076   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2077     0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
2078   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2079     0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
2080   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2081     0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
2082   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2083     0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
2084   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2085     0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
2086   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2087     0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
2088   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2089     0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
2090   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2091     0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
2092   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2093     0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
2094   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2095     0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
2096   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2097     0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
2098   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2099     0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
2100   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2101     0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
2102   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2103     0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
2104   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2105     0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
2106   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2107     0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
2108   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2109     0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2110   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2111     0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2112   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2113     0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2114   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2115     0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
2116   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2117     0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2118   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2119     0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2120   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2121     0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2122   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2123     0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
2124   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2125     0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2126   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2127     0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2128   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2129     0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2130   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2131     0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
2132   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2133     0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2134   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2135     0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2136   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2137     0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2138   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2139     0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
2140   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2141     0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2142   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2143     0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2144   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2145     0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
2146   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2147     0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
2148   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2149     0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2150   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2151     0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2152   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2153     0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2154   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2155     0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
2156   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2157     0xf1010000, 0xfffffc00, "setend\t%9?ble"},
2158   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2159     0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
2160   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2161     0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
2162   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2163     0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2164   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2165     0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2166   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2167     0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2168   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2169     0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2170   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2171     0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
2172   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2173     0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2174   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2175     0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2176   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2177     0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
2178   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2179     0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
2180   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2181     0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
2182   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2183     0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
2184   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2185     0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
2186   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2187     0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
2188   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2189     0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
2190   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2191     0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
2192   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2193     0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2194   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2195     0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
2196   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2197     0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
2198   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2199     0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
2200   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2201     0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
2202
2203   /* V5J instruction.  */
2204   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
2205     0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
2206
2207   /* V5 Instructions.  */
2208   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2209     0xe1200070, 0xfff000f0,
2210     "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
2211   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2212     0xfa000000, 0xfe000000, "blx\t%B"},
2213   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2214     0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
2215   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2216     0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
2217
2218   /* V5E "El Segundo" Instructions.  */
2219   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2220     0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
2221   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2222     0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
2223   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2224     0xf450f000, 0xfc70f000, "pld\t%a"},
2225   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2226     0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2227   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2228     0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2229   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2230     0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2231   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2232     0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
2233
2234   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2235     0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2236   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2237     0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
2238
2239   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2240     0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2241   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2242     0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2243   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2244     0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2245   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2246     0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2247
2248   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2249     0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
2250   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2251     0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
2252   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2253     0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
2254   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2255     0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
2256
2257   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2258     0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
2259   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2260     0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
2261
2262   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2263     0x01000050, 0x0ff00ff0,  "qadd%c\t%12-15R, %0-3R, %16-19R"},
2264   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2265     0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
2266   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2267     0x01200050, 0x0ff00ff0,  "qsub%c\t%12-15R, %0-3R, %16-19R"},
2268   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2269     0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
2270
2271   /* ARM Instructions.  */
2272   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2273     0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
2274
2275   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2276     0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
2277   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2278     0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
2279   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2280     0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
2281   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2282     0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
2283   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2284     0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
2285   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2286     0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
2287
2288   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2289     0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
2290   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2291     0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
2292   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2293     0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
2294   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2295     0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
2296
2297   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2298     0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
2299   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2300     0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
2301   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2302     0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
2303   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2304     0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
2305
2306   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2307     0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
2308   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2309     0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
2310   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2311     0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
2312
2313   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2314     0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
2315   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2316     0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
2317   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2318     0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
2319
2320   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2321     0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
2322   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2323     0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
2324   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2325     0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
2326
2327   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2328     0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2329   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2330     0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2331   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2332     0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
2333
2334   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2335     0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
2336   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2337     0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
2338   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2339     0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
2340
2341   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2342     0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
2343   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2344     0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
2345   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2346     0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
2347
2348   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2349     0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2350   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2351     0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2352   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2353     0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
2354
2355   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2356     0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2357   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2358     0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2359   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2360     0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
2361
2362   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
2363     0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
2364   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2365     0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
2366   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2367     0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
2368
2369   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2370     0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
2371   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2372     0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
2373   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2374     0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
2375
2376   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2377     0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
2378   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2379     0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
2380   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2381     0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
2382
2383   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2384     0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
2385   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2386     0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
2387   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2388     0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
2389
2390   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2391     0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
2392   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2393     0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
2394   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2395     0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
2396
2397   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2398     0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
2399   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2400     0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
2401   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2402     0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
2403
2404   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2405     0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
2406   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2407     0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
2408   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2409     0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
2410   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2411     0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
2412   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2413     0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
2414   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2415     0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
2416   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2417     0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
2418
2419   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2420     0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
2421   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2422     0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
2423   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2424     0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
2425
2426   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2427     0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
2428   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2429     0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
2430   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2431     0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
2432
2433   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2434     0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
2435   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2436     0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
2437
2438   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2439     0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
2440
2441   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2442     0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
2443   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2444     0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
2445
2446   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2447     0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2448   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2449     0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2450   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2451     0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2452   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2453     0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2454   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2455     0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2456   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2457     0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2458   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2459     0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2460   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2461     0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2462   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2463     0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2464   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2465     0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2466   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2467     0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2468   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2469     0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2470   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2471     0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2472   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2473     0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2474   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2475     0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2476   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2477     0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2478   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2479     0x092d0000, 0x0fff0000, "push%c\t%m"},
2480   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2481     0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
2482   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2483     0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2484
2485   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2486     0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2487   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2488     0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2489   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2490     0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2491   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2492     0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2493   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2494     0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2495   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2496     0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2497   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2498     0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2499   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2500     0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2501   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2502     0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2503   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2504     0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2505   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2506     0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2507   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2508     0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2509   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2510     0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2511   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2512     0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2513   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2514     0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2515   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2516     0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2517   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2518     0x08bd0000, 0x0fff0000, "pop%c\t%m"},
2519   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2520     0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
2521   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2522     0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2523
2524   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2525     0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
2526   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2527     0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
2528
2529   /* The rest.  */
2530   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
2531     0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
2532   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2533     0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
2534   {ARM_FEATURE_CORE_LOW (0),
2535     0x00000000, 0x00000000, 0}
2536 };
2537
2538 /* print_insn_thumb16 recognizes the following format control codes:
2539
2540    %S                   print Thumb register (bits 3..5 as high number if bit 6 set)
2541    %D                   print Thumb register (bits 0..2 as high number if bit 7 set)
2542    %<bitfield>I         print bitfield as a signed decimal
2543                                 (top bit of range being the sign bit)
2544    %N                   print Thumb register mask (with LR)
2545    %O                   print Thumb register mask (with PC)
2546    %M                   print Thumb register mask
2547    %b                   print CZB's 6-bit unsigned branch destination
2548    %s                   print Thumb right-shift immediate (6..10; 0 == 32).
2549    %c                   print the condition code
2550    %C                   print the condition code, or "s" if not conditional
2551    %x                   print warning if conditional an not at end of IT block"
2552    %X                   print "\t; unpredictable <IT:code>" if conditional
2553    %I                   print IT instruction suffix and operands
2554    %W                   print Thumb Writeback indicator for LDMIA
2555    %<bitfield>r         print bitfield as an ARM register
2556    %<bitfield>d         print bitfield as a decimal
2557    %<bitfield>H         print (bitfield * 2) as a decimal
2558    %<bitfield>W         print (bitfield * 4) as a decimal
2559    %<bitfield>a         print (bitfield * 4) as a pc-rel offset + decoded symbol
2560    %<bitfield>B         print Thumb branch destination (signed displacement)
2561    %<bitfield>c         print bitfield as a condition code
2562    %<bitnum>'c          print specified char iff bit is one
2563    %<bitnum>?ab         print a if bit is one else print b.  */
2564
2565 static const struct opcode16 thumb_opcodes[] =
2566 {
2567   /* Thumb instructions.  */
2568
2569   /* ARMv8-M Security Extensions instructions.  */
2570   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
2571   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
2572
2573   /* ARM V8 instructions.  */
2574   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),  0xbf50, 0xffff, "sevl%c"},
2575   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),  0xba80, 0xffc0, "hlt\t%0-5x"},
2576   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),  0xb610, 0xfff7, "setpan\t#%3-3d"},
2577
2578   /* ARM V6K no-argument instructions.  */
2579   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
2580   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
2581   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
2582   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
2583   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
2584   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
2585
2586   /* ARM V6T2 instructions.  */
2587   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2588     0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
2589   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2590     0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
2591   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
2592
2593   /* ARM V6.  */
2594   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
2595   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
2596   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
2597   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
2598   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
2599   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
2600   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
2601   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
2602   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
2603   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
2604   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
2605
2606   /* ARM V5 ISA extends Thumb.  */
2607   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2608     0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional.  */
2609   /* This is BLX(2).  BLX(1) is a 32-bit instruction.  */
2610   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2611     0x4780, 0xff87, "blx%c\t%3-6r%x"},  /* note: 4 bit register number.  */
2612   /* ARM V4T ISA (Thumb v1).  */
2613   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2614     0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
2615   /* Format 4.  */
2616   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
2617   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
2618   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
2619   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
2620   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
2621   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
2622   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
2623   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
2624   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
2625   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
2626   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
2627   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
2628   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
2629   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
2630   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
2631   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
2632   /* format 13 */
2633   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
2634   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
2635   /* format 5 */
2636   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
2637   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
2638   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
2639   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
2640   /* format 14 */
2641   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
2642   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
2643   /* format 2 */
2644   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2645     0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
2646   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2647     0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
2648   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2649     0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
2650   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2651     0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
2652   /* format 8 */
2653   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2654     0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
2655   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2656     0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
2657   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2658     0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
2659   /* format 7 */
2660   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2661     0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2662   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2663     0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2664   /* format 1 */
2665   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
2666   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2667     0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
2668   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
2669   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
2670   /* format 3 */
2671   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
2672   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
2673   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
2674   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
2675   /* format 6 */
2676   /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
2677   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2678     0x4800, 0xF800,
2679     "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
2680   /* format 9 */
2681   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2682     0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
2683   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2684     0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
2685   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2686     0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
2687   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2688     0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
2689   /* format 10 */
2690   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2691     0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
2692   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2693     0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
2694   /* format 11 */
2695   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2696     0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
2697   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2698     0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
2699   /* format 12 */
2700   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2701     0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
2702   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2703     0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
2704   /* format 15 */
2705   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
2706   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
2707   /* format 17 */
2708   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
2709   /* format 16 */
2710   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
2711   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
2712   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
2713   /* format 18 */
2714   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
2715
2716   /* The E800 .. FFFF range is unconditionally redirected to the
2717      32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
2718      are processed via that table.  Thus, we can never encounter a
2719      bare "second half of BL/BLX(1)" instruction here.  */
2720   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),  0x0000, 0x0000, UNDEFINED_INSTRUCTION},
2721   {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2722 };
2723
2724 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
2725    We adopt the convention that hw1 is the high 16 bits of .value and
2726    .mask, hw2 the low 16 bits.
2727
2728    print_insn_thumb32 recognizes the following format control codes:
2729
2730        %%               %
2731
2732        %I               print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
2733        %M               print a modified 12-bit immediate (same location)
2734        %J               print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
2735        %K               print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
2736        %H               print a 16-bit immediate from hw2[3:0],hw1[11:0]
2737        %S               print a possibly-shifted Rm
2738
2739        %L               print address for a ldrd/strd instruction
2740        %a               print the address of a plain load/store
2741        %w               print the width and signedness of a core load/store
2742        %m               print register mask for ldm/stm
2743        %n               print register mask for clrm
2744
2745        %E               print the lsb and width fields of a bfc/bfi instruction
2746        %F               print the lsb and width fields of a sbfx/ubfx instruction
2747        %G               print a fallback offset for Branch Future instructions
2748        %W               print an offset for BF instruction
2749        %Y               print an offset for BFL instruction
2750        %Z               print an offset for BFCSEL instruction
2751        %Q               print an offset for Low Overhead Loop instructions
2752        %P               print an offset for Low Overhead Loop end instructions
2753        %b               print a conditional branch offset
2754        %B               print an unconditional branch offset
2755        %s               print the shift field of an SSAT instruction
2756        %R               print the rotation field of an SXT instruction
2757        %U               print barrier type.
2758        %P               print address for pli instruction.
2759        %c               print the condition code
2760        %x               print warning if conditional an not at end of IT block"
2761        %X               print "\t; unpredictable <IT:code>" if conditional
2762
2763        %<bitfield>d     print bitfield in decimal
2764        %<bitfield>D     print bitfield plus one in decimal
2765        %<bitfield>W     print bitfield*4 in decimal
2766        %<bitfield>r     print bitfield as an ARM register
2767        %<bitfield>R     as %<>r but r15 is UNPREDICTABLE
2768        %<bitfield>S     as %<>r but r13 and r15 is UNPREDICTABLE
2769        %<bitfield>c     print bitfield as a condition code
2770
2771        %<bitfield>'c    print specified char iff bitfield is all ones
2772        %<bitfield>`c    print specified char iff bitfield is all zeroes
2773        %<bitfield>?ab... select from array of values in big endian order
2774
2775    With one exception at the bottom (done because BL and BLX(1) need
2776    to come dead last), this table was machine-sorted first in
2777    decreasing order of number of bits set in the mask, then in
2778    increasing numeric order of mask, then in increasing numeric order
2779    of opcode.  This order is not the clearest for a human reader, but
2780    is guaranteed never to catch a special-case bit pattern with a more
2781    general mask, which is important, because this instruction encoding
2782    makes heavy use of special-case bit patterns.  */
2783 static const struct opcode32 thumb32_opcodes[] =
2784 {
2785   /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
2786      instructions.  */
2787   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2788     0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
2789   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2790     0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
2791   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2792     0xf02fc001, 0xfffff001, "le\t%P"},
2793   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2794     0xf00fc001, 0xfffff001, "le\tlr, %P"},
2795
2796   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2797     0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
2798   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2799     0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
2800   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2801     0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
2802   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2803     0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
2804   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2805     0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
2806
2807   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2808     0xe89f0000, 0xffff2000, "clrm%c\t%n"},
2809
2810   /* ARMv8-M and ARMv8-M Security Extensions instructions.  */
2811   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
2812   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2813     0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
2814   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2815     0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
2816   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2817     0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
2818   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2819     0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
2820
2821   /* ARM V8.2 RAS extension instructions.  */
2822   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
2823     0xf3af8010, 0xffffffff, "esb"},
2824
2825   /* V8 instructions.  */
2826   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2827     0xf3af8005, 0xffffffff, "sevl%c.w"},
2828   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2829     0xf78f8000, 0xfffffffc, "dcps%0-1d"},
2830   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2831     0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
2832   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2833     0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
2834   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2835     0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
2836   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2837     0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
2838   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2839     0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
2840   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2841     0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
2842   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2843     0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
2844   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2845     0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
2846   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2847     0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
2848   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2849     0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
2850   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2851     0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
2852   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2853     0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
2854   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2855     0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
2856   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2857     0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
2858
2859   /* CRC32 instructions.  */
2860   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2861     0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
2862   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2863     0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
2864   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2865     0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
2866   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2867     0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
2868   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2869     0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
2870   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2871     0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
2872
2873   /* Speculation Barriers.  */
2874   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
2875   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
2876   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
2877
2878   /* V7 instructions.  */
2879   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
2880   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
2881   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
2882   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
2883   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
2884   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
2885   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
2886   {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2887     0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
2888   {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2889     0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
2890
2891   /* Virtualization Extension instructions.  */
2892   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
2893   /* We skip ERET as that is SUBS pc, lr, #0.  */
2894
2895   /* MP Extension instructions.  */
2896   {ARM_FEATURE_CORE_LOW (ARM_EXT_MP),   0xf830f000, 0xff70f000, "pldw%c\t%a"},
2897
2898   /* Security extension instructions.  */
2899   {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),  0xf7f08000, 0xfff0f000, "smc%c\t%K"},
2900
2901   /* ARMv8.5-A instructions.  */
2902   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
2903
2904   /* Instructions defined in the basic V6T2 set.  */
2905   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
2906   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
2907   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
2908   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
2909   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
2910   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2911     0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
2912   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
2913
2914   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2915     0xf3bf8f2f, 0xffffffff, "clrex%c"},
2916   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2917     0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
2918   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2919     0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
2920   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2921     0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
2922   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2923     0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
2924   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2925     0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
2926   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2927     0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
2928   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2929     0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
2930   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2931     0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
2932   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2933     0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
2934   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2935     0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
2936   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2937     0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
2938   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2939     0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
2940   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2941     0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
2942   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2943     0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
2944   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2945     0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
2946   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2947     0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
2948   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2949     0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
2950   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2951     0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
2952   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2953     0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
2954   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2955     0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
2956   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2957     0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
2958   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2959     0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
2960   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2961     0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
2962   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2963     0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
2964   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2965     0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
2966   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2967     0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
2968   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2969     0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
2970   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2971     0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
2972   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2973     0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
2974   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2975     0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
2976   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2977     0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
2978   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2979     0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
2980   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2981     0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
2982   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2983     0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
2984   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2985     0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
2986   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2987     0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
2988   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2989     0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
2990   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2991     0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
2992   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2993     0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
2994   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2995     0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
2996   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2997     0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
2998   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2999     0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
3000   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3001     0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
3002   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3003     0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
3004   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3005     0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
3006   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3007     0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
3008   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3009     0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
3010   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3011     0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
3012   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3013     0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
3014   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3015     0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
3016   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3017     0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
3018   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3019     0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
3020   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3021     0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
3022   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3023     0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
3024   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3025     0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
3026   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3027     0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
3028   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3029     0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
3030   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3031     0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
3032   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3033     0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
3034   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3035     0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
3036   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3037     0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
3038   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3039     0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
3040   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3041     0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
3042   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3043     0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
3044   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3045     0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
3046   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3047     0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
3048   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3049     0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
3050   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3051     0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
3052   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3053     0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
3054   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3055     0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
3056   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3057     0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
3058   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3059     0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
3060   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3061     0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
3062   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3063     0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3064   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3065     0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3066   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3067     0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3068   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3069     0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
3070   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3071     0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
3072   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3073     0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
3074   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3075     0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
3076   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3077     0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
3078   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3079     0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
3080   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3081     0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
3082   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3083     0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
3084   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3085     0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
3086   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3087     0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
3088   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3089     0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
3090   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3091     0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
3092   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3093     0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
3094   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3095     0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
3096   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3097     0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
3098   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3099     0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
3100   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3101     0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
3102   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3103     0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
3104   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3105     0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
3106   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3107     0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
3108   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3109     0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
3110   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3111     0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
3112   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3113     0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
3114   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3115     0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
3116   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3117     0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
3118   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3119     0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
3120   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3121     0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
3122   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3123     0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3124   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3125     0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3126   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3127     0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3128   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3129     0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3130   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3131     0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3132   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3133     0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3134   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3135     0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3136   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3137     0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3138   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3139     0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
3140   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3141     0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
3142   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3143     0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
3144   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3145     0xf810f000, 0xff70f000, "pld%c\t%a"},
3146   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3147     0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3148   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3149     0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3150   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3151     0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3152   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3153     0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3154   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3155     0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3156   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3157     0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3158   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3159     0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3160   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3161     0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
3162   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3163     0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
3164   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3165     0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
3166   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3167     0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
3168   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3169     0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
3170   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3171     0xfb100000, 0xfff000c0,
3172     "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3173   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3174     0xfbc00080, 0xfff000c0,
3175     "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
3176   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3177     0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
3178   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3179     0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
3180   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3181     0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
3182   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3183     0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
3184   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3185     0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
3186   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3187     0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
3188   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3189     0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
3190   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3191     0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
3192   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3193     0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
3194   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3195     0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
3196   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3197     0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
3198   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3199     0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
3200   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3201     0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
3202   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3203     0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
3204   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3205     0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
3206   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3207     0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
3208   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3209     0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
3210   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3211     0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
3212   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3213     0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
3214   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3215     0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
3216   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3217     0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
3218   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3219     0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
3220   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3221     0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
3222   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3223     0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
3224   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3225     0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
3226   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3227     0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
3228   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3229     0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
3230   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3231     0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
3232   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3233     0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
3234   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3235     0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
3236   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3237     0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
3238   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3239     0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
3240   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3241     0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
3242   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3243     0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
3244   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3245     0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
3246   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3247     0xe9400000, 0xff500000,
3248     "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3249   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3250     0xe9500000, 0xff500000,
3251     "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3252   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3253     0xe8600000, 0xff700000,
3254     "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3255   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3256     0xe8700000, 0xff700000,
3257     "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3258   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3259     0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
3260   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3261     0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
3262
3263   /* Filter out Bcc with cond=E or F, which are used for other instructions.  */
3264   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3265     0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
3266   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3267     0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
3268   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3269     0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
3270   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3271     0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
3272
3273   /* These have been 32-bit since the invention of Thumb.  */
3274   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3275      0xf000c000, 0xf800d001, "blx%c\t%B%x"},
3276   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3277      0xf000d000, 0xf800d000, "bl%c\t%B%x"},
3278
3279   /* Fallback.  */
3280   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3281       0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
3282   {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
3283 };
3284
3285 static const char *const arm_conditional[] =
3286 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
3287  "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
3288
3289 static const char *const arm_fp_const[] =
3290 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
3291
3292 static const char *const arm_shift[] =
3293 {"lsl", "lsr", "asr", "ror"};
3294
3295 typedef struct
3296 {
3297   const char *name;
3298   const char *description;
3299   const char *reg_names[16];
3300 }
3301 arm_regname;
3302
3303 static const arm_regname regnames[] =
3304 {
3305   { "reg-names-raw", N_("Select raw register names"),
3306     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
3307   { "reg-names-gcc", N_("Select register names used by GCC"),
3308     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl",  "fp",  "ip",  "sp",  "lr",  "pc" }},
3309   { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
3310     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp",  "lr",  "pc" }},
3311   { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
3312   { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
3313   { "reg-names-apcs", N_("Select register names used in the APCS"),
3314     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl",  "fp",  "ip",  "sp",  "lr",  "pc" }},
3315   { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
3316     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7",  "v8",  "IP",  "SP",  "LR",  "PC" }},
3317   { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
3318     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL",  "FP",  "IP",  "SP",  "LR",  "PC" }}
3319 };
3320
3321 static const char *const iwmmxt_wwnames[] =
3322 {"b", "h", "w", "d"};
3323
3324 static const char *const iwmmxt_wwssnames[] =
3325 {"b", "bus", "bc", "bss",
3326  "h", "hus", "hc", "hss",
3327  "w", "wus", "wc", "wss",
3328  "d", "dus", "dc", "dss"
3329 };
3330
3331 static const char *const iwmmxt_regnames[] =
3332 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
3333   "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
3334 };
3335
3336 static const char *const iwmmxt_cregnames[] =
3337 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
3338   "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
3339 };
3340
3341 /* Default to GCC register name set.  */
3342 static unsigned int regname_selected = 1;
3343
3344 #define NUM_ARM_OPTIONS   ARRAY_SIZE (regnames)
3345 #define arm_regnames      regnames[regname_selected].reg_names
3346
3347 static bfd_boolean force_thumb = FALSE;
3348
3349 /* Current IT instruction state.  This contains the same state as the IT
3350    bits in the CPSR.  */
3351 static unsigned int ifthen_state;
3352 /* IT state for the next instruction.  */
3353 static unsigned int ifthen_next_state;
3354 /* The address of the insn for which the IT state is valid.  */
3355 static bfd_vma ifthen_address;
3356 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
3357 /* Indicates that the current Conditional state is unconditional or outside
3358    an IT block.  */
3359 #define COND_UNCOND 16
3360
3361 \f
3362 /* Functions.  */
3363
3364 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
3365    Returns pointer to following character of the format string and
3366    fills in *VALUEP and *WIDTHP with the extracted value and number of
3367    bits extracted.  WIDTHP can be NULL.  */
3368
3369 static const char *
3370 arm_decode_bitfield (const char *ptr,
3371                      unsigned long insn,
3372                      unsigned long *valuep,
3373                      int *widthp)
3374 {
3375   unsigned long value = 0;
3376   int width = 0;
3377
3378   do
3379     {
3380       int start, end;
3381       int bits;
3382
3383       for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
3384         start = start * 10 + *ptr - '0';
3385       if (*ptr == '-')
3386         for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
3387           end = end * 10 + *ptr - '0';
3388       else
3389         end = start;
3390       bits = end - start;
3391       if (bits < 0)
3392         abort ();
3393       value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
3394       width += bits + 1;
3395     }
3396   while (*ptr++ == ',');
3397   *valuep = value;
3398   if (widthp)
3399     *widthp = width;
3400   return ptr - 1;
3401 }
3402
3403 static void
3404 arm_decode_shift (long given, fprintf_ftype func, void *stream,
3405                   bfd_boolean print_shift)
3406 {
3407   func (stream, "%s", arm_regnames[given & 0xf]);
3408
3409   if ((given & 0xff0) != 0)
3410     {
3411       if ((given & 0x10) == 0)
3412         {
3413           int amount = (given & 0xf80) >> 7;
3414           int shift = (given & 0x60) >> 5;
3415
3416           if (amount == 0)
3417             {
3418               if (shift == 3)
3419                 {
3420                   func (stream, ", rrx");
3421                   return;
3422                 }
3423
3424               amount = 32;
3425             }
3426
3427           if (print_shift)
3428             func (stream, ", %s #%d", arm_shift[shift], amount);
3429           else
3430             func (stream, ", #%d", amount);
3431         }
3432       else if ((given & 0x80) == 0x80)
3433         func (stream, "\t; <illegal shifter operand>");
3434       else if (print_shift)
3435         func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
3436               arm_regnames[(given & 0xf00) >> 8]);
3437       else
3438         func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
3439     }
3440 }
3441
3442 #define W_BIT 21
3443 #define I_BIT 22
3444 #define U_BIT 23
3445 #define P_BIT 24
3446
3447 #define WRITEBACK_BIT_SET   (given & (1 << W_BIT))
3448 #define IMMEDIATE_BIT_SET   (given & (1 << I_BIT))
3449 #define NEGATIVE_BIT_SET   ((given & (1 << U_BIT)) == 0)
3450 #define PRE_BIT_SET         (given & (1 << P_BIT))
3451
3452 /* Print one coprocessor instruction on INFO->STREAM.
3453    Return TRUE if the instuction matched, FALSE if this is not a
3454    recognised coprocessor instruction.  */
3455
3456 static bfd_boolean
3457 print_insn_coprocessor (bfd_vma pc,
3458                         struct disassemble_info *info,
3459                         long given,
3460                         bfd_boolean thumb)
3461 {
3462   const struct sopcode32 *insn;
3463   void *stream = info->stream;
3464   fprintf_ftype func = info->fprintf_func;
3465   unsigned long mask;
3466   unsigned long value = 0;
3467   int cond;
3468   int cp_num;
3469   struct arm_private_data *private_data = info->private_data;
3470   arm_feature_set allowed_arches = ARM_ARCH_NONE;
3471   arm_feature_set arm_ext_v8_1m_main =
3472     ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
3473
3474   allowed_arches = private_data->features;
3475
3476   for (insn = coprocessor_opcodes; insn->assembler; insn++)
3477     {
3478       unsigned long u_reg = 16;
3479       bfd_boolean is_unpredictable = FALSE;
3480       signed long value_in_comment = 0;
3481       const char *c;
3482
3483       if (ARM_FEATURE_ZERO (insn->arch))
3484         switch (insn->value)
3485           {
3486           case SENTINEL_IWMMXT_START:
3487             if (info->mach != bfd_mach_arm_XScale
3488                 && info->mach != bfd_mach_arm_iWMMXt
3489                 && info->mach != bfd_mach_arm_iWMMXt2)
3490               do
3491                 insn++;
3492               while ((! ARM_FEATURE_ZERO (insn->arch))
3493                      && insn->value != SENTINEL_IWMMXT_END);
3494             continue;
3495
3496           case SENTINEL_IWMMXT_END:
3497             continue;
3498
3499           case SENTINEL_GENERIC_START:
3500             allowed_arches = private_data->features;
3501             continue;
3502
3503           default:
3504             abort ();
3505           }
3506
3507       mask = insn->mask;
3508       value = insn->value;
3509       cp_num = (given >> 8) & 0xf;
3510
3511       if (thumb)
3512         {
3513           /* The high 4 bits are 0xe for Arm conditional instructions, and
3514              0xe for arm unconditional instructions.  The rest of the
3515              encoding is the same.  */
3516           mask |= 0xf0000000;
3517           value |= 0xe0000000;
3518           if (ifthen_state)
3519             cond = IFTHEN_COND;
3520           else
3521             cond = COND_UNCOND;
3522         }
3523       else
3524         {
3525           /* Only match unconditional instuctions against unconditional
3526              patterns.  */
3527           if ((given & 0xf0000000) == 0xf0000000)
3528             {
3529               mask |= 0xf0000000;
3530               cond = COND_UNCOND;
3531             }
3532           else
3533             {
3534               cond = (given >> 28) & 0xf;
3535               if (cond == 0xe)
3536                 cond = COND_UNCOND;
3537             }
3538         }
3539
3540       if ((insn->isa == T32 && !thumb)
3541           || (insn->isa == ARM && thumb))
3542         continue;
3543
3544       if ((given & mask) != value)
3545         continue;
3546
3547       if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
3548         continue;
3549
3550       if (insn->value == 0xfe000010     /* mcr2  */
3551           || insn->value == 0xfe100010  /* mrc2  */
3552           || insn->value == 0xfc100000  /* ldc2  */
3553           || insn->value == 0xfc000000) /* stc2  */
3554         {
3555           if (cp_num == 9 || cp_num == 10 || cp_num == 11)
3556             is_unpredictable = TRUE;
3557         }
3558       else if (insn->value == 0x0e000000     /* cdp  */
3559                || insn->value == 0xfe000000  /* cdp2  */
3560                || insn->value == 0x0e000010  /* mcr  */
3561                || insn->value == 0x0e100010  /* mrc  */
3562                || insn->value == 0x0c100000  /* ldc  */
3563                || insn->value == 0x0c000000) /* stc  */
3564         {
3565           /* Floating-point instructions.  */
3566           if (cp_num == 9 || cp_num == 10 || cp_num == 11)
3567             continue;
3568
3569           /* Armv8.1-M Mainline FP & MVE instructions.  */
3570           if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
3571               && !ARM_CPU_IS_ANY (allowed_arches)
3572               && (cp_num == 8 || cp_num == 14 || cp_num == 15))
3573             continue;
3574         }
3575
3576       for (c = insn->assembler; *c; c++)
3577         {
3578           if (*c == '%')
3579             {
3580               const char mod = *++c;
3581               switch (mod)
3582                 {
3583                 case '%':
3584                   func (stream, "%%");
3585                   break;
3586
3587                 case 'A':
3588                 case 'K':
3589                   {
3590                     int rn = (given >> 16) & 0xf;
3591                     bfd_vma offset = given & 0xff;
3592
3593                     if (mod == 'K')
3594                       offset = given & 0x7f;
3595
3596                     func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
3597
3598                     if (PRE_BIT_SET || WRITEBACK_BIT_SET)
3599                       {
3600                         /* Not unindexed.  The offset is scaled.  */
3601                         if (cp_num == 9)
3602                           /* vldr.16/vstr.16 will shift the address
3603                              left by 1 bit only.  */
3604                           offset = offset * 2;
3605                         else
3606                           offset = offset * 4;
3607
3608                         if (NEGATIVE_BIT_SET)
3609                           offset = - offset;
3610                         if (rn != 15)
3611                           value_in_comment = offset;
3612                       }
3613
3614                     if (PRE_BIT_SET)
3615                       {
3616                         if (offset)
3617                           func (stream, ", #%d]%s",
3618                                 (int) offset,
3619                                 WRITEBACK_BIT_SET ? "!" : "");
3620                         else if (NEGATIVE_BIT_SET)
3621                           func (stream, ", #-0]");
3622                         else
3623                           func (stream, "]");
3624                       }
3625                     else
3626                       {
3627                         func (stream, "]");
3628
3629                         if (WRITEBACK_BIT_SET)
3630                           {
3631                             if (offset)
3632                               func (stream, ", #%d", (int) offset);
3633                             else if (NEGATIVE_BIT_SET)
3634                               func (stream, ", #-0");
3635                           }
3636                         else
3637                           {
3638                             func (stream, ", {%s%d}",
3639                                   (NEGATIVE_BIT_SET && !offset) ? "-" : "",
3640                                   (int) offset);
3641                             value_in_comment = offset;
3642                           }
3643                       }
3644                     if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
3645                       {
3646                         func (stream, "\t; ");
3647                         /* For unaligned PCs, apply off-by-alignment
3648                            correction.  */
3649                         info->print_address_func (offset + pc
3650                                                   + info->bytes_per_chunk * 2
3651                                                   - (pc & 3),
3652                                                   info);
3653                       }
3654                   }
3655                   break;
3656
3657                 case 'B':
3658                   {
3659                     int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
3660                     int offset = (given >> 1) & 0x3f;
3661
3662                     if (offset == 1)
3663                       func (stream, "{d%d}", regno);
3664                     else if (regno + offset > 32)
3665                       func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
3666                     else
3667                       func (stream, "{d%d-d%d}", regno, regno + offset - 1);
3668                   }
3669                   break;
3670
3671                 case 'C':
3672                   {
3673                     bfd_boolean single = ((given >> 8) & 1) == 0;
3674                     char reg_prefix = single ? 's' : 'd';
3675                     int Dreg = (given >> 22) & 0x1;
3676                     int Vdreg = (given >> 12) & 0xf;
3677                     int reg = single ? ((Vdreg << 1) | Dreg)
3678                                      : ((Dreg << 4) | Vdreg);
3679                     int num = (given >> (single ? 0 : 1)) & 0x7f;
3680                     int maxreg = single ? 31 : 15;
3681                     int topreg = reg + num - 1;
3682
3683                     if (!num)
3684                       func (stream, "{VPR}");
3685                     else if (num == 1)
3686                       func (stream, "{%c%d, VPR}", reg_prefix, reg);
3687                     else if (topreg > maxreg)
3688                       func (stream, "{%c%d-<overflow reg d%d, VPR}",
3689                             reg_prefix, reg, single ? topreg >> 1 : topreg);
3690                     else
3691                       func (stream, "{%c%d-%c%d, VPR}", reg_prefix, reg,
3692                             reg_prefix, topreg);
3693                   }
3694                   break;
3695
3696                 case 'u':
3697                   if (cond != COND_UNCOND)
3698                     is_unpredictable = TRUE;
3699
3700                   /* Fall through.  */
3701                 case 'c':
3702                   if (cond != COND_UNCOND && cp_num == 9)
3703                     is_unpredictable = TRUE;
3704
3705                   func (stream, "%s", arm_conditional[cond]);
3706                   break;
3707
3708                 case 'I':
3709                   /* Print a Cirrus/DSP shift immediate.  */
3710                   /* Immediates are 7bit signed ints with bits 0..3 in
3711                      bits 0..3 of opcode and bits 4..6 in bits 5..7
3712                      of opcode.  */
3713                   {
3714                     int imm;
3715
3716                     imm = (given & 0xf) | ((given & 0xe0) >> 1);
3717
3718                     /* Is ``imm'' a negative number?  */
3719                     if (imm & 0x40)
3720                       imm -= 0x80;
3721
3722                     func (stream, "%d", imm);
3723                   }
3724
3725                   break;
3726
3727                 case 'J':
3728                   {
3729                     int regno = ((given >> 19) & 0x8) | ((given >> 13) & 0x7);
3730
3731                     switch (regno)
3732                       {
3733                       case 0x1:
3734                         func (stream, "FPSCR");
3735                         break;
3736                       case 0x2:
3737                         func (stream, "FPSCR_nzcvqc");
3738                         break;
3739                       case 0xc:
3740                         func (stream, "VPR");
3741                         break;
3742                       case 0xd:
3743                         func (stream, "P0");
3744                         break;
3745                       case 0xe:
3746                         func (stream, "FPCXTNS");
3747                         break;
3748                       case 0xf:
3749                         func (stream, "FPCXTS");
3750                         break;
3751                       default:
3752                         func (stream, "<invalid reg %d>", regno);
3753                         break;
3754                       }
3755                   }
3756                   break;
3757
3758                 case 'F':
3759                   switch (given & 0x00408000)
3760                     {
3761                     case 0:
3762                       func (stream, "4");
3763                       break;
3764                     case 0x8000:
3765                       func (stream, "1");
3766                       break;
3767                     case 0x00400000:
3768                       func (stream, "2");
3769                       break;
3770                     default:
3771                       func (stream, "3");
3772                     }
3773                   break;
3774
3775                 case 'P':
3776                   switch (given & 0x00080080)
3777                     {
3778                     case 0:
3779                       func (stream, "s");
3780                       break;
3781                     case 0x80:
3782                       func (stream, "d");
3783                       break;
3784                     case 0x00080000:
3785                       func (stream, "e");
3786                       break;
3787                     default:
3788                       func (stream, _("<illegal precision>"));
3789                       break;
3790                     }
3791                   break;
3792
3793                 case 'Q':
3794                   switch (given & 0x00408000)
3795                     {
3796                     case 0:
3797                       func (stream, "s");
3798                       break;
3799                     case 0x8000:
3800                       func (stream, "d");
3801                       break;
3802                     case 0x00400000:
3803                       func (stream, "e");
3804                       break;
3805                     default:
3806                       func (stream, "p");
3807                       break;
3808                     }
3809                   break;
3810
3811                 case 'R':
3812                   switch (given & 0x60)
3813                     {
3814                     case 0:
3815                       break;
3816                     case 0x20:
3817                       func (stream, "p");
3818                       break;
3819                     case 0x40:
3820                       func (stream, "m");
3821                       break;
3822                     default:
3823                       func (stream, "z");
3824                       break;
3825                     }
3826                   break;
3827
3828                 case '0': case '1': case '2': case '3': case '4':
3829                 case '5': case '6': case '7': case '8': case '9':
3830                   {
3831                     int width;
3832
3833                     c = arm_decode_bitfield (c, given, &value, &width);
3834
3835                     switch (*c)
3836                       {
3837                       case 'R':
3838                         if (value == 15)
3839                           is_unpredictable = TRUE;
3840                         /* Fall through.  */
3841                       case 'r':
3842                         if (c[1] == 'u')
3843                           {
3844                             /* Eat the 'u' character.  */
3845                             ++ c;
3846
3847                             if (u_reg == value)
3848                               is_unpredictable = TRUE;
3849                             u_reg = value;
3850                           }
3851                         func (stream, "%s", arm_regnames[value]);
3852                         break;
3853                       case 'V':
3854                         if (given & (1 << 6))
3855                           goto Q;
3856                         /* FALLTHROUGH */
3857                       case 'D':
3858                         func (stream, "d%ld", value);
3859                         break;
3860                       case 'Q':
3861                       Q:
3862                         if (value & 1)
3863                           func (stream, "<illegal reg q%ld.5>", value >> 1);
3864                         else
3865                           func (stream, "q%ld", value >> 1);
3866                         break;
3867                       case 'd':
3868                         func (stream, "%ld", value);
3869                         value_in_comment = value;
3870                         break;
3871                       case 'E':
3872                         {
3873                           /* Converts immediate 8 bit back to float value.  */
3874                           unsigned floatVal = (value & 0x80) << 24
3875                             | (value & 0x3F) << 19
3876                             | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
3877
3878                           /* Quarter float have a maximum value of 31.0.
3879                              Get floating point value multiplied by 1e7.
3880                              The maximum value stays in limit of a 32-bit int.  */
3881                           unsigned decVal =
3882                             (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
3883                             (16 + (value & 0xF));
3884
3885                           if (!(decVal % 1000000))
3886                             func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
3887                                   floatVal, value & 0x80 ? '-' : ' ',
3888                                   decVal / 10000000,
3889                                   decVal % 10000000 / 1000000);
3890                           else if (!(decVal % 10000))
3891                             func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
3892                                   floatVal, value & 0x80 ? '-' : ' ',
3893                                   decVal / 10000000,
3894                                   decVal % 10000000 / 10000);
3895                           else
3896                             func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
3897                                   floatVal, value & 0x80 ? '-' : ' ',
3898                                   decVal / 10000000, decVal % 10000000);
3899                           break;
3900                         }
3901                       case 'k':
3902                         {
3903                           int from = (given & (1 << 7)) ? 32 : 16;
3904                           func (stream, "%ld", from - value);
3905                         }
3906                         break;
3907
3908                       case 'f':
3909                         if (value > 7)
3910                           func (stream, "#%s", arm_fp_const[value & 7]);
3911                         else
3912                           func (stream, "f%ld", value);
3913                         break;
3914
3915                       case 'w':
3916                         if (width == 2)
3917                           func (stream, "%s", iwmmxt_wwnames[value]);
3918                         else
3919                           func (stream, "%s", iwmmxt_wwssnames[value]);
3920                         break;
3921
3922                       case 'g':
3923                         func (stream, "%s", iwmmxt_regnames[value]);
3924                         break;
3925                       case 'G':
3926                         func (stream, "%s", iwmmxt_cregnames[value]);
3927                         break;
3928
3929                       case 'x':
3930                         func (stream, "0x%lx", (value & 0xffffffffUL));
3931                         break;
3932
3933                       case 'c':
3934                         switch (value)
3935                           {
3936                           case 0:
3937                             func (stream, "eq");
3938                             break;
3939
3940                           case 1:
3941                             func (stream, "vs");
3942                             break;
3943
3944                           case 2:
3945                             func (stream, "ge");
3946                             break;
3947
3948                           case 3:
3949                             func (stream, "gt");
3950                             break;
3951
3952                           default:
3953                             func (stream, "??");
3954                             break;
3955                           }
3956                         break;
3957
3958                       case '`':
3959                         c++;
3960                         if (value == 0)
3961                           func (stream, "%c", *c);
3962                         break;
3963                       case '\'':
3964                         c++;
3965                         if (value == ((1ul << width) - 1))
3966                           func (stream, "%c", *c);
3967                         break;
3968                       case '?':
3969                         func (stream, "%c", c[(1 << width) - (int) value]);
3970                         c += 1 << width;
3971                         break;
3972                       default:
3973                         abort ();
3974                       }
3975                   }
3976                   break;
3977
3978                 case 'y':
3979                 case 'z':
3980                   {
3981                     int single = *c++ == 'y';
3982                     int regno;
3983
3984                     switch (*c)
3985                       {
3986                       case '4': /* Sm pair */
3987                       case '0': /* Sm, Dm */
3988                         regno = given & 0x0000000f;
3989                         if (single)
3990                           {
3991                             regno <<= 1;
3992                             regno += (given >> 5) & 1;
3993                           }
3994                         else
3995                           regno += ((given >> 5) & 1) << 4;
3996                         break;
3997
3998                       case '1': /* Sd, Dd */
3999                         regno = (given >> 12) & 0x0000000f;
4000                         if (single)
4001                           {
4002                             regno <<= 1;
4003                             regno += (given >> 22) & 1;
4004                           }
4005                         else
4006                           regno += ((given >> 22) & 1) << 4;
4007                         break;
4008
4009                       case '2': /* Sn, Dn */
4010                         regno = (given >> 16) & 0x0000000f;
4011                         if (single)
4012                           {
4013                             regno <<= 1;
4014                             regno += (given >> 7) & 1;
4015                           }
4016                         else
4017                           regno += ((given >> 7) & 1) << 4;
4018                         break;
4019
4020                       case '3': /* List */
4021                         func (stream, "{");
4022                         regno = (given >> 12) & 0x0000000f;
4023                         if (single)
4024                           {
4025                             regno <<= 1;
4026                             regno += (given >> 22) & 1;
4027                           }
4028                         else
4029                           regno += ((given >> 22) & 1) << 4;
4030                         break;
4031
4032                       default:
4033                         abort ();
4034                       }
4035
4036                     func (stream, "%c%d", single ? 's' : 'd', regno);
4037
4038                     if (*c == '3')
4039                       {
4040                         int count = given & 0xff;
4041
4042                         if (single == 0)
4043                           count >>= 1;
4044
4045                         if (--count)
4046                           {
4047                             func (stream, "-%c%d",
4048                                   single ? 's' : 'd',
4049                                   regno + count);
4050                           }
4051
4052                         func (stream, "}");
4053                       }
4054                     else if (*c == '4')
4055                       func (stream, ", %c%d", single ? 's' : 'd',
4056                             regno + 1);
4057                   }
4058                   break;
4059
4060                 case 'L':
4061                   switch (given & 0x00400100)
4062                     {
4063                     case 0x00000000: func (stream, "b"); break;
4064                     case 0x00400000: func (stream, "h"); break;
4065                     case 0x00000100: func (stream, "w"); break;
4066                     case 0x00400100: func (stream, "d"); break;
4067                     default:
4068                       break;
4069                     }
4070                   break;
4071
4072                 case 'Z':
4073                   {
4074                     /* given (20, 23) | given (0, 3) */
4075                     value = ((given >> 16) & 0xf0) | (given & 0xf);
4076                     func (stream, "%d", (int) value);
4077                   }
4078                   break;
4079
4080                 case 'l':
4081                   /* This is like the 'A' operator, except that if
4082                      the width field "M" is zero, then the offset is
4083                      *not* multiplied by four.  */
4084                   {
4085                     int offset = given & 0xff;
4086                     int multiplier = (given & 0x00000100) ? 4 : 1;
4087
4088                     func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
4089
4090                     if (multiplier > 1)
4091                       {
4092                         value_in_comment = offset * multiplier;
4093                         if (NEGATIVE_BIT_SET)
4094                           value_in_comment = - value_in_comment;
4095                       }
4096
4097                     if (offset)
4098                       {
4099                         if (PRE_BIT_SET)
4100                           func (stream, ", #%s%d]%s",
4101                                 NEGATIVE_BIT_SET ? "-" : "",
4102                                 offset * multiplier,
4103                                 WRITEBACK_BIT_SET ? "!" : "");
4104                         else
4105                           func (stream, "], #%s%d",
4106                                 NEGATIVE_BIT_SET ? "-" : "",
4107                                 offset * multiplier);
4108                       }
4109                     else
4110                       func (stream, "]");
4111                   }
4112                   break;
4113
4114                 case 'r':
4115                   {
4116                     int imm4 = (given >> 4) & 0xf;
4117                     int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
4118                     int ubit = ! NEGATIVE_BIT_SET;
4119                     const char *rm = arm_regnames [given & 0xf];
4120                     const char *rn = arm_regnames [(given >> 16) & 0xf];
4121
4122                     switch (puw_bits)
4123                       {
4124                       case 1:
4125                       case 3:
4126                         func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
4127                         if (imm4)
4128                           func (stream, ", lsl #%d", imm4);
4129                         break;
4130
4131                       case 4:
4132                       case 5:
4133                       case 6:
4134                       case 7:
4135                         func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
4136                         if (imm4 > 0)
4137                           func (stream, ", lsl #%d", imm4);
4138                         func (stream, "]");
4139                         if (puw_bits == 5 || puw_bits == 7)
4140                           func (stream, "!");
4141                         break;
4142
4143                       default:
4144                         func (stream, "INVALID");
4145                       }
4146                   }
4147                   break;
4148
4149                 case 'i':
4150                   {
4151                     long imm5;
4152                     imm5 = ((given & 0x100) >> 4) | (given & 0xf);
4153                     func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
4154                   }
4155                   break;
4156
4157                 default:
4158                   abort ();
4159                 }
4160             }
4161           else
4162             func (stream, "%c", *c);
4163         }
4164
4165       if (value_in_comment > 32 || value_in_comment < -16)
4166         func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
4167
4168       if (is_unpredictable)
4169         func (stream, UNPREDICTABLE_INSTRUCTION);
4170
4171       return TRUE;
4172     }
4173   return FALSE;
4174 }
4175
4176 /* Decodes and prints ARM addressing modes.  Returns the offset
4177    used in the address, if any, if it is worthwhile printing the
4178    offset as a hexadecimal value in a comment at the end of the
4179    line of disassembly.  */
4180
4181 static signed long
4182 print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
4183 {
4184   void *stream = info->stream;
4185   fprintf_ftype func = info->fprintf_func;
4186   bfd_vma offset = 0;
4187
4188   if (((given & 0x000f0000) == 0x000f0000)
4189       && ((given & 0x02000000) == 0))
4190     {
4191       offset = given & 0xfff;
4192
4193       func (stream, "[pc");
4194
4195       if (PRE_BIT_SET)
4196         {
4197           /* Pre-indexed.  Elide offset of positive zero when
4198              non-writeback.  */
4199           if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
4200             func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4201
4202           if (NEGATIVE_BIT_SET)
4203             offset = -offset;
4204
4205           offset += pc + 8;
4206
4207           /* Cope with the possibility of write-back
4208              being used.  Probably a very dangerous thing
4209              for the programmer to do, but who are we to
4210              argue ?  */
4211           func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
4212         }
4213       else  /* Post indexed.  */
4214         {
4215           func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4216
4217           /* Ie ignore the offset.  */
4218           offset = pc + 8;
4219         }
4220
4221       func (stream, "\t; ");
4222       info->print_address_func (offset, info);
4223       offset = 0;
4224     }
4225   else
4226     {
4227       func (stream, "[%s",
4228             arm_regnames[(given >> 16) & 0xf]);
4229
4230       if (PRE_BIT_SET)
4231         {
4232           if ((given & 0x02000000) == 0)
4233             {
4234               /* Elide offset of positive zero when non-writeback.  */
4235               offset = given & 0xfff;
4236               if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
4237                 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4238             }
4239           else
4240             {
4241               func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
4242               arm_decode_shift (given, func, stream, TRUE);
4243             }
4244
4245           func (stream, "]%s",
4246                 WRITEBACK_BIT_SET ? "!" : "");
4247         }
4248       else
4249         {
4250           if ((given & 0x02000000) == 0)
4251             {
4252               /* Always show offset.  */
4253               offset = given & 0xfff;
4254               func (stream, "], #%s%d",
4255                     NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4256             }
4257           else
4258             {
4259               func (stream, "], %s",
4260                     NEGATIVE_BIT_SET ? "-" : "");
4261               arm_decode_shift (given, func, stream, TRUE);
4262             }
4263         }
4264       if (NEGATIVE_BIT_SET)
4265         offset = -offset;
4266     }
4267
4268   return (signed long) offset;
4269 }
4270
4271 /* Print one neon instruction on INFO->STREAM.
4272    Return TRUE if the instuction matched, FALSE if this is not a
4273    recognised neon instruction.  */
4274
4275 static bfd_boolean
4276 print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
4277 {
4278   const struct opcode32 *insn;
4279   void *stream = info->stream;
4280   fprintf_ftype func = info->fprintf_func;
4281
4282   if (thumb)
4283     {
4284       if ((given & 0xef000000) == 0xef000000)
4285         {
4286           /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding.  */
4287           unsigned long bit28 = given & (1 << 28);
4288
4289           given &= 0x00ffffff;
4290           if (bit28)
4291             given |= 0xf3000000;
4292           else
4293             given |= 0xf2000000;
4294         }
4295       else if ((given & 0xff000000) == 0xf9000000)
4296         given ^= 0xf9000000 ^ 0xf4000000;
4297       else
4298         return FALSE;
4299     }
4300
4301   for (insn = neon_opcodes; insn->assembler; insn++)
4302     {
4303       if ((given & insn->mask) == insn->value)
4304         {
4305           signed long value_in_comment = 0;
4306           bfd_boolean is_unpredictable = FALSE;
4307           const char *c;
4308
4309           for (c = insn->assembler; *c; c++)
4310             {
4311               if (*c == '%')
4312                 {
4313                   switch (*++c)
4314                     {
4315                     case '%':
4316                       func (stream, "%%");
4317                       break;
4318
4319                     case 'u':
4320                       if (thumb && ifthen_state)
4321                         is_unpredictable = TRUE;
4322
4323                       /* Fall through.  */
4324                     case 'c':
4325                       if (thumb && ifthen_state)
4326                         func (stream, "%s", arm_conditional[IFTHEN_COND]);
4327                       break;
4328
4329                     case 'A':
4330                       {
4331                         static const unsigned char enc[16] =
4332                         {
4333                           0x4, 0x14, /* st4 0,1 */
4334                           0x4, /* st1 2 */
4335                           0x4, /* st2 3 */
4336                           0x3, /* st3 4 */
4337                           0x13, /* st3 5 */
4338                           0x3, /* st1 6 */
4339                           0x1, /* st1 7 */
4340                           0x2, /* st2 8 */
4341                           0x12, /* st2 9 */
4342                           0x2, /* st1 10 */
4343                           0, 0, 0, 0, 0
4344                         };
4345                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4346                         int rn = ((given >> 16) & 0xf);
4347                         int rm = ((given >> 0) & 0xf);
4348                         int align = ((given >> 4) & 0x3);
4349                         int type = ((given >> 8) & 0xf);
4350                         int n = enc[type] & 0xf;
4351                         int stride = (enc[type] >> 4) + 1;
4352                         int ix;
4353
4354                         func (stream, "{");
4355                         if (stride > 1)
4356                           for (ix = 0; ix != n; ix++)
4357                             func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
4358                         else if (n == 1)
4359                           func (stream, "d%d", rd);
4360                         else
4361                           func (stream, "d%d-d%d", rd, rd + n - 1);
4362                         func (stream, "}, [%s", arm_regnames[rn]);
4363                         if (align)
4364                           func (stream, " :%d", 32 << align);
4365                         func (stream, "]");
4366                         if (rm == 0xd)
4367                           func (stream, "!");
4368                         else if (rm != 0xf)
4369                           func (stream, ", %s", arm_regnames[rm]);
4370                       }
4371                       break;
4372
4373                     case 'B':
4374                       {
4375                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4376                         int rn = ((given >> 16) & 0xf);
4377                         int rm = ((given >> 0) & 0xf);
4378                         int idx_align = ((given >> 4) & 0xf);
4379                         int align = 0;
4380                         int size = ((given >> 10) & 0x3);
4381                         int idx = idx_align >> (size + 1);
4382                         int length = ((given >> 8) & 3) + 1;
4383                         int stride = 1;
4384                         int i;
4385
4386                         if (length > 1 && size > 0)
4387                           stride = (idx_align & (1 << size)) ? 2 : 1;
4388
4389                         switch (length)
4390                           {
4391                           case 1:
4392                             {
4393                               int amask = (1 << size) - 1;
4394                               if ((idx_align & (1 << size)) != 0)
4395                                 return FALSE;
4396                               if (size > 0)
4397                                 {
4398                                   if ((idx_align & amask) == amask)
4399                                     align = 8 << size;
4400                                   else if ((idx_align & amask) != 0)
4401                                     return FALSE;
4402                                 }
4403                               }
4404                             break;
4405
4406                           case 2:
4407                             if (size == 2 && (idx_align & 2) != 0)
4408                               return FALSE;
4409                             align = (idx_align & 1) ? 16 << size : 0;
4410                             break;
4411
4412                           case 3:
4413                             if ((size == 2 && (idx_align & 3) != 0)
4414                                 || (idx_align & 1) != 0)
4415                               return FALSE;
4416                             break;
4417
4418                           case 4:
4419                             if (size == 2)
4420                               {
4421                                 if ((idx_align & 3) == 3)
4422                                   return FALSE;
4423                                 align = (idx_align & 3) * 64;
4424                               }
4425                             else
4426                               align = (idx_align & 1) ? 32 << size : 0;
4427                             break;
4428
4429                           default:
4430                             abort ();
4431                           }
4432
4433                         func (stream, "{");
4434                         for (i = 0; i < length; i++)
4435                           func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
4436                             rd + i * stride, idx);
4437                         func (stream, "}, [%s", arm_regnames[rn]);
4438                         if (align)
4439                           func (stream, " :%d", align);
4440                         func (stream, "]");
4441                         if (rm == 0xd)
4442                           func (stream, "!");
4443                         else if (rm != 0xf)
4444                           func (stream, ", %s", arm_regnames[rm]);
4445                       }
4446                       break;
4447
4448                     case 'C':
4449                       {
4450                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4451                         int rn = ((given >> 16) & 0xf);
4452                         int rm = ((given >> 0) & 0xf);
4453                         int align = ((given >> 4) & 0x1);
4454                         int size = ((given >> 6) & 0x3);
4455                         int type = ((given >> 8) & 0x3);
4456                         int n = type + 1;
4457                         int stride = ((given >> 5) & 0x1);
4458                         int ix;
4459
4460                         if (stride && (n == 1))
4461                           n++;
4462                         else
4463                           stride++;
4464
4465                         func (stream, "{");
4466                         if (stride > 1)
4467                           for (ix = 0; ix != n; ix++)
4468                             func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
4469                         else if (n == 1)
4470                           func (stream, "d%d[]", rd);
4471                         else
4472                           func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
4473                         func (stream, "}, [%s", arm_regnames[rn]);
4474                         if (align)
4475                           {
4476                             align = (8 * (type + 1)) << size;
4477                             if (type == 3)
4478                               align = (size > 1) ? align >> 1 : align;
4479                             if (type == 2 || (type == 0 && !size))
4480                               func (stream, " :<bad align %d>", align);
4481                             else
4482                               func (stream, " :%d", align);
4483                           }
4484                         func (stream, "]");
4485                         if (rm == 0xd)
4486                           func (stream, "!");
4487                         else if (rm != 0xf)
4488                           func (stream, ", %s", arm_regnames[rm]);
4489                       }
4490                       break;
4491
4492                     case 'D':
4493                       {
4494                         int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
4495                         int size = (given >> 20) & 3;
4496                         int reg = raw_reg & ((4 << size) - 1);
4497                         int ix = raw_reg >> size >> 2;
4498
4499                         func (stream, "d%d[%d]", reg, ix);
4500                       }
4501                       break;
4502
4503                     case 'E':
4504                       /* Neon encoded constant for mov, mvn, vorr, vbic.  */
4505                       {
4506                         int bits = 0;
4507                         int cmode = (given >> 8) & 0xf;
4508                         int op = (given >> 5) & 0x1;
4509                         unsigned long value = 0, hival = 0;
4510                         unsigned shift;
4511                         int size = 0;
4512                         int isfloat = 0;
4513
4514                         bits |= ((given >> 24) & 1) << 7;
4515                         bits |= ((given >> 16) & 7) << 4;
4516                         bits |= ((given >> 0) & 15) << 0;
4517
4518                         if (cmode < 8)
4519                           {
4520                             shift = (cmode >> 1) & 3;
4521                             value = (unsigned long) bits << (8 * shift);
4522                             size = 32;
4523                           }
4524                         else if (cmode < 12)
4525                           {
4526                             shift = (cmode >> 1) & 1;
4527                             value = (unsigned long) bits << (8 * shift);
4528                             size = 16;
4529                           }
4530                         else if (cmode < 14)
4531                           {
4532                             shift = (cmode & 1) + 1;
4533                             value = (unsigned long) bits << (8 * shift);
4534                             value |= (1ul << (8 * shift)) - 1;
4535                             size = 32;
4536                           }
4537                         else if (cmode == 14)
4538                           {
4539                             if (op)
4540                               {
4541                                 /* Bit replication into bytes.  */
4542                                 int ix;
4543                                 unsigned long mask;
4544
4545                                 value = 0;
4546                                 hival = 0;
4547                                 for (ix = 7; ix >= 0; ix--)
4548                                   {
4549                                     mask = ((bits >> ix) & 1) ? 0xff : 0;
4550                                     if (ix <= 3)
4551                                       value = (value << 8) | mask;
4552                                     else
4553                                       hival = (hival << 8) | mask;
4554                                   }
4555                                 size = 64;
4556                               }
4557                             else
4558                               {
4559                                 /* Byte replication.  */
4560                                 value = (unsigned long) bits;
4561                                 size = 8;
4562                               }
4563                           }
4564                         else if (!op)
4565                           {
4566                             /* Floating point encoding.  */
4567                             int tmp;
4568
4569                             value = (unsigned long)  (bits & 0x7f) << 19;
4570                             value |= (unsigned long) (bits & 0x80) << 24;
4571                             tmp = bits & 0x40 ? 0x3c : 0x40;
4572                             value |= (unsigned long) tmp << 24;
4573                             size = 32;
4574                             isfloat = 1;
4575                           }
4576                         else
4577                           {
4578                             func (stream, "<illegal constant %.8x:%x:%x>",
4579                                   bits, cmode, op);
4580                             size = 32;
4581                             break;
4582                           }
4583                         switch (size)
4584                           {
4585                           case 8:
4586                             func (stream, "#%ld\t; 0x%.2lx", value, value);
4587                             break;
4588
4589                           case 16:
4590                             func (stream, "#%ld\t; 0x%.4lx", value, value);
4591                             break;
4592
4593                           case 32:
4594                             if (isfloat)
4595                               {
4596                                 unsigned char valbytes[4];
4597                                 double fvalue;
4598
4599                                 /* Do this a byte at a time so we don't have to
4600                                    worry about the host's endianness.  */
4601                                 valbytes[0] = value & 0xff;
4602                                 valbytes[1] = (value >> 8) & 0xff;
4603                                 valbytes[2] = (value >> 16) & 0xff;
4604                                 valbytes[3] = (value >> 24) & 0xff;
4605
4606                                 floatformat_to_double
4607                                   (& floatformat_ieee_single_little, valbytes,
4608                                   & fvalue);
4609
4610                                 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
4611                                       value);
4612                               }
4613                             else
4614                               func (stream, "#%ld\t; 0x%.8lx",
4615                                     (long) (((value & 0x80000000L) != 0)
4616                                             ? value | ~0xffffffffL : value),
4617                                     value);
4618                             break;
4619
4620                           case 64:
4621                             func (stream, "#0x%.8lx%.8lx", hival, value);
4622                             break;
4623
4624                           default:
4625                             abort ();
4626                           }
4627                       }
4628                       break;
4629
4630                     case 'F':
4631                       {
4632                         int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
4633                         int num = (given >> 8) & 0x3;
4634
4635                         if (!num)
4636                           func (stream, "{d%d}", regno);
4637                         else if (num + regno >= 32)
4638                           func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
4639                         else
4640                           func (stream, "{d%d-d%d}", regno, regno + num);
4641                       }
4642                       break;
4643
4644
4645                     case '0': case '1': case '2': case '3': case '4':
4646                     case '5': case '6': case '7': case '8': case '9':
4647                       {
4648                         int width;
4649                         unsigned long value;
4650
4651                         c = arm_decode_bitfield (c, given, &value, &width);
4652
4653                         switch (*c)
4654                           {
4655                           case 'r':
4656                             func (stream, "%s", arm_regnames[value]);
4657                             break;
4658                           case 'd':
4659                             func (stream, "%ld", value);
4660                             value_in_comment = value;
4661                             break;
4662                           case 'e':
4663                             func (stream, "%ld", (1ul << width) - value);
4664                             break;
4665
4666                           case 'S':
4667                           case 'T':
4668                           case 'U':
4669                             /* Various width encodings.  */
4670                             {
4671                               int base = 8 << (*c - 'S'); /* 8,16 or 32 */
4672                               int limit;
4673                               unsigned low, high;
4674
4675                               c++;
4676                               if (*c >= '0' && *c <= '9')
4677                                 limit = *c - '0';
4678                               else if (*c >= 'a' && *c <= 'f')
4679                                 limit = *c - 'a' + 10;
4680                               else
4681                                 abort ();
4682                               low = limit >> 2;
4683                               high = limit & 3;
4684
4685                               if (value < low || value > high)
4686                                 func (stream, "<illegal width %d>", base << value);
4687                               else
4688                                 func (stream, "%d", base << value);
4689                             }
4690                             break;
4691                           case 'R':
4692                             if (given & (1 << 6))
4693                               goto Q;
4694                             /* FALLTHROUGH */
4695                           case 'D':
4696                             func (stream, "d%ld", value);
4697                             break;
4698                           case 'Q':
4699                           Q:
4700                             if (value & 1)
4701                               func (stream, "<illegal reg q%ld.5>", value >> 1);
4702                             else
4703                               func (stream, "q%ld", value >> 1);
4704                             break;
4705
4706                           case '`':
4707                             c++;
4708                             if (value == 0)
4709                               func (stream, "%c", *c);
4710                             break;
4711                           case '\'':
4712                             c++;
4713                             if (value == ((1ul << width) - 1))
4714                               func (stream, "%c", *c);
4715                             break;
4716                           case '?':
4717                             func (stream, "%c", c[(1 << width) - (int) value]);
4718                             c += 1 << width;
4719                             break;
4720                           default:
4721                             abort ();
4722                           }
4723                       }
4724                       break;
4725
4726                     default:
4727                       abort ();
4728                     }
4729                 }
4730               else
4731                 func (stream, "%c", *c);
4732             }
4733
4734           if (value_in_comment > 32 || value_in_comment < -16)
4735             func (stream, "\t; 0x%lx", value_in_comment);
4736
4737           if (is_unpredictable)
4738             func (stream, UNPREDICTABLE_INSTRUCTION);
4739
4740           return TRUE;
4741         }
4742     }
4743   return FALSE;
4744 }
4745
4746 /* Return the name of a v7A special register.  */
4747
4748 static const char *
4749 banked_regname (unsigned reg)
4750 {
4751   switch (reg)
4752     {
4753       case 15: return "CPSR";
4754       case 32: return "R8_usr";
4755       case 33: return "R9_usr";
4756       case 34: return "R10_usr";
4757       case 35: return "R11_usr";
4758       case 36: return "R12_usr";
4759       case 37: return "SP_usr";
4760       case 38: return "LR_usr";
4761       case 40: return "R8_fiq";
4762       case 41: return "R9_fiq";
4763       case 42: return "R10_fiq";
4764       case 43: return "R11_fiq";
4765       case 44: return "R12_fiq";
4766       case 45: return "SP_fiq";
4767       case 46: return "LR_fiq";
4768       case 48: return "LR_irq";
4769       case 49: return "SP_irq";
4770       case 50: return "LR_svc";
4771       case 51: return "SP_svc";
4772       case 52: return "LR_abt";
4773       case 53: return "SP_abt";
4774       case 54: return "LR_und";
4775       case 55: return "SP_und";
4776       case 60: return "LR_mon";
4777       case 61: return "SP_mon";
4778       case 62: return "ELR_hyp";
4779       case 63: return "SP_hyp";
4780       case 79: return "SPSR";
4781       case 110: return "SPSR_fiq";
4782       case 112: return "SPSR_irq";
4783       case 114: return "SPSR_svc";
4784       case 116: return "SPSR_abt";
4785       case 118: return "SPSR_und";
4786       case 124: return "SPSR_mon";
4787       case 126: return "SPSR_hyp";
4788       default: return NULL;
4789     }
4790 }
4791
4792 /* Return the name of the DMB/DSB option.  */
4793 static const char *
4794 data_barrier_option (unsigned option)
4795 {
4796   switch (option & 0xf)
4797     {
4798     case 0xf: return "sy";
4799     case 0xe: return "st";
4800     case 0xd: return "ld";
4801     case 0xb: return "ish";
4802     case 0xa: return "ishst";
4803     case 0x9: return "ishld";
4804     case 0x7: return "un";
4805     case 0x6: return "unst";
4806     case 0x5: return "nshld";
4807     case 0x3: return "osh";
4808     case 0x2: return "oshst";
4809     case 0x1: return "oshld";
4810     default:  return NULL;
4811     }
4812 }
4813
4814 /* Print one ARM instruction from PC on INFO->STREAM.  */
4815
4816 static void
4817 print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
4818 {
4819   const struct opcode32 *insn;
4820   void *stream = info->stream;
4821   fprintf_ftype func = info->fprintf_func;
4822   struct arm_private_data *private_data = info->private_data;
4823
4824   if (print_insn_coprocessor (pc, info, given, FALSE))
4825     return;
4826
4827   if (print_insn_neon (info, given, FALSE))
4828     return;
4829
4830   for (insn = arm_opcodes; insn->assembler; insn++)
4831     {
4832       if ((given & insn->mask) != insn->value)
4833         continue;
4834
4835       if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
4836         continue;
4837
4838       /* Special case: an instruction with all bits set in the condition field
4839          (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
4840          or by the catchall at the end of the table.  */
4841       if ((given & 0xF0000000) != 0xF0000000
4842           || (insn->mask & 0xF0000000) == 0xF0000000
4843           || (insn->mask == 0 && insn->value == 0))
4844         {
4845           unsigned long u_reg = 16;
4846           unsigned long U_reg = 16;
4847           bfd_boolean is_unpredictable = FALSE;
4848           signed long value_in_comment = 0;
4849           const char *c;
4850
4851           for (c = insn->assembler; *c; c++)
4852             {
4853               if (*c == '%')
4854                 {
4855                   bfd_boolean allow_unpredictable = FALSE;
4856
4857                   switch (*++c)
4858                     {
4859                     case '%':
4860                       func (stream, "%%");
4861                       break;
4862
4863                     case 'a':
4864                       value_in_comment = print_arm_address (pc, info, given);
4865                       break;
4866
4867                     case 'P':
4868                       /* Set P address bit and use normal address
4869                          printing routine.  */
4870                       value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
4871                       break;
4872
4873                     case 'S':
4874                       allow_unpredictable = TRUE;
4875                       /* Fall through.  */
4876                     case 's':
4877                       if ((given & 0x004f0000) == 0x004f0000)
4878                         {
4879                           /* PC relative with immediate offset.  */
4880                           bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
4881
4882                           if (PRE_BIT_SET)
4883                             {
4884                               /* Elide positive zero offset.  */
4885                               if (offset || NEGATIVE_BIT_SET)
4886                                 func (stream, "[pc, #%s%d]\t; ",
4887                                       NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4888                               else
4889                                 func (stream, "[pc]\t; ");
4890                               if (NEGATIVE_BIT_SET)
4891                                 offset = -offset;
4892                               info->print_address_func (offset + pc + 8, info);
4893                             }
4894                           else
4895                             {
4896                               /* Always show the offset.  */
4897                               func (stream, "[pc], #%s%d",
4898                                     NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4899                               if (! allow_unpredictable)
4900                                 is_unpredictable = TRUE;
4901                             }
4902                         }
4903                       else
4904                         {
4905                           int offset = ((given & 0xf00) >> 4) | (given & 0xf);
4906
4907                           func (stream, "[%s",
4908                                 arm_regnames[(given >> 16) & 0xf]);
4909
4910                           if (PRE_BIT_SET)
4911                             {
4912                               if (IMMEDIATE_BIT_SET)
4913                                 {
4914                                   /* Elide offset for non-writeback
4915                                      positive zero.  */
4916                                   if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
4917                                       || offset)
4918                                     func (stream, ", #%s%d",
4919                                           NEGATIVE_BIT_SET ? "-" : "", offset);
4920
4921                                   if (NEGATIVE_BIT_SET)
4922                                     offset = -offset;
4923
4924                                   value_in_comment = offset;
4925                                 }
4926                               else
4927                                 {
4928                                   /* Register Offset or Register Pre-Indexed.  */
4929                                   func (stream, ", %s%s",
4930                                         NEGATIVE_BIT_SET ? "-" : "",
4931                                         arm_regnames[given & 0xf]);
4932
4933                                   /* Writing back to the register that is the source/
4934                                      destination of the load/store is unpredictable.  */
4935                                   if (! allow_unpredictable
4936                                       && WRITEBACK_BIT_SET
4937                                       && ((given & 0xf) == ((given >> 12) & 0xf)))
4938                                     is_unpredictable = TRUE;
4939                                 }
4940
4941                               func (stream, "]%s",
4942                                     WRITEBACK_BIT_SET ? "!" : "");
4943                             }
4944                           else
4945                             {
4946                               if (IMMEDIATE_BIT_SET)
4947                                 {
4948                                   /* Immediate Post-indexed.  */
4949                                   /* PR 10924: Offset must be printed, even if it is zero.  */
4950                                   func (stream, "], #%s%d",
4951                                         NEGATIVE_BIT_SET ? "-" : "", offset);
4952                                   if (NEGATIVE_BIT_SET)
4953                                     offset = -offset;
4954                                   value_in_comment = offset;
4955                                 }
4956                               else
4957                                 {
4958                                   /* Register Post-indexed.  */
4959                                   func (stream, "], %s%s",
4960                                         NEGATIVE_BIT_SET ? "-" : "",
4961                                         arm_regnames[given & 0xf]);
4962
4963                                   /* Writing back to the register that is the source/
4964                                      destination of the load/store is unpredictable.  */
4965                                   if (! allow_unpredictable
4966                                       && (given & 0xf) == ((given >> 12) & 0xf))
4967                                     is_unpredictable = TRUE;
4968                                 }
4969
4970                               if (! allow_unpredictable)
4971                                 {
4972                                   /* Writeback is automatically implied by post- addressing.
4973                                      Setting the W bit is unnecessary and ARM specify it as
4974                                      being unpredictable.  */
4975                                   if (WRITEBACK_BIT_SET
4976                                       /* Specifying the PC register as the post-indexed
4977                                          registers is also unpredictable.  */
4978                                       || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
4979                                     is_unpredictable = TRUE;
4980                                 }
4981                             }
4982                         }
4983                       break;
4984
4985                     case 'b':
4986                       {
4987                         bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
4988                         info->print_address_func (disp * 4 + pc + 8, info);
4989                       }
4990                       break;
4991
4992                     case 'c':
4993                       if (((given >> 28) & 0xf) != 0xe)
4994                         func (stream, "%s",
4995                               arm_conditional [(given >> 28) & 0xf]);
4996                       break;
4997
4998                     case 'm':
4999                       {
5000                         int started = 0;
5001                         int reg;
5002
5003                         func (stream, "{");
5004                         for (reg = 0; reg < 16; reg++)
5005                           if ((given & (1 << reg)) != 0)
5006                             {
5007                               if (started)
5008                                 func (stream, ", ");
5009                               started = 1;
5010                               func (stream, "%s", arm_regnames[reg]);
5011                             }
5012                         func (stream, "}");
5013                         if (! started)
5014                           is_unpredictable = TRUE;
5015                       }
5016                       break;
5017
5018                     case 'q':
5019                       arm_decode_shift (given, func, stream, FALSE);
5020                       break;
5021
5022                     case 'o':
5023                       if ((given & 0x02000000) != 0)
5024                         {
5025                           unsigned int rotate = (given & 0xf00) >> 7;
5026                           unsigned int immed = (given & 0xff);
5027                           unsigned int a, i;
5028
5029                           a = (((immed << (32 - rotate))
5030                                 | (immed >> rotate)) & 0xffffffff);
5031                           /* If there is another encoding with smaller rotate,
5032                              the rotate should be specified directly.  */
5033                           for (i = 0; i < 32; i += 2)
5034                             if ((a << i | a >> (32 - i)) <= 0xff)
5035                               break;
5036
5037                           if (i != rotate)
5038                             func (stream, "#%d, %d", immed, rotate);
5039                           else
5040                             func (stream, "#%d", a);
5041                           value_in_comment = a;
5042                         }
5043                       else
5044                         arm_decode_shift (given, func, stream, TRUE);
5045                       break;
5046
5047                     case 'p':
5048                       if ((given & 0x0000f000) == 0x0000f000)
5049                         {
5050                           arm_feature_set arm_ext_v6 =
5051                             ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
5052
5053                           /* The p-variants of tst/cmp/cmn/teq are the pre-V6
5054                              mechanism for setting PSR flag bits.  They are
5055                              obsolete in V6 onwards.  */
5056                           if (! ARM_CPU_HAS_FEATURE (private_data->features, \
5057                                                      arm_ext_v6))
5058                             func (stream, "p");
5059                           else
5060                             is_unpredictable = TRUE;
5061                         }
5062                       break;
5063
5064                     case 't':
5065                       if ((given & 0x01200000) == 0x00200000)
5066                         func (stream, "t");
5067                       break;
5068
5069                     case 'A':
5070                       {
5071                         int offset = given & 0xff;
5072
5073                         value_in_comment = offset * 4;
5074                         if (NEGATIVE_BIT_SET)
5075                           value_in_comment = - value_in_comment;
5076
5077                         func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
5078
5079                         if (PRE_BIT_SET)
5080                           {
5081                             if (offset)
5082                               func (stream, ", #%d]%s",
5083                                     (int) value_in_comment,
5084                                     WRITEBACK_BIT_SET ? "!" : "");
5085                             else
5086                               func (stream, "]");
5087                           }
5088                         else
5089                           {
5090                             func (stream, "]");
5091
5092                             if (WRITEBACK_BIT_SET)
5093                               {
5094                                 if (offset)
5095                                   func (stream, ", #%d", (int) value_in_comment);
5096                               }
5097                             else
5098                               {
5099                                 func (stream, ", {%d}", (int) offset);
5100                                 value_in_comment = offset;
5101                               }
5102                           }
5103                       }
5104                       break;
5105
5106                     case 'B':
5107                       /* Print ARM V5 BLX(1) address: pc+25 bits.  */
5108                       {
5109                         bfd_vma address;
5110                         bfd_vma offset = 0;
5111
5112                         if (! NEGATIVE_BIT_SET)
5113                           /* Is signed, hi bits should be ones.  */
5114                           offset = (-1) ^ 0x00ffffff;
5115
5116                         /* Offset is (SignExtend(offset field)<<2).  */
5117                         offset += given & 0x00ffffff;
5118                         offset <<= 2;
5119                         address = offset + pc + 8;
5120
5121                         if (given & 0x01000000)
5122                           /* H bit allows addressing to 2-byte boundaries.  */
5123                           address += 2;
5124
5125                         info->print_address_func (address, info);
5126                       }
5127                       break;
5128
5129                     case 'C':
5130                       if ((given & 0x02000200) == 0x200)
5131                         {
5132                           const char * name;
5133                           unsigned sysm = (given & 0x004f0000) >> 16;
5134
5135                           sysm |= (given & 0x300) >> 4;
5136                           name = banked_regname (sysm);
5137
5138                           if (name != NULL)
5139                             func (stream, "%s", name);
5140                           else
5141                             func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
5142                         }
5143                       else
5144                         {
5145                           func (stream, "%cPSR_",
5146                                 (given & 0x00400000) ? 'S' : 'C');
5147                           if (given & 0x80000)
5148                             func (stream, "f");
5149                           if (given & 0x40000)
5150                             func (stream, "s");
5151                           if (given & 0x20000)
5152                             func (stream, "x");
5153                           if (given & 0x10000)
5154                             func (stream, "c");
5155                         }
5156                       break;
5157
5158                     case 'U':
5159                       if ((given & 0xf0) == 0x60)
5160                         {
5161                           switch (given & 0xf)
5162                             {
5163                             case 0xf: func (stream, "sy"); break;
5164                             default:
5165                               func (stream, "#%d", (int) given & 0xf);
5166                               break;
5167                             }
5168                         }
5169                       else
5170                         {
5171                           const char * opt = data_barrier_option (given & 0xf);
5172                           if (opt != NULL)
5173                             func (stream, "%s", opt);
5174                           else
5175                               func (stream, "#%d", (int) given & 0xf);
5176                         }
5177                       break;
5178
5179                     case '0': case '1': case '2': case '3': case '4':
5180                     case '5': case '6': case '7': case '8': case '9':
5181                       {
5182                         int width;
5183                         unsigned long value;
5184
5185                         c = arm_decode_bitfield (c, given, &value, &width);
5186
5187                         switch (*c)
5188                           {
5189                           case 'R':
5190                             if (value == 15)
5191                               is_unpredictable = TRUE;
5192                             /* Fall through.  */
5193                           case 'r':
5194                           case 'T':
5195                             /* We want register + 1 when decoding T.  */
5196                             if (*c == 'T')
5197                               ++value;
5198
5199                             if (c[1] == 'u')
5200                               {
5201                                 /* Eat the 'u' character.  */
5202                                 ++ c;
5203
5204                                 if (u_reg == value)
5205                                   is_unpredictable = TRUE;
5206                                 u_reg = value;
5207                               }
5208                             if (c[1] == 'U')
5209                               {
5210                                 /* Eat the 'U' character.  */
5211                                 ++ c;
5212
5213                                 if (U_reg == value)
5214                                   is_unpredictable = TRUE;
5215                                 U_reg = value;
5216                               }
5217                             func (stream, "%s", arm_regnames[value]);
5218                             break;
5219                           case 'd':
5220                             func (stream, "%ld", value);
5221                             value_in_comment = value;
5222                             break;
5223                           case 'b':
5224                             func (stream, "%ld", value * 8);
5225                             value_in_comment = value * 8;
5226                             break;
5227                           case 'W':
5228                             func (stream, "%ld", value + 1);
5229                             value_in_comment = value + 1;
5230                             break;
5231                           case 'x':
5232                             func (stream, "0x%08lx", value);
5233
5234                             /* Some SWI instructions have special
5235                                meanings.  */
5236                             if ((given & 0x0fffffff) == 0x0FF00000)
5237                               func (stream, "\t; IMB");
5238                             else if ((given & 0x0fffffff) == 0x0FF00001)
5239                               func (stream, "\t; IMBRange");
5240                             break;
5241                           case 'X':
5242                             func (stream, "%01lx", value & 0xf);
5243                             value_in_comment = value;
5244                             break;
5245                           case '`':
5246                             c++;
5247                             if (value == 0)
5248                               func (stream, "%c", *c);
5249                             break;
5250                           case '\'':
5251                             c++;
5252                             if (value == ((1ul << width) - 1))
5253                               func (stream, "%c", *c);
5254                             break;
5255                           case '?':
5256                             func (stream, "%c", c[(1 << width) - (int) value]);
5257                             c += 1 << width;
5258                             break;
5259                           default:
5260                             abort ();
5261                           }
5262                       }
5263                       break;
5264
5265                     case 'e':
5266                       {
5267                         int imm;
5268
5269                         imm = (given & 0xf) | ((given & 0xfff00) >> 4);
5270                         func (stream, "%d", imm);
5271                         value_in_comment = imm;
5272                       }
5273                       break;
5274
5275                     case 'E':
5276                       /* LSB and WIDTH fields of BFI or BFC.  The machine-
5277                          language instruction encodes LSB and MSB.  */
5278                       {
5279                         long msb = (given & 0x001f0000) >> 16;
5280                         long lsb = (given & 0x00000f80) >> 7;
5281                         long w = msb - lsb + 1;
5282
5283                         if (w > 0)
5284                           func (stream, "#%lu, #%lu", lsb, w);
5285                         else
5286                           func (stream, "(invalid: %lu:%lu)", lsb, msb);
5287                       }
5288                       break;
5289
5290                     case 'R':
5291                       /* Get the PSR/banked register name.  */
5292                       {
5293                         const char * name;
5294                         unsigned sysm = (given & 0x004f0000) >> 16;
5295
5296                         sysm |= (given & 0x300) >> 4;
5297                         name = banked_regname (sysm);
5298
5299                         if (name != NULL)
5300                           func (stream, "%s", name);
5301                         else
5302                           func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
5303                       }
5304                       break;
5305
5306                     case 'V':
5307                       /* 16-bit unsigned immediate from a MOVT or MOVW
5308                          instruction, encoded in bits 0:11 and 15:19.  */
5309                       {
5310                         long hi = (given & 0x000f0000) >> 4;
5311                         long lo = (given & 0x00000fff);
5312                         long imm16 = hi | lo;
5313
5314                         func (stream, "#%lu", imm16);
5315                         value_in_comment = imm16;
5316                       }
5317                       break;
5318
5319                     default:
5320                       abort ();
5321                     }
5322                 }
5323               else
5324                 func (stream, "%c", *c);
5325             }
5326
5327           if (value_in_comment > 32 || value_in_comment < -16)
5328             func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
5329
5330           if (is_unpredictable)
5331             func (stream, UNPREDICTABLE_INSTRUCTION);
5332
5333           return;
5334         }
5335     }
5336   func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
5337   return;
5338 }
5339
5340 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM.  */
5341
5342 static void
5343 print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
5344 {
5345   const struct opcode16 *insn;
5346   void *stream = info->stream;
5347   fprintf_ftype func = info->fprintf_func;
5348
5349   for (insn = thumb_opcodes; insn->assembler; insn++)
5350     if ((given & insn->mask) == insn->value)
5351       {
5352         signed long value_in_comment = 0;
5353         const char *c = insn->assembler;
5354
5355         for (; *c; c++)
5356           {
5357             int domaskpc = 0;
5358             int domasklr = 0;
5359
5360             if (*c != '%')
5361               {
5362                 func (stream, "%c", *c);
5363                 continue;
5364               }
5365
5366             switch (*++c)
5367               {
5368               case '%':
5369                 func (stream, "%%");
5370                 break;
5371
5372               case 'c':
5373                 if (ifthen_state)
5374                   func (stream, "%s", arm_conditional[IFTHEN_COND]);
5375                 break;
5376
5377               case 'C':
5378                 if (ifthen_state)
5379                   func (stream, "%s", arm_conditional[IFTHEN_COND]);
5380                 else
5381                   func (stream, "s");
5382                 break;
5383
5384               case 'I':
5385                 {
5386                   unsigned int tmp;
5387
5388                   ifthen_next_state = given & 0xff;
5389                   for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
5390                     func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
5391                   func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
5392                 }
5393                 break;
5394
5395               case 'x':
5396                 if (ifthen_next_state)
5397                   func (stream, "\t; unpredictable branch in IT block\n");
5398                 break;
5399
5400               case 'X':
5401                 if (ifthen_state)
5402                   func (stream, "\t; unpredictable <IT:%s>",
5403                         arm_conditional[IFTHEN_COND]);
5404                 break;
5405
5406               case 'S':
5407                 {
5408                   long reg;
5409
5410                   reg = (given >> 3) & 0x7;
5411                   if (given & (1 << 6))
5412                     reg += 8;
5413
5414                   func (stream, "%s", arm_regnames[reg]);
5415                 }
5416                 break;
5417
5418               case 'D':
5419                 {
5420                   long reg;
5421
5422                   reg = given & 0x7;
5423                   if (given & (1 << 7))
5424                     reg += 8;
5425
5426                   func (stream, "%s", arm_regnames[reg]);
5427                 }
5428                 break;
5429
5430               case 'N':
5431                 if (given & (1 << 8))
5432                   domasklr = 1;
5433                 /* Fall through.  */
5434               case 'O':
5435                 if (*c == 'O' && (given & (1 << 8)))
5436                   domaskpc = 1;
5437                 /* Fall through.  */
5438               case 'M':
5439                 {
5440                   int started = 0;
5441                   int reg;
5442
5443                   func (stream, "{");
5444
5445                   /* It would be nice if we could spot
5446                      ranges, and generate the rS-rE format: */
5447                   for (reg = 0; (reg < 8); reg++)
5448                     if ((given & (1 << reg)) != 0)
5449                       {
5450                         if (started)
5451                           func (stream, ", ");
5452                         started = 1;
5453                         func (stream, "%s", arm_regnames[reg]);
5454                       }
5455
5456                   if (domasklr)
5457                     {
5458                       if (started)
5459                         func (stream, ", ");
5460                       started = 1;
5461                       func (stream, "%s", arm_regnames[14] /* "lr" */);
5462                     }
5463
5464                   if (domaskpc)
5465                     {
5466                       if (started)
5467                         func (stream, ", ");
5468                       func (stream, "%s", arm_regnames[15] /* "pc" */);
5469                     }
5470
5471                   func (stream, "}");
5472                 }
5473                 break;
5474
5475               case 'W':
5476                 /* Print writeback indicator for a LDMIA.  We are doing a
5477                    writeback if the base register is not in the register
5478                    mask.  */
5479                 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
5480                   func (stream, "!");
5481                 break;
5482
5483               case 'b':
5484                 /* Print ARM V6T2 CZB address: pc+4+6 bits.  */
5485                 {
5486                   bfd_vma address = (pc + 4
5487                                      + ((given & 0x00f8) >> 2)
5488                                      + ((given & 0x0200) >> 3));
5489                   info->print_address_func (address, info);
5490                 }
5491                 break;
5492
5493               case 's':
5494                 /* Right shift immediate -- bits 6..10; 1-31 print
5495                    as themselves, 0 prints as 32.  */
5496                 {
5497                   long imm = (given & 0x07c0) >> 6;
5498                   if (imm == 0)
5499                     imm = 32;
5500                   func (stream, "#%ld", imm);
5501                 }
5502                 break;
5503
5504               case '0': case '1': case '2': case '3': case '4':
5505               case '5': case '6': case '7': case '8': case '9':
5506                 {
5507                   int bitstart = *c++ - '0';
5508                   int bitend = 0;
5509
5510                   while (*c >= '0' && *c <= '9')
5511                     bitstart = (bitstart * 10) + *c++ - '0';
5512
5513                   switch (*c)
5514                     {
5515                     case '-':
5516                       {
5517                         bfd_vma reg;
5518
5519                         c++;
5520                         while (*c >= '0' && *c <= '9')
5521                           bitend = (bitend * 10) + *c++ - '0';
5522                         if (!bitend)
5523                           abort ();
5524                         reg = given >> bitstart;
5525                         reg &= (2 << (bitend - bitstart)) - 1;
5526
5527                         switch (*c)
5528                           {
5529                           case 'r':
5530                             func (stream, "%s", arm_regnames[reg]);
5531                             break;
5532
5533                           case 'd':
5534                             func (stream, "%ld", (long) reg);
5535                             value_in_comment = reg;
5536                             break;
5537
5538                           case 'H':
5539                             func (stream, "%ld", (long) (reg << 1));
5540                             value_in_comment = reg << 1;
5541                             break;
5542
5543                           case 'W':
5544                             func (stream, "%ld", (long) (reg << 2));
5545                             value_in_comment = reg << 2;
5546                             break;
5547
5548                           case 'a':
5549                             /* PC-relative address -- the bottom two
5550                                bits of the address are dropped
5551                                before the calculation.  */
5552                             info->print_address_func
5553                               (((pc + 4) & ~3) + (reg << 2), info);
5554                             value_in_comment = 0;
5555                             break;
5556
5557                           case 'x':
5558                             func (stream, "0x%04lx", (long) reg);
5559                             break;
5560
5561                           case 'B':
5562                             reg = ((reg ^ (1 << bitend)) - (1 << bitend));
5563                             info->print_address_func (reg * 2 + pc + 4, info);
5564                             value_in_comment = 0;
5565                             break;
5566
5567                           case 'c':
5568                             func (stream, "%s", arm_conditional [reg]);
5569                             break;
5570
5571                           default:
5572                             abort ();
5573                           }
5574                       }
5575                       break;
5576
5577                     case '\'':
5578                       c++;
5579                       if ((given & (1 << bitstart)) != 0)
5580                         func (stream, "%c", *c);
5581                       break;
5582
5583                     case '?':
5584                       ++c;
5585                       if ((given & (1 << bitstart)) != 0)
5586                         func (stream, "%c", *c++);
5587                       else
5588                         func (stream, "%c", *++c);
5589                       break;
5590
5591                     default:
5592                       abort ();
5593                     }
5594                 }
5595                 break;
5596
5597               default:
5598                 abort ();
5599               }
5600           }
5601
5602         if (value_in_comment > 32 || value_in_comment < -16)
5603           func (stream, "\t; 0x%lx", value_in_comment);
5604         return;
5605       }
5606
5607   /* No match.  */
5608   func (stream, UNKNOWN_INSTRUCTION_16BIT, (unsigned)given);
5609   return;
5610 }
5611
5612 /* Return the name of an V7M special register.  */
5613
5614 static const char *
5615 psr_name (int regno)
5616 {
5617   switch (regno)
5618     {
5619     case 0x0: return "APSR";
5620     case 0x1: return "IAPSR";
5621     case 0x2: return "EAPSR";
5622     case 0x3: return "PSR";
5623     case 0x5: return "IPSR";
5624     case 0x6: return "EPSR";
5625     case 0x7: return "IEPSR";
5626     case 0x8: return "MSP";
5627     case 0x9: return "PSP";
5628     case 0xa: return "MSPLIM";
5629     case 0xb: return "PSPLIM";
5630     case 0x10: return "PRIMASK";
5631     case 0x11: return "BASEPRI";
5632     case 0x12: return "BASEPRI_MAX";
5633     case 0x13: return "FAULTMASK";
5634     case 0x14: return "CONTROL";
5635     case 0x88: return "MSP_NS";
5636     case 0x89: return "PSP_NS";
5637     case 0x8a: return "MSPLIM_NS";
5638     case 0x8b: return "PSPLIM_NS";
5639     case 0x90: return "PRIMASK_NS";
5640     case 0x91: return "BASEPRI_NS";
5641     case 0x93: return "FAULTMASK_NS";
5642     case 0x94: return "CONTROL_NS";
5643     case 0x98: return "SP_NS";
5644     default: return "<unknown>";
5645     }
5646 }
5647
5648 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM.  */
5649
5650 static void
5651 print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
5652 {
5653   const struct opcode32 *insn;
5654   void *stream = info->stream;
5655   fprintf_ftype func = info->fprintf_func;
5656
5657   if (print_insn_coprocessor (pc, info, given, TRUE))
5658     return;
5659
5660   if (print_insn_neon (info, given, TRUE))
5661     return;
5662
5663   for (insn = thumb32_opcodes; insn->assembler; insn++)
5664     if ((given & insn->mask) == insn->value)
5665       {
5666         bfd_boolean is_clrm = FALSE;
5667         bfd_boolean is_unpredictable = FALSE;
5668         signed long value_in_comment = 0;
5669         const char *c = insn->assembler;
5670
5671         for (; *c; c++)
5672           {
5673             if (*c != '%')
5674               {
5675                 func (stream, "%c", *c);
5676                 continue;
5677               }
5678
5679             switch (*++c)
5680               {
5681               case '%':
5682                 func (stream, "%%");
5683                 break;
5684
5685               case 'c':
5686                 if (ifthen_state)
5687                   func (stream, "%s", arm_conditional[IFTHEN_COND]);
5688                 break;
5689
5690               case 'x':
5691                 if (ifthen_next_state)
5692                   func (stream, "\t; unpredictable branch in IT block\n");
5693                 break;
5694
5695               case 'X':
5696                 if (ifthen_state)
5697                   func (stream, "\t; unpredictable <IT:%s>",
5698                         arm_conditional[IFTHEN_COND]);
5699                 break;
5700
5701               case 'I':
5702                 {
5703                   unsigned int imm12 = 0;
5704
5705                   imm12 |= (given & 0x000000ffu);
5706                   imm12 |= (given & 0x00007000u) >> 4;
5707                   imm12 |= (given & 0x04000000u) >> 15;
5708                   func (stream, "#%u", imm12);
5709                   value_in_comment = imm12;
5710                 }
5711                 break;
5712
5713               case 'M':
5714                 {
5715                   unsigned int bits = 0, imm, imm8, mod;
5716
5717                   bits |= (given & 0x000000ffu);
5718                   bits |= (given & 0x00007000u) >> 4;
5719                   bits |= (given & 0x04000000u) >> 15;
5720                   imm8 = (bits & 0x0ff);
5721                   mod = (bits & 0xf00) >> 8;
5722                   switch (mod)
5723                     {
5724                     case 0: imm = imm8; break;
5725                     case 1: imm = ((imm8 << 16) | imm8); break;
5726                     case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
5727                     case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
5728                     default:
5729                       mod  = (bits & 0xf80) >> 7;
5730                       imm8 = (bits & 0x07f) | 0x80;
5731                       imm  = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
5732                     }
5733                   func (stream, "#%u", imm);
5734                   value_in_comment = imm;
5735                 }
5736                 break;
5737
5738               case 'J':
5739                 {
5740                   unsigned int imm = 0;
5741
5742                   imm |= (given & 0x000000ffu);
5743                   imm |= (given & 0x00007000u) >> 4;
5744                   imm |= (given & 0x04000000u) >> 15;
5745                   imm |= (given & 0x000f0000u) >> 4;
5746                   func (stream, "#%u", imm);
5747                   value_in_comment = imm;
5748                 }
5749                 break;
5750
5751               case 'K':
5752                 {
5753                   unsigned int imm = 0;
5754
5755                   imm |= (given & 0x000f0000u) >> 16;
5756                   imm |= (given & 0x00000ff0u) >> 0;
5757                   imm |= (given & 0x0000000fu) << 12;
5758                   func (stream, "#%u", imm);
5759                   value_in_comment = imm;
5760                 }
5761                 break;
5762
5763               case 'H':
5764                 {
5765                   unsigned int imm = 0;
5766
5767                   imm |= (given & 0x000f0000u) >> 4;
5768                   imm |= (given & 0x00000fffu) >> 0;
5769                   func (stream, "#%u", imm);
5770                   value_in_comment = imm;
5771                 }
5772                 break;
5773
5774               case 'V':
5775                 {
5776                   unsigned int imm = 0;
5777
5778                   imm |= (given & 0x00000fffu);
5779                   imm |= (given & 0x000f0000u) >> 4;
5780                   func (stream, "#%u", imm);
5781                   value_in_comment = imm;
5782                 }
5783                 break;
5784
5785               case 'S':
5786                 {
5787                   unsigned int reg = (given & 0x0000000fu);
5788                   unsigned int stp = (given & 0x00000030u) >> 4;
5789                   unsigned int imm = 0;
5790                   imm |= (given & 0x000000c0u) >> 6;
5791                   imm |= (given & 0x00007000u) >> 10;
5792
5793                   func (stream, "%s", arm_regnames[reg]);
5794                   switch (stp)
5795                     {
5796                     case 0:
5797                       if (imm > 0)
5798                         func (stream, ", lsl #%u", imm);
5799                       break;
5800
5801                     case 1:
5802                       if (imm == 0)
5803                         imm = 32;
5804                       func (stream, ", lsr #%u", imm);
5805                       break;
5806
5807                     case 2:
5808                       if (imm == 0)
5809                         imm = 32;
5810                       func (stream, ", asr #%u", imm);
5811                       break;
5812
5813                     case 3:
5814                       if (imm == 0)
5815                         func (stream, ", rrx");
5816                       else
5817                         func (stream, ", ror #%u", imm);
5818                     }
5819                 }
5820                 break;
5821
5822               case 'a':
5823                 {
5824                   unsigned int Rn  = (given & 0x000f0000) >> 16;
5825                   unsigned int U   = ! NEGATIVE_BIT_SET;
5826                   unsigned int op  = (given & 0x00000f00) >> 8;
5827                   unsigned int i12 = (given & 0x00000fff);
5828                   unsigned int i8  = (given & 0x000000ff);
5829                   bfd_boolean writeback = FALSE, postind = FALSE;
5830                   bfd_vma offset = 0;
5831
5832                   func (stream, "[%s", arm_regnames[Rn]);
5833                   if (U) /* 12-bit positive immediate offset.  */
5834                     {
5835                       offset = i12;
5836                       if (Rn != 15)
5837                         value_in_comment = offset;
5838                     }
5839                   else if (Rn == 15) /* 12-bit negative immediate offset.  */
5840                     offset = - (int) i12;
5841                   else if (op == 0x0) /* Shifted register offset.  */
5842                     {
5843                       unsigned int Rm = (i8 & 0x0f);
5844                       unsigned int sh = (i8 & 0x30) >> 4;
5845
5846                       func (stream, ", %s", arm_regnames[Rm]);
5847                       if (sh)
5848                         func (stream, ", lsl #%u", sh);
5849                       func (stream, "]");
5850                       break;
5851                     }
5852                   else switch (op)
5853                     {
5854                     case 0xE:  /* 8-bit positive immediate offset.  */
5855                       offset = i8;
5856                       break;
5857
5858                     case 0xC:  /* 8-bit negative immediate offset.  */
5859                       offset = -i8;
5860                       break;
5861
5862                     case 0xF:  /* 8-bit + preindex with wb.  */
5863                       offset = i8;
5864                       writeback = TRUE;
5865                       break;
5866
5867                     case 0xD:  /* 8-bit - preindex with wb.  */
5868                       offset = -i8;
5869                       writeback = TRUE;
5870                       break;
5871
5872                     case 0xB:  /* 8-bit + postindex.  */
5873                       offset = i8;
5874                       postind = TRUE;
5875                       break;
5876
5877                     case 0x9:  /* 8-bit - postindex.  */
5878                       offset = -i8;
5879                       postind = TRUE;
5880                       break;
5881
5882                     default:
5883                       func (stream, ", <undefined>]");
5884                       goto skip;
5885                     }
5886
5887                   if (postind)
5888                     func (stream, "], #%d", (int) offset);
5889                   else
5890                     {
5891                       if (offset)
5892                         func (stream, ", #%d", (int) offset);
5893                       func (stream, writeback ? "]!" : "]");
5894                     }
5895
5896                   if (Rn == 15)
5897                     {
5898                       func (stream, "\t; ");
5899                       info->print_address_func (((pc + 4) & ~3) + offset, info);
5900                     }
5901                 }
5902               skip:
5903                 break;
5904
5905               case 'A':
5906                 {
5907                   unsigned int U   = ! NEGATIVE_BIT_SET;
5908                   unsigned int W   = WRITEBACK_BIT_SET;
5909                   unsigned int Rn  = (given & 0x000f0000) >> 16;
5910                   unsigned int off = (given & 0x000000ff);
5911
5912                   func (stream, "[%s", arm_regnames[Rn]);
5913
5914                   if (PRE_BIT_SET)
5915                     {
5916                       if (off || !U)
5917                         {
5918                           func (stream, ", #%c%u", U ? '+' : '-', off * 4);
5919                           value_in_comment = off * 4 * (U ? 1 : -1);
5920                         }
5921                       func (stream, "]");
5922                       if (W)
5923                         func (stream, "!");
5924                     }
5925                   else
5926                     {
5927                       func (stream, "], ");
5928                       if (W)
5929                         {
5930                           func (stream, "#%c%u", U ? '+' : '-', off * 4);
5931                           value_in_comment = off * 4 * (U ? 1 : -1);
5932                         }
5933                       else
5934                         {
5935                           func (stream, "{%u}", off);
5936                           value_in_comment = off;
5937                         }
5938                     }
5939                 }
5940                 break;
5941
5942               case 'w':
5943                 {
5944                   unsigned int Sbit = (given & 0x01000000) >> 24;
5945                   unsigned int type = (given & 0x00600000) >> 21;
5946
5947                   switch (type)
5948                     {
5949                     case 0: func (stream, Sbit ? "sb" : "b"); break;
5950                     case 1: func (stream, Sbit ? "sh" : "h"); break;
5951                     case 2:
5952                       if (Sbit)
5953                         func (stream, "??");
5954                       break;
5955                     case 3:
5956                       func (stream, "??");
5957                       break;
5958                     }
5959                 }
5960                 break;
5961
5962               case 'n':
5963                 is_clrm = TRUE;
5964                 /* Fall through.  */
5965               case 'm':
5966                 {
5967                   int started = 0;
5968                   int reg;
5969
5970                   func (stream, "{");
5971                   for (reg = 0; reg < 16; reg++)
5972                     if ((given & (1 << reg)) != 0)
5973                       {
5974                         if (started)
5975                           func (stream, ", ");
5976                         started = 1;
5977                         if (is_clrm && reg == 13)
5978                           func (stream, "(invalid: %s)", arm_regnames[reg]);
5979                         else if (is_clrm && reg == 15)
5980                           func (stream, "%s", "APSR");
5981                         else
5982                           func (stream, "%s", arm_regnames[reg]);
5983                       }
5984                   func (stream, "}");
5985                 }
5986                 break;
5987
5988               case 'E':
5989                 {
5990                   unsigned int msb = (given & 0x0000001f);
5991                   unsigned int lsb = 0;
5992
5993                   lsb |= (given & 0x000000c0u) >> 6;
5994                   lsb |= (given & 0x00007000u) >> 10;
5995                   func (stream, "#%u, #%u", lsb, msb - lsb + 1);
5996                 }
5997                 break;
5998
5999               case 'F':
6000                 {
6001                   unsigned int width = (given & 0x0000001f) + 1;
6002                   unsigned int lsb = 0;
6003
6004                   lsb |= (given & 0x000000c0u) >> 6;
6005                   lsb |= (given & 0x00007000u) >> 10;
6006                   func (stream, "#%u, #%u", lsb, width);
6007                 }
6008                 break;
6009
6010               case 'G':
6011                 {
6012                   unsigned int boff = (((given & 0x07800000) >> 23) << 1);
6013                   func (stream, "%x", boff);
6014                 }
6015                 break;
6016
6017               case 'W':
6018                 {
6019                   unsigned int immA = (given & 0x001f0000u) >> 16;
6020                   unsigned int immB = (given & 0x000007feu) >> 1;
6021                   unsigned int immC = (given & 0x00000800u) >> 11;
6022                   bfd_vma offset = 0;
6023
6024                   offset |= immA << 12;
6025                   offset |= immB << 2;
6026                   offset |= immC << 1;
6027                   /* Sign extend.  */
6028                   offset = (offset & 0x10000) ? offset - (1 << 17) : offset;
6029
6030                   info->print_address_func (pc + 4 + offset, info);
6031                 }
6032                 break;
6033
6034               case 'Y':
6035                 {
6036                   unsigned int immA = (given & 0x007f0000u) >> 16;
6037                   unsigned int immB = (given & 0x000007feu) >> 1;
6038                   unsigned int immC = (given & 0x00000800u) >> 11;
6039                   bfd_vma offset = 0;
6040
6041                   offset |= immA << 12;
6042                   offset |= immB << 2;
6043                   offset |= immC << 1;
6044                   /* Sign extend.  */
6045                   offset = (offset & 0x40000) ? offset - (1 << 19) : offset;
6046
6047                   info->print_address_func (pc + 4 + offset, info);
6048                 }
6049                 break;
6050
6051               case 'Z':
6052                 {
6053                   unsigned int immA = (given & 0x00010000u) >> 16;
6054                   unsigned int immB = (given & 0x000007feu) >> 1;
6055                   unsigned int immC = (given & 0x00000800u) >> 11;
6056                   bfd_vma offset = 0;
6057
6058                   offset |= immA << 12;
6059                   offset |= immB << 2;
6060                   offset |= immC << 1;
6061                   /* Sign extend.  */
6062                   offset = (offset & 0x1000) ? offset - (1 << 13) : offset;
6063
6064                   info->print_address_func (pc + 4 + offset, info);
6065
6066                   unsigned int T    = (given & 0x00020000u) >> 17;
6067                   unsigned int endoffset = (((given & 0x07800000) >> 23) << 1);
6068                   unsigned int boffset   = (T == 1) ? 4 : 2;
6069                   func (stream, ", ");
6070                   func (stream, "%x", endoffset + boffset);
6071                 }
6072                 break;
6073
6074               case 'Q':
6075                 {
6076                   unsigned int immh = (given & 0x000007feu) >> 1;
6077                   unsigned int imml = (given & 0x00000800u) >> 11;
6078                   bfd_vma imm32 = 0;
6079
6080                   imm32 |= immh << 2;
6081                   imm32 |= imml << 1;
6082
6083                   info->print_address_func (pc + 4 + imm32, info);
6084                 }
6085                 break;
6086
6087               case 'P':
6088                 {
6089                   unsigned int immh = (given & 0x000007feu) >> 1;
6090                   unsigned int imml = (given & 0x00000800u) >> 11;
6091                   bfd_vma imm32 = 0;
6092
6093                   imm32 |= immh << 2;
6094                   imm32 |= imml << 1;
6095
6096                   info->print_address_func (pc + 4 - imm32, info);
6097                 }
6098                 break;
6099
6100               case 'b':
6101                 {
6102                   unsigned int S = (given & 0x04000000u) >> 26;
6103                   unsigned int J1 = (given & 0x00002000u) >> 13;
6104                   unsigned int J2 = (given & 0x00000800u) >> 11;
6105                   bfd_vma offset = 0;
6106
6107                   offset |= !S << 20;
6108                   offset |= J2 << 19;
6109                   offset |= J1 << 18;
6110                   offset |= (given & 0x003f0000) >> 4;
6111                   offset |= (given & 0x000007ff) << 1;
6112                   offset -= (1 << 20);
6113
6114                   info->print_address_func (pc + 4 + offset, info);
6115                 }
6116                 break;
6117
6118               case 'B':
6119                 {
6120                   unsigned int S = (given & 0x04000000u) >> 26;
6121                   unsigned int I1 = (given & 0x00002000u) >> 13;
6122                   unsigned int I2 = (given & 0x00000800u) >> 11;
6123                   bfd_vma offset = 0;
6124
6125                   offset |= !S << 24;
6126                   offset |= !(I1 ^ S) << 23;
6127                   offset |= !(I2 ^ S) << 22;
6128                   offset |= (given & 0x03ff0000u) >> 4;
6129                   offset |= (given & 0x000007ffu) << 1;
6130                   offset -= (1 << 24);
6131                   offset += pc + 4;
6132
6133                   /* BLX target addresses are always word aligned.  */
6134                   if ((given & 0x00001000u) == 0)
6135                       offset &= ~2u;
6136
6137                   info->print_address_func (offset, info);
6138                 }
6139                 break;
6140
6141               case 's':
6142                 {
6143                   unsigned int shift = 0;
6144
6145                   shift |= (given & 0x000000c0u) >> 6;
6146                   shift |= (given & 0x00007000u) >> 10;
6147                   if (WRITEBACK_BIT_SET)
6148                     func (stream, ", asr #%u", shift);
6149                   else if (shift)
6150                     func (stream, ", lsl #%u", shift);
6151                   /* else print nothing - lsl #0 */
6152                 }
6153                 break;
6154
6155               case 'R':
6156                 {
6157                   unsigned int rot = (given & 0x00000030) >> 4;
6158
6159                   if (rot)
6160                     func (stream, ", ror #%u", rot * 8);
6161                 }
6162                 break;
6163
6164               case 'U':
6165                 if ((given & 0xf0) == 0x60)
6166                   {
6167                     switch (given & 0xf)
6168                       {
6169                         case 0xf: func (stream, "sy"); break;
6170                         default:
6171                           func (stream, "#%d", (int) given & 0xf);
6172                               break;
6173                       }
6174                   }
6175                 else
6176                   {
6177                     const char * opt = data_barrier_option (given & 0xf);
6178                     if (opt != NULL)
6179                       func (stream, "%s", opt);
6180                     else
6181                       func (stream, "#%d", (int) given & 0xf);
6182                    }
6183                 break;
6184
6185               case 'C':
6186                 if ((given & 0xff) == 0)
6187                   {
6188                     func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
6189                     if (given & 0x800)
6190                       func (stream, "f");
6191                     if (given & 0x400)
6192                       func (stream, "s");
6193                     if (given & 0x200)
6194                       func (stream, "x");
6195                     if (given & 0x100)
6196                       func (stream, "c");
6197                   }
6198                 else if ((given & 0x20) == 0x20)
6199                   {
6200                     char const* name;
6201                     unsigned sysm = (given & 0xf00) >> 8;
6202
6203                     sysm |= (given & 0x30);
6204                     sysm |= (given & 0x00100000) >> 14;
6205                     name = banked_regname (sysm);
6206
6207                     if (name != NULL)
6208                       func (stream, "%s", name);
6209                     else
6210                       func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
6211                   }
6212                 else
6213                   {
6214                     func (stream, "%s", psr_name (given & 0xff));
6215                   }
6216                 break;
6217
6218               case 'D':
6219                 if (((given & 0xff) == 0)
6220                     || ((given & 0x20) == 0x20))
6221                   {
6222                     char const* name;
6223                     unsigned sm = (given & 0xf0000) >> 16;
6224
6225                     sm |= (given & 0x30);
6226                     sm |= (given & 0x00100000) >> 14;
6227                     name = banked_regname (sm);
6228
6229                     if (name != NULL)
6230                       func (stream, "%s", name);
6231                     else
6232                       func (stream, "(UNDEF: %lu)", (unsigned long) sm);
6233                   }
6234                 else
6235                   func (stream, "%s", psr_name (given & 0xff));
6236                 break;
6237
6238               case '0': case '1': case '2': case '3': case '4':
6239               case '5': case '6': case '7': case '8': case '9':
6240                 {
6241                   int width;
6242                   unsigned long val;
6243
6244                   c = arm_decode_bitfield (c, given, &val, &width);
6245
6246                   switch (*c)
6247                     {
6248                     case 'd':
6249                       func (stream, "%lu", val);
6250                       value_in_comment = val;
6251                       break;
6252
6253                     case 'D':
6254                       func (stream, "%lu", val + 1);
6255                       value_in_comment = val + 1;
6256                       break;
6257
6258                     case 'W':
6259                       func (stream, "%lu", val * 4);
6260                       value_in_comment = val * 4;
6261                       break;
6262
6263                     case 'S':
6264                       if (val == 13)
6265                         is_unpredictable = TRUE;
6266                       /* Fall through.  */
6267                     case 'R':
6268                       if (val == 15)
6269                         is_unpredictable = TRUE;
6270                       /* Fall through.  */
6271                     case 'r':
6272                       func (stream, "%s", arm_regnames[val]);
6273                       break;
6274
6275                     case 'c':
6276                       func (stream, "%s", arm_conditional[val]);
6277                       break;
6278
6279                     case '\'':
6280                       c++;
6281                       if (val == ((1ul << width) - 1))
6282                         func (stream, "%c", *c);
6283                       break;
6284
6285                     case '`':
6286                       c++;
6287                       if (val == 0)
6288                         func (stream, "%c", *c);
6289                       break;
6290
6291                     case '?':
6292                       func (stream, "%c", c[(1 << width) - (int) val]);
6293                       c += 1 << width;
6294                       break;
6295
6296                     case 'x':
6297                       func (stream, "0x%lx", val & 0xffffffffUL);
6298                       break;
6299
6300                     default:
6301                       abort ();
6302                     }
6303                 }
6304                 break;
6305
6306               case 'L':
6307                 /* PR binutils/12534
6308                    If we have a PC relative offset in an LDRD or STRD
6309                    instructions then display the decoded address.  */
6310                 if (((given >> 16) & 0xf) == 0xf)
6311                   {
6312                     bfd_vma offset = (given & 0xff) * 4;
6313
6314                     if ((given & (1 << 23)) == 0)
6315                       offset = - offset;
6316                     func (stream, "\t; ");
6317                     info->print_address_func ((pc & ~3) + 4 + offset, info);
6318                   }
6319                 break;
6320
6321               default:
6322                 abort ();
6323               }
6324           }
6325
6326         if (value_in_comment > 32 || value_in_comment < -16)
6327           func (stream, "\t; 0x%lx", value_in_comment);
6328
6329         if (is_unpredictable)
6330           func (stream, UNPREDICTABLE_INSTRUCTION);
6331
6332         return;
6333       }
6334
6335   /* No match.  */
6336   func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
6337   return;
6338 }
6339
6340 /* Print data bytes on INFO->STREAM.  */
6341
6342 static void
6343 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
6344                  struct disassemble_info *info,
6345                  long given)
6346 {
6347   switch (info->bytes_per_chunk)
6348     {
6349     case 1:
6350       info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
6351       break;
6352     case 2:
6353       info->fprintf_func (info->stream, ".short\t0x%04lx", given);
6354       break;
6355     case 4:
6356       info->fprintf_func (info->stream, ".word\t0x%08lx", given);
6357       break;
6358     default:
6359       abort ();
6360     }
6361 }
6362
6363 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
6364    being displayed in symbol relative addresses.
6365
6366    Also disallow private symbol, with __tagsym$$ prefix,
6367    from ARM RVCT toolchain being displayed.  */
6368
6369 bfd_boolean
6370 arm_symbol_is_valid (asymbol * sym,
6371                      struct disassemble_info * info ATTRIBUTE_UNUSED)
6372 {
6373   const char * name;
6374
6375   if (sym == NULL)
6376     return FALSE;
6377
6378   name = bfd_asymbol_name (sym);
6379
6380   return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
6381 }
6382
6383 /* Parse the string of disassembler options.  */
6384
6385 static void
6386 parse_arm_disassembler_options (const char *options)
6387 {
6388   const char *opt;
6389
6390   FOR_EACH_DISASSEMBLER_OPTION (opt, options)
6391     {
6392       if (CONST_STRNEQ (opt, "reg-names-"))
6393         {
6394           unsigned int i;
6395           for (i = 0; i < NUM_ARM_OPTIONS; i++)
6396             if (disassembler_options_cmp (opt, regnames[i].name) == 0)
6397               {
6398                 regname_selected = i;
6399                 break;
6400               }
6401
6402           if (i >= NUM_ARM_OPTIONS)
6403             /* xgettext: c-format */
6404             opcodes_error_handler (_("unrecognised register name set: %s"),
6405                                    opt);
6406         }
6407       else if (CONST_STRNEQ (opt, "force-thumb"))
6408         force_thumb = 1;
6409       else if (CONST_STRNEQ (opt, "no-force-thumb"))
6410         force_thumb = 0;
6411       else
6412         /* xgettext: c-format */
6413         opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
6414     }
6415
6416   return;
6417 }
6418
6419 static bfd_boolean
6420 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
6421                          enum map_type *map_symbol);
6422
6423 /* Search back through the insn stream to determine if this instruction is
6424    conditionally executed.  */
6425
6426 static void
6427 find_ifthen_state (bfd_vma pc,
6428                    struct disassemble_info *info,
6429                    bfd_boolean little)
6430 {
6431   unsigned char b[2];
6432   unsigned int insn;
6433   int status;
6434   /* COUNT is twice the number of instructions seen.  It will be odd if we
6435      just crossed an instruction boundary.  */
6436   int count;
6437   int it_count;
6438   unsigned int seen_it;
6439   bfd_vma addr;
6440
6441   ifthen_address = pc;
6442   ifthen_state = 0;
6443
6444   addr = pc;
6445   count = 1;
6446   it_count = 0;
6447   seen_it = 0;
6448   /* Scan backwards looking for IT instructions, keeping track of where
6449      instruction boundaries are.  We don't know if something is actually an
6450      IT instruction until we find a definite instruction boundary.  */
6451   for (;;)
6452     {
6453       if (addr == 0 || info->symbol_at_address_func (addr, info))
6454         {
6455           /* A symbol must be on an instruction boundary, and will not
6456              be within an IT block.  */
6457           if (seen_it && (count & 1))
6458             break;
6459
6460           return;
6461         }
6462       addr -= 2;
6463       status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
6464       if (status)
6465         return;
6466
6467       if (little)
6468         insn = (b[0]) | (b[1] << 8);
6469       else
6470         insn = (b[1]) | (b[0] << 8);
6471       if (seen_it)
6472         {
6473           if ((insn & 0xf800) < 0xe800)
6474             {
6475               /* Addr + 2 is an instruction boundary.  See if this matches
6476                  the expected boundary based on the position of the last
6477                  IT candidate.  */
6478               if (count & 1)
6479                 break;
6480               seen_it = 0;
6481             }
6482         }
6483       if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
6484         {
6485           enum map_type type = MAP_ARM;
6486           bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
6487
6488           if (!found || (found && type == MAP_THUMB))
6489             {
6490               /* This could be an IT instruction.  */
6491               seen_it = insn;
6492               it_count = count >> 1;
6493             }
6494         }
6495       if ((insn & 0xf800) >= 0xe800)
6496         count++;
6497       else
6498         count = (count + 2) | 1;
6499       /* IT blocks contain at most 4 instructions.  */
6500       if (count >= 8 && !seen_it)
6501         return;
6502     }
6503   /* We found an IT instruction.  */
6504   ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
6505   if ((ifthen_state & 0xf) == 0)
6506     ifthen_state = 0;
6507 }
6508
6509 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
6510    mapping symbol.  */
6511
6512 static int
6513 is_mapping_symbol (struct disassemble_info *info, int n,
6514                    enum map_type *map_type)
6515 {
6516   const char *name;
6517
6518   name = bfd_asymbol_name (info->symtab[n]);
6519   if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
6520       && (name[2] == 0 || name[2] == '.'))
6521     {
6522       *map_type = ((name[1] == 'a') ? MAP_ARM
6523                    : (name[1] == 't') ? MAP_THUMB
6524                    : MAP_DATA);
6525       return TRUE;
6526     }
6527
6528   return FALSE;
6529 }
6530
6531 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
6532    Returns nonzero if *MAP_TYPE was set.  */
6533
6534 static int
6535 get_map_sym_type (struct disassemble_info *info,
6536                   int n,
6537                   enum map_type *map_type)
6538 {
6539   /* If the symbol is in a different section, ignore it.  */
6540   if (info->section != NULL && info->section != info->symtab[n]->section)
6541     return FALSE;
6542
6543   return is_mapping_symbol (info, n, map_type);
6544 }
6545
6546 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
6547    Returns nonzero if *MAP_TYPE was set.  */
6548
6549 static int
6550 get_sym_code_type (struct disassemble_info *info,
6551                    int n,
6552                    enum map_type *map_type)
6553 {
6554   elf_symbol_type *es;
6555   unsigned int type;
6556
6557   /* If the symbol is in a different section, ignore it.  */
6558   if (info->section != NULL && info->section != info->symtab[n]->section)
6559     return FALSE;
6560
6561   es = *(elf_symbol_type **)(info->symtab + n);
6562   type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
6563
6564   /* If the symbol has function type then use that.  */
6565   if (type == STT_FUNC || type == STT_GNU_IFUNC)
6566     {
6567       if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
6568           == ST_BRANCH_TO_THUMB)
6569         *map_type = MAP_THUMB;
6570       else
6571         *map_type = MAP_ARM;
6572       return TRUE;
6573     }
6574
6575   return FALSE;
6576 }
6577
6578 /* Search the mapping symbol state for instruction at pc.  This is only
6579    applicable for elf target.
6580
6581    There is an assumption Here, info->private_data contains the correct AND
6582    up-to-date information about current scan process.  The information will be
6583    used to speed this search process.
6584
6585    Return TRUE if the mapping state can be determined, and map_symbol
6586    will be updated accordingly.  Otherwise, return FALSE.  */
6587
6588 static bfd_boolean
6589 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
6590                          enum map_type *map_symbol)
6591 {
6592   bfd_vma addr, section_vma = 0;
6593   int n, last_sym = -1;
6594   bfd_boolean found = FALSE;
6595   bfd_boolean can_use_search_opt_p = FALSE;
6596
6597   /* Default to DATA.  A text section is required by the ABI to contain an
6598      INSN mapping symbol at the start.  A data section has no such
6599      requirement, hence if no mapping symbol is found the section must
6600      contain only data.  This however isn't very useful if the user has
6601      fully stripped the binaries.  If this is the case use the section
6602      attributes to determine the default.  If we have no section default to
6603      INSN as well, as we may be disassembling some raw bytes on a baremetal
6604      HEX file or similar.  */
6605   enum map_type type = MAP_DATA;
6606   if ((info->section && info->section->flags & SEC_CODE) || !info->section)
6607     type = MAP_ARM;
6608   struct arm_private_data *private_data;
6609
6610   if (info->private_data == NULL
6611       || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
6612     return FALSE;
6613
6614   private_data = info->private_data;
6615
6616   /* First, look for mapping symbols.  */
6617   if (info->symtab_size != 0)
6618   {
6619     if (pc <= private_data->last_mapping_addr)
6620       private_data->last_mapping_sym = -1;
6621
6622     /* Start scanning at the start of the function, or wherever
6623        we finished last time.  */
6624     n = info->symtab_pos + 1;
6625
6626     /* If the last stop offset is different from the current one it means we
6627        are disassembling a different glob of bytes.  As such the optimization
6628        would not be safe and we should start over.  */
6629     can_use_search_opt_p
6630       = private_data->last_mapping_sym >= 0
6631         && info->stop_offset == private_data->last_stop_offset;
6632
6633     if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
6634       n = private_data->last_mapping_sym;
6635
6636     /* Look down while we haven't passed the location being disassembled.
6637        The reason for this is that there's no defined order between a symbol
6638        and an mapping symbol that may be at the same address.  We may have to
6639        look at least one position ahead.  */
6640     for (; n < info->symtab_size; n++)
6641       {
6642         addr = bfd_asymbol_value (info->symtab[n]);
6643         if (addr > pc)
6644           break;
6645         if (get_map_sym_type (info, n, &type))
6646           {
6647             last_sym = n;
6648             found = TRUE;
6649           }
6650       }
6651
6652     if (!found)
6653       {
6654         n = info->symtab_pos;
6655         if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
6656           n = private_data->last_mapping_sym;
6657
6658         /* No mapping symbol found at this address.  Look backwards
6659            for a preceeding one, but don't go pass the section start
6660            otherwise a data section with no mapping symbol can pick up
6661            a text mapping symbol of a preceeding section.  The documentation
6662            says section can be NULL, in which case we will seek up all the
6663            way to the top.  */
6664         if (info->section)
6665           section_vma = info->section->vma;
6666
6667         for (; n >= 0; n--)
6668           {
6669             addr = bfd_asymbol_value (info->symtab[n]);
6670             if (addr < section_vma)
6671               break;
6672
6673             if (get_map_sym_type (info, n, &type))
6674               {
6675                 last_sym = n;
6676                 found = TRUE;
6677                 break;
6678               }
6679           }
6680       }
6681   }
6682
6683   /* If no mapping symbol was found, try looking up without a mapping
6684      symbol.  This is done by walking up from the current PC to the nearest
6685      symbol.  We don't actually have to loop here since symtab_pos will
6686      contain the nearest symbol already.  */
6687   if (!found)
6688     {
6689       n = info->symtab_pos;
6690       if (n >= 0 && get_sym_code_type (info, n, &type))
6691         {
6692           last_sym = n;
6693           found = TRUE;
6694         }
6695     }
6696
6697   private_data->last_mapping_sym = last_sym;
6698   private_data->last_type = type;
6699   private_data->last_stop_offset = info->stop_offset;
6700
6701   *map_symbol = type;
6702   return found;
6703 }
6704
6705 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
6706    of the supplied arm_feature_set structure with bitmasks indicating
6707    the supported base architectures and coprocessor extensions.
6708
6709    FIXME: This could more efficiently implemented as a constant array,
6710    although it would also be less robust.  */
6711
6712 static void
6713 select_arm_features (unsigned long mach,
6714                      arm_feature_set * features)
6715 {
6716   arm_feature_set arch_fset;
6717   const arm_feature_set fpu_any = FPU_ANY;
6718
6719 #undef ARM_SET_FEATURES
6720 #define ARM_SET_FEATURES(FSET) \
6721   {                                                     \
6722     const arm_feature_set fset = FSET;                  \
6723     arch_fset = fset;                                   \
6724   }
6725
6726   /* When several architecture versions share the same bfd_mach_arm_XXX value
6727      the most featureful is chosen.  */
6728   switch (mach)
6729     {
6730     case bfd_mach_arm_2:         ARM_SET_FEATURES (ARM_ARCH_V2); break;
6731     case bfd_mach_arm_2a:        ARM_SET_FEATURES (ARM_ARCH_V2S); break;
6732     case bfd_mach_arm_3:         ARM_SET_FEATURES (ARM_ARCH_V3); break;
6733     case bfd_mach_arm_3M:        ARM_SET_FEATURES (ARM_ARCH_V3M); break;
6734     case bfd_mach_arm_4:         ARM_SET_FEATURES (ARM_ARCH_V4); break;
6735     case bfd_mach_arm_4T:        ARM_SET_FEATURES (ARM_ARCH_V4T); break;
6736     case bfd_mach_arm_5:         ARM_SET_FEATURES (ARM_ARCH_V5); break;
6737     case bfd_mach_arm_5T:        ARM_SET_FEATURES (ARM_ARCH_V5T); break;
6738     case bfd_mach_arm_5TE:       ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
6739     case bfd_mach_arm_XScale:    ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
6740     case bfd_mach_arm_ep9312:
6741         ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
6742                                            ARM_CEXT_MAVERICK | FPU_MAVERICK));
6743        break;
6744     case bfd_mach_arm_iWMMXt:    ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
6745     case bfd_mach_arm_iWMMXt2:   ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
6746     case bfd_mach_arm_5TEJ:      ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
6747     case bfd_mach_arm_6:         ARM_SET_FEATURES (ARM_ARCH_V6); break;
6748     case bfd_mach_arm_6KZ:       ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
6749     case bfd_mach_arm_6T2:       ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
6750     case bfd_mach_arm_6K:        ARM_SET_FEATURES (ARM_ARCH_V6K); break;
6751     case bfd_mach_arm_7:         ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
6752     case bfd_mach_arm_6M:        ARM_SET_FEATURES (ARM_ARCH_V6M); break;
6753     case bfd_mach_arm_6SM:       ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
6754     case bfd_mach_arm_7EM:       ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
6755     case bfd_mach_arm_8:
6756         {
6757           /* Add bits for extensions that Armv8.5-A recognizes.  */
6758           arm_feature_set armv8_5_ext_fset
6759             = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
6760           ARM_SET_FEATURES (ARM_ARCH_V8_5A);
6761           ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_5_ext_fset);
6762           break;
6763         }
6764     case bfd_mach_arm_8R:        ARM_SET_FEATURES (ARM_ARCH_V8R); break;
6765     case bfd_mach_arm_8M_BASE:   ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
6766     case bfd_mach_arm_8M_MAIN:   ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
6767     case bfd_mach_arm_8_1M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN); break;
6768       /* If the machine type is unknown allow all architecture types and all
6769          extensions.  */
6770     case bfd_mach_arm_unknown:   ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
6771     default:
6772       abort ();
6773     }
6774 #undef ARM_SET_FEATURES
6775
6776   /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
6777      and thus on bfd_mach_arm_XXX value.  Therefore for a given
6778      bfd_mach_arm_XXX value all coprocessor feature bits should be allowed.  */
6779   ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
6780 }
6781
6782
6783 /* NOTE: There are no checks in these routines that
6784    the relevant number of data bytes exist.  */
6785
6786 static int
6787 print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
6788 {
6789   unsigned char b[4];
6790   long          given;
6791   int           status;
6792   int           is_thumb = FALSE;
6793   int           is_data = FALSE;
6794   int           little_code;
6795   unsigned int  size = 4;
6796   void          (*printer) (bfd_vma, struct disassemble_info *, long);
6797   bfd_boolean   found = FALSE;
6798   struct arm_private_data *private_data;
6799
6800   if (info->disassembler_options)
6801     {
6802       parse_arm_disassembler_options (info->disassembler_options);
6803
6804       /* To avoid repeated parsing of these options, we remove them here.  */
6805       info->disassembler_options = NULL;
6806     }
6807
6808   /* PR 10288: Control which instructions will be disassembled.  */
6809   if (info->private_data == NULL)
6810     {
6811       static struct arm_private_data private;
6812
6813       if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
6814         /* If the user did not use the -m command line switch then default to
6815            disassembling all types of ARM instruction.
6816
6817            The info->mach value has to be ignored as this will be based on
6818            the default archictecture for the target and/or hints in the notes
6819            section, but it will never be greater than the current largest arm
6820            machine value (iWMMXt2), which is only equivalent to the V5TE
6821            architecture.  ARM architectures have advanced beyond the machine
6822            value encoding, and these newer architectures would be ignored if
6823            the machine value was used.
6824
6825            Ie the -m switch is used to restrict which instructions will be
6826            disassembled.  If it is necessary to use the -m switch to tell
6827            objdump that an ARM binary is being disassembled, eg because the
6828            input is a raw binary file, but it is also desired to disassemble
6829            all ARM instructions then use "-marm".  This will select the
6830            "unknown" arm architecture which is compatible with any ARM
6831            instruction.  */
6832           info->mach = bfd_mach_arm_unknown;
6833
6834       /* Compute the architecture bitmask from the machine number.
6835          Note: This assumes that the machine number will not change
6836          during disassembly....  */
6837       select_arm_features (info->mach, & private.features);
6838
6839       private.last_mapping_sym = -1;
6840       private.last_mapping_addr = 0;
6841       private.last_stop_offset = 0;
6842
6843       info->private_data = & private;
6844     }
6845
6846   private_data = info->private_data;
6847
6848   /* Decide if our code is going to be little-endian, despite what the
6849      function argument might say.  */
6850   little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
6851
6852   /* For ELF, consult the symbol table to determine what kind of code
6853      or data we have.  */
6854   if (info->symtab_size != 0
6855       && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
6856     {
6857       bfd_vma addr;
6858       int n;
6859       int last_sym = -1;
6860       enum map_type type = MAP_ARM;
6861
6862       found = mapping_symbol_for_insn (pc, info, &type);
6863       last_sym = private_data->last_mapping_sym;
6864
6865       is_thumb = (private_data->last_type == MAP_THUMB);
6866       is_data = (private_data->last_type == MAP_DATA);
6867
6868       /* Look a little bit ahead to see if we should print out
6869          two or four bytes of data.  If there's a symbol,
6870          mapping or otherwise, after two bytes then don't
6871          print more.  */
6872       if (is_data)
6873         {
6874           size = 4 - (pc & 3);
6875           for (n = last_sym + 1; n < info->symtab_size; n++)
6876             {
6877               addr = bfd_asymbol_value (info->symtab[n]);
6878               if (addr > pc
6879                   && (info->section == NULL
6880                       || info->section == info->symtab[n]->section))
6881                 {
6882                   if (addr - pc < size)
6883                     size = addr - pc;
6884                   break;
6885                 }
6886             }
6887           /* If the next symbol is after three bytes, we need to
6888              print only part of the data, so that we can use either
6889              .byte or .short.  */
6890           if (size == 3)
6891             size = (pc & 1) ? 1 : 2;
6892         }
6893     }
6894
6895   if (info->symbols != NULL)
6896     {
6897       if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
6898         {
6899           coff_symbol_type * cs;
6900
6901           cs = coffsymbol (*info->symbols);
6902           is_thumb = (   cs->native->u.syment.n_sclass == C_THUMBEXT
6903                       || cs->native->u.syment.n_sclass == C_THUMBSTAT
6904                       || cs->native->u.syment.n_sclass == C_THUMBLABEL
6905                       || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
6906                       || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
6907         }
6908       else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
6909                && !found)
6910         {
6911           /* If no mapping symbol has been found then fall back to the type
6912              of the function symbol.  */
6913           elf_symbol_type *  es;
6914           unsigned int       type;
6915
6916           es = *(elf_symbol_type **)(info->symbols);
6917           type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
6918
6919           is_thumb =
6920             ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
6921               == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
6922         }
6923       else if (bfd_asymbol_flavour (*info->symbols)
6924                == bfd_target_mach_o_flavour)
6925         {
6926           bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
6927
6928           is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
6929         }
6930     }
6931
6932   if (force_thumb)
6933     is_thumb = TRUE;
6934
6935   if (is_data)
6936     info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6937   else
6938     info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6939
6940   info->bytes_per_line = 4;
6941
6942   /* PR 10263: Disassemble data if requested to do so by the user.  */
6943   if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
6944     {
6945       int i;
6946
6947       /* Size was already set above.  */
6948       info->bytes_per_chunk = size;
6949       printer = print_insn_data;
6950
6951       status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
6952       given = 0;
6953       if (little)
6954         for (i = size - 1; i >= 0; i--)
6955           given = b[i] | (given << 8);
6956       else
6957         for (i = 0; i < (int) size; i++)
6958           given = b[i] | (given << 8);
6959     }
6960   else if (!is_thumb)
6961     {
6962       /* In ARM mode endianness is a straightforward issue: the instruction
6963          is four bytes long and is either ordered 0123 or 3210.  */
6964       printer = print_insn_arm;
6965       info->bytes_per_chunk = 4;
6966       size = 4;
6967
6968       status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
6969       if (little_code)
6970         given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
6971       else
6972         given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
6973     }
6974   else
6975     {
6976       /* In Thumb mode we have the additional wrinkle of two
6977          instruction lengths.  Fortunately, the bits that determine
6978          the length of the current instruction are always to be found
6979          in the first two bytes.  */
6980       printer = print_insn_thumb16;
6981       info->bytes_per_chunk = 2;
6982       size = 2;
6983
6984       status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
6985       if (little_code)
6986         given = (b[0]) | (b[1] << 8);
6987       else
6988         given = (b[1]) | (b[0] << 8);
6989
6990       if (!status)
6991         {
6992           /* These bit patterns signal a four-byte Thumb
6993              instruction.  */
6994           if ((given & 0xF800) == 0xF800
6995               || (given & 0xF800) == 0xF000
6996               || (given & 0xF800) == 0xE800)
6997             {
6998               status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
6999               if (little_code)
7000                 given = (b[0]) | (b[1] << 8) | (given << 16);
7001               else
7002                 given = (b[1]) | (b[0] << 8) | (given << 16);
7003
7004               printer = print_insn_thumb32;
7005               size = 4;
7006             }
7007         }
7008
7009       if (ifthen_address != pc)
7010         find_ifthen_state (pc, info, little_code);
7011
7012       if (ifthen_state)
7013         {
7014           if ((ifthen_state & 0xf) == 0x8)
7015             ifthen_next_state = 0;
7016           else
7017             ifthen_next_state = (ifthen_state & 0xe0)
7018                                 | ((ifthen_state & 0xf) << 1);
7019         }
7020     }
7021
7022   if (status)
7023     {
7024       info->memory_error_func (status, pc, info);
7025       return -1;
7026     }
7027   if (info->flags & INSN_HAS_RELOC)
7028     /* If the instruction has a reloc associated with it, then
7029        the offset field in the instruction will actually be the
7030        addend for the reloc.  (We are using REL type relocs).
7031        In such cases, we can ignore the pc when computing
7032        addresses, since the addend is not currently pc-relative.  */
7033     pc = 0;
7034
7035   printer (pc, info, given);
7036
7037   if (is_thumb)
7038     {
7039       ifthen_state = ifthen_next_state;
7040       ifthen_address += size;
7041     }
7042   return size;
7043 }
7044
7045 int
7046 print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
7047 {
7048   /* Detect BE8-ness and record it in the disassembler info.  */
7049   if (info->flavour == bfd_target_elf_flavour
7050       && info->section != NULL
7051       && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
7052     info->endian_code = BFD_ENDIAN_LITTLE;
7053
7054   return print_insn (pc, info, FALSE);
7055 }
7056
7057 int
7058 print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
7059 {
7060   return print_insn (pc, info, TRUE);
7061 }
7062
7063 const disasm_options_and_args_t *
7064 disassembler_options_arm (void)
7065 {
7066   static disasm_options_and_args_t *opts_and_args;
7067
7068   if (opts_and_args == NULL)
7069     {
7070       disasm_options_t *opts;
7071       unsigned int i;
7072
7073       opts_and_args = XNEW (disasm_options_and_args_t);
7074       opts_and_args->args = NULL;
7075
7076       opts = &opts_and_args->options;
7077       opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
7078       opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
7079       opts->arg = NULL;
7080       for (i = 0; i < NUM_ARM_OPTIONS; i++)
7081         {
7082           opts->name[i] = regnames[i].name;
7083           if (regnames[i].description != NULL)
7084             opts->description[i] = _(regnames[i].description);
7085           else
7086             opts->description[i] = NULL;
7087         }
7088       /* The array we return must be NULL terminated.  */
7089       opts->name[i] = NULL;
7090       opts->description[i] = NULL;
7091     }
7092
7093   return opts_and_args;
7094 }
7095
7096 void
7097 print_arm_disassembler_options (FILE *stream)
7098 {
7099   unsigned int i, max_len = 0;
7100   fprintf (stream, _("\n\
7101 The following ARM specific disassembler options are supported for use with\n\
7102 the -M switch:\n"));
7103
7104   for (i = 0; i < NUM_ARM_OPTIONS; i++)
7105     {
7106       unsigned int len = strlen (regnames[i].name);
7107       if (max_len < len)
7108         max_len = len;
7109     }
7110
7111   for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
7112     fprintf (stream, "  %s%*c %s\n",
7113              regnames[i].name,
7114              (int)(max_len - strlen (regnames[i].name)), ' ',
7115              _(regnames[i].description));
7116 }