opcodes/arm-dis.c

   1 /* Instruction printing code for the ARM
   2    Copyright (C) 1994-2024 Free Software Foundation, Inc.
   3    Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
   4    Modification by James G. Smith (jsmith@cygnus.co.uk)
   5
   6    This file is part of libopcodes.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23 #include "sysdep.h"
  24 #include <assert.h>
  25
  26 #include "disassemble.h"
  27 #include "opcode/arm.h"
  28 #include "opintl.h"
  29 #include "safe-ctype.h"
  30 #include "libiberty.h"
  31 #include "floatformat.h"
  32
  33 /* FIXME: This shouldn't be done here.  */
  34 #include "coff/internal.h"
  35 #include "libcoff.h"
  36 #include "bfd.h"
  37 #include "elf-bfd.h"
  38 #include "elf/internal.h"
  39 #include "elf/arm.h"
  40 #include "mach-o.h"
  41
  42 /* Cached mapping symbol state.  */
  43 enum map_type
  44 {
  45   MAP_ARM,
  46   MAP_THUMB,
  47   MAP_DATA
  48 };
  49
  50 struct arm_private_data
  51 {
  52   /* The features to use when disassembling optional instructions.  */
  53   arm_feature_set features;
  54
  55   /* Track the last type (although this doesn't seem to be useful) */
  56   enum map_type last_type;
  57
  58   /* Tracking symbol table information */
  59   int last_mapping_sym;
  60
  61   /* The end range of the current range being disassembled.  */
  62   bfd_vma last_stop_offset;
  63   bfd_vma last_mapping_addr;
  64 };
  65
  66 enum mve_instructions
  67 {
  68   MVE_VPST,
  69   MVE_VPT_FP_T1,
  70   MVE_VPT_FP_T2,
  71   MVE_VPT_VEC_T1,
  72   MVE_VPT_VEC_T2,
  73   MVE_VPT_VEC_T3,
  74   MVE_VPT_VEC_T4,
  75   MVE_VPT_VEC_T5,
  76   MVE_VPT_VEC_T6,
  77   MVE_VCMP_FP_T1,
  78   MVE_VCMP_FP_T2,
  79   MVE_VCMP_VEC_T1,
  80   MVE_VCMP_VEC_T2,
  81   MVE_VCMP_VEC_T3,
  82   MVE_VCMP_VEC_T4,
  83   MVE_VCMP_VEC_T5,
  84   MVE_VCMP_VEC_T6,
  85   MVE_VDUP,
  86   MVE_VEOR,
  87   MVE_VFMAS_FP_SCALAR,
  88   MVE_VFMA_FP_SCALAR,
  89   MVE_VFMA_FP,
  90   MVE_VFMS_FP,
  91   MVE_VHADD_T1,
  92   MVE_VHADD_T2,
  93   MVE_VHSUB_T1,
  94   MVE_VHSUB_T2,
  95   MVE_VRHADD,
  96   MVE_VLD2,
  97   MVE_VLD4,
  98   MVE_VST2,
  99   MVE_VST4,
 100   MVE_VLDRB_T1,
 101   MVE_VLDRH_T2,
 102   MVE_VLDRB_T5,
 103   MVE_VLDRH_T6,
 104   MVE_VLDRW_T7,
 105   MVE_VSTRB_T1,
 106   MVE_VSTRH_T2,
 107   MVE_VSTRB_T5,
 108   MVE_VSTRH_T6,
 109   MVE_VSTRW_T7,
 110   MVE_VLDRB_GATHER_T1,
 111   MVE_VLDRH_GATHER_T2,
 112   MVE_VLDRW_GATHER_T3,
 113   MVE_VLDRD_GATHER_T4,
 114   MVE_VLDRW_GATHER_T5,
 115   MVE_VLDRD_GATHER_T6,
 116   MVE_VSTRB_SCATTER_T1,
 117   MVE_VSTRH_SCATTER_T2,
 118   MVE_VSTRW_SCATTER_T3,
 119   MVE_VSTRD_SCATTER_T4,
 120   MVE_VSTRW_SCATTER_T5,
 121   MVE_VSTRD_SCATTER_T6,
 122   MVE_VCVT_FP_FIX_VEC,
 123   MVE_VCVT_BETWEEN_FP_INT,
 124   MVE_VCVT_FP_HALF_FP,
 125   MVE_VCVT_FROM_FP_TO_INT,
 126   MVE_VRINT_FP,
 127   MVE_VMOV_HFP_TO_GP,
 128   MVE_VMOV_GP_TO_VEC_LANE,
 129   MVE_VMOV_IMM_TO_VEC,
 130   MVE_VMOV_VEC_TO_VEC,
 131   MVE_VMOV2_VEC_LANE_TO_GP,
 132   MVE_VMOV2_GP_TO_VEC_LANE,
 133   MVE_VMOV_VEC_LANE_TO_GP,
 134   MVE_VMVN_IMM,
 135   MVE_VMVN_REG,
 136   MVE_VORR_IMM,
 137   MVE_VORR_REG,
 138   MVE_VORN,
 139   MVE_VBIC_IMM,
 140   MVE_VBIC_REG,
 141   MVE_VMOVX,
 142   MVE_VMOVL,
 143   MVE_VMOVN,
 144   MVE_VMULL_INT,
 145   MVE_VMULL_POLY,
 146   MVE_VQDMULL_T1,
 147   MVE_VQDMULL_T2,
 148   MVE_VQMOVN,
 149   MVE_VQMOVUN,
 150   MVE_VADDV,
 151   MVE_VMLADAV_T1,
 152   MVE_VMLADAV_T2,
 153   MVE_VMLALDAV,
 154   MVE_VMLAS,
 155   MVE_VADDLV,
 156   MVE_VMLSDAV_T1,
 157   MVE_VMLSDAV_T2,
 158   MVE_VMLSLDAV,
 159   MVE_VRMLALDAVH,
 160   MVE_VRMLSLDAVH,
 161   MVE_VQDMLADH,
 162   MVE_VQRDMLADH,
 163   MVE_VQDMLAH,
 164   MVE_VQRDMLAH,
 165   MVE_VQDMLASH,
 166   MVE_VQRDMLASH,
 167   MVE_VQDMLSDH,
 168   MVE_VQRDMLSDH,
 169   MVE_VQDMULH_T1,
 170   MVE_VQRDMULH_T2,
 171   MVE_VQDMULH_T3,
 172   MVE_VQRDMULH_T4,
 173   MVE_VDDUP,
 174   MVE_VDWDUP,
 175   MVE_VIWDUP,
 176   MVE_VIDUP,
 177   MVE_VCADD_FP,
 178   MVE_VCADD_VEC,
 179   MVE_VHCADD,
 180   MVE_VCMLA_FP,
 181   MVE_VCMUL_FP,
 182   MVE_VQRSHL_T1,
 183   MVE_VQRSHL_T2,
 184   MVE_VQRSHRN,
 185   MVE_VQRSHRUN,
 186   MVE_VQSHL_T1,
 187   MVE_VQSHL_T2,
 188   MVE_VQSHLU_T3,
 189   MVE_VQSHL_T4,
 190   MVE_VQSHRN,
 191   MVE_VQSHRUN,
 192   MVE_VRSHL_T1,
 193   MVE_VRSHL_T2,
 194   MVE_VRSHR,
 195   MVE_VRSHRN,
 196   MVE_VSHL_T1,
 197   MVE_VSHL_T2,
 198   MVE_VSHL_T3,
 199   MVE_VSHLC,
 200   MVE_VSHLL_T1,
 201   MVE_VSHLL_T2,
 202   MVE_VSHR,
 203   MVE_VSHRN,
 204   MVE_VSLI,
 205   MVE_VSRI,
 206   MVE_VADC,
 207   MVE_VABAV,
 208   MVE_VABD_FP,
 209   MVE_VABD_VEC,
 210   MVE_VABS_FP,
 211   MVE_VABS_VEC,
 212   MVE_VADD_FP_T1,
 213   MVE_VADD_FP_T2,
 214   MVE_VADD_VEC_T1,
 215   MVE_VADD_VEC_T2,
 216   MVE_VSBC,
 217   MVE_VSUB_FP_T1,
 218   MVE_VSUB_FP_T2,
 219   MVE_VSUB_VEC_T1,
 220   MVE_VSUB_VEC_T2,
 221   MVE_VAND,
 222   MVE_VBRSR,
 223   MVE_VCLS,
 224   MVE_VCLZ,
 225   MVE_VCTP,
 226   MVE_VMAX,
 227   MVE_VMAXA,
 228   MVE_VMAXNM_FP,
 229   MVE_VMAXNMA_FP,
 230   MVE_VMAXNMV_FP,
 231   MVE_VMAXNMAV_FP,
 232   MVE_VMAXV,
 233   MVE_VMAXAV,
 234   MVE_VMIN,
 235   MVE_VMINA,
 236   MVE_VMINNM_FP,
 237   MVE_VMINNMA_FP,
 238   MVE_VMINNMV_FP,
 239   MVE_VMINNMAV_FP,
 240   MVE_VMINV,
 241   MVE_VMINAV,
 242   MVE_VMLA,
 243   MVE_VMUL_FP_T1,
 244   MVE_VMUL_FP_T2,
 245   MVE_VMUL_VEC_T1,
 246   MVE_VMUL_VEC_T2,
 247   MVE_VMULH,
 248   MVE_VRMULH,
 249   MVE_VNEG_FP,
 250   MVE_VNEG_VEC,
 251   MVE_VPNOT,
 252   MVE_VPSEL,
 253   MVE_VQABS,
 254   MVE_VQADD_T1,
 255   MVE_VQADD_T2,
 256   MVE_VQSUB_T1,
 257   MVE_VQSUB_T2,
 258   MVE_VQNEG,
 259   MVE_VREV16,
 260   MVE_VREV32,
 261   MVE_VREV64,
 262   MVE_LSLL,
 263   MVE_LSLLI,
 264   MVE_LSRL,
 265   MVE_ASRL,
 266   MVE_ASRLI,
 267   MVE_SQRSHRL,
 268   MVE_SQRSHR,
 269   MVE_UQRSHL,
 270   MVE_UQRSHLL,
 271   MVE_UQSHL,
 272   MVE_UQSHLL,
 273   MVE_URSHRL,
 274   MVE_URSHR,
 275   MVE_SRSHRL,
 276   MVE_SRSHR,
 277   MVE_SQSHLL,
 278   MVE_SQSHL,
 279   MVE_CINC,
 280   MVE_CINV,
 281   MVE_CNEG,
 282   MVE_CSINC,
 283   MVE_CSINV,
 284   MVE_CSET,
 285   MVE_CSETM,
 286   MVE_CSNEG,
 287   MVE_CSEL,
 288   MVE_NONE
 289 };
 290
 291 enum mve_unpredictable
 292 {
 293   UNPRED_IT_BLOCK,              /* Unpredictable because mve insn in it block.
 294                                  */
 295   UNPRED_FCA_0_FCB_1,           /* Unpredictable because fcA = 0 and
 296                                    fcB = 1 (vpt).  */
 297   UNPRED_R13,                   /* Unpredictable because r13 (sp) or
 298                                    r15 (sp) used.  */
 299   UNPRED_R15,                   /* Unpredictable because r15 (pc) is used.  */
 300   UNPRED_Q_GT_4,                /* Unpredictable because
 301                                    vec reg start > 4 (vld4/st4).  */
 302   UNPRED_Q_GT_6,                /* Unpredictable because
 303                                    vec reg start > 6 (vld2/st2).  */
 304   UNPRED_R13_AND_WB,            /* Unpredictable becase gp reg = r13
 305                                    and WB bit = 1.  */
 306   UNPRED_Q_REGS_EQUAL,          /* Unpredictable because vector registers are
 307                                    equal.  */
 308   UNPRED_OS,                    /* Unpredictable because offset scaled == 1.  */
 309   UNPRED_GP_REGS_EQUAL,         /* Unpredictable because gp registers are the
 310                                    same.  */
 311   UNPRED_Q_REGS_EQ_AND_SIZE_1,  /* Unpredictable because q regs equal and
 312                                    size = 1.  */
 313   UNPRED_Q_REGS_EQ_AND_SIZE_2,  /* Unpredictable because q regs equal and
 314                                    size = 2.  */
 315   UNPRED_NONE                   /* No unpredictable behavior.  */
 316 };
 317
 318 enum mve_undefined
 319 {
 320   UNDEF_SIZE,                   /* undefined size.  */
 321   UNDEF_SIZE_0,                 /* undefined because size == 0.  */
 322   UNDEF_SIZE_2,                 /* undefined because size == 2.  */
 323   UNDEF_SIZE_3,                 /* undefined because size == 3.  */
 324   UNDEF_SIZE_LE_1,              /* undefined because size <= 1.  */
 325   UNDEF_SIZE_NOT_0,             /* undefined because size != 0.  */
 326   UNDEF_SIZE_NOT_2,             /* undefined because size != 2.  */
 327   UNDEF_SIZE_NOT_3,             /* undefined because size != 3.  */
 328   UNDEF_NOT_UNS_SIZE_0,         /* undefined because U == 0 and
 329                                    size == 0.  */
 330   UNDEF_NOT_UNS_SIZE_1,         /* undefined because U == 0 and
 331                                    size == 1.  */
 332   UNDEF_NOT_UNSIGNED,           /* undefined because U == 0.  */
 333   UNDEF_VCVT_IMM6,              /* imm6 < 32.  */
 334   UNDEF_VCVT_FSI_IMM6,          /* fsi = 0 and 32 >= imm6 <= 47.  */
 335   UNDEF_BAD_OP1_OP2,            /* undefined with op2 = 2 and
 336                                    op1 == (0 or 1).  */
 337   UNDEF_BAD_U_OP1_OP2,          /* undefined with U = 1 and
 338                                    op2 == 0 and op1 == (0 or 1).  */
 339   UNDEF_OP_0_BAD_CMODE,         /* undefined because op == 0 and cmode
 340                                    in {0xx1, x0x1}.  */
 341   UNDEF_XCHG_UNS,               /* undefined because X == 1 and U == 1.  */
 342   UNDEF_NONE                    /* no undefined behavior.  */
 343 };
 344
 345 struct opcode32
 346 {
 347   arm_feature_set arch;         /* Architecture defining this insn.  */
 348   unsigned long value;          /* If arch is 0 then value is a sentinel.  */
 349   unsigned long mask;           /* Recognise insn if (op & mask) == value.  */
 350   const char *  assembler;      /* How to disassemble this insn.  */
 351 };
 352
 353 struct cdeopcode32
 354 {
 355   arm_feature_set arch;         /* Architecture defining this insn.  */
 356   uint8_t coproc_shift;         /* coproc is this far into op.  */
 357   uint16_t coproc_mask;         /* Length of coproc field in op.  */
 358   unsigned long value;          /* If arch is 0 then value is a sentinel.  */
 359   unsigned long mask;           /* Recognise insn if (op & mask) == value.  */
 360   const char *  assembler;      /* How to disassemble this insn.  */
 361 };
 362
 363 /* MVE opcodes.  */
 364
 365 struct mopcode32
 366 {
 367   arm_feature_set arch;         /* Architecture defining this insn.  */
 368   enum mve_instructions mve_op;  /* Specific mve instruction for faster
 369                                     decoding.  */
 370   unsigned long value;          /* If arch is 0 then value is a sentinel.  */
 371   unsigned long mask;           /* Recognise insn if (op & mask) == value.  */
 372   const char *  assembler;      /* How to disassemble this insn.  */
 373 };
 374
 375 enum isa {
 376   ANY,
 377   T32,
 378   ARM
 379 };
 380
 381
 382 /* Shared (between Arm and Thumb mode) opcode.  */
 383 struct sopcode32
 384 {
 385   enum isa isa;                 /* Execution mode instruction availability.  */
 386   arm_feature_set arch;         /* Architecture defining this insn.  */
 387   unsigned long value;          /* If arch is 0 then value is a sentinel.  */
 388   unsigned long mask;           /* Recognise insn if (op & mask) == value.  */
 389   const char *  assembler;      /* How to disassemble this insn.  */
 390 };
 391
 392 struct opcode16
 393 {
 394   arm_feature_set arch;         /* Architecture defining this insn.  */
 395   unsigned short value, mask;   /* Recognise insn if (op & mask) == value.  */
 396   const char *assembler;        /* How to disassemble this insn.  */
 397 };
 398
 399 /* print_insn_coprocessor recognizes the following format control codes:
 400
 401    %%                   %
 402
 403    %c                   print condition code (always bits 28-31 in ARM mode)
 404    %b                   print condition code allowing cp_num == 9
 405    %q                   print shifter argument
 406    %u                   print condition code (unconditional in ARM mode,
 407                           UNPREDICTABLE if not AL in Thumb)
 408    %A                   print address for ldc/stc instruction
 409    %B                   print vstm/vldm register list
 410    %C                   print vscclrm register list
 411    %J                   print register for VLDR instruction
 412    %K                   print address for VLDR instruction
 413
 414    %<bitfield>c         print as a condition code (for vsel)
 415    %<bitfield>r         print as an ARM register
 416    %<bitfield>R         as %<>r but r15 is UNPREDICTABLE
 417    %<bitfield>ru        as %<>r but each u register must be unique.
 418    %<bitfield>d         print the bitfield in decimal
 419    %<bitfield>k         print immediate for VFPv3 conversion instruction
 420    %<bitfield>x         print the bitfield in hex
 421    %<bitfield>X         print the bitfield as 1 hex digit without leading "0x"
 422    %<bitfield>w         print as an iWMMXt width field - [bhwd]ss/us
 423    %<bitfield>g         print as an iWMMXt 64-bit register
 424    %<bitfield>G         print as an iWMMXt general purpose or control register
 425    %<bitfield>D         print as a NEON D register
 426    %<bitfield>Q         print as a NEON Q register
 427    %<bitfield>V         print as a NEON D or Q register
 428    %<bitfield>E         print a quarter-float immediate value
 429
 430    %y<code>             print a single precision VFP reg.
 431                           Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
 432    %z<code>             print a double precision VFP reg
 433                           Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
 434
 435    %<bitfield>'c        print specified char iff bitfield is all ones
 436    %<bitfield>`c        print specified char iff bitfield is all zeroes
 437    %<bitfield>?ab...    select from array of values in big endian order
 438
 439    %L                   print as an iWMMXt N/M width field.
 440    %Z                   print the Immediate of a WSHUFH instruction.
 441    %l                   like 'A' except use byte offsets for 'B' & 'H'
 442                         versions.
 443    %i                   print 5-bit immediate in bits 8,3..0
 444                         (print "32" when 0)
 445    %r                   print register offset address for wldt/wstr instruction.  */
 446
 447 enum opcode_sentinel_enum
 448 {
 449   SENTINEL_IWMMXT_START = 1,
 450   SENTINEL_IWMMXT_END,
 451   SENTINEL_GENERIC_START
 452 } opcode_sentinels;
 453
 454 #define UNDEFINED_INSTRUCTION      "\t\t@ <UNDEFINED> instruction: %0-31x"
 455 #define UNKNOWN_INSTRUCTION_32BIT  "\t\t@ <UNDEFINED> instruction: %08x"
 456 #define UNKNOWN_INSTRUCTION_16BIT  "\t\t@ <UNDEFINED> instruction: %04x"
 457 #define UNPREDICTABLE_INSTRUCTION  "\t@ <UNPREDICTABLE>"
 458
 459 /* Common coprocessor opcodes shared between Arm and Thumb-2.  */
 460
 461 /* print_insn_cde recognizes the following format control codes:
 462
 463    %%                   %
 464
 465    %a                   print 'a' iff bit 28 is 1
 466    %p                   print bits 8-10 as coprocessor
 467    %<bitfield>d         print as decimal
 468    %<bitfield>r         print as an ARM register
 469    %<bitfield>n         print as an ARM register but r15 is APSR_nzcv
 470    %<bitfield>T         print as an ARM register + 1
 471    %<bitfield>R         as %r but r13 is UNPREDICTABLE
 472    %<bitfield>S         as %r but rX where X > 10 is UNPREDICTABLE
 473    %j                   print immediate taken from bits (16..21,7,0..5)
 474    %k                   print immediate taken from bits (20..21,7,0..5).
 475    %l                   print immediate taken from bits (20..22,7,4..5).  */
 476
 477 /* At the moment there is only one valid position for the coprocessor number,
 478    and hence that's encoded in the macro below.  */
 479 #define CDE_OPCODE(ARCH, VALUE, MASK, ASM) \
 480   { ARCH, 8, 7, VALUE, MASK, ASM }
 481 static const struct cdeopcode32 cde_opcodes[] =
 482 {
 483   /* Custom Datapath Extension instructions.  */
 484   CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
 485               0xee000000, 0xefc00840,
 486               "cx1%a\t%p, %12-15n, %{I:#%0-5,7,16-21d%}"),
 487   CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
 488               0xee000040, 0xefc00840,
 489               "cx1d%a\t%p, %12-15S, %12-15T, %{I:#%0-5,7,16-21d%}"),
 490
 491   CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
 492               0xee400000, 0xefc00840,
 493               "cx2%a\t%p, %12-15n, %16-19n, %{I:#%0-5,7,20-21d%}"),
 494   CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
 495               0xee400040, 0xefc00840,
 496               "cx2d%a\t%p, %12-15S, %12-15T, %16-19n, %{I:#%0-5,7,20-21d%}"),
 497
 498   CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
 499               0xee800000, 0xef800840,
 500               "cx3%a\t%p, %0-3n, %16-19n, %12-15n, %{I:#%4-5,7,20-22d%}"),
 501   CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
 502               0xee800040, 0xef800840,
 503              "cx3d%a\t%p, %0-3S, %0-3T, %16-19n, %12-15n, %{I:#%4-5,7,20-22d%}"),
 504
 505   CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
 506               0xec200000, 0xeeb00840,
 507               "vcx1%a\t%p, %12-15,22V, %{I:#%0-5,7,16-19d%}"),
 508   CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
 509               0xec200040, 0xeeb00840,
 510               "vcx1%a\t%p, %12-15,22V, %{I:#%0-5,7,16-19,24d%}"),
 511
 512   CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
 513               0xec300000, 0xeeb00840,
 514               "vcx2%a\t%p, %12-15,22V, %0-3,5V, %{I:#%4,7,16-19d%}"),
 515   CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
 516               0xec300040, 0xeeb00840,
 517               "vcx2%a\t%p, %12-15,22V, %0-3,5V, %{I:#%4,7,16-19,24d%}"),
 518
 519   CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
 520               0xec800000, 0xee800840,
 521               "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, %{I:#%4,20-21d%}"),
 522   CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
 523               0xec800040, 0xee800840,
 524               "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, %{I:#%4,20-21,24d%}"),
 525
 526   CDE_OPCODE (ARM_FEATURE_CORE_LOW (0), 0, 0, 0)
 527
 528 };
 529
 530 static const struct sopcode32 coprocessor_opcodes[] =
 531 {
 532   /* XScale instructions.  */
 533   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 534     0x0e200010, 0x0fff0ff0,
 535     "mia%c\t%{R:acc0%}, %0-3r, %12-15r"},
 536   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 537     0x0e280010, 0x0fff0ff0,
 538     "miaph%c\t%{R:acc0%}, %0-3r, %12-15r"},
 539   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 540     0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\t%{R:acc0%}, %0-3r, %12-15r"},
 541   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 542     0x0c400000, 0x0ff00fff, "mar%c\t%{R:acc0%}, %12-15r, %16-19r"},
 543   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 544     0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, %{R:acc0%}"},
 545
 546   /* Intel Wireless MMX technology instructions.  */
 547   {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
 548   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
 549     0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
 550   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 551     0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
 552   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 553     0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, %{I:#%0-2d%}"},
 554   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 555     0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, %{I:#%0-2d%}"},
 556   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 557     0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, %{I:#%0-2d%}"},
 558   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 559     0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
 560   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 561     0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
 562   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 563     0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
 564   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 565     0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
 566   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 567     0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
 568   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 569     0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
 570   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 571     0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
 572   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 573     0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
 574   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 575     0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
 576   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 577     0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
 578   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 579     0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
 580   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 581     0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
 582   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 583     0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 584   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 585     0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
 586   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 587     0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
 588   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 589     0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, %{I:#%20-22d%}"},
 590   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 591     0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
 592   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 593     0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
 594   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 595     0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
 596   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 597     0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
 598   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 599     0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 600   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 601     0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 602   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 603     0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
 604   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 605     0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
 606   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 607     0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
 608   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 609     0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
 610   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 611     0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
 612   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 613     0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
 614   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 615     0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 616   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 617     0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, %{I:#%21-23d%}"},
 618   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 619     0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 620   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 621     0x0e800120, 0x0f800ff0,
 622     "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 623   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 624     0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 625   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 626     0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
 627   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 628     0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
 629   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 630     0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
 631   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 632     0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
 633   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 634     0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
 635   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 636     0x0e8000a0, 0x0f800ff0,
 637     "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 638   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 639     0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
 640   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 641     0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
 642   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 643     0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
 644   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 645     0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 646   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 647     0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, %{I:#%i%}"},
 648   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 649     0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 650   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 651     0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
 652   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 653     0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
 654   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 655     0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, %{I:#%Z%}"},
 656   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 657     0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, %{I:#%i%}"},
 658   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 659     0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 660   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 661     0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 662   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 663     0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, %{I:#%i%}"},
 664   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 665     0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 666   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 667     0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 668   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 669     0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, %{I:#%i%}"},
 670   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 671     0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 672   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 673     0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 674   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 675     0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
 676   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 677     0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
 678   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 679     0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
 680   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 681     0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 682   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 683     0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
 684   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 685     0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 686   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 687     0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
 688   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 689     0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
 690   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 691     0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
 692   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 693     0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
 694   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 695     0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 696   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 697     0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 698   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 699     0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
 700   {ANY, ARM_FEATURE_CORE_LOW (0),
 701     SENTINEL_IWMMXT_END, 0, "" },
 702
 703   /* Armv8.1-M Mainline instructions.  */
 704   {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
 705     0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
 706   {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
 707     0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
 708
 709   /* ARMv8-M Mainline Security Extensions instructions.  */
 710   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
 711     0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
 712   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
 713     0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
 714
 715   /* Register load/store.  */
 716   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 717     0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
 718   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 719     0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
 720   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 721     0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
 722   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 723     0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
 724   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 725     0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
 726   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 727     0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
 728   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 729     0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
 730   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 731     0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
 732   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 733     0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
 734   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 735     0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
 736   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 737     0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
 738   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 739     0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
 740   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 741     0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
 742   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 743     0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
 744   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 745     0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
 746   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 747     0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
 748   {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
 749     0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
 750   {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
 751     0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
 752
 753   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 754     0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t@ Deprecated"},
 755   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 756     0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t@ Deprecated"},
 757   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 758     0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t@ Deprecated"},
 759   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 760     0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t@ Deprecated"},
 761
 762   /* Data transfer between ARM and NEON registers.  */
 763   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 764     0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
 765   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 766     0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
 767   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 768     0x0e000b10, 0x0fd00f70, "vmov%c.32\t%{R:%16-19,7D[%21d]%}, %12-15r"},
 769   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 770     0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %{R:%16-19,7D[%21d]%}"},
 771   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 772     0x0e000b30, 0x0fd00f30, "vmov%c.16\t%{R:%16-19,7D[%6,21d]%}, %12-15r"},
 773   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 774     0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %{R:%16-19,7D[%6,21d]%}"},
 775   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 776     0x0e400b10, 0x0fd00f10, "vmov%c.8\t%{R:%16-19,7D[%5,6,21d]%}, %12-15r"},
 777   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 778     0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %{R:%16-19,7D[%5,6,21d]%}"},
 779   /* Half-precision conversion instructions.  */
 780   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 781     0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
 782   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 783     0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
 784   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
 785     0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
 786   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
 787     0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
 788
 789   /* Floating point coprocessor (VFP) instructions.  */
 790   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 791     0x0ee00a10, 0x0fff0fff, "vmsr%c\t%{R:fpsid%}, %12-15r"},
 792   {ANY, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN, FPU_VFP_EXT_V1xD),
 793     0x0ee10a10, 0x0fff0fff, "vmsr%c\t%{R:fpscr%}, %12-15r"},
 794   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
 795     0x0ee20a10, 0x0fff0fff, "vmsr%c\t%{R:fpscr_nzcvqc%}, %12-15r"},
 796   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 797     0x0ee60a10, 0x0fff0fff, "vmsr%c\t%{R:mvfr1%}, %12-15r"},
 798   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 799     0x0ee70a10, 0x0fff0fff, "vmsr%c\t%{R:mvfr0%}, %12-15r"},
 800   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 801     0x0ee50a10, 0x0fff0fff, "vmsr%c\t%{R:mvfr2%}, %12-15r"},
 802   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 803     0x0ee80a10, 0x0fff0fff, "vmsr%c\t%{R:fpexc%}, %12-15r"},
 804   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 805     0x0ee90a10, 0x0fff0fff, "vmsr%c\t%{R:fpinst%}, %12-15r\t@ Impl def"},
 806   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 807     0x0eea0a10, 0x0fff0fff, "vmsr%c\t%{R:fpinst2%}, %12-15r\t@ Impl def"},
 808   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
 809     0x0eec0a10, 0x0fff0fff, "vmsr%c\t%{R:vpr%}, %12-15r"},
 810   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
 811     0x0eed0a10, 0x0fff0fff, "vmsr%c\t%{R:p0%}, %12-15r"},
 812   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
 813     0x0eee0a10, 0x0fff0fff, "vmsr%c\t%{R:fpcxt_ns%}, %12-15r"},
 814   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
 815     0x0eef0a10, 0x0fff0fff, "vmsr%c\t%{R:fpcxt_s%}, %12-15r"},
 816   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 817     0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpsid%}"},
 818   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 819     0x0ef1fa10, 0x0fffffff, "vmrs%c\t%{R:APSR_nzcv%}, %{R:fpscr%}"},
 820   {ANY, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN, FPU_VFP_EXT_V1xD),
 821     0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpscr%}"},
 822   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
 823     0x0ef20a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpscr_nzcvqc%}"},
 824   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 825     0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:mvfr2%}"},
 826   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 827     0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:mvfr1%}"},
 828   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 829     0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:mvfr0%}"},
 830   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 831     0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpexc%}"},
 832   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 833     0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpinst%}\t@ Impl def"},
 834   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 835     0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpinst2%}\t@ Impl def"},
 836   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
 837     0x0efc0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:vpr%}"},
 838   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
 839     0x0efd0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:p0%}"},
 840   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
 841     0x0efe0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpcxt_ns%}"},
 842   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
 843     0x0eff0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpcxt_s%}"},
 844   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 845     0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%{I:%21d%}], %12-15r"},
 846   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 847     0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%{I:%21d%}]"},
 848   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 849     0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
 850   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 851     0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
 852   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 853     0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
 854   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 855     0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
 856   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 857     0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, %{I:#0.0%}"},
 858   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 859     0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, %{I:#0.0%}"},
 860   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 861     0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
 862   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 863     0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
 864   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 865     0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
 866   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 867     0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
 868   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 869     0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
 870   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 871     0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
 872   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 873     0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
 874   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 875     0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
 876   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 877     0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
 878   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 879     0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
 880   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 881     0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
 882   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 883     0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
 884   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 885     0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
 886   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 887     0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
 888   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
 889     0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, %{I:#%5,0-3k%}"},
 890   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
 891     0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, %{I:#%5,0-3k%}"},
 892   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 893     0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
 894   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 895     0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
 896   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
 897     0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, %{I:#%5,0-3k%}"},
 898   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
 899     0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, %{I:#%5,0-3k%}"},
 900   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 901     0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
 902   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
 903     0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, %{I:#%0-3,16-19E%}"},
 904   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
 905     0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, %{I:#%0-3,16-19E%}"},
 906   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
 907     0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
 908   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
 909     0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
 910   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
 911     0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
 912   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 913     0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
 914   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 915     0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
 916   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 917     0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
 918   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 919     0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
 920   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 921     0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
 922   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 923     0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
 924   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 925     0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
 926   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 927     0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
 928   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 929     0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
 930   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 931     0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
 932   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 933     0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
 934   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 935     0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
 936   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 937     0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
 938   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 939     0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
 940   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 941     0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
 942   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 943     0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
 944   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 945     0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
 946   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 947     0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
 948
 949   /* VFP Fused multiply add instructions.  */
 950   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 951     0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
 952   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 953     0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
 954   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 955     0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
 956   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 957     0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
 958   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 959     0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
 960   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 961     0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
 962   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 963     0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
 964   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 965     0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
 966
 967   /* FP v5.  */
 968   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 969     0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
 970   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 971     0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
 972   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 973     0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
 974   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 975     0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
 976   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 977     0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
 978   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 979     0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
 980   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 981     0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
 982   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 983     0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
 984   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 985     0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
 986   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 987     0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
 988   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 989     0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
 990   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 991     0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
 992
 993   {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
 994   /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8.  */
 995   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 996     0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%24?29%24'70%}"},
 997   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 998     0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%24?29%24'70%}"},
 999   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1000     0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23'90%}"},
1001   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1002     0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23?21%23?780%}"},
1003   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1004     0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23'90%}"},
1005   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1006     0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23?21%23?780%}"},
1007   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1008     0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %{R:%0-3D[%5?10]%}, %{I:#%20'90%}"},
1009   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1010     0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %{R:%0-3D[%5?10]%}, %{I:#%20?21%20?780%}"},
1011   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1012     0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %{R:%0-3,5D[0]%}, %{I:#%20'90%}"},
1013   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1014     0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %{R:%0-3,5D[0]%}, %{I:#%20?21%20?780%}"},
1015
1016   /* BFloat16 instructions.  */
1017   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1018     0x0eb30940, 0x0fbf0f50, "vcvt%7?tb%b.bf16.f32\t%y1, %y0"},
1019
1020   /* Dot Product instructions in the space of coprocessor 13.  */
1021   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
1022     0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
1023   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
1024     0xfe200d00, 0xff200f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %{R:%0-3D[%5?10]%}"},
1025
1026   /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8.  */
1027   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1028     0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-3d%}"},
1029   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1030     0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-3d%}"},
1031   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1032     0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-3,5d%}"},
1033   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1034     0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-3,5d%}"},
1035   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1036     0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-2d[%3d]%}"},
1037   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1038     0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-2d[%3d]%}"},
1039   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1040     0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-2d[%3,5d]%}"},
1041   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1042     0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-2d[%3,5d]%}"},
1043
1044   /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1045      cp_num: bit <11:8> == 0b1001.
1046      cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE.  */
1047   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1048     0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
1049   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1050     0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
1051   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1052     0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
1053   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1054     0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, %{I:#0.0%}"},
1055   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1056     0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, %{I:#%5,0-3k%}"},
1057   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1058     0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, %{I:#%5,0-3k%}"},
1059   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1060     0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
1061   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1062     0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
1063   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1064     0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
1065   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1066     0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
1067   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1068     0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
1069   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1070     0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
1071   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1072     0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
1073   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1074     0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
1075   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1076     0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
1077   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1078     0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
1079   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1080     0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
1081   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1082     0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
1083   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1084     0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
1085   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1086     0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
1087   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1088     0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
1089   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1090     0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
1091   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1092     0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
1093   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1094     0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
1095   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1096     0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, %{I:#%0-3,16-19E%}"},
1097   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1098     0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
1099   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1100     0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
1101   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1102     0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
1103   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1104     0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
1105   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1106     0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
1107   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1108     0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
1109   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1110     0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
1111   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1112     0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
1113   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1114     0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
1115   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1116     0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1117
1118   /* ARMv8.3 javascript conversion instruction.  */
1119   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1120     0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1121
1122   {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1123 };
1124
1125 /* Generic coprocessor instructions.  These are only matched if a more specific
1126    SIMD or co-processor instruction does not match first.  */
1127
1128 static const struct sopcode32 generic_coprocessor_opcodes[] =
1129 {
1130   /* Generic coprocessor instructions.  */
1131   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1132     0x0c400000, 0x0ff00000, "mcrr%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15R, %16-19r, %{R:cr%0-3d%}"},
1133   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1134     0x0c500000, 0x0ff00000,
1135     "mrrc%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15Ru, %16-19Ru, %{R:cr%0-3d%}"},
1136   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1137     0x0e000000, 0x0f000010,
1138     "cdp%c\t%{I:%8-11d%}, %{I:%20-23d%}, %{R:cr%12-15d%}, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
1139   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1140     0x0e10f010, 0x0f10f010,
1141     "mrc%c\t%{I:%8-11d%}, %{I:%21-23d%}, %{R:APSR_nzcv%}, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
1142   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1143     0x0e100010, 0x0f100010,
1144     "mrc%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15r, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
1145   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1146     0x0e000010, 0x0f100010,
1147     "mcr%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15R, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
1148   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1149     0x0c000000, 0x0e100000, "stc%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"},
1150   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1151     0x0c100000, 0x0e100000, "ldc%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"},
1152
1153   /* V6 coprocessor instructions.  */
1154   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1155     0xfc500000, 0xfff00000,
1156     "mrrc2%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15Ru, %16-19Ru, %{R:cr%0-3d%}"},
1157   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1158     0xfc400000, 0xfff00000,
1159     "mcrr2%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15R, %16-19R, %{R:cr%0-3d%}"},
1160
1161   /* V5 coprocessor instructions.  */
1162   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1163     0xfc100000, 0xfe100000, "ldc2%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"},
1164   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1165     0xfc000000, 0xfe100000, "stc2%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"},
1166   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1167     0xfe000000, 0xff000010,
1168     "cdp2%c\t%{I:%8-11d%}, %{I:%20-23d%}, %{R:cr%12-15d%}, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
1169   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1170     0xfe000010, 0xff100010,
1171     "mcr2%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15R, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
1172   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1173     0xfe100010, 0xff100010,
1174     "mrc2%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15r, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
1175
1176   {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1177 };
1178
1179 /* Neon opcode table:  This does not encode the top byte -- that is
1180    checked by the print_insn_neon routine, as it depends on whether we are
1181    doing thumb32 or arm32 disassembly.  */
1182
1183 /* print_insn_neon recognizes the following format control codes:
1184
1185    %%                   %
1186
1187    %c                   print condition code
1188    %u                   print condition code (unconditional in ARM mode,
1189                           UNPREDICTABLE if not AL in Thumb)
1190    %A                   print v{st,ld}[1234] operands
1191    %B                   print v{st,ld}[1234] any one operands
1192    %C                   print v{st,ld}[1234] single->all operands
1193    %D                   print scalar
1194    %E                   print vmov, vmvn, vorr, vbic encoded constant
1195    %F                   print vtbl,vtbx register list
1196
1197    %<bitfield>r         print as an ARM register
1198    %<bitfield>d         print the bitfield in decimal
1199    %<bitfield>e         print the 2^N - bitfield in decimal
1200    %<bitfield>D         print as a NEON D register
1201    %<bitfield>Q         print as a NEON Q register
1202    %<bitfield>R         print as a NEON D or Q register
1203    %<bitfield>Sn        print byte scaled width limited by n
1204    %<bitfield>Tn        print short scaled width limited by n
1205    %<bitfield>Un        print long scaled width limited by n
1206
1207    %<bitfield>'c        print specified char iff bitfield is all ones
1208    %<bitfield>`c        print specified char iff bitfield is all zeroes
1209    %<bitfield>?ab...    select from array of values in big endian order.  */
1210
1211 static const struct opcode32 neon_opcodes[] =
1212 {
1213   /* Extract.  */
1214   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1215     0xf2b00840, 0xffb00850,
1216     "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, %{I:#%8-11d%}"},
1217   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1218     0xf2b00000, 0xffb00810,
1219     "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, %{I:#%8-11d%}"},
1220
1221   /* Data transfer between ARM and NEON registers.  */
1222   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1223     0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
1224   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1225     0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
1226   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1227     0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
1228   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1229     0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
1230   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1231     0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
1232   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1233     0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
1234
1235   /* Move data element to all lanes.  */
1236   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1237     0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %{R:%0-3,5D[%19d]%}"},
1238   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1239     0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %{R:%0-3,5D[%18-19d]%}"},
1240   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1241     0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %{R:%0-3,5D[%17-19d]%}"},
1242
1243   /* Table lookup.  */
1244   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1245     0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1246   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1247     0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1248
1249   /* Half-precision conversions.  */
1250   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1251     0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1252   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1253     0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
1254
1255   /* NEON fused multiply add instructions.  */
1256   {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1257     0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1258   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1259     0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1260   {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1261     0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1262   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1263     0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1264
1265   /* BFloat16 instructions.  */
1266   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1267     0xfc000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1268   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1269     0xfe000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, %{R:d%0-3d[%5d]%}"},
1270   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1271     0xfc000c40, 0xffb00f50, "vmmla.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1272   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1273     0xf3b60640, 0xffbf0fd0, "vcvt%c.bf16.f32\t%12-15,22D, %0-3,5Q"},
1274   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1275     0xfc300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1276   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1277     0xfe300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %{R:%0-2D[%3,5d]%}"},
1278
1279   /* Matrix Multiply instructions.  */
1280   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1281     0xfc200c40, 0xffb00f50, "vsmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1282   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1283     0xfc200c50, 0xffb00f50, "vummla.u8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1284   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1285     0xfca00c40, 0xffb00f50, "vusmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1286   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1287     0xfca00d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1288   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1289     0xfe800d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, %{R:d%0-3d[%5d]%}"},
1290   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1291     0xfe800d10, 0xffb00f10, "vsudot.u8\t%12-15,22R, %16-19,7R, %{R:d%0-3d[%5d]%}"},
1292
1293   /* Two registers, miscellaneous.  */
1294   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1295     0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
1296   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1297     0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
1298   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1299     0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
1300   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1301     0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
1302   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1303     0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1304   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1305     0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1306   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1307     0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1308   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1309     0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1310   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1311     0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1312   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1313     0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1314   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1315     0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1316   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1317     0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1318   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1319     0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1320   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1321     0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1322   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1323     0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1324   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1325     0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1326   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1327     0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1328   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1329     0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1330   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1331     0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1332   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1333     0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1334   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1335     0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1336   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1337     0xf3b20300, 0xffb30fd0,
1338     "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, %{I:#%18-19S2%}"},
1339   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1340     0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1341   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1342     0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1343   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1344     0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1345   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1346     0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1347   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1348     0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1349   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1350     0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1351   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1352     0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1353   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1354     0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1355   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1356     0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1357   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1358     0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1359   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1360     0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1361   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1362     0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1363   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1364     0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1365   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1366     0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1367   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1368     0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
1369   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1370     0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
1371   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1372     0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
1373   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1374     0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
1375   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1376     0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
1377   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1378     0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1379   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1380     0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1381   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1382     0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1383   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1384     0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1385   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1386     0xf3bb0600, 0xffbf0e10,
1387     "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
1388   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1389     0xf3b70600, 0xffbf0e10,
1390     "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
1391
1392   /* Three registers of the same length.  */
1393   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1394     0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1395   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1396     0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1397   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1398     0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1399   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1400     0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1401   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1402     0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1403   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1404     0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1405   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1406     0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1407   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1408     0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1409   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1410     0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1411   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1412     0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1413   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1414     0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1415   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1416     0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1417   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1418     0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1419   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1420     0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1421   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1422     0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1423   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1424     0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1425   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1426     0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1427   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1428     0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1429   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1430     0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1431   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1432     0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1433   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1434     0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1435   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1436     0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1437   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1438     0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1439   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1440     0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1441   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1442     0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1443   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1444     0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1445   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1446     0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1447   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1448     0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1449   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1450     0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1451   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1452     0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1453   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1454     0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1455   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1456     0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1457   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1458     0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1459   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1460     0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1461   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1462     0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1463   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1464     0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1465   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1466     0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1467   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1468     0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1469   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1470     0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1471   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1472     0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1473   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1474     0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1475   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1476     0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1477   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1478     0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1479   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1480     0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1481   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1482     0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1483   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1484     0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1485   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1486     0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1487   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1488     0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1489   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1490     0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1491   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1492     0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1493   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1494     0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1495   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1496     0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1497   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1498     0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1499   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1500     0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1501   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1502     0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1503   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1504     0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1505   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1506     0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1507   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1508     0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1509   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1510     0xf2000b00, 0xff800f10,
1511     "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1512   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1513     0xf2000b10, 0xff800f10,
1514     "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1515   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1516     0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1517   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1518     0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1519   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1520     0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1521   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1522     0xf3000b00, 0xff800f10,
1523     "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1524   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1525     0xf2000000, 0xfe800f10,
1526     "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1527   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1528     0xf2000010, 0xfe800f10,
1529     "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1530   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1531     0xf2000100, 0xfe800f10,
1532     "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1533   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1534     0xf2000200, 0xfe800f10,
1535     "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1536   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1537     0xf2000210, 0xfe800f10,
1538     "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1539   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1540     0xf2000300, 0xfe800f10,
1541     "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1542   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1543     0xf2000310, 0xfe800f10,
1544     "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1545   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1546     0xf2000400, 0xfe800f10,
1547     "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1548   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1549     0xf2000410, 0xfe800f10,
1550     "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1551   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1552     0xf2000500, 0xfe800f10,
1553     "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1554   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1555     0xf2000510, 0xfe800f10,
1556     "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1557   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1558     0xf2000600, 0xfe800f10,
1559     "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1560   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1561     0xf2000610, 0xfe800f10,
1562     "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1563   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1564     0xf2000700, 0xfe800f10,
1565     "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1566   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1567     0xf2000710, 0xfe800f10,
1568     "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1569   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1570     0xf2000910, 0xfe800f10,
1571     "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1572   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1573     0xf2000a00, 0xfe800f10,
1574     "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1575   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1576     0xf2000a10, 0xfe800f10,
1577     "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1578   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1579     0xf3000b10, 0xff800f10,
1580     "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1581   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1582     0xf3000c10, 0xff800f10,
1583     "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1584
1585   /* One register and an immediate value.  */
1586   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1587     0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1588   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1589     0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1590   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1591     0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1592   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1593     0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1594   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1595     0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1596   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1597     0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1598   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1599     0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1600   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1601     0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1602   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1603     0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1604   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1605     0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1606   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1607     0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1608   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1609     0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1610   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1611     0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
1612
1613   /* Two registers and a shift amount.  */
1614   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1615     0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
1616   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1617     0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
1618   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1619     0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
1620   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1621     0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
1622   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1623     0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
1624   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1625     0xf2880950, 0xfeb80fd0,
1626     "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
1627   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1628     0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, %{I:#%16-18d%}"},
1629   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1630     0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
1631   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1632     0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
1633   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1634     0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"},
1635   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1636     0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
1637   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1638     0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"},
1639   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1640     0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"},
1641   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1642     0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
1643   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1644     0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
1645   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1646     0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
1647   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1648     0xf2900950, 0xfeb00fd0,
1649     "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
1650   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1651     0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, %{I:#%16-19d%}"},
1652   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1653     0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
1654   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1655     0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
1656   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1657     0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
1658   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1659     0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
1660   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1661     0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"},
1662   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1663     0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
1664   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1665     0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
1666   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1667     0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"},
1668   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1669     0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
1670   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1671     0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"},
1672   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1673     0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"},
1674   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1675     0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, %{I:#%16-20d%}"},
1676   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1677     0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
1678   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1679     0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
1680   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1681     0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
1682   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1683     0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
1684   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1685     0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"},
1686   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1687     0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
1688   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1689     0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
1690   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1691     0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
1692   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1693     0xf2a00950, 0xfea00fd0,
1694     "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
1695   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1696     0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"},
1697   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1698     0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
1699   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1700     0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"},
1701   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1702     0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"},
1703   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1704     0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
1705   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1706     0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
1707   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1708     0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
1709   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1710     0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
1711   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1712     0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"},
1713   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1714     0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"},
1715   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1716     0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
1717   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1718     0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"},
1719   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1720     0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"},
1721   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1722     0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
1723   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1724     0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
1725   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1726     0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
1727   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1728     0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
1729   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1730     0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"},
1731   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1732     0xf2a00e10, 0xfea00e90,
1733     "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
1734   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1735     0xf2a00c10, 0xfea00e90,
1736     "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
1737
1738   /* Three registers of different lengths.  */
1739   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1740     0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1741   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1742     0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1743   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1744     0xf2800400, 0xff800f50,
1745     "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1746   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1747     0xf2800600, 0xff800f50,
1748     "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1749   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1750     0xf2800900, 0xff800f50,
1751     "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1752   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1753     0xf2800b00, 0xff800f50,
1754     "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1755   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1756     0xf2800d00, 0xff800f50,
1757     "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1758   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1759     0xf3800400, 0xff800f50,
1760     "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1761   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1762     0xf3800600, 0xff800f50,
1763     "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1764   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1765     0xf2800000, 0xfe800f50,
1766     "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1767   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1768     0xf2800100, 0xfe800f50,
1769     "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1770   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1771     0xf2800200, 0xfe800f50,
1772     "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1773   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1774     0xf2800300, 0xfe800f50,
1775     "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1776   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1777     0xf2800500, 0xfe800f50,
1778     "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1779   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1780     0xf2800700, 0xfe800f50,
1781     "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1782   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1783     0xf2800800, 0xfe800f50,
1784     "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1785   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1786     0xf2800a00, 0xfe800f50,
1787     "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1788   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1789     0xf2800c00, 0xfe800f50,
1790     "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1791
1792   /* Two registers and a scalar.  */
1793   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1794     0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1795   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1796     0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1797   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1798     0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
1799   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1800     0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1801   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1802     0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1803   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1804     0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1805   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1806     0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
1807   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1808     0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1809   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1810     0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1811   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1812     0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1813   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1814     0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
1815   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1816     0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1817   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1818     0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1819   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1820     0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1821   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1822     0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1823   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1824     0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1825   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1826     0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1827   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1828     0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1829   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1830     0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1831   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1832     0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1833   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1834     0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1835   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1836     0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1837   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1838     0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1839   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1840     0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1841   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1842     0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1843   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1844     0xf2800240, 0xfe800f50,
1845     "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1846   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1847     0xf2800640, 0xfe800f50,
1848     "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1849   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1850     0xf2800a40, 0xfe800f50,
1851     "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1852   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1853     0xf2800e40, 0xff800f50,
1854    "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1855   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1856     0xf2800f40, 0xff800f50,
1857    "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1858   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1859     0xf3800e40, 0xff800f50,
1860    "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1861   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1862     0xf3800f40, 0xff800f50,
1863    "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1864   },
1865
1866   /* Element and structure load/store.  */
1867   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1868     0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1869   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1870     0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1871   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1872     0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1873   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1874     0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1875   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1876     0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1877   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1878     0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1879   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1880     0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1881   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1882     0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1883   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1884     0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1885   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1886     0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1887   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1888     0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1889   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1890     0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1891   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1892     0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1893   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1894     0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1895   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1896     0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1897   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1898     0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1899   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1900     0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1901   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1902     0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1903   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1904     0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1905
1906   {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
1907 };
1908
1909 /* mve opcode table.  */
1910
1911 /* print_insn_mve recognizes the following format control codes:
1912
1913    %%                   %
1914
1915    %a                   print '+' or '-' or imm offset in vldr[bhwd] and
1916                         vstr[bhwd]
1917    %c                   print condition code
1918    %d                   print addr mode of MVE vldr[bhw] and vstr[bhw]
1919    %u                   print 'U' (unsigned) or 'S' for various mve instructions
1920    %i                   print MVE predicate(s) for vpt and vpst
1921    %j                   print a 5-bit immediate from hw2[14:12,7:6]
1922    %k                   print 48 if the 7th position bit is set else print 64.
1923    %m                   print rounding mode for vcvt and vrint
1924    %n                   print vector comparison code for predicated instruction
1925    %s                   print size for various vcvt instructions
1926    %v                   print vector predicate for instruction in predicated
1927                         block
1928    %o                   print offset scaled for vldr[hwd] and vstr[hwd]
1929    %w                   print writeback mode for MVE v{st,ld}[24]
1930    %B                   print v{st,ld}[24] any one operands
1931    %E                   print vmov, vmvn, vorr, vbic encoded constant
1932    %N                   print generic index for vmov
1933    %T                   print bottom ('b') or top ('t') of source register
1934    %X                   print exchange field in vmla* instructions
1935
1936    %<bitfield>r         print as an ARM register
1937    %<bitfield>d         print the bitfield in decimal
1938    %<bitfield>A         print accumulate or not
1939    %<bitfield>c         print bitfield as a condition code
1940    %<bitfield>C         print bitfield as an inverted condition code
1941    %<bitfield>Q         print as a MVE Q register
1942    %<bitfield>F         print as a MVE S register
1943    %<bitfield>Z         as %<>r but r15 is ZR instead of PC and r13 is
1944                         UNPREDICTABLE
1945
1946    %<bitfield>S         as %<>r but r15 or r13 is UNPREDICTABLE
1947    %<bitfield>s         print size for vector predicate & non VMOV instructions
1948    %<bitfield>I         print carry flag or not
1949    %<bitfield>i         print immediate for vstr/vldr reg +/- imm
1950    %<bitfield>h         print high half of 64-bit destination reg
1951    %<bitfield>k         print immediate for vector conversion instruction
1952    %<bitfield>l         print low half of 64-bit destination reg
1953    %<bitfield>o         print rotate value for vcmul
1954    %<bitfield>u         print immediate value for vddup/vdwdup
1955    %<bitfield>x         print the bitfield in hex.
1956   */
1957
1958 static const struct mopcode32 mve_opcodes[] =
1959 {
1960   /* MVE.  */
1961
1962   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
1963    MVE_VPST,
1964    0xfe310f4d, 0xffbf1fff,
1965    "vpst%i"
1966   },
1967
1968   /* Floating point VPT T1.  */
1969   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
1970    MVE_VPT_FP_T1,
1971    0xee310f00, 0xefb10f50,
1972    "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
1973   /* Floating point VPT T2.  */
1974   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
1975    MVE_VPT_FP_T2,
1976    0xee310f40, 0xefb10f50,
1977    "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
1978
1979   /* Vector VPT T1.  */
1980   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
1981    MVE_VPT_VEC_T1,
1982    0xfe010f00, 0xff811f51,
1983    "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
1984   /* Vector VPT T2.  */
1985   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
1986    MVE_VPT_VEC_T2,
1987    0xfe010f01, 0xff811f51,
1988    "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
1989   /* Vector VPT T3.  */
1990   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
1991    MVE_VPT_VEC_T3,
1992    0xfe011f00, 0xff811f50,
1993    "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
1994   /* Vector VPT T4.  */
1995   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
1996    MVE_VPT_VEC_T4,
1997    0xfe010f40, 0xff811f70,
1998    "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
1999   /* Vector VPT T5.  */
2000   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2001    MVE_VPT_VEC_T5,
2002    0xfe010f60, 0xff811f70,
2003    "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
2004   /* Vector VPT T6.  */
2005   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2006    MVE_VPT_VEC_T6,
2007    0xfe011f40, 0xff811f50,
2008    "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
2009
2010   /* Vector VBIC immediate.  */
2011   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2012    MVE_VBIC_IMM,
2013    0xef800070, 0xefb81070,
2014    "vbic%v.i%8-11s\t%13-15,22Q, %E"},
2015
2016   /* Vector VBIC register.  */
2017   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2018    MVE_VBIC_REG,
2019    0xef100150, 0xffb11f51,
2020    "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2021
2022   /* Vector VABAV.  */
2023   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2024    MVE_VABAV,
2025    0xee800f01, 0xefc10f51,
2026    "vabav%v.%u%20-21s\t%12-15r, %17-19,7Q, %1-3,5Q"},
2027
2028   /* Vector VABD floating point.  */
2029   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2030    MVE_VABD_FP,
2031    0xff200d40, 0xffa11f51,
2032    "vabd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2033
2034   /* Vector VABD.  */
2035   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2036    MVE_VABD_VEC,
2037    0xef000740, 0xef811f51,
2038    "vabd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2039
2040   /* Vector VABS floating point.  */
2041   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2042    MVE_VABS_FP,
2043    0xFFB10740, 0xFFB31FD1,
2044    "vabs%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2045   /* Vector VABS.  */
2046   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2047    MVE_VABS_VEC,
2048    0xffb10340, 0xffb31fd1,
2049    "vabs%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2050
2051   /* Vector VADD floating point T1.  */
2052   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2053    MVE_VADD_FP_T1,
2054    0xef000d40, 0xffa11f51,
2055    "vadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2056   /* Vector VADD floating point T2.  */
2057   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2058    MVE_VADD_FP_T2,
2059    0xee300f40, 0xefb11f70,
2060    "vadd%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2061   /* Vector VADD T1.  */
2062   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2063    MVE_VADD_VEC_T1,
2064    0xef000840, 0xff811f51,
2065    "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2066   /* Vector VADD T2.  */
2067   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2068    MVE_VADD_VEC_T2,
2069    0xee010f40, 0xff811f70,
2070    "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2071
2072   /* Vector VADDLV.  */
2073   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2074    MVE_VADDLV,
2075    0xee890f00, 0xef8f1fd1,
2076    "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"},
2077
2078   /* Vector VADDV.  */
2079   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2080    MVE_VADDV,
2081    0xeef10f00, 0xeff31fd1,
2082    "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"},
2083
2084   /* Vector VADC.  */
2085   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2086    MVE_VADC,
2087    0xee300f00, 0xffb10f51,
2088    "vadc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2089
2090   /* Vector VAND.  */
2091   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2092    MVE_VAND,
2093    0xef000150, 0xffb11f51,
2094    "vand%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2095
2096   /* Vector VBRSR register.  */
2097   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2098    MVE_VBRSR,
2099    0xfe011e60, 0xff811f70,
2100    "vbrsr%v.%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2101
2102   /* Vector VCADD floating point.  */
2103   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2104    MVE_VCADD_FP,
2105    0xfc800840, 0xfea11f51,
2106    "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%24o%}"},
2107
2108   /* Vector VCADD.  */
2109   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2110    MVE_VCADD_VEC,
2111    0xfe000f00, 0xff810f51,
2112    "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%12o%}"},
2113
2114   /* Vector VCLS.  */
2115   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2116    MVE_VCLS,
2117    0xffb00440, 0xffb31fd1,
2118    "vcls%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2119
2120   /* Vector VCLZ.  */
2121   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2122    MVE_VCLZ,
2123    0xffb004c0, 0xffb31fd1,
2124    "vclz%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2125
2126   /* Vector VCMLA.  */
2127   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2128    MVE_VCMLA_FP,
2129    0xfc200840, 0xfe211f51,
2130    "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%23-24o%}"},
2131
2132   /* Vector VCMP floating point T1.  */
2133   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2134    MVE_VCMP_FP_T1,
2135    0xee310f00, 0xeff1ef50,
2136    "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
2137
2138   /* Vector VCMP floating point T2.  */
2139   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2140    MVE_VCMP_FP_T2,
2141    0xee310f40, 0xeff1ef50,
2142    "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
2143
2144   /* Vector VCMP T1.  */
2145   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2146    MVE_VCMP_VEC_T1,
2147    0xfe010f00, 0xffc1ff51,
2148    "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2149   /* Vector VCMP T2.  */
2150   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2151    MVE_VCMP_VEC_T2,
2152    0xfe010f01, 0xffc1ff51,
2153    "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2154   /* Vector VCMP T3.  */
2155   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2156    MVE_VCMP_VEC_T3,
2157    0xfe011f00, 0xffc1ff50,
2158    "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2159   /* Vector VCMP T4.  */
2160   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2161    MVE_VCMP_VEC_T4,
2162    0xfe010f40, 0xffc1ff70,
2163    "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
2164   /* Vector VCMP T5.  */
2165   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2166    MVE_VCMP_VEC_T5,
2167    0xfe010f60, 0xffc1ff70,
2168    "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
2169   /* Vector VCMP T6.  */
2170   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2171    MVE_VCMP_VEC_T6,
2172    0xfe011f40, 0xffc1ff50,
2173    "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
2174
2175   /* Vector VDUP.  */
2176   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2177    MVE_VDUP,
2178    0xeea00b10, 0xffb10f5f,
2179    "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2180
2181   /* Vector VEOR.  */
2182   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2183    MVE_VEOR,
2184    0xff000150, 0xffd11f51,
2185    "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2186
2187   /* Vector VFMA, vector * scalar.  */
2188   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2189    MVE_VFMA_FP_SCALAR,
2190    0xee310e40, 0xefb11f70,
2191    "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2192
2193   /* Vector VFMA floating point.  */
2194   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2195    MVE_VFMA_FP,
2196    0xef000c50, 0xffa11f51,
2197    "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2198
2199   /* Vector VFMS floating point.  */
2200   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2201    MVE_VFMS_FP,
2202    0xef200c50, 0xffa11f51,
2203    "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2204
2205   /* Vector VFMAS, vector * scalar.  */
2206   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2207    MVE_VFMAS_FP_SCALAR,
2208    0xee311e40, 0xefb11f70,
2209    "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2210
2211   /* Vector VHADD T1.  */
2212   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2213    MVE_VHADD_T1,
2214    0xef000040, 0xef811f51,
2215    "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2216
2217   /* Vector VHADD T2.  */
2218   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2219    MVE_VHADD_T2,
2220    0xee000f40, 0xef811f70,
2221    "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2222
2223   /* Vector VHSUB T1.  */
2224   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2225    MVE_VHSUB_T1,
2226    0xef000240, 0xef811f51,
2227    "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2228
2229   /* Vector VHSUB T2.  */
2230   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2231    MVE_VHSUB_T2,
2232    0xee001f40, 0xef811f70,
2233    "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2234
2235   /* Vector VCMUL.  */
2236   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2237    MVE_VCMUL_FP,
2238    0xee300e00, 0xefb10f50,
2239    "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%0,12o%}"},
2240
2241    /* Vector VCTP.  */
2242   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2243    MVE_VCTP,
2244    0xf000e801, 0xffc0ffff,
2245    "vctp%v.%20-21s\t%16-19r"},
2246
2247   /* Vector VDUP.  */
2248   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2249    MVE_VDUP,
2250    0xeea00b10, 0xffb10f5f,
2251    "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2252
2253   /* Vector VRHADD.  */
2254   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2255    MVE_VRHADD,
2256    0xef000140, 0xef811f51,
2257    "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2258
2259   /* Vector VCVT.  */
2260   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2261    MVE_VCVT_FP_FIX_VEC,
2262    0xef800c50, 0xef801cd1,
2263    "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, %{I:#%16-21k%}"},
2264
2265   /* Vector VCVT.  */
2266   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2267    MVE_VCVT_BETWEEN_FP_INT,
2268    0xffb30640, 0xffb31e51,
2269    "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
2270
2271   /* Vector VCVT between single and half-precision float, bottom half.  */
2272   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2273    MVE_VCVT_FP_HALF_FP,
2274    0xee3f0e01, 0xefbf1fd1,
2275    "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
2276
2277   /* Vector VCVT between single and half-precision float, top half.  */
2278   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2279    MVE_VCVT_FP_HALF_FP,
2280    0xee3f1e01, 0xefbf1fd1,
2281    "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
2282
2283   /* Vector VCVT.  */
2284   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2285    MVE_VCVT_FROM_FP_TO_INT,
2286    0xffb30040, 0xffb31c51,
2287    "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
2288
2289   /* Vector VDDUP.  */
2290   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2291    MVE_VDDUP,
2292    0xee011f6e, 0xff811f7e,
2293    "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, %{I:#%0,7u%}"},
2294
2295   /* Vector VDWDUP.  */
2296   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2297    MVE_VDWDUP,
2298    0xee011f60, 0xff811f70,
2299    "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, %{I:#%0,7u%}"},
2300
2301   /* Vector VHCADD.  */
2302   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2303    MVE_VHCADD,
2304    0xee000f00, 0xff810f51,
2305    "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%12o%}"},
2306
2307   /* Vector VIWDUP.  */
2308   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2309    MVE_VIWDUP,
2310    0xee010f60, 0xff811f70,
2311    "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, %{I:#%0,7u%}"},
2312
2313   /* Vector VIDUP.  */
2314   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2315    MVE_VIDUP,
2316    0xee010f6e, 0xff811f7e,
2317    "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, %{I:#%0,7u%}"},
2318
2319   /* Vector VLD2.  */
2320   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2321    MVE_VLD2,
2322    0xfc901e00, 0xff901e5f,
2323    "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2324
2325   /* Vector VLD4.  */
2326   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2327    MVE_VLD4,
2328    0xfc901e01, 0xff901e1f,
2329    "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2330
2331   /* Vector VLDRB gather load.  */
2332   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2333    MVE_VLDRB_GATHER_T1,
2334    0xec900e00, 0xefb01e50,
2335    "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2336
2337   /* Vector VLDRH gather load.  */
2338   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2339    MVE_VLDRH_GATHER_T2,
2340    0xec900e10, 0xefb01e50,
2341    "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2342
2343   /* Vector VLDRW gather load.  */
2344   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2345    MVE_VLDRW_GATHER_T3,
2346    0xfc900f40, 0xffb01fd0,
2347    "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2348
2349   /* Vector VLDRD gather load.  */
2350   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2351    MVE_VLDRD_GATHER_T4,
2352    0xec900fd0, 0xefb01fd0,
2353    "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2354
2355   /* Vector VLDRW gather load.  */
2356   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2357    MVE_VLDRW_GATHER_T5,
2358    0xfd101e00, 0xff111f00,
2359    "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"},
2360
2361   /* Vector VLDRD gather load, variant T6.  */
2362   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2363    MVE_VLDRD_GATHER_T6,
2364    0xfd101f00, 0xff111f00,
2365    "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"},
2366
2367   /* Vector VLDRB.  */
2368   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2369    MVE_VLDRB_T1,
2370    0xec100e00, 0xee581e00,
2371    "vldrb%v.%u%7-8s\t%13-15Q, %d"},
2372
2373   /* Vector VLDRH.  */
2374   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2375    MVE_VLDRH_T2,
2376    0xec180e00, 0xee581e00,
2377    "vldrh%v.%u%7-8s\t%13-15Q, %d"},
2378
2379   /* Vector VLDRB unsigned, variant T5.  */
2380   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2381    MVE_VLDRB_T5,
2382    0xec101e00, 0xfe101f80,
2383    "vldrb%v.u8\t%13-15,22Q, %d"},
2384
2385   /* Vector VLDRH unsigned, variant T6.  */
2386   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2387    MVE_VLDRH_T6,
2388    0xec101e80, 0xfe101f80,
2389    "vldrh%v.u16\t%13-15,22Q, %d"},
2390
2391   /* Vector VLDRW unsigned, variant T7.  */
2392   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2393    MVE_VLDRW_T7,
2394    0xec101f00, 0xfe101f80,
2395    "vldrw%v.u32\t%13-15,22Q, %d"},
2396
2397   /* Vector VMAX.  */
2398   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2399    MVE_VMAX,
2400    0xef000640, 0xef811f51,
2401    "vmax%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2402
2403   /* Vector VMAXA.  */
2404   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2405    MVE_VMAXA,
2406    0xee330e81, 0xffb31fd1,
2407    "vmaxa%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2408
2409   /* Vector VMAXNM floating point.  */
2410   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2411    MVE_VMAXNM_FP,
2412    0xff000f50, 0xffa11f51,
2413    "vmaxnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2414
2415   /* Vector VMAXNMA floating point.  */
2416   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2417    MVE_VMAXNMA_FP,
2418    0xee3f0e81, 0xefbf1fd1,
2419    "vmaxnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2420
2421   /* Vector VMAXNMV floating point.  */
2422   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2423    MVE_VMAXNMV_FP,
2424    0xeeee0f00, 0xefff0fd1,
2425    "vmaxnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2426
2427   /* Vector VMAXNMAV floating point.  */
2428   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2429    MVE_VMAXNMAV_FP,
2430    0xeeec0f00, 0xefff0fd1,
2431    "vmaxnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2432
2433   /* Vector VMAXV.  */
2434   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2435    MVE_VMAXV,
2436    0xeee20f00, 0xeff30fd1,
2437    "vmaxv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2438
2439   /* Vector VMAXAV.  */
2440   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2441    MVE_VMAXAV,
2442    0xeee00f00, 0xfff30fd1,
2443    "vmaxav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2444
2445   /* Vector VMIN.  */
2446   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2447    MVE_VMIN,
2448    0xef000650, 0xef811f51,
2449    "vmin%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2450
2451   /* Vector VMINA.  */
2452   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2453    MVE_VMINA,
2454    0xee331e81, 0xffb31fd1,
2455    "vmina%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2456
2457   /* Vector VMINNM floating point.  */
2458   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2459    MVE_VMINNM_FP,
2460    0xff200f50, 0xffa11f51,
2461    "vminnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2462
2463   /* Vector VMINNMA floating point.  */
2464   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2465    MVE_VMINNMA_FP,
2466    0xee3f1e81, 0xefbf1fd1,
2467    "vminnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2468
2469   /* Vector VMINNMV floating point.  */
2470   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2471    MVE_VMINNMV_FP,
2472    0xeeee0f80, 0xefff0fd1,
2473    "vminnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2474
2475   /* Vector VMINNMAV floating point.  */
2476   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2477    MVE_VMINNMAV_FP,
2478    0xeeec0f80, 0xefff0fd1,
2479    "vminnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2480
2481   /* Vector VMINV.  */
2482   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2483    MVE_VMINV,
2484    0xeee20f80, 0xeff30fd1,
2485    "vminv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2486
2487   /* Vector VMINAV.  */
2488   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2489    MVE_VMINAV,
2490    0xeee00f80, 0xfff30fd1,
2491    "vminav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2492
2493   /* Vector VMLA.  */
2494   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2495    MVE_VMLA,
2496    0xee010e40, 0xef811f70,
2497    "vmla%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2498
2499   /* Vector VMLALDAV.  Note must appear before VMLADAV due to instruction
2500      opcode aliasing.  */
2501   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2502    MVE_VMLALDAV,
2503    0xee801e00, 0xef801f51,
2504    "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2505
2506   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2507    MVE_VMLALDAV,
2508    0xee800e00, 0xef801f51,
2509    "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2510
2511   /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0.  */
2512   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2513    MVE_VMLADAV_T1,
2514    0xeef00e00, 0xeff01f51,
2515    "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2516
2517   /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0.  */
2518   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2519    MVE_VMLADAV_T2,
2520    0xeef00f00, 0xeff11f51,
2521    "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2522
2523   /* Vector VMLADAV T1 variant.  */
2524   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2525    MVE_VMLADAV_T1,
2526    0xeef01e00, 0xeff01f51,
2527    "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2528
2529   /* Vector VMLADAV T2 variant.  */
2530   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2531    MVE_VMLADAV_T2,
2532    0xeef01f00, 0xeff11f51,
2533    "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2534
2535   /* Vector VMLAS.  */
2536   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2537    MVE_VMLAS,
2538    0xee011e40, 0xef811f70,
2539    "vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2540
2541   /* Vector VRMLSLDAVH.  Note must appear before VMLSDAV due to instruction
2542      opcode aliasing.  */
2543   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2544    MVE_VRMLSLDAVH,
2545    0xfe800e01, 0xff810f51,
2546    "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2547
2548   /* Vector VMLSLDAV.  Note must appear before VMLSDAV due to instruction
2549      opcdoe aliasing.  */
2550   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2551    MVE_VMLSLDAV,
2552    0xee800e01, 0xff800f51,
2553    "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2554
2555   /* Vector VMLSDAV T1 Variant.  */
2556   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2557    MVE_VMLSDAV_T1,
2558    0xeef00e01, 0xfff00f51,
2559    "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2560
2561   /* Vector VMLSDAV T2 Variant.  */
2562   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2563    MVE_VMLSDAV_T2,
2564    0xfef00e01, 0xfff10f51,
2565    "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"},
2566
2567   /* Vector VMOV between gpr and half precision register, op == 0.  */
2568   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2569    MVE_VMOV_HFP_TO_GP,
2570    0xee000910, 0xfff00f7f,
2571    "vmov.f16\t%7,16-19F, %12-15r"},
2572
2573   /* Vector VMOV between gpr and half precision register, op == 1.  */
2574   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2575    MVE_VMOV_HFP_TO_GP,
2576    0xee100910, 0xfff00f7f,
2577    "vmov.f16\t%12-15r, %7,16-19F"},
2578
2579   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2580    MVE_VMOV_GP_TO_VEC_LANE,
2581    0xee000b10, 0xff900f1f,
2582    "vmov%c.%5-6,21-22s\t%{R:%17-19,7Q[%N]%}, %12-15r"},
2583
2584   /* Vector VORR immediate to vector.
2585      NOTE: MVE_VORR_IMM must appear in the table
2586      before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2587   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2588    MVE_VORR_IMM,
2589    0xef800050, 0xefb810f0,
2590    "vorr%v.i%8-11s\t%13-15,22Q, %E"},
2591
2592   /* Vector VQSHL T2 Variant.
2593      NOTE: MVE_VQSHL_T2 must appear in the table before
2594      before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2595   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2596    MVE_VQSHL_T2,
2597    0xef800750, 0xef801fd1,
2598    "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
2599
2600   /* Vector VQSHLU T3 Variant
2601      NOTE: MVE_VQSHL_T2 must appear in the table before
2602      before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2603
2604   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2605    MVE_VQSHLU_T3,
2606    0xff800650, 0xff801fd1,
2607    "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
2608
2609   /* Vector VRSHR
2610      NOTE: MVE_VRSHR must appear in the table before
2611      before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2612   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2613    MVE_VRSHR,
2614    0xef800250, 0xef801fd1,
2615    "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
2616
2617   /* Vector VSHL.
2618      NOTE: MVE_VSHL must appear in the table before
2619      before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2620   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2621    MVE_VSHL_T1,
2622    0xef800550, 0xff801fd1,
2623    "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
2624
2625   /* Vector VSHR
2626      NOTE: MVE_VSHR must appear in the table before
2627      before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2628   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2629    MVE_VSHR,
2630    0xef800050, 0xef801fd1,
2631    "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
2632
2633   /* Vector VSLI
2634      NOTE: MVE_VSLI must appear in the table before
2635      before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2636   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2637    MVE_VSLI,
2638    0xff800550, 0xff801fd1,
2639    "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
2640
2641   /* Vector VSRI
2642      NOTE: MVE_VSRI must appear in the table before
2643      before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2644   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2645    MVE_VSRI,
2646    0xff800450, 0xff801fd1,
2647    "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
2648
2649   /* Vector VMOV immediate to vector,
2650      undefinded for cmode == 1111 */
2651   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2652    MVE_VMVN_IMM, 0xef800f70, 0xefb81ff0, UNDEFINED_INSTRUCTION},
2653
2654   /* Vector VMOV immediate to vector,
2655      cmode == 1101 */
2656   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2657    MVE_VMOV_IMM_TO_VEC, 0xef800d50, 0xefb81fd0,
2658    "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2659
2660   /* Vector VMOV immediate to vector.  */
2661   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2662    MVE_VMOV_IMM_TO_VEC,
2663    0xef800050, 0xefb810d0,
2664    "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2665
2666   /* Vector VMOV two 32-bit lanes to two gprs, idx = 0.  */
2667   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2668    MVE_VMOV2_VEC_LANE_TO_GP,
2669    0xec000f00, 0xffb01ff0,
2670    "vmov%c\t%0-3r, %16-19r, %{R:%13-15,22Q[2]%}, %{R:%13-15,22Q[0]%}"},
2671
2672   /* Vector VMOV two 32-bit lanes to two gprs, idx = 1.  */
2673   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2674    MVE_VMOV2_VEC_LANE_TO_GP,
2675    0xec000f10, 0xffb01ff0,
2676    "vmov%c\t%0-3r, %16-19r, %{R:%13-15,22Q[3]%}, %{R:%13-15,22Q[1]%}"},
2677
2678   /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0.  */
2679   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2680    MVE_VMOV2_GP_TO_VEC_LANE,
2681    0xec100f00, 0xffb01ff0,
2682    "vmov%c\t%{R:%13-15,22Q[2]%}, %{R:%13-15,22Q[0]%}, %0-3r, %16-19r"},
2683
2684   /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1.  */
2685   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2686    MVE_VMOV2_GP_TO_VEC_LANE,
2687    0xec100f10, 0xffb01ff0,
2688    "vmov%c\t%{R:%13-15,22Q[3]%}, %{R:%13-15,22Q[1]%}, %0-3r, %16-19r"},
2689
2690   /* Vector VMOV Vector lane to gpr.  */
2691   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2692    MVE_VMOV_VEC_LANE_TO_GP,
2693    0xee100b10, 0xff100f1f,
2694    "vmov%c.%u%5-6,21-22s\t%12-15r, %{R:%17-19,7Q[%N]%}"},
2695
2696   /* Vector VSHLL T1 Variant.  Note: VSHLL T1 must appear before MVE_VMOVL due
2697      to instruction opcode aliasing.  */
2698   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2699    MVE_VSHLL_T1,
2700    0xeea00f40, 0xefa00fd1,
2701    "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
2702
2703   /* Vector VMOVL long.  */
2704   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2705    MVE_VMOVL,
2706    0xeea00f40, 0xefa70fd1,
2707    "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"},
2708
2709   /* Vector VMOV and narrow.  */
2710   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2711    MVE_VMOVN,
2712    0xfe310e81, 0xffb30fd1,
2713    "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2714
2715   /* Floating point move extract.  */
2716   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2717    MVE_VMOVX,
2718    0xfeb00a40, 0xffbf0fd0,
2719    "vmovx.f16\t%22,12-15F, %5,0-3F"},
2720
2721   /* Vector VMUL floating-point T1 variant.  */
2722   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2723    MVE_VMUL_FP_T1,
2724    0xff000d50, 0xffa11f51,
2725    "vmul%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2726
2727   /* Vector VMUL floating-point T2 variant.  */
2728   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2729    MVE_VMUL_FP_T2,
2730    0xee310e60, 0xefb11f70,
2731    "vmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2732
2733   /* Vector VMUL T1 variant.  */
2734   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2735    MVE_VMUL_VEC_T1,
2736    0xef000950, 0xff811f51,
2737    "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2738
2739   /* Vector VMUL T2 variant.  */
2740   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2741    MVE_VMUL_VEC_T2,
2742    0xee011e60, 0xff811f70,
2743    "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2744
2745   /* Vector VMULH.  */
2746   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2747    MVE_VMULH,
2748    0xee010e01, 0xef811f51,
2749    "vmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2750
2751   /* Vector VRMULH.  */
2752   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2753    MVE_VRMULH,
2754    0xee011e01, 0xef811f51,
2755    "vrmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2756
2757   /* Vector VMULL integer.  */
2758   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2759    MVE_VMULL_INT,
2760    0xee010e00, 0xef810f51,
2761    "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2762
2763   /* Vector VMULL polynomial.  */
2764   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2765    MVE_VMULL_POLY,
2766    0xee310e00, 0xefb10f51,
2767    "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2768
2769   /* Vector VMVN immediate to vector.  */
2770   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2771    MVE_VMVN_IMM,
2772    0xef800070, 0xefb810f0,
2773    "vmvn%v.i%8-11s\t%13-15,22Q, %E"},
2774
2775   /* Vector VMVN register.  */
2776   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2777    MVE_VMVN_REG,
2778    0xffb005c0, 0xffbf1fd1,
2779    "vmvn%v\t%13-15,22Q, %1-3,5Q"},
2780
2781   /* Vector VNEG floating point.  */
2782   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2783    MVE_VNEG_FP,
2784    0xffb107c0, 0xffb31fd1,
2785    "vneg%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2786
2787   /* Vector VNEG.  */
2788   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2789    MVE_VNEG_VEC,
2790    0xffb103c0, 0xffb31fd1,
2791    "vneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2792
2793   /* Vector VORN, vector bitwise or not.  */
2794   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2795    MVE_VORN,
2796    0xef300150, 0xffb11f51,
2797    "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2798
2799   /* Vector VORR register.  */
2800   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2801    MVE_VORR_REG,
2802    0xef200150, 0xffb11f51,
2803    "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2804
2805   /* Vector VMOV, vector to vector move. While decoding MVE_VORR_REG if
2806      "Qm==Qn", VORR should replaced by its alias VMOV. For that to happen
2807      MVE_VMOV_VEC_TO_VEC need to placed after MVE_VORR_REG in this mve_opcodes
2808      array.  */
2809
2810   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2811    MVE_VMOV_VEC_TO_VEC,
2812    0xef200150, 0xffb11f51,
2813    "vmov%v\t%13-15,22Q, %17-19,7Q"},
2814
2815   /* Vector VQDMULL T1 variant.  */
2816   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2817    MVE_VQDMULL_T1,
2818    0xee300f01, 0xefb10f51,
2819    "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2820
2821   /* Vector VPNOT.  */
2822   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2823    MVE_VPNOT,
2824    0xfe310f4d, 0xffffffff,
2825    "vpnot%v"},
2826
2827   /* Vector VPSEL.  */
2828   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2829    MVE_VPSEL,
2830    0xfe310f01, 0xffb11f51,
2831    "vpsel%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2832
2833   /* Vector VQABS.  */
2834   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2835    MVE_VQABS,
2836    0xffb00740, 0xffb31fd1,
2837    "vqabs%v.s%18-19s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2838
2839   /* Vector VQADD T1 variant.  */
2840   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2841    MVE_VQADD_T1,
2842    0xef000050, 0xef811f51,
2843    "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2844
2845   /* Vector VQADD T2 variant.  */
2846   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2847    MVE_VQADD_T2,
2848    0xee000f60, 0xef811f70,
2849    "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2850
2851   /* Vector VQDMULL T2 variant.  */
2852   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2853    MVE_VQDMULL_T2,
2854    0xee300f60, 0xefb10f70,
2855    "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2856
2857   /* Vector VQMOVN.  */
2858   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2859    MVE_VQMOVN,
2860    0xee330e01, 0xefb30fd1,
2861    "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"},
2862
2863   /* Vector VQMOVUN.  */
2864   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2865    MVE_VQMOVUN,
2866    0xee310e81, 0xffb30fd1,
2867    "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2868
2869   /* Vector VQDMLADH.  */
2870   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2871    MVE_VQDMLADH,
2872    0xee000e00, 0xff810f51,
2873    "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2874
2875   /* Vector VQRDMLADH.  */
2876   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2877    MVE_VQRDMLADH,
2878    0xee000e01, 0xff810f51,
2879    "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2880
2881   /* Vector VQDMLAH.  */
2882   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2883    MVE_VQDMLAH,
2884    0xee000e60, 0xff811f70,
2885    "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2886
2887   /* Vector VQRDMLAH.  */
2888   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2889    MVE_VQRDMLAH,
2890    0xee000e40, 0xff811f70,
2891    "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2892
2893   /* Vector VQDMLASH.  */
2894   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2895    MVE_VQDMLASH,
2896    0xee001e60, 0xff811f70,
2897    "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2898
2899   /* Vector VQRDMLASH.  */
2900   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2901    MVE_VQRDMLASH,
2902    0xee001e40, 0xff811f70,
2903    "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2904
2905   /* Vector VQDMLSDH.  */
2906   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2907    MVE_VQDMLSDH,
2908    0xfe000e00, 0xff810f51,
2909    "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2910
2911   /* Vector VQRDMLSDH.  */
2912   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2913    MVE_VQRDMLSDH,
2914    0xfe000e01, 0xff810f51,
2915    "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2916
2917   /* Vector VQDMULH T1 variant.  */
2918   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2919    MVE_VQDMULH_T1,
2920    0xef000b40, 0xff811f51,
2921    "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2922
2923   /* Vector VQRDMULH T2 variant.  */
2924   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2925    MVE_VQRDMULH_T2,
2926    0xff000b40, 0xff811f51,
2927    "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2928
2929   /* Vector VQDMULH T3 variant.  */
2930   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2931    MVE_VQDMULH_T3,
2932    0xee010e60, 0xff811f70,
2933    "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2934
2935   /* Vector VQRDMULH T4 variant.  */
2936   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2937    MVE_VQRDMULH_T4,
2938    0xfe010e60, 0xff811f70,
2939    "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2940
2941   /* Vector VQNEG.  */
2942   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2943    MVE_VQNEG,
2944    0xffb007c0, 0xffb31fd1,
2945    "vqneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2946
2947   /* Vector VQRSHL T1 variant.  */
2948   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2949    MVE_VQRSHL_T1,
2950    0xef000550, 0xef811f51,
2951    "vqrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
2952
2953   /* Vector VQRSHL T2 variant.  */
2954   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2955    MVE_VQRSHL_T2,
2956    0xee331ee0, 0xefb31ff0,
2957    "vqrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
2958
2959   /* Vector VQRSHRN.  */
2960   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2961    MVE_VQRSHRN,
2962    0xee800f41, 0xefa00fd1,
2963    "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
2964
2965   /* Vector VQRSHRUN.  */
2966   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2967    MVE_VQRSHRUN,
2968    0xfe800fc0, 0xffa00fd1,
2969    "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
2970
2971   /* Vector VQSHL T1 Variant.  */
2972   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2973    MVE_VQSHL_T1,
2974    0xee311ee0, 0xefb31ff0,
2975    "vqshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
2976
2977   /* Vector VQSHL T4 Variant.  */
2978   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2979    MVE_VQSHL_T4,
2980    0xef000450, 0xef811f51,
2981    "vqshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
2982
2983   /* Vector VQSHRN.  */
2984   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2985    MVE_VQSHRN,
2986    0xee800f40, 0xefa00fd1,
2987    "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
2988
2989   /* Vector VQSHRUN.  */
2990   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2991    MVE_VQSHRUN,
2992    0xee800fc0, 0xffa00fd1,
2993    "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
2994
2995   /* Vector VQSUB T1 Variant.  */
2996   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2997    MVE_VQSUB_T1,
2998    0xef000250, 0xef811f51,
2999    "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3000
3001   /* Vector VQSUB T2 Variant.  */
3002   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3003    MVE_VQSUB_T2,
3004    0xee001f60, 0xef811f70,
3005    "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3006
3007   /* Vector VREV16.  */
3008   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3009    MVE_VREV16,
3010    0xffb00140, 0xffb31fd1,
3011    "vrev16%v.8\t%13-15,22Q, %1-3,5Q"},
3012
3013   /* Vector VREV32.  */
3014   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3015    MVE_VREV32,
3016    0xffb000c0, 0xffb31fd1,
3017    "vrev32%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3018
3019   /* Vector VREV64.  */
3020   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3021    MVE_VREV64,
3022    0xffb00040, 0xffb31fd1,
3023    "vrev64%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3024
3025   /* Vector VRINT floating point.  */
3026   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
3027    MVE_VRINT_FP,
3028    0xffb20440, 0xffb31c51,
3029    "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
3030
3031   /* Vector VRMLALDAVH.  */
3032   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3033    MVE_VRMLALDAVH,
3034    0xee800f00, 0xef811f51,
3035    "vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3036
3037   /* Vector VRMLALDAVH.  */
3038   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3039    MVE_VRMLALDAVH,
3040    0xee801f00, 0xef811f51,
3041    "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3042
3043   /* Vector VRSHL T1 Variant.  */
3044   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3045    MVE_VRSHL_T1,
3046    0xef000540, 0xef811f51,
3047    "vrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3048
3049   /* Vector VRSHL T2 Variant.  */
3050   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3051    MVE_VRSHL_T2,
3052    0xee331e60, 0xefb31ff0,
3053    "vrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3054
3055   /* Vector VRSHRN.  */
3056   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3057    MVE_VRSHRN,
3058    0xfe800fc1, 0xffa00fd1,
3059    "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
3060
3061   /* Vector VSBC.  */
3062   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3063    MVE_VSBC,
3064    0xfe300f00, 0xffb10f51,
3065    "vsbc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3066
3067   /* Vector VSHL T2 Variant.  */
3068   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3069    MVE_VSHL_T2,
3070    0xee311e60, 0xefb31ff0,
3071    "vshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3072
3073   /* Vector VSHL T3 Variant.  */
3074   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3075    MVE_VSHL_T3,
3076    0xef000440, 0xef811f51,
3077    "vshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3078
3079   /* Vector VSHLC.  */
3080   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3081    MVE_VSHLC,
3082    0xeea00fc0, 0xffa01ff0,
3083    "vshlc%v\t%13-15,22Q, %0-3r, %{I:#%16-20d%}"},
3084
3085   /* Vector VSHLL T2 Variant.  */
3086   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3087    MVE_VSHLL_T2,
3088    0xee310e01, 0xefb30fd1,
3089    "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, %{I:#%18-19d%}"},
3090
3091   /* Vector VSHRN.  */
3092   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3093    MVE_VSHRN,
3094    0xee800fc1, 0xffa00fd1,
3095    "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
3096
3097   /* Vector VST2 no writeback.  */
3098   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3099    MVE_VST2,
3100    0xfc801e00, 0xffb01e5f,
3101    "vst2%5d.%7-8s\t%B, [%16-19r]"},
3102
3103   /* Vector VST2 writeback.  */
3104   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3105    MVE_VST2,
3106    0xfca01e00, 0xffb01e5f,
3107    "vst2%5d.%7-8s\t%B, [%16-19r]!"},
3108
3109   /* Vector VST4 no writeback.  */
3110   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3111    MVE_VST4,
3112    0xfc801e01, 0xffb01e1f,
3113    "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
3114
3115   /* Vector VST4 writeback.  */
3116   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3117    MVE_VST4,
3118    0xfca01e01, 0xffb01e1f,
3119    "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
3120
3121   /* Vector VSTRB scatter store, T1 variant.  */
3122   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3123    MVE_VSTRB_SCATTER_T1,
3124    0xec800e00, 0xffb01e50,
3125    "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
3126
3127   /* Vector VSTRH scatter store, T2 variant.  */
3128   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3129    MVE_VSTRH_SCATTER_T2,
3130    0xec800e10, 0xffb01e50,
3131    "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3132
3133   /* Vector VSTRW scatter store, T3 variant.  */
3134   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3135    MVE_VSTRW_SCATTER_T3,
3136    0xec800e40, 0xffb01e50,
3137    "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3138
3139   /* Vector VSTRD scatter store, T4 variant.  */
3140   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3141    MVE_VSTRD_SCATTER_T4,
3142    0xec800fd0, 0xffb01fd0,
3143    "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3144
3145   /* Vector VSTRW scatter store, T5 variant.  */
3146   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3147    MVE_VSTRW_SCATTER_T5,
3148    0xfd001e00, 0xff111f00,
3149    "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"},
3150
3151   /* Vector VSTRD scatter store, T6 variant.  */
3152   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3153    MVE_VSTRD_SCATTER_T6,
3154    0xfd001f00, 0xff111f00,
3155    "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"},
3156
3157   /* Vector VSTRB.  */
3158   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3159    MVE_VSTRB_T1,
3160    0xec000e00, 0xfe581e00,
3161    "vstrb%v.%7-8s\t%13-15Q, %d"},
3162
3163   /* Vector VSTRH.  */
3164   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3165    MVE_VSTRH_T2,
3166    0xec080e00, 0xfe581e00,
3167    "vstrh%v.%7-8s\t%13-15Q, %d"},
3168
3169   /* Vector VSTRB variant T5.  */
3170   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3171    MVE_VSTRB_T5,
3172    0xec001e00, 0xfe101f80,
3173    "vstrb%v.8\t%13-15,22Q, %d"},
3174
3175   /* Vector VSTRH variant T6.  */
3176   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3177    MVE_VSTRH_T6,
3178    0xec001e80, 0xfe101f80,
3179    "vstrh%v.16\t%13-15,22Q, %d"},
3180
3181   /* Vector VSTRW variant T7.  */
3182   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3183    MVE_VSTRW_T7,
3184    0xec001f00, 0xfe101f80,
3185    "vstrw%v.32\t%13-15,22Q, %d"},
3186
3187   /* Vector VSUB floating point T1 variant.  */
3188   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
3189    MVE_VSUB_FP_T1,
3190    0xef200d40, 0xffa11f51,
3191    "vsub%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3192
3193   /* Vector VSUB floating point T2 variant.  */
3194   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
3195    MVE_VSUB_FP_T2,
3196    0xee301f40, 0xefb11f70,
3197    "vsub%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3198
3199   /* Vector VSUB T1 variant.  */
3200   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3201    MVE_VSUB_VEC_T1,
3202    0xff000840, 0xff811f51,
3203    "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3204
3205   /* Vector VSUB T2 variant.  */
3206   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3207    MVE_VSUB_VEC_T2,
3208    0xee011f40, 0xff811f70,
3209    "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3210
3211   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3212    MVE_ASRLI,
3213    0xea50012f, 0xfff1813f,
3214    "asrl%c\t%17-19l, %9-11h, %j"},
3215
3216   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3217    MVE_ASRL,
3218    0xea50012d, 0xfff101ff,
3219    "asrl%c\t%17-19l, %9-11h, %12-15S"},
3220
3221   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3222    MVE_LSLLI,
3223    0xea50010f, 0xfff1813f,
3224    "lsll%c\t%17-19l, %9-11h, %j"},
3225
3226   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3227    MVE_LSLL,
3228    0xea50010d, 0xfff101ff,
3229    "lsll%c\t%17-19l, %9-11h, %12-15S"},
3230
3231   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3232    MVE_LSRL,
3233    0xea50011f, 0xfff1813f,
3234    "lsrl%c\t%17-19l, %9-11h, %j"},
3235
3236   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3237    MVE_SQRSHRL,
3238    0xea51012d, 0xfff1017f,
3239    "sqrshrl%c\t%17-19l, %9-11h, %k, %12-15S"},
3240
3241   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3242    MVE_SQRSHR,
3243    0xea500f2d, 0xfff00fff,
3244    "sqrshr%c\t%16-19S, %12-15S"},
3245
3246   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3247    MVE_SQSHLL,
3248    0xea51013f, 0xfff1813f,
3249    "sqshll%c\t%17-19l, %9-11h, %j"},
3250
3251   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3252    MVE_SQSHL,
3253    0xea500f3f, 0xfff08f3f,
3254    "sqshl%c\t%16-19S, %j"},
3255
3256   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3257    MVE_SRSHRL,
3258    0xea51012f, 0xfff1813f,
3259    "srshrl%c\t%17-19l, %9-11h, %j"},
3260
3261   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3262    MVE_SRSHR,
3263    0xea500f2f, 0xfff08f3f,
3264    "srshr%c\t%16-19S, %j"},
3265
3266   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3267    MVE_UQRSHLL,
3268    0xea51010d, 0xfff1017f,
3269    "uqrshll%c\t%17-19l, %9-11h, %k, %12-15S"},
3270
3271   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3272    MVE_UQRSHL,
3273    0xea500f0d, 0xfff00fff,
3274    "uqrshl%c\t%16-19S, %12-15S"},
3275
3276   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3277    MVE_UQSHLL,
3278     0xea51010f, 0xfff1813f,
3279    "uqshll%c\t%17-19l, %9-11h, %j"},
3280
3281   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3282    MVE_UQSHL,
3283    0xea500f0f, 0xfff08f3f,
3284    "uqshl%c\t%16-19S, %j"},
3285
3286   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3287    MVE_URSHRL,
3288     0xea51011f, 0xfff1813f,
3289    "urshrl%c\t%17-19l, %9-11h, %j"},
3290
3291   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3292    MVE_URSHR,
3293    0xea500f1f, 0xfff08f3f,
3294    "urshr%c\t%16-19S, %j"},
3295
3296   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3297    MVE_CSINC,
3298    0xea509000, 0xfff0f000,
3299    "csinc\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3300
3301   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3302    MVE_CSINV,
3303    0xea50a000, 0xfff0f000,
3304    "csinv\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3305
3306   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3307    MVE_CSET,
3308    0xea5f900f, 0xfffff00f,
3309    "cset\t%8-11S, %4-7C"},
3310
3311   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3312    MVE_CSETM,
3313    0xea5fa00f, 0xfffff00f,
3314    "csetm\t%8-11S, %4-7C"},
3315
3316   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3317    MVE_CSEL,
3318    0xea508000, 0xfff0f000,
3319    "csel\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3320
3321   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3322    MVE_CSNEG,
3323    0xea50b000, 0xfff0f000,
3324    "csneg\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3325
3326   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3327    MVE_CINC,
3328    0xea509000, 0xfff0f000,
3329    "cinc\t%8-11S, %16-19Z, %4-7C"},
3330
3331   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3332    MVE_CINV,
3333    0xea50a000, 0xfff0f000,
3334    "cinv\t%8-11S, %16-19Z, %4-7C"},
3335
3336   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3337    MVE_CNEG,
3338    0xea50b000, 0xfff0f000,
3339    "cneg\t%8-11S, %16-19Z, %4-7C"},
3340
3341   {ARM_FEATURE_CORE_LOW (0),
3342    MVE_NONE,
3343    0x00000000, 0x00000000, 0}
3344 };
3345
3346 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb.  All three are partially
3347    ordered: they must be searched linearly from the top to obtain a correct
3348    match.  */
3349
3350 /* print_insn_arm recognizes the following format control codes:
3351
3352    %%                   %
3353
3354    %a                   print address for ldr/str instruction
3355    %s                   print address for ldr/str halfword/signextend instruction
3356    %S                   like %s but allow UNPREDICTABLE addressing
3357    %b                   print branch destination
3358    %c                   print condition code (always bits 28-31)
3359    %m                   print register mask for ldm/stm instruction
3360    %o                   print operand2 (immediate or register + shift)
3361    %p                   print 'p' iff bits 12-15 are 15
3362    %t                   print 't' iff bit 21 set and bit 24 clear
3363    %B                   print arm BLX(1) destination
3364    %C                   print the PSR sub type.
3365    %U                   print barrier type.
3366    %P                   print address for pli instruction.
3367
3368    %<bitfield>r         print as an ARM register
3369    %<bitfield>T         print as an ARM register + 1
3370    %<bitfield>R         as %r but r15 is UNPREDICTABLE
3371    %<bitfield>{r|R}u    as %{r|R} but if matches the other %u field then is UNPREDICTABLE
3372    %<bitfield>{r|R}U    as %{r|R} but if matches the other %U field then is UNPREDICTABLE
3373    %<bitfield>d         print the bitfield in decimal
3374    %<bitfield>W         print the bitfield plus one in decimal
3375    %<bitfield>x         print the bitfield in hex
3376    %<bitfield>X         print the bitfield as 1 hex digit without leading "0x"
3377
3378    %<bitfield>'c        print specified char iff bitfield is all ones
3379    %<bitfield>`c        print specified char iff bitfield is all zeroes
3380    %<bitfield>?ab...    select from array of values in big endian order
3381
3382    %e                   print arm SMI operand (bits 0..7,8..19).
3383    %E                   print the LSB and WIDTH fields of a BFI or BFC instruction.
3384    %V                   print the 16-bit immediate field of a MOVT or MOVW instruction.
3385    %R                   print the SPSR/CPSR or banked register of an MRS.  */
3386
3387 static const struct opcode32 arm_opcodes[] =
3388 {
3389   /* ARM instructions.  */
3390   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3391     0xe1a00000, 0xffffffff, "nop\t\t\t@ (mov r0, r0)"},
3392   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3393     0xe7f000f0, 0xfff000f0, "udf\t%{I:#%e%}"},
3394
3395   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
3396     0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
3397   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3398     0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
3399   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3400     0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3401   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
3402     0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
3403   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3404     0x00800090, 0x0fa000f0,
3405     "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3406   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3407     0x00a00090, 0x0fa000f0,
3408     "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3409
3410   /* V8.2 RAS extension instructions.  */
3411   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
3412     0xe320f010, 0xffffffff, "esb"},
3413
3414   /* V8-R instructions.  */
3415   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R),
3416     0xf57ff04c, 0xffffffff, "dfb"},
3417
3418   /* V8 instructions.  */
3419   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3420     0x0320f005, 0x0fffffff, "sevl"},
3421   /* Defined in V8 but is in NOP space so available to all arch.  */
3422   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3423     0xe1000070, 0xfff000f0, "hlt\t%{I:0x%16-19X%12-15X%8-11X%0-3X%}"},
3424   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
3425     0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
3426   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3427     0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
3428   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3429     0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
3430   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3431     0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
3432   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3433     0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
3434   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3435     0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
3436   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3437     0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
3438   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3439     0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
3440   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3441     0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
3442   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3443     0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
3444   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3445     0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
3446   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3447     0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
3448   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3449     0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
3450   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3451     0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
3452   /* CRC32 instructions.  */
3453   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
3454     0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
3455   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
3456     0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
3457   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
3458     0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
3459   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
3460     0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
3461   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
3462     0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
3463   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
3464     0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
3465
3466   /* Privileged Access Never extension instructions.  */
3467   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
3468     0xf1100000, 0xfffffdff, "setpan\t%{I:#%9-9d%}"},
3469
3470   /* Virtualization Extension instructions.  */
3471   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
3472   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
3473
3474   /* Integer Divide Extension instructions.  */
3475   {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3476     0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
3477   {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3478     0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
3479
3480   /* MP Extension instructions.  */
3481   {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
3482
3483   /* Speculation Barriers.  */
3484   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
3485   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
3486   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
3487
3488   /* V7 instructions.  */
3489   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
3490   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t%{I:#%0-3d%}"},
3491   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
3492   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
3493   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
3494   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
3495   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
3496    {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
3497     0x0320f000, 0x0fffffff, "nop%c\t{%{I:%0-7d%}}"},
3498
3499   /* ARM V6T2 instructions.  */
3500   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3501     0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
3502   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3503     0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
3504   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3505     0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3506   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3507     0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
3508
3509   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3510     0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
3511   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3512     0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
3513
3514   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3515     0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
3516   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3517     0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
3518   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3519     0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
3520   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3521     0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, %{I:#%7-11d%}, %{I:#%16-20W%}"},
3522
3523   /* ARM Security extension instructions.  */
3524   {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
3525     0x01600070, 0x0ff000f0, "smc%c\t%e"},
3526
3527   /* ARM V6K instructions.  */
3528   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3529     0xf57ff01f, 0xffffffff, "clrex"},
3530   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3531     0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
3532   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3533     0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
3534   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3535     0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
3536   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3537     0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
3538   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3539     0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
3540   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3541     0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
3542
3543   /* ARMv8.5-A instructions.  */
3544   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
3545
3546   /* ARM V6K NOP hints.  */
3547   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3548     0x0320f001, 0x0fffffff, "yield%c"},
3549   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3550     0x0320f002, 0x0fffffff, "wfe%c"},
3551   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3552     0x0320f003, 0x0fffffff, "wfi%c"},
3553   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3554     0x0320f004, 0x0fffffff, "sev%c"},
3555   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3556     0x0320f000, 0x0fffff00, "nop%c\t{%{I:%0-7d%}}"},
3557
3558   /* ARM V6 instructions.  */
3559   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3560     0xf1080000, 0xfffffe3f, "cpsie\t%{B:%8'a%7'i%6'f%}"},
3561   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3562     0xf10a0000, 0xfffffe20, "cpsie\t%{B:%8'a%7'i%6'f%}, %{I:#%0-4d%}"},
3563   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3564     0xf10C0000, 0xfffffe3f, "cpsid\t%{B:%8'a%7'i%6'f%}"},
3565   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3566     0xf10e0000, 0xfffffe20, "cpsid\t%{B:%8'a%7'i%6'f%}, %{I:#%0-4d%}"},
3567   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3568     0xf1000000, 0xfff1fe20, "cps\t%{I:#%0-4d%}"},
3569   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3570     0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
3571   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3572     0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, %{B:lsl%} %{I:#%7-11d%}"},
3573   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3574     0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, %{B:asr%} %{I:#32%}"},
3575   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3576     0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, %{B:asr%} %{I:#%7-11d%}"},
3577   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3578     0x01900f9f, 0x0ff00fff, "ldrex%c\t%{R:r%12-15d%}, [%16-19R]"},
3579   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3580     0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
3581   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3582     0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
3583   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3584     0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
3585   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3586     0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
3587   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3588     0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
3589   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3590     0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
3591   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3592     0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
3593   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3594     0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
3595   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3596     0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
3597   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3598     0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
3599   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3600     0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
3601   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3602     0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
3603   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3604     0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
3605   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3606     0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
3607   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3608     0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
3609   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3610     0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
3611   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3612     0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
3613   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3614     0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
3615   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3616     0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
3617   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3618     0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
3619   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3620     0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
3621   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3622     0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
3623   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3624     0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
3625   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3626     0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
3627   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3628     0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
3629   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3630     0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
3631   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3632     0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
3633   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3634     0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
3635   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3636     0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
3637   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3638     0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
3639   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3640     0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
3641   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3642     0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
3643   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3644     0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
3645   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3646     0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
3647   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3648     0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
3649   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3650     0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
3651   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3652     0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
3653   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3654     0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
3655   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3656     0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
3657   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3658     0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
3659   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3660     0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
3661   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3662     0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
3663   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3664     0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
3665   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3666     0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
3667   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3668     0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
3669   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3670     0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
3671   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3672     0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
3673   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3674     0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
3675   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3676     0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
3677   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3678     0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
3679   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3680     0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
3681   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3682     0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
3683   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3684     0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
3685   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3686     0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
3687   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3688     0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
3689   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3690     0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
3691   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3692     0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
3693   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3694     0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
3695   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3696     0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
3697   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3698     0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
3699   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3700     0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
3701   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3702     0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
3703   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3704     0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
3705   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3706     0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
3707   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3708     0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
3709   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3710     0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
3711   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3712     0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
3713   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3714     0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
3715   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3716     0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
3717   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3718     0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
3719   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3720     0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
3721   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3722     0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
3723   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3724     0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
3725   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3726     0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
3727   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3728     0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
3729   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3730     0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
3731   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3732     0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
3733   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3734     0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
3735   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3736     0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
3737   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3738     0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
3739   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3740     0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
3741   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3742     0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
3743   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3744     0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
3745   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3746     0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR %{I:#24%}"},
3747   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3748     0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
3749   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3750     0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
3751   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3752     0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
3753   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3754     0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
3755   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3756     0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
3757   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3758     0xf1010000, 0xfffffc00, "setend\t%{B:%9?ble%}"},
3759   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3760     0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
3761   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3762     0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
3763   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3764     0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3765   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3766     0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3767   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3768     0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3769   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3770     0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3771   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3772     0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
3773   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3774     0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3775   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3776     0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3777   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3778     0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, %{I:#%0-4d%}"},
3779   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3780     0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, %{I:#%16-20W%}, %0-3R"},
3781   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3782     0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, %{I:#%16-20W%}, %0-3R, %{B:lsl%} %{I:#%7-11d%}"},
3783   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3784     0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, %{I:#%16-20W%}, %0-3R, %{B:asr%} %{I:#%7-11d%}"},
3785   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3786     0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, %{I:#%16-19W%}, %0-3r"},
3787   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3788     0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
3789   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3790     0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
3791   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3792     0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
3793   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3794     0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3795   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3796     0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, %{I:#%16-20d%}, %0-3R"},
3797   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3798     0x06e00010, 0x0fe00070, "usat%c\t%12-15R, %{I:#%16-20d%}, %0-3R, %{B:lsl%} %{I:#%7-11d%}"},
3799   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3800     0x06e00050, 0x0fe00070, "usat%c\t%12-15R, %{I:#%16-20d%}, %0-3R, %{B:asr%} %{I:#%7-11d%}"},
3801   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3802     0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, %{I:#%16-19d%}, %0-3R"},
3803
3804   /* V5J instruction.  */
3805   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
3806     0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
3807
3808   /* V5 Instructions.  */
3809   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3810     0xe1200070, 0xfff000f0,
3811     "bkpt\t%{I:0x%16-19X%12-15X%8-11X%0-3X%}"},
3812   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3813     0xfa000000, 0xfe000000, "blx\t%B"},
3814   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3815     0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
3816   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3817     0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
3818
3819   /* V5E "El Segundo" Instructions.  */
3820   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3821     0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
3822   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3823     0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
3824   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3825     0xf450f000, 0xfc70f000, "pld\t%a"},
3826   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3827     0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3828   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3829     0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3830   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3831     0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3832   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3833     0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
3834
3835   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3836     0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3837   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3838     0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
3839
3840   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3841     0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3842   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3843     0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3844   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3845     0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3846   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3847     0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3848
3849   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3850     0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
3851   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3852     0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
3853   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3854     0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
3855   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3856     0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
3857
3858   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3859     0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
3860   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3861     0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
3862
3863   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3864     0x01000050, 0x0ff00ff0,  "qadd%c\t%12-15R, %0-3R, %16-19R"},
3865   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3866     0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
3867   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3868     0x01200050, 0x0ff00ff0,  "qsub%c\t%12-15R, %0-3R, %16-19R"},
3869   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3870     0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
3871
3872   /* ARM Instructions.  */
3873   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3874     0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t@ (str%c %12-15r, %a)"},
3875
3876   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3877     0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
3878   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3879     0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
3880   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3881     0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
3882   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3883     0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
3884   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3885     0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
3886   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3887     0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
3888
3889   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3890     0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
3891   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3892     0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
3893   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3894     0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
3895   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3896     0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
3897
3898   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3899     0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
3900   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3901     0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
3902   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3903     0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
3904   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3905     0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
3906
3907   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3908     0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
3909   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3910     0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
3911   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3912     0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
3913
3914   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3915     0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
3916   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3917     0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
3918   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3919     0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
3920
3921   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3922     0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
3923   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3924     0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
3925   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3926     0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
3927
3928   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3929     0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
3930   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3931     0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
3932   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3933     0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
3934
3935   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3936     0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
3937   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3938     0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
3939   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3940     0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
3941
3942   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3943     0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
3944   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3945     0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
3946   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3947     0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
3948
3949   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3950     0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
3951   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3952     0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
3953   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3954     0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
3955
3956   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3957     0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
3958   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3959     0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
3960   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3961     0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
3962
3963   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
3964     0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
3965   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
3966     0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
3967   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
3968     0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
3969
3970   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3971     0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
3972   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3973     0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
3974   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3975     0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
3976
3977   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3978     0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
3979   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3980     0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
3981   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3982     0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
3983
3984   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3985     0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
3986   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3987     0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
3988   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3989     0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
3990
3991   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3992     0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
3993   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3994     0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
3995   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3996     0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
3997
3998   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3999     0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
4000   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4001     0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
4002   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4003     0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
4004
4005   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4006     0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
4007   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4008     0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
4009   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4010     0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
4011   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4012     0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
4013   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4014     0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
4015   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4016     0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
4017   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4018     0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
4019
4020   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4021     0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
4022   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4023     0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
4024   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4025     0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
4026
4027   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4028     0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
4029   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4030     0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
4031   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4032     0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
4033
4034   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4035     0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
4036   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4037     0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t@ (ldr%c %12-15r, %a)"},
4038
4039   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4040     0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
4041
4042   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4043     0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
4044   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4045     0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
4046
4047   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4048     0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4049   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4050     0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4051   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4052     0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4053   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4054     0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4055   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4056     0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4057   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4058     0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4059   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4060     0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4061   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4062     0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4063   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4064     0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4065   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4066     0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4067   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4068     0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4069   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4070     0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4071   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4072     0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4073   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4074     0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4075   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4076     0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4077   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4078     0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4079   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4080     0x092d0000, 0x0fff0000, "push%c\t%m"},
4081   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4082     0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
4083   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4084     0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4085
4086   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4087     0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4088   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4089     0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4090   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4091     0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4092   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4093     0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4094   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4095     0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4096   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4097     0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4098   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4099     0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4100   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4101     0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4102   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4103     0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4104   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4105     0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4106   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4107     0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4108   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4109     0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4110   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4111     0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4112   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4113     0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4114   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4115     0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4116   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4117     0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4118   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4119     0x08bd0000, 0x0fff0000, "pop%c\t%m"},
4120   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4121     0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
4122   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4123     0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4124
4125   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4126     0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
4127   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4128     0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
4129
4130   /* The rest.  */
4131   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
4132     0x03200000, 0x0fff00ff, "nop%c\t{%{I:%0-7d%}}" UNPREDICTABLE_INSTRUCTION},
4133   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4134     0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
4135   {ARM_FEATURE_CORE_LOW (0),
4136     0x00000000, 0x00000000, 0}
4137 };
4138
4139 /* print_insn_thumb16 recognizes the following format control codes:
4140
4141    %S                   print Thumb register (bits 3..5 as high number if bit 6 set)
4142    %D                   print Thumb register (bits 0..2 as high number if bit 7 set)
4143    %<bitfield>I         print bitfield as a signed decimal
4144                                 (top bit of range being the sign bit)
4145    %N                   print Thumb register mask (with LR)
4146    %O                   print Thumb register mask (with PC)
4147    %M                   print Thumb register mask
4148    %b                   print CZB's 6-bit unsigned branch destination
4149    %s                   print Thumb right-shift immediate (6..10; 0 == 32).
4150    %c                   print the condition code
4151    %C                   print the condition code, or "s" if not conditional
4152    %x                   print warning if conditional an not at end of IT block"
4153    %X                   print "\t@ unpredictable <IT:code>" if conditional
4154    %I                   print IT instruction suffix and operands
4155    %W                   print Thumb Writeback indicator for LDMIA
4156    %<bitfield>r         print bitfield as an ARM register
4157    %<bitfield>d         print bitfield as a decimal
4158    %<bitfield>H         print (bitfield * 2) as a decimal
4159    %<bitfield>W         print (bitfield * 4) as a decimal
4160    %<bitfield>a         print (bitfield * 4) as a pc-rel offset + decoded symbol
4161    %<bitfield>B         print Thumb branch destination (signed displacement)
4162    %<bitfield>c         print bitfield as a condition code
4163    %<bitnum>'c          print specified char iff bit is one
4164    %<bitnum>?ab         print a if bit is one else print b.  */
4165
4166 static const struct opcode16 thumb_opcodes[] =
4167 {
4168   /* Thumb instructions.  */
4169
4170   /* ARMv8-M Security Extensions instructions.  */
4171   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
4172   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
4173
4174   /* ARM V8 instructions.  */
4175   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),  0xbf50, 0xffff, "sevl%c"},
4176   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),  0xba80, 0xffc0, "hlt\t%0-5x"},
4177   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),  0xb610, 0xfff7, "setpan\t%{I:#%3-3d%}"},
4178
4179   /* ARM V6K no-argument instructions.  */
4180   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
4181   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
4182   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
4183   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
4184   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
4185   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
4186
4187   /* ARM V6T2 instructions.  */
4188   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4189     0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
4190   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4191     0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
4192   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
4193
4194   /* ARM V6.  */
4195   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%{B:%2'a%1'i%0'f%}%X"},
4196   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%{B:%2'a%1'i%0'f%}%X"},
4197   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
4198   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
4199   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
4200   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
4201   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%{B:%3?ble%}%X"},
4202   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
4203   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
4204   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
4205   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
4206
4207   /* ARM V5 ISA extends Thumb.  */
4208   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4209     0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional.  */
4210   /* This is BLX(2).  BLX(1) is a 32-bit instruction.  */
4211   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4212     0x4780, 0xff87, "blx%c\t%3-6r%x"},  /* note: 4 bit register number.  */
4213   /* ARM V4T ISA (Thumb v1).  */
4214   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4215     0x46C0, 0xFFFF, "nop%c\t\t\t@ (mov r8, r8)"},
4216   /* Format 4.  */
4217   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
4218   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
4219   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
4220   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
4221   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
4222   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
4223   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
4224   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
4225   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
4226   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
4227   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
4228   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
4229   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
4230   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
4231   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
4232   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
4233   /* format 13 */
4234   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\t%{R:sp%}, %{I:#%0-6W%}"},
4235   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\t%{R:sp%}, %{I:#%0-6W%}"},
4236   /* format 5 */
4237   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
4238   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
4239   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
4240   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
4241   /* format 14 */
4242   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
4243   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
4244   /* format 2 */
4245   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4246     0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
4247   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4248     0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
4249   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4250     0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, %{I:#%6-8d%}"},
4251   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4252     0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, %{I:#%6-8d%}"},
4253   /* format 8 */
4254   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4255     0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
4256   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4257     0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
4258   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4259     0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
4260   /* format 7 */
4261   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4262     0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4263   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4264     0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4265   /* format 1 */
4266   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
4267   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4268     0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, %{I:#%6-10d%}"},
4269   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
4270   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
4271   /* format 3 */
4272   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, %{I:#%0-7d%}"},
4273   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, %{I:#%0-7d%}"},
4274   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, %{I:#%0-7d%}"},
4275   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, %{I:#%0-7d%}"},
4276   /* format 6 */
4277   /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
4278   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4279     0x4800, 0xF800,
4280     "ldr%c\t%8-10r, [%{R:pc%}, %{I:#%0-7W%}]\t@ (%0-7a)"},
4281   /* format 9 */
4282   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4283     0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, %{I:#%6-10W%}]"},
4284   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4285     0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, %{I:#%6-10W%}]"},
4286   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4287     0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, %{I:#%6-10d%}]"},
4288   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4289     0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, %{I:#%6-10d%}]"},
4290   /* format 10 */
4291   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4292     0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, %{I:#%6-10H%}]"},
4293   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4294     0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, %{I:#%6-10H%}]"},
4295   /* format 11 */
4296   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4297     0x9000, 0xF800, "str%c\t%8-10r, [%{R:sp%}, %{I:#%0-7W%}]"},
4298   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4299     0x9800, 0xF800, "ldr%c\t%8-10r, [%{R:sp%}, %{I:#%0-7W%}]"},
4300   /* format 12 */
4301   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4302     0xA000, 0xF800, "add%c\t%8-10r, %{R:pc%}, %{I:#%0-7W%}\t@ (adr %8-10r, %0-7a)"},
4303   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4304     0xA800, 0xF800, "add%c\t%8-10r, %{R:sp%}, %{I:#%0-7W%}"},
4305   /* format 15 */
4306   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
4307   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
4308   /* format 17 */
4309   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
4310   /* format 16 */
4311   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t%{I:#%0-7d%}"},
4312   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
4313   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
4314   /* format 18 */
4315   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
4316
4317   /* The E800 .. FFFF range is unconditionally redirected to the
4318      32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
4319      are processed via that table.  Thus, we can never encounter a
4320      bare "second half of BL/BLX(1)" instruction here.  */
4321   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),  0x0000, 0x0000, UNDEFINED_INSTRUCTION},
4322   {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
4323 };
4324
4325 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
4326    We adopt the convention that hw1 is the high 16 bits of .value and
4327    .mask, hw2 the low 16 bits.
4328
4329    print_insn_thumb32 recognizes the following format control codes:
4330
4331        %%               %
4332
4333        %I               print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
4334        %M               print a modified 12-bit immediate (same location)
4335        %J               print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
4336        %K               print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
4337        %H               print a 16-bit immediate from hw2[3:0],hw1[11:0]
4338        %S               print a possibly-shifted Rm
4339
4340        %L               print address for a ldrd/strd instruction
4341        %a               print the address of a plain load/store
4342        %w               print the width and signedness of a core load/store
4343        %m               print register mask for ldm/stm
4344        %n               print register mask for clrm
4345
4346        %E               print the lsb and width fields of a bfc/bfi instruction
4347        %F               print the lsb and width fields of a sbfx/ubfx instruction
4348        %G               print a fallback offset for Branch Future instructions
4349        %W               print an offset for BF instruction
4350        %Y               print an offset for BFL instruction
4351        %Z               print an offset for BFCSEL instruction
4352        %Q               print an offset for Low Overhead Loop instructions
4353        %P               print an offset for Low Overhead Loop end instructions
4354        %b               print a conditional branch offset
4355        %B               print an unconditional branch offset
4356        %s               print the shift field of an SSAT instruction
4357        %R               print the rotation field of an SXT instruction
4358        %U               print barrier type.
4359        %P               print address for pli instruction.
4360        %c               print the condition code
4361        %x               print warning if conditional an not at end of IT block"
4362        %X               print "\t@ unpredictable <IT:code>" if conditional
4363
4364        %<bitfield>d     print bitfield in decimal
4365        %<bitfield>D     print bitfield plus one in decimal
4366        %<bitfield>W     print bitfield*4 in decimal
4367        %<bitfield>r     print bitfield as an ARM register
4368        %<bitfield>R     as %<>r but r15 is UNPREDICTABLE
4369        %<bitfield>S     as %<>r but r13 and r15 is UNPREDICTABLE
4370        %<bitfield>c     print bitfield as a condition code
4371
4372        %<bitfield>'c    print specified char iff bitfield is all ones
4373        %<bitfield>`c    print specified char iff bitfield is all zeroes
4374        %<bitfield>?ab... select from array of values in big endian order
4375
4376    With one exception at the bottom (done because BL and BLX(1) need
4377    to come dead last), this table was machine-sorted first in
4378    decreasing order of number of bits set in the mask, then in
4379    increasing numeric order of mask, then in increasing numeric order
4380    of opcode.  This order is not the clearest for a human reader, but
4381    is guaranteed never to catch a special-case bit pattern with a more
4382    general mask, which is important, because this instruction encoding
4383    makes heavy use of special-case bit patterns.  */
4384 static const struct opcode32 thumb32_opcodes[] =
4385 {
4386   /* Arm v8.1-M Mainline Pointer Authentication and Branch Target
4387      Identification Extension.  */
4388   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4389    0xf3af802d, 0xffffffff, "aut\t%{R:r12%}, %{R:lr%}, %{R:sp%}"},
4390   {ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI),
4391    0xfb500f00, 0xfff00ff0, "autg%c\t%12-15r, %16-19r, %0-3r"},
4392   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4393    0xf3af800f, 0xffffffff, "bti"},
4394   {ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI),
4395    0xfb500f10, 0xfff00ff0, "bxaut%c\t%12-15r, %16-19r, %0-3r"},
4396   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4397    0xf3af801d, 0xffffffff, "pac\t%{R:r12%}, %{R:lr%}, %{R:sp%}"},
4398   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4399    0xf3af800d, 0xffffffff, "pacbti\t%{R:r12%}, %{R:lr%}, %{R:sp%}"},
4400   {ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI),
4401    0xfb60f000, 0xfff0f0f0, "pacg%c\t%8-11r, %16-19r, %0-3r"},
4402
4403   /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
4404      instructions.  */
4405   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4406     0xf00fe001, 0xffffffff, "lctp%c"},
4407   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4408     0xf02fc001, 0xfffff001, "le\t%P"},
4409   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4410     0xf00fc001, 0xfffff001, "le\t%{R:lr%}, %P"},
4411   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4412     0xf01fc001, 0xfffff001, "letp\t%{R:lr%}, %P"},
4413   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4414     0xf040c001, 0xfff0f001, "wls\t%{R:lr%}, %16-19S, %Q"},
4415   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4416     0xf000c001, 0xffc0f001, "wlstp.%20-21s\t%{R:lr%}, %16-19S, %Q"},
4417   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4418     0xf040e001, 0xfff0ffff, "dls\t%{R:lr%}, %16-19S"},
4419   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4420     0xf000e001, 0xffc0ffff, "dlstp.%20-21s\t%{R:lr%}, %16-19S"},
4421
4422   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4423     0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
4424   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4425     0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
4426   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4427     0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
4428   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4429     0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
4430   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4431     0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %{B:%18-21c%}"},
4432
4433   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4434     0xe89f0000, 0xffff2000, "clrm%c\t%n"},
4435
4436   /* ARMv8-M and ARMv8-M Security Extensions instructions.  */
4437   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
4438   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4439     0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
4440   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4441     0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
4442   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4443     0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
4444   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4445     0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4446
4447   /* ARM V8.2 RAS extension instructions.  */
4448   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
4449     0xf3af8010, 0xffffffff, "esb"},
4450
4451   /* V8 instructions.  */
4452   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4453     0xf3af8005, 0xffffffff, "sevl%c.w"},
4454   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4455     0xf78f8000, 0xfffffffc, "dcps%0-1d"},
4456   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4457     0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
4458   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4459     0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
4460   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4461     0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
4462   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4463     0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
4464   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4465     0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
4466   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4467     0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
4468   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4469     0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
4470   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4471     0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4472   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4473     0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
4474   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4475     0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
4476   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4477     0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4478   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4479     0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4480   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4481     0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
4482   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4483     0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
4484
4485   /* V8-R instructions.  */
4486   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R),
4487     0xf3bf8f4c, 0xffffffff, "dfb%c"},
4488
4489   /* CRC32 instructions.  */
4490   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
4491     0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
4492   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
4493     0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
4494   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
4495     0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
4496   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
4497     0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
4498   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
4499     0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
4500   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
4501     0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
4502
4503   /* Speculation Barriers.  */
4504   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
4505   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
4506   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
4507
4508   /* V7 instructions.  */
4509   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
4510   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t%{I:#%0-3d%}"},
4511   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
4512   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
4513   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
4514   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
4515   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
4516   {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4517     0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
4518   {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4519     0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
4520
4521   /* Virtualization Extension instructions.  */
4522   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
4523   /* We skip ERET as that is SUBS pc, lr, #0.  */
4524
4525   /* MP Extension instructions.  */
4526   {ARM_FEATURE_CORE_LOW (ARM_EXT_MP),   0xf830f000, 0xff70f000, "pldw%c\t%a"},
4527
4528   /* Security extension instructions.  */
4529   {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),  0xf7f08000, 0xfff0f000, "smc%c\t%K"},
4530
4531   /* ARMv8.5-A instructions.  */
4532   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
4533
4534   /* Instructions defined in the basic V6T2 set.  */
4535   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
4536   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
4537   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
4538   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
4539   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
4540   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4541     0xf3af8000, 0xffffff00, "nop%c.w\t{%{I:%0-7d%}}"},
4542   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
4543
4544   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4545     0xf3bf8f2f, 0xffffffff, "clrex%c"},
4546   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4547     0xf3af8400, 0xffffff1f, "cpsie.w\t%{B:%7'a%6'i%5'f%}%X"},
4548   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4549     0xf3af8600, 0xffffff1f, "cpsid.w\t%{B:%7'a%6'i%5'f%}%X"},
4550   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4551     0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
4552   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4553     0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
4554   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4555     0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
4556   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4557     0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
4558   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4559     0xf3af8100, 0xffffffe0, "cps\t%{I:#%0-4d%}%X"},
4560   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4561     0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
4562   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4563     0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, %{B:lsl%} %{I:#1%}]%x"},
4564   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4565     0xf3af8500, 0xffffff00, "cpsie\t%{B:%7'a%6'i%5'f%}, %{I:#%0-4d%}%X"},
4566   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4567     0xf3af8700, 0xffffff00, "cpsid\t%{B:%7'a%6'i%5'f%}, %{I:#%0-4d%}%X"},
4568   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4569     0xf3de8f00, 0xffffff00, "subs%c\t%{R:pc%}, %{R:lr%}, %{I:#%0-7d%}"},
4570   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4571     0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
4572   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4573     0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
4574   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4575     0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
4576   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4577     0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, %{I:#%0-4d%}"},
4578   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4579     0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, %{I:#%0-4d%}"},
4580   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4581     0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
4582   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4583     0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
4584   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4585     0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
4586   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4587     0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
4588   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4589     0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
4590   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4591     0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
4592   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4593     0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
4594   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4595     0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
4596   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4597     0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
4598   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4599     0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
4600   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4601     0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
4602   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4603     0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
4604   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4605     0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
4606   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4607     0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
4608   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4609     0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
4610   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4611     0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
4612   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4613     0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
4614   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4615     0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
4616   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4617     0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
4618   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4619     0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
4620   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4621     0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
4622   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4623     0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
4624   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4625     0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
4626   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4627     0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
4628   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4629     0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
4630   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4631     0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
4632   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4633     0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
4634   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4635     0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
4636   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4637     0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
4638   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4639     0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
4640   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4641     0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
4642   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4643     0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
4644   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4645     0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
4646   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4647     0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
4648   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4649     0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
4650   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4651     0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
4652   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4653     0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
4654   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4655     0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
4656   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4657     0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
4658   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4659     0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
4660   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4661     0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
4662   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4663     0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
4664   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4665     0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
4666   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4667     0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
4668   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4669     0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
4670   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4671     0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
4672   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4673     0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
4674   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4675     0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
4676   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4677     0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
4678   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4679     0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
4680   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4681     0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
4682   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4683     0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
4684   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4685     0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
4686   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4687     0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
4688   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4689     0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
4690   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4691     0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
4692   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4693     0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4694   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4695     0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4696   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4697     0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4698   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4699     0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
4700   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4701     0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
4702   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4703     0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, %{I:#%0-4D%}, %16-19r"},
4704   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4705     0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, %{I:#%0-4d%}, %16-19r"},
4706   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4707     0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
4708   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4709     0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4710   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4711     0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
4712   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4713     0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
4714   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4715     0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4716   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4717     0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4718   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4719     0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4720   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4721     0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4722   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4723     0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4724   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4725     0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4726   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4727     0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4728   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4729     0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
4730   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4731     0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
4732   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4733     0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
4734   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4735     0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
4736   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4737     0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
4738   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4739     0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
4740   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4741     0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
4742   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4743     0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
4744   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4745     0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
4746   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4747     0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
4748   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4749     0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
4750   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4751     0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
4752   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4753     0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4754   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4755     0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4756   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4757     0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4758   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4759     0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4760   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4761     0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4762   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4763     0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4764   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4765     0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4766   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4767     0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4768   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4769     0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, %{I:#%0-7W%}]"},
4770   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4771     0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
4772   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4773     0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
4774   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4775     0xf810f000, 0xff70f000, "pld%c\t%a"},
4776   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4777     0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4778   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4779     0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4780   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4781     0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4782   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4783     0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4784   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4785     0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4786   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4787     0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4788   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4789     0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4790   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4791     0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
4792   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4793     0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
4794   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4795     0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
4796   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4797     0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
4798   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4799     0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
4800   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4801     0xfb100000, 0xfff000c0,
4802     "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4803   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4804     0xfbc00080, 0xfff000c0,
4805     "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
4806   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4807     0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
4808   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4809     0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
4810   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4811     0xf3000000, 0xffd08020, "ssat%c\t%8-11r, %{I:#%0-4D%}, %16-19r%s"},
4812   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4813     0xf3800000, 0xffd08020, "usat%c\t%8-11r, %{I:#%0-4d%}, %16-19r%s"},
4814   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4815     0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
4816   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4817     0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
4818   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4819     0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
4820   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4821     0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
4822   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4823     0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
4824   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4825     0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
4826   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4827     0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
4828   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4829     0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
4830   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4831     0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
4832   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4833     0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
4834   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4835     0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
4836   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4837     0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
4838   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4839     0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
4840   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4841     0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
4842   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4843     0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, %{I:#%0-7W%}]"},
4844   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4845     0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
4846   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4847     0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
4848   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4849     0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
4850   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4851     0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
4852   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4853     0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
4854   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4855     0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
4856   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4857     0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
4858   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4859     0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
4860   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4861     0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
4862   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4863     0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
4864   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4865     0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
4866   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4867     0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
4868   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4869     0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
4870   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4871     0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
4872   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4873     0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
4874   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4875     0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
4876   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4877     0xe9400000, 0xff500000,
4878     "strd%c\t%12-15r, %8-11r, [%16-19r, %{I:#%23`-%0-7W%}]%21'!%L"},
4879   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4880     0xe9500000, 0xff500000,
4881     "ldrd%c\t%12-15r, %8-11r, [%16-19r, %{I:#%23`-%0-7W%}]%21'!%L"},
4882   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4883     0xe8600000, 0xff700000,
4884     "strd%c\t%12-15r, %8-11r, [%16-19r], %{I:#%23`-%0-7W%}%L"},
4885   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4886     0xe8700000, 0xff700000,
4887     "ldrd%c\t%12-15r, %8-11r, [%16-19r], %{I:#%23`-%0-7W%}%L"},
4888   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4889     0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
4890   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4891     0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
4892
4893   /* Filter out Bcc with cond=E or F, which are used for other instructions.  */
4894   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4895     0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
4896   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4897     0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
4898   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4899     0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
4900   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4901     0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
4902
4903   /* These have been 32-bit since the invention of Thumb.  */
4904   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4905      0xf000c000, 0xf800d001, "blx%c\t%B%x"},
4906   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4907      0xf000d000, 0xf800d000, "bl%c\t%B%x"},
4908
4909   /* Fallback.  */
4910   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4911       0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
4912   {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
4913 };
4914
4915 static const char *const arm_conditional[] =
4916 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
4917  "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
4918
4919 static const char *const arm_shift[] =
4920 {"lsl", "lsr", "asr", "ror"};
4921
4922 typedef struct
4923 {
4924   const char *name;
4925   const char *description;
4926   const char *reg_names[16];
4927 }
4928 arm_regname;
4929
4930 static const arm_regname regnames[] =
4931 {
4932   { "reg-names-raw", N_("Select raw register names"),
4933     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
4934   { "reg-names-gcc", N_("Select register names used by GCC"),
4935     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl",  "fp",  "ip",  "sp",  "lr",  "pc" }},
4936   { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
4937     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp",  "lr",  "pc" }},
4938   { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
4939   { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
4940   { "reg-names-apcs", N_("Select register names used in the APCS"),
4941     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl",  "fp",  "ip",  "sp",  "lr",  "pc" }},
4942   { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
4943     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7",  "v8",  "IP",  "SP",  "LR",  "PC" }},
4944   { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
4945     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL",  "FP",  "IP",  "SP",  "LR",  "PC" }},
4946   { "coproc<N>=(cde|generic)", N_("Enable CDE extensions for coprocessor N space"), { NULL } }
4947 };
4948
4949 static const char *const iwmmxt_wwnames[] =
4950 {"b", "h", "w", "d"};
4951
4952 static const char *const iwmmxt_wwssnames[] =
4953 {"b", "bus", "bc", "bss",
4954  "h", "hus", "hc", "hss",
4955  "w", "wus", "wc", "wss",
4956  "d", "dus", "dc", "dss"
4957 };
4958
4959 static const char *const iwmmxt_regnames[] =
4960 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
4961   "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
4962 };
4963
4964 static const char *const iwmmxt_cregnames[] =
4965 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
4966   "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
4967 };
4968
4969 static const char *const vec_condnames[] =
4970 { "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
4971 };
4972
4973 static const char *const mve_predicatenames[] =
4974 { "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
4975   "eee", "ee", "eet", "e", "ett", "et", "ete"
4976 };
4977
4978 /* Names for 2-bit size field for mve vector isntructions.  */
4979 static const char *const mve_vec_sizename[] =
4980   { "8", "16", "32", "64"};
4981
4982 /* Indicates whether we are processing a then predicate,
4983    else predicate or none at all.  */
4984 enum vpt_pred_state
4985 {
4986   PRED_NONE,
4987   PRED_THEN,
4988   PRED_ELSE
4989 };
4990
4991 /* Information used to process a vpt block and subsequent instructions.  */
4992 struct vpt_block
4993 {
4994   /* Are we in a vpt block.  */
4995   bool in_vpt_block;
4996
4997   /* Next predicate state if in vpt block.  */
4998   enum vpt_pred_state next_pred_state;
4999
5000   /* Mask from vpt/vpst instruction.  */
5001   long predicate_mask;
5002
5003   /* Instruction number in vpt block.  */
5004   long current_insn_num;
5005
5006   /* Number of instructions in vpt block..   */
5007   long num_pred_insn;
5008 };
5009
5010 static struct vpt_block vpt_block_state =
5011 {
5012   false,
5013   PRED_NONE,
5014   0,
5015   0,
5016   0
5017 };
5018
5019 /* Default to GCC register name set.  */
5020 static unsigned int regname_selected = 1;
5021
5022 #define NUM_ARM_OPTIONS   ARRAY_SIZE (regnames)
5023 #define arm_regnames      regnames[regname_selected].reg_names
5024
5025 static bool force_thumb = false;
5026 static uint16_t cde_coprocs = 0;
5027
5028 /* Current IT instruction state.  This contains the same state as the IT
5029    bits in the CPSR.  */
5030 static unsigned int ifthen_state;
5031 /* IT state for the next instruction.  */
5032 static unsigned int ifthen_next_state;
5033 /* The address of the insn for which the IT state is valid.  */
5034 static bfd_vma ifthen_address;
5035 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
5036 /* Indicates that the current Conditional state is unconditional or outside
5037    an IT block.  */
5038 #define COND_UNCOND 16
5039
5040 \f
5041 /* Functions.  */
5042 /* Extract the predicate mask for a VPT or VPST instruction.
5043    The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh).  */
5044
5045 static long
5046 mve_extract_pred_mask (long given)
5047 {
5048   return ((given & 0x00400000) >> 19) | ((given & 0xe000) >> 13);
5049 }
5050
5051 /* Return the number of instructions in a MVE predicate block.  */
5052 static long
5053 num_instructions_vpt_block (long given)
5054 {
5055   long mask = mve_extract_pred_mask (given);
5056   if (mask == 0)
5057     return 0;
5058
5059   if (mask == 8)
5060     return 1;
5061
5062   if ((mask & 7) == 4)
5063     return 2;
5064
5065   if ((mask & 3) == 2)
5066     return 3;
5067
5068   if ((mask & 1) == 1)
5069     return 4;
5070
5071   return 0;
5072 }
5073
5074 static void
5075 mark_outside_vpt_block (void)
5076 {
5077   vpt_block_state.in_vpt_block = false;
5078   vpt_block_state.next_pred_state = PRED_NONE;
5079   vpt_block_state.predicate_mask = 0;
5080   vpt_block_state.current_insn_num = 0;
5081   vpt_block_state.num_pred_insn = 0;
5082 }
5083
5084 static void
5085 mark_inside_vpt_block (long given)
5086 {
5087   vpt_block_state.in_vpt_block = true;
5088   vpt_block_state.next_pred_state = PRED_THEN;
5089   vpt_block_state.predicate_mask = mve_extract_pred_mask (given);
5090   vpt_block_state.current_insn_num = 0;
5091   vpt_block_state.num_pred_insn = num_instructions_vpt_block (given);
5092   assert (vpt_block_state.num_pred_insn >= 1);
5093 }
5094
5095 static enum vpt_pred_state
5096 invert_next_predicate_state (enum vpt_pred_state astate)
5097 {
5098   if (astate == PRED_THEN)
5099     return PRED_ELSE;
5100   else if (astate == PRED_ELSE)
5101     return PRED_THEN;
5102   else
5103     return PRED_NONE;
5104 }
5105
5106 static enum vpt_pred_state
5107 update_next_predicate_state (void)
5108 {
5109   long pred_mask = vpt_block_state.predicate_mask;
5110   long mask_for_insn = 0;
5111
5112   switch (vpt_block_state.current_insn_num)
5113     {
5114     case 1:
5115       mask_for_insn = 8;
5116       break;
5117
5118     case 2:
5119       mask_for_insn = 4;
5120       break;
5121
5122     case 3:
5123       mask_for_insn = 2;
5124       break;
5125
5126     case 4:
5127       return PRED_NONE;
5128     }
5129
5130   if (pred_mask & mask_for_insn)
5131     return invert_next_predicate_state (vpt_block_state.next_pred_state);
5132   else
5133     return vpt_block_state.next_pred_state;
5134 }
5135
5136 static void
5137 update_vpt_block_state (void)
5138 {
5139   vpt_block_state.current_insn_num++;
5140   if (vpt_block_state.current_insn_num == vpt_block_state.num_pred_insn)
5141     {
5142       /* No more instructions to process in vpt block.  */
5143       mark_outside_vpt_block ();
5144       return;
5145     }
5146
5147   vpt_block_state.next_pred_state = update_next_predicate_state ();
5148 }
5149
5150 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
5151    Returns pointer to following character of the format string and
5152    fills in *VALUEP and *WIDTHP with the extracted value and number of
5153    bits extracted.  WIDTHP can be NULL.  */
5154
5155 static const char *
5156 arm_decode_bitfield (const char *ptr,
5157                      unsigned long insn,
5158                      unsigned long *valuep,
5159                      int *widthp)
5160 {
5161   unsigned long value = 0;
5162   int width = 0;
5163
5164   do
5165     {
5166       int start, end;
5167       int bits;
5168
5169       for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
5170         start = start * 10 + *ptr - '0';
5171       if (*ptr == '-')
5172         for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
5173           end = end * 10 + *ptr - '0';
5174       else
5175         end = start;
5176       bits = end - start;
5177       if (bits < 0)
5178         abort ();
5179       value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
5180       width += bits + 1;
5181     }
5182   while (*ptr++ == ',');
5183   *valuep = value;
5184   if (widthp)
5185     *widthp = width;
5186   return ptr - 1;
5187 }
5188
5189 static void
5190 arm_decode_shift (long given, fprintf_styled_ftype func, void *stream,
5191                   bool print_shift)
5192 {
5193   func (stream, dis_style_register, "%s", arm_regnames[given & 0xf]);
5194
5195   if ((given & 0xff0) != 0)
5196     {
5197       if ((given & 0x10) == 0)
5198         {
5199           int amount = (given & 0xf80) >> 7;
5200           int shift = (given & 0x60) >> 5;
5201
5202           if (amount == 0)
5203             {
5204               if (shift == 3)
5205                 {
5206                   func (stream, dis_style_text, ", ");
5207                   func (stream, dis_style_sub_mnemonic, "rrx");
5208                   return;
5209                 }
5210
5211               amount = 32;
5212             }
5213
5214           if (print_shift)
5215             {
5216               func (stream, dis_style_text, ", ");
5217               func (stream, dis_style_sub_mnemonic, "%s ", arm_shift[shift]);
5218               func (stream, dis_style_immediate, "#%d", amount);
5219             }
5220           else
5221             {
5222               func (stream, dis_style_text, ", ");
5223               func (stream, dis_style_immediate, "#%d", amount);
5224             }
5225         }
5226       else if ((given & 0x80) == 0x80)
5227         func (stream, dis_style_comment_start,
5228               "\t@ <illegal shifter operand>");
5229       else if (print_shift)
5230         {
5231           func (stream, dis_style_text, ", ");
5232           func (stream, dis_style_sub_mnemonic, "%s ",
5233                 arm_shift[(given & 0x60) >> 5]);
5234           func (stream, dis_style_register, "%s",
5235                 arm_regnames[(given & 0xf00) >> 8]);
5236         }
5237       else
5238         {
5239           func (stream, dis_style_text, ", ");
5240           func (stream, dis_style_register, "%s",
5241                 arm_regnames[(given & 0xf00) >> 8]);
5242         }
5243     }
5244 }
5245
5246 /* Return TRUE if the MATCHED_INSN can be inside an IT block.  */
5247
5248 static bool
5249 is_mve_okay_in_it (enum mve_instructions matched_insn)
5250 {
5251   switch (matched_insn)
5252     {
5253     case MVE_VMOV_GP_TO_VEC_LANE:
5254     case MVE_VMOV2_VEC_LANE_TO_GP:
5255     case MVE_VMOV2_GP_TO_VEC_LANE:
5256     case MVE_VMOV_VEC_LANE_TO_GP:
5257     case MVE_LSLL:
5258     case MVE_LSLLI:
5259     case MVE_LSRL:
5260     case MVE_ASRL:
5261     case MVE_ASRLI:
5262     case MVE_SQRSHRL:
5263     case MVE_SQRSHR:
5264     case MVE_UQRSHL:
5265     case MVE_UQRSHLL:
5266     case MVE_UQSHL:
5267     case MVE_UQSHLL:
5268     case MVE_URSHRL:
5269     case MVE_URSHR:
5270     case MVE_SRSHRL:
5271     case MVE_SRSHR:
5272     case MVE_SQSHLL:
5273     case MVE_SQSHL:
5274       return true;
5275     default:
5276       return false;
5277     }
5278 }
5279
5280 static bool
5281 is_mve_architecture (struct disassemble_info *info)
5282 {
5283   struct arm_private_data *private_data = info->private_data;
5284   arm_feature_set allowed_arches = private_data->features;
5285
5286   arm_feature_set arm_ext_v8_1m_main
5287     = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
5288
5289   if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
5290       && !ARM_CPU_IS_ANY (allowed_arches))
5291     return true;
5292   else
5293     return false;
5294 }
5295
5296 static bool
5297 is_vpt_instruction (long given)
5298 {
5299
5300   /* If mkh:mkl is '0000' then its not a vpt/vpst instruction.  */
5301   if ((given & 0x0040e000) == 0)
5302     return false;
5303
5304   /* VPT floating point T1 variant.  */
5305   if (((given & 0xefb10f50) == 0xee310f00 && ((given & 0x1001) != 0x1))
5306   /* VPT floating point T2 variant.  */
5307       || ((given & 0xefb10f50) == 0xee310f40)
5308   /* VPT vector T1 variant.  */
5309       || ((given & 0xff811f51) == 0xfe010f00)
5310   /* VPT vector T2 variant.  */
5311       || ((given & 0xff811f51) == 0xfe010f01
5312           && ((given & 0x300000) != 0x300000))
5313   /* VPT vector T3 variant.  */
5314       || ((given & 0xff811f50) == 0xfe011f00)
5315   /* VPT vector T4 variant.  */
5316       || ((given & 0xff811f70) == 0xfe010f40)
5317   /* VPT vector T5 variant.  */
5318       || ((given & 0xff811f70) == 0xfe010f60)
5319   /* VPT vector T6 variant.  */
5320       || ((given & 0xff811f50) == 0xfe011f40)
5321   /* VPST vector T variant.  */
5322       || ((given & 0xffbf1fff) == 0xfe310f4d))
5323     return true;
5324   else
5325     return false;
5326 }
5327
5328 /* Decode a bitfield from opcode GIVEN, with starting bitfield = START
5329    and ending bitfield = END.  END must be greater than START.  */
5330
5331 static unsigned long
5332 arm_decode_field (unsigned long given, unsigned int start, unsigned int end)
5333 {
5334   int bits = end - start;
5335
5336   if (bits < 0)
5337     abort ();
5338
5339   return ((given >> start) & ((2ul << bits) - 1));
5340 }
5341
5342 /* Decode a bitfield from opcode GIVEN, with multiple bitfields:
5343    START:END and START2:END2.  END/END2 must be greater than
5344    START/START2.  */
5345
5346 static unsigned long
5347 arm_decode_field_multiple (unsigned long given, unsigned int start,
5348                            unsigned int end, unsigned int start2,
5349                            unsigned int end2)
5350 {
5351   int bits = end - start;
5352   int bits2 = end2 - start2;
5353   unsigned long value = 0;
5354   int width = 0;
5355
5356   if (bits2 < 0)
5357     abort ();
5358
5359   value = arm_decode_field (given, start, end);
5360   width += bits + 1;
5361
5362   value |= ((given >> start2) & ((2ul << bits2) - 1)) << width;
5363   return value;
5364 }
5365
5366 /* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
5367    This helps us decode instructions that change mnemonic depending on specific
5368    operand values/encodings.  */
5369
5370 static bool
5371 is_mve_encoding_conflict (unsigned long given,
5372                           enum mve_instructions matched_insn)
5373 {
5374   switch (matched_insn)
5375     {
5376     case MVE_VPST:
5377       if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5378         return true;
5379       else
5380         return false;
5381
5382     case MVE_VPT_FP_T1:
5383       if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5384         return true;
5385       if ((arm_decode_field (given, 12, 12) == 0)
5386           && (arm_decode_field (given, 0, 0) == 1))
5387         return true;
5388       return false;
5389
5390     case MVE_VPT_FP_T2:
5391       if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5392         return true;
5393       if (arm_decode_field (given, 0, 3) == 0xd)
5394         return true;
5395       return false;
5396
5397     case MVE_VPT_VEC_T1:
5398     case MVE_VPT_VEC_T2:
5399     case MVE_VPT_VEC_T3:
5400     case MVE_VPT_VEC_T4:
5401     case MVE_VPT_VEC_T5:
5402     case MVE_VPT_VEC_T6:
5403       if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5404         return true;
5405       if (arm_decode_field (given, 20, 21) == 3)
5406         return true;
5407       return false;
5408
5409     case MVE_VCMP_FP_T1:
5410       if ((arm_decode_field (given, 12, 12) == 0)
5411           && (arm_decode_field (given, 0, 0) == 1))
5412         return true;
5413       else
5414         return false;
5415
5416     case MVE_VCMP_FP_T2:
5417       if (arm_decode_field (given, 0, 3) == 0xd)
5418         return true;
5419       else
5420         return false;
5421
5422     case MVE_VQADD_T2:
5423     case MVE_VQSUB_T2:
5424     case MVE_VMUL_VEC_T2:
5425     case MVE_VMULH:
5426     case MVE_VRMULH:
5427     case MVE_VMLA:
5428     case MVE_VMAX:
5429     case MVE_VMIN:
5430     case MVE_VBRSR:
5431     case MVE_VADD_VEC_T2:
5432     case MVE_VSUB_VEC_T2:
5433     case MVE_VABAV:
5434     case MVE_VQRSHL_T1:
5435     case MVE_VQSHL_T4:
5436     case MVE_VRSHL_T1:
5437     case MVE_VSHL_T3:
5438     case MVE_VCADD_VEC:
5439     case MVE_VHCADD:
5440     case MVE_VDDUP:
5441     case MVE_VIDUP:
5442     case MVE_VQRDMLADH:
5443     case MVE_VQDMLAH:
5444     case MVE_VQRDMLAH:
5445     case MVE_VQDMLASH:
5446     case MVE_VQRDMLASH:
5447     case MVE_VQDMLSDH:
5448     case MVE_VQRDMLSDH:
5449     case MVE_VQDMULH_T3:
5450     case MVE_VQRDMULH_T4:
5451     case MVE_VQDMLADH:
5452     case MVE_VMLAS:
5453     case MVE_VMULL_INT:
5454     case MVE_VHADD_T2:
5455     case MVE_VHSUB_T2:
5456     case MVE_VCMP_VEC_T1:
5457     case MVE_VCMP_VEC_T2:
5458     case MVE_VCMP_VEC_T3:
5459     case MVE_VCMP_VEC_T4:
5460     case MVE_VCMP_VEC_T5:
5461     case MVE_VCMP_VEC_T6:
5462       if (arm_decode_field (given, 20, 21) == 3)
5463         return true;
5464       else
5465         return false;
5466
5467     case MVE_VLD2:
5468     case MVE_VLD4:
5469     case MVE_VST2:
5470     case MVE_VST4:
5471       if (arm_decode_field (given, 7, 8) == 3)
5472         return true;
5473       else
5474         return false;
5475
5476     case MVE_VSTRB_T1:
5477     case MVE_VSTRH_T2:
5478       if ((arm_decode_field (given, 24, 24) == 0)
5479           && (arm_decode_field (given, 21, 21) == 0))
5480         {
5481             return true;
5482         }
5483       else if ((arm_decode_field (given, 7, 8) == 3))
5484         return true;
5485       else
5486         return false;
5487
5488     case MVE_VLDRB_T1:
5489     case MVE_VLDRH_T2:
5490     case MVE_VLDRW_T7:
5491     case MVE_VSTRB_T5:
5492     case MVE_VSTRH_T6:
5493     case MVE_VSTRW_T7:
5494       if ((arm_decode_field (given, 24, 24) == 0)
5495           && (arm_decode_field (given, 21, 21) == 0))
5496         {
5497             return true;
5498         }
5499       else
5500         return false;
5501
5502     case MVE_VCVT_FP_FIX_VEC:
5503       return (arm_decode_field (given, 16, 21) & 0x38) == 0;
5504
5505     case MVE_VBIC_IMM:
5506     case MVE_VORR_IMM:
5507       {
5508         unsigned long cmode = arm_decode_field (given, 8, 11);
5509
5510         if ((cmode & 1) == 0)
5511           return true;
5512         else if ((cmode & 0xc) == 0xc)
5513           return true;
5514         else
5515           return false;
5516       }
5517
5518     case MVE_VMVN_IMM:
5519       {
5520         unsigned long cmode = arm_decode_field (given, 8, 11);
5521
5522         if (cmode == 0xe)
5523           return true;
5524         else if ((cmode & 0x9) == 1)
5525           return true;
5526         else if ((cmode & 0xd) == 9)
5527           return true;
5528         else
5529           return false;
5530       }
5531
5532     case MVE_VMOV_IMM_TO_VEC:
5533       if ((arm_decode_field (given, 5, 5) == 1)
5534           && (arm_decode_field (given, 8, 11) != 0xe))
5535         return true;
5536       else
5537         return false;
5538
5539     case MVE_VMOVL:
5540       {
5541         unsigned long size = arm_decode_field (given, 19, 20);
5542         if ((size == 0) || (size == 3))
5543           return true;
5544         else
5545           return false;
5546       }
5547
5548     case MVE_VMAXA:
5549     case MVE_VMINA:
5550     case MVE_VMAXV:
5551     case MVE_VMAXAV:
5552     case MVE_VMINV:
5553     case MVE_VMINAV:
5554     case MVE_VQRSHL_T2:
5555     case MVE_VQSHL_T1:
5556     case MVE_VRSHL_T2:
5557     case MVE_VSHL_T2:
5558     case MVE_VSHLL_T2:
5559     case MVE_VADDV:
5560     case MVE_VMOVN:
5561     case MVE_VQMOVUN:
5562     case MVE_VQMOVN:
5563       if (arm_decode_field (given, 18, 19) == 3)
5564         return true;
5565       else
5566         return false;
5567
5568     case MVE_VMLSLDAV:
5569     case MVE_VRMLSLDAVH:
5570     case MVE_VMLALDAV:
5571     case MVE_VADDLV:
5572       if (arm_decode_field (given, 20, 22) == 7)
5573         return true;
5574       else
5575         return false;
5576
5577     case MVE_VRMLALDAVH:
5578       if ((arm_decode_field (given, 20, 22) & 6) == 6)
5579         return true;
5580       else
5581         return false;
5582
5583     case MVE_VDWDUP:
5584     case MVE_VIWDUP:
5585       if ((arm_decode_field (given, 20, 21) == 3)
5586           || (arm_decode_field (given, 1, 3) == 7))
5587         return true;
5588       else
5589         return false;
5590
5591
5592     case MVE_VSHLL_T1:
5593       if (arm_decode_field (given, 16, 18) == 0)
5594         {
5595           unsigned long sz = arm_decode_field (given, 19, 20);
5596
5597           if ((sz == 1) || (sz == 2))
5598             return true;
5599           else
5600             return false;
5601         }
5602       else
5603         return false;
5604
5605     case MVE_VQSHL_T2:
5606     case MVE_VQSHLU_T3:
5607     case MVE_VRSHR:
5608     case MVE_VSHL_T1:
5609     case MVE_VSHR:
5610     case MVE_VSLI:
5611     case MVE_VSRI:
5612       if (arm_decode_field (given, 19, 21) == 0)
5613         return true;
5614       else
5615         return false;
5616
5617     case MVE_VCTP:
5618     if (arm_decode_field (given, 16, 19) == 0xf)
5619       return true;
5620     else
5621       return false;
5622
5623     case MVE_ASRLI:
5624     case MVE_ASRL:
5625     case MVE_LSLLI:
5626     case MVE_LSLL:
5627     case MVE_LSRL:
5628     case MVE_SQRSHRL:
5629     case MVE_SQSHLL:
5630     case MVE_SRSHRL:
5631     case MVE_UQRSHLL:
5632     case MVE_UQSHLL:
5633     case MVE_URSHRL:
5634       if (arm_decode_field (given, 9, 11) == 0x7)
5635         return true;
5636       else
5637         return false;
5638
5639     case MVE_CSINC:
5640     case MVE_CSINV:
5641       {
5642         unsigned long rm, rn;
5643         rm = arm_decode_field (given, 0, 3);
5644         rn = arm_decode_field (given, 16, 19);
5645         /* CSET/CSETM.  */
5646         if (rm == 0xf && rn == 0xf)
5647           return true;
5648         /* CINC/CINV.  */
5649         else if (rn == rm && rn != 0xf)
5650           return true;
5651       }
5652     /* Fall through.  */
5653     case MVE_CSEL:
5654     case MVE_CSNEG:
5655       if (arm_decode_field (given, 0, 3) == 0xd)
5656         return true;
5657       /* CNEG.  */
5658       else if (matched_insn == MVE_CSNEG)
5659         if (arm_decode_field (given, 0, 3) == arm_decode_field (given, 16, 19))
5660           return true;
5661       return false;
5662
5663     default:
5664     case MVE_VADD_FP_T1:
5665     case MVE_VADD_FP_T2:
5666     case MVE_VADD_VEC_T1:
5667       return false;
5668
5669     }
5670 }
5671
5672 static void
5673 print_mve_vld_str_addr (struct disassemble_info *info,
5674                         unsigned long given,
5675                         enum mve_instructions matched_insn)
5676 {
5677   void *stream = info->stream;
5678   fprintf_styled_ftype func = info->fprintf_styled_func;
5679
5680   unsigned long p, w, gpr, imm, add, mod_imm;
5681
5682   imm = arm_decode_field (given, 0, 6);
5683   mod_imm = imm;
5684
5685   switch (matched_insn)
5686     {
5687     case MVE_VLDRB_T1:
5688     case MVE_VSTRB_T1:
5689       gpr = arm_decode_field (given, 16, 18);
5690       break;
5691
5692     case MVE_VLDRH_T2:
5693     case MVE_VSTRH_T2:
5694       gpr = arm_decode_field (given, 16, 18);
5695       mod_imm = imm << 1;
5696       break;
5697
5698     case MVE_VLDRH_T6:
5699     case MVE_VSTRH_T6:
5700       gpr = arm_decode_field (given, 16, 19);
5701       mod_imm = imm << 1;
5702       break;
5703
5704     case MVE_VLDRW_T7:
5705     case MVE_VSTRW_T7:
5706       gpr = arm_decode_field (given, 16, 19);
5707       mod_imm = imm << 2;
5708       break;
5709
5710     case MVE_VLDRB_T5:
5711     case MVE_VSTRB_T5:
5712       gpr = arm_decode_field (given, 16, 19);
5713       break;
5714
5715     default:
5716       return;
5717     }
5718
5719   p = arm_decode_field (given, 24, 24);
5720   w = arm_decode_field (given, 21, 21);
5721
5722   add = arm_decode_field (given, 23, 23);
5723
5724   char * add_sub;
5725
5726   /* Don't print anything for '+' as it is implied.  */
5727   if (add == 1)
5728     add_sub = "";
5729   else
5730     add_sub = "-";
5731
5732   func (stream, dis_style_text, "[");
5733   func (stream, dis_style_register, "%s", arm_regnames[gpr]);
5734   if (p == 1)
5735     {
5736       func (stream, dis_style_text, ", ");
5737       func (stream, dis_style_immediate, "#%s%lu", add_sub, mod_imm);
5738       /* Offset mode.  */
5739       if (w == 0)
5740         func (stream, dis_style_text, "]");
5741       /* Pre-indexed mode.  */
5742       else
5743         func (stream, dis_style_text, "]!");
5744     }
5745   else if ((p == 0) && (w == 1))
5746     {
5747       /* Post-index mode.  */
5748       func (stream, dis_style_text, "], ");
5749       func (stream, dis_style_immediate, "#%s%lu", add_sub, mod_imm);
5750     }
5751 }
5752
5753 /* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
5754    Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
5755    this encoding is undefined.  */
5756
5757 static bool
5758 is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
5759                   enum mve_undefined *undefined_code)
5760 {
5761   *undefined_code = UNDEF_NONE;
5762
5763   switch (matched_insn)
5764     {
5765     case MVE_VDUP:
5766       if (arm_decode_field_multiple (given, 5, 5, 22, 22) == 3)
5767         {
5768           *undefined_code = UNDEF_SIZE_3;
5769           return true;
5770         }
5771       else
5772         return false;
5773
5774     case MVE_VQADD_T1:
5775     case MVE_VQSUB_T1:
5776     case MVE_VMUL_VEC_T1:
5777     case MVE_VABD_VEC:
5778     case MVE_VADD_VEC_T1:
5779     case MVE_VSUB_VEC_T1:
5780     case MVE_VQDMULH_T1:
5781     case MVE_VQRDMULH_T2:
5782     case MVE_VRHADD:
5783     case MVE_VHADD_T1:
5784     case MVE_VHSUB_T1:
5785       if (arm_decode_field (given, 20, 21) == 3)
5786         {
5787           *undefined_code = UNDEF_SIZE_3;
5788           return true;
5789         }
5790       else
5791         return false;
5792
5793     case MVE_VLDRB_T1:
5794       if (arm_decode_field (given, 7, 8) == 3)
5795         {
5796           *undefined_code = UNDEF_SIZE_3;
5797           return true;
5798         }
5799       else
5800         return false;
5801
5802     case MVE_VLDRH_T2:
5803       if (arm_decode_field (given, 7, 8) <= 1)
5804         {
5805           *undefined_code = UNDEF_SIZE_LE_1;
5806           return true;
5807         }
5808       else
5809         return false;
5810
5811     case MVE_VSTRB_T1:
5812       if ((arm_decode_field (given, 7, 8) == 0))
5813         {
5814           *undefined_code = UNDEF_SIZE_0;
5815           return true;
5816         }
5817       else
5818         return false;
5819
5820     case MVE_VSTRH_T2:
5821       if ((arm_decode_field (given, 7, 8) <= 1))
5822         {
5823           *undefined_code = UNDEF_SIZE_LE_1;
5824           return true;
5825         }
5826       else
5827         return false;
5828
5829     case MVE_VLDRB_GATHER_T1:
5830       if (arm_decode_field (given, 7, 8) == 3)
5831         {
5832           *undefined_code = UNDEF_SIZE_3;
5833           return true;
5834         }
5835       else if ((arm_decode_field (given, 28, 28) == 0)
5836                && (arm_decode_field (given, 7, 8) == 0))
5837         {
5838           *undefined_code = UNDEF_NOT_UNS_SIZE_0;
5839           return true;
5840         }
5841       else
5842         return false;
5843
5844     case MVE_VLDRH_GATHER_T2:
5845       if (arm_decode_field (given, 7, 8) == 3)
5846         {
5847           *undefined_code = UNDEF_SIZE_3;
5848           return true;
5849         }
5850       else if ((arm_decode_field (given, 28, 28) == 0)
5851                && (arm_decode_field (given, 7, 8) == 1))
5852         {
5853           *undefined_code = UNDEF_NOT_UNS_SIZE_1;
5854           return true;
5855         }
5856       else if (arm_decode_field (given, 7, 8) == 0)
5857         {
5858           *undefined_code = UNDEF_SIZE_0;
5859           return true;
5860         }
5861       else
5862         return false;
5863
5864     case MVE_VLDRW_GATHER_T3:
5865       if (arm_decode_field (given, 7, 8) != 2)
5866         {
5867           *undefined_code = UNDEF_SIZE_NOT_2;
5868           return true;
5869         }
5870       else if (arm_decode_field (given, 28, 28) == 0)
5871         {
5872           *undefined_code = UNDEF_NOT_UNSIGNED;
5873           return true;
5874         }
5875       else
5876         return false;
5877
5878     case MVE_VLDRD_GATHER_T4:
5879       if (arm_decode_field (given, 7, 8) != 3)
5880         {
5881           *undefined_code = UNDEF_SIZE_NOT_3;
5882           return true;
5883         }
5884       else if (arm_decode_field (given, 28, 28) == 0)
5885         {
5886           *undefined_code = UNDEF_NOT_UNSIGNED;
5887           return true;
5888         }
5889       else
5890         return false;
5891
5892     case MVE_VSTRB_SCATTER_T1:
5893       if (arm_decode_field (given, 7, 8) == 3)
5894         {
5895           *undefined_code = UNDEF_SIZE_3;
5896           return true;
5897         }
5898       else
5899         return false;
5900
5901     case MVE_VSTRH_SCATTER_T2:
5902       {
5903         unsigned long size = arm_decode_field (given, 7, 8);
5904         if (size == 3)
5905           {
5906             *undefined_code = UNDEF_SIZE_3;
5907             return true;
5908           }
5909         else if (size == 0)
5910           {
5911             *undefined_code = UNDEF_SIZE_0;
5912             return true;
5913           }
5914         else
5915           return false;
5916       }
5917
5918     case MVE_VSTRW_SCATTER_T3:
5919       if (arm_decode_field (given, 7, 8) != 2)
5920         {
5921           *undefined_code = UNDEF_SIZE_NOT_2;
5922           return true;
5923         }
5924       else
5925         return false;
5926
5927     case MVE_VSTRD_SCATTER_T4:
5928       if (arm_decode_field (given, 7, 8) != 3)
5929         {
5930           *undefined_code = UNDEF_SIZE_NOT_3;
5931           return true;
5932         }
5933       else
5934         return false;
5935
5936     case MVE_VCVT_FP_FIX_VEC:
5937       {
5938         unsigned long imm6 = arm_decode_field (given, 16, 21);
5939         if ((imm6 & 0x20) == 0)
5940           {
5941             *undefined_code = UNDEF_VCVT_IMM6;
5942             return true;
5943           }
5944
5945         if ((arm_decode_field (given, 9, 9) == 0)
5946             && ((imm6 & 0x30) == 0x20))
5947           {
5948             *undefined_code = UNDEF_VCVT_FSI_IMM6;
5949             return true;
5950           }
5951
5952         return false;
5953       }
5954
5955     case MVE_VNEG_FP:
5956     case MVE_VABS_FP:
5957     case MVE_VCVT_BETWEEN_FP_INT:
5958     case MVE_VCVT_FROM_FP_TO_INT:
5959       {
5960         unsigned long size = arm_decode_field (given, 18, 19);
5961         if (size == 0)
5962           {
5963             *undefined_code = UNDEF_SIZE_0;
5964             return true;
5965           }
5966         else if (size == 3)
5967           {
5968             *undefined_code = UNDEF_SIZE_3;
5969             return true;
5970           }
5971         else
5972           return false;
5973       }
5974
5975     case MVE_VMOV_VEC_LANE_TO_GP:
5976       {
5977         unsigned long op1 = arm_decode_field (given, 21, 22);
5978         unsigned long op2 = arm_decode_field (given, 5, 6);
5979         unsigned long u = arm_decode_field (given, 23, 23);
5980
5981         if ((op2 == 0) && (u == 1))
5982           {
5983             if ((op1 == 0) || (op1 == 1))
5984               {
5985                 *undefined_code = UNDEF_BAD_U_OP1_OP2;
5986                 return true;
5987               }
5988             else
5989               return false;
5990           }
5991         else if (op2 == 2)
5992           {
5993             if ((op1 == 0) || (op1 == 1))
5994               {
5995                 *undefined_code = UNDEF_BAD_OP1_OP2;
5996                 return true;
5997               }
5998             else
5999               return false;
6000           }
6001
6002         return false;
6003       }
6004
6005     case MVE_VMOV_GP_TO_VEC_LANE:
6006       if (arm_decode_field (given, 5, 6) == 2)
6007         {
6008           unsigned long op1 = arm_decode_field (given, 21, 22);
6009           if ((op1 == 0) || (op1 == 1))
6010             {
6011               *undefined_code = UNDEF_BAD_OP1_OP2;
6012               return true;
6013             }
6014           else
6015             return false;
6016         }
6017       else
6018         return false;
6019
6020     case MVE_VMOV_VEC_TO_VEC:
6021       if ((arm_decode_field (given, 5, 5) == 1)
6022           || (arm_decode_field (given, 22, 22) == 1))
6023           return true;
6024       return false;
6025
6026     case MVE_VMOV_IMM_TO_VEC:
6027       if (arm_decode_field (given, 5, 5) == 0)
6028       {
6029         unsigned long cmode = arm_decode_field (given, 8, 11);
6030
6031         if (((cmode & 9) == 1) || ((cmode & 5) == 1))
6032           {
6033             *undefined_code = UNDEF_OP_0_BAD_CMODE;
6034             return true;
6035           }
6036         else
6037           return false;
6038       }
6039       else
6040         return false;
6041
6042     case MVE_VSHLL_T2:
6043     case MVE_VMOVN:
6044       if (arm_decode_field (given, 18, 19) == 2)
6045         {
6046           *undefined_code = UNDEF_SIZE_2;
6047           return true;
6048         }
6049       else
6050         return false;
6051
6052     case MVE_VRMLALDAVH:
6053     case MVE_VMLADAV_T1:
6054     case MVE_VMLADAV_T2:
6055     case MVE_VMLALDAV:
6056       if ((arm_decode_field (given, 28, 28) == 1)
6057           && (arm_decode_field (given, 12, 12) == 1))
6058         {
6059           *undefined_code = UNDEF_XCHG_UNS;
6060           return true;
6061         }
6062       else
6063         return false;
6064
6065     case MVE_VQSHRN:
6066     case MVE_VQSHRUN:
6067     case MVE_VSHLL_T1:
6068     case MVE_VSHRN:
6069       {
6070         unsigned long sz = arm_decode_field (given, 19, 20);
6071         if (sz == 1)
6072           return false;
6073         else if ((sz & 2) == 2)
6074           return false;
6075         else
6076           {
6077             *undefined_code = UNDEF_SIZE;
6078             return true;
6079           }
6080       }
6081       break;
6082
6083     case MVE_VQSHL_T2:
6084     case MVE_VQSHLU_T3:
6085     case MVE_VRSHR:
6086     case MVE_VSHL_T1:
6087     case MVE_VSHR:
6088     case MVE_VSLI:
6089     case MVE_VSRI:
6090       {
6091         unsigned long sz = arm_decode_field (given, 19, 21);
6092         if ((sz & 7) == 1)
6093           return false;
6094         else if ((sz & 6) == 2)
6095           return false;
6096         else if ((sz & 4) == 4)
6097           return false;
6098         else
6099           {
6100             *undefined_code = UNDEF_SIZE;
6101             return true;
6102           }
6103       }
6104
6105     case MVE_VQRSHRN:
6106     case MVE_VQRSHRUN:
6107       if (arm_decode_field (given, 19, 20) == 0)
6108         {
6109           *undefined_code = UNDEF_SIZE_0;
6110           return true;
6111         }
6112       else
6113         return false;
6114
6115     case MVE_VABS_VEC:
6116         if (arm_decode_field (given, 18, 19) == 3)
6117         {
6118           *undefined_code = UNDEF_SIZE_3;
6119           return true;
6120         }
6121         else
6122           return false;
6123
6124     case MVE_VQNEG:
6125     case MVE_VQABS:
6126     case MVE_VNEG_VEC:
6127     case MVE_VCLS:
6128     case MVE_VCLZ:
6129       if (arm_decode_field (given, 18, 19) == 3)
6130         {
6131           *undefined_code = UNDEF_SIZE_3;
6132           return true;
6133         }
6134       else
6135         return false;
6136
6137     case MVE_VREV16:
6138       if (arm_decode_field (given, 18, 19) == 0)
6139         return false;
6140       else
6141         {
6142           *undefined_code = UNDEF_SIZE_NOT_0;
6143           return true;
6144         }
6145
6146     case MVE_VREV32:
6147       {
6148         unsigned long size = arm_decode_field (given, 18, 19);
6149         if ((size & 2) == 2)
6150           {
6151             *undefined_code = UNDEF_SIZE_2;
6152             return true;
6153           }
6154         else
6155           return false;
6156       }
6157
6158     case MVE_VREV64:
6159       if (arm_decode_field (given, 18, 19) != 3)
6160         return false;
6161       else
6162         {
6163           *undefined_code = UNDEF_SIZE_3;
6164           return true;
6165         }
6166
6167     default:
6168       return false;
6169     }
6170 }
6171
6172 /* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
6173    Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
6174    why this encoding is unpredictable.  */
6175
6176 static bool
6177 is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
6178                       enum mve_unpredictable *unpredictable_code)
6179 {
6180   *unpredictable_code = UNPRED_NONE;
6181
6182   switch (matched_insn)
6183     {
6184     case MVE_VCMP_FP_T2:
6185     case MVE_VPT_FP_T2:
6186       if ((arm_decode_field (given, 12, 12) == 0)
6187           && (arm_decode_field (given, 5, 5) == 1))
6188         {
6189           *unpredictable_code = UNPRED_FCA_0_FCB_1;
6190           return true;
6191         }
6192       else
6193         return false;
6194
6195     case MVE_VPT_VEC_T4:
6196     case MVE_VPT_VEC_T5:
6197     case MVE_VPT_VEC_T6:
6198     case MVE_VCMP_VEC_T4:
6199     case MVE_VCMP_VEC_T5:
6200     case MVE_VCMP_VEC_T6:
6201       if (arm_decode_field (given, 0, 3) == 0xd)
6202         {
6203           *unpredictable_code = UNPRED_R13;
6204           return true;
6205         }
6206       else
6207         return false;
6208
6209     case MVE_VDUP:
6210       {
6211         unsigned long gpr = arm_decode_field (given, 12, 15);
6212         if (gpr == 0xd)
6213           {
6214             *unpredictable_code = UNPRED_R13;
6215             return true;
6216           }
6217         else if (gpr == 0xf)
6218           {
6219             *unpredictable_code = UNPRED_R15;
6220             return true;
6221           }
6222
6223         return false;
6224       }
6225
6226     case MVE_VQADD_T2:
6227     case MVE_VQSUB_T2:
6228     case MVE_VMUL_FP_T2:
6229     case MVE_VMUL_VEC_T2:
6230     case MVE_VMLA:
6231     case MVE_VBRSR:
6232     case MVE_VADD_FP_T2:
6233     case MVE_VSUB_FP_T2:
6234     case MVE_VADD_VEC_T2:
6235     case MVE_VSUB_VEC_T2:
6236     case MVE_VQRSHL_T2:
6237     case MVE_VQSHL_T1:
6238     case MVE_VRSHL_T2:
6239     case MVE_VSHL_T2:
6240     case MVE_VSHLC:
6241     case MVE_VQDMLAH:
6242     case MVE_VQRDMLAH:
6243     case MVE_VQDMLASH:
6244     case MVE_VQRDMLASH:
6245     case MVE_VQDMULH_T3:
6246     case MVE_VQRDMULH_T4:
6247     case MVE_VMLAS:
6248     case MVE_VFMA_FP_SCALAR:
6249     case MVE_VFMAS_FP_SCALAR:
6250     case MVE_VHADD_T2:
6251     case MVE_VHSUB_T2:
6252       {
6253         unsigned long gpr = arm_decode_field (given, 0, 3);
6254         if (gpr == 0xd)
6255           {
6256             *unpredictable_code = UNPRED_R13;
6257             return true;
6258           }
6259         else if (gpr == 0xf)
6260           {
6261             *unpredictable_code = UNPRED_R15;
6262             return true;
6263           }
6264
6265         return false;
6266       }
6267
6268     case MVE_VLD2:
6269     case MVE_VST2:
6270       {
6271         unsigned long rn = arm_decode_field (given, 16, 19);
6272
6273         if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6274           {
6275             *unpredictable_code = UNPRED_R13_AND_WB;
6276             return true;
6277           }
6278
6279         if (rn == 0xf)
6280           {
6281             *unpredictable_code = UNPRED_R15;
6282             return true;
6283           }
6284
6285         if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 6)
6286           {
6287             *unpredictable_code = UNPRED_Q_GT_6;
6288             return true;
6289           }
6290         else
6291           return false;
6292       }
6293
6294     case MVE_VLD4:
6295     case MVE_VST4:
6296       {
6297         unsigned long rn = arm_decode_field (given, 16, 19);
6298
6299         if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6300           {
6301             *unpredictable_code = UNPRED_R13_AND_WB;
6302             return true;
6303           }
6304
6305         if (rn == 0xf)
6306           {
6307             *unpredictable_code = UNPRED_R15;
6308             return true;
6309           }
6310
6311         if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 4)
6312           {
6313             *unpredictable_code = UNPRED_Q_GT_4;
6314             return true;
6315           }
6316         else
6317           return false;
6318       }
6319
6320     case MVE_VLDRB_T5:
6321     case MVE_VLDRH_T6:
6322     case MVE_VLDRW_T7:
6323     case MVE_VSTRB_T5:
6324     case MVE_VSTRH_T6:
6325     case MVE_VSTRW_T7:
6326       {
6327         unsigned long rn = arm_decode_field (given, 16, 19);
6328
6329         if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6330           {
6331             *unpredictable_code = UNPRED_R13_AND_WB;
6332             return true;
6333           }
6334         else if (rn == 0xf)
6335           {
6336             *unpredictable_code = UNPRED_R15;
6337             return true;
6338           }
6339         else
6340           return false;
6341       }
6342
6343     case MVE_VLDRB_GATHER_T1:
6344       if (arm_decode_field (given, 0, 0) == 1)
6345         {
6346           *unpredictable_code = UNPRED_OS;
6347           return true;
6348         }
6349
6350       /*  fall through.  */
6351       /* To handle common code with T2-T4 variants.  */
6352     case MVE_VLDRH_GATHER_T2:
6353     case MVE_VLDRW_GATHER_T3:
6354     case MVE_VLDRD_GATHER_T4:
6355       {
6356         unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6357         unsigned long qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6358
6359         if (qd == qm)
6360           {
6361             *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6362             return true;
6363           }
6364
6365         if (arm_decode_field (given, 16, 19) == 0xf)
6366           {
6367             *unpredictable_code = UNPRED_R15;
6368             return true;
6369           }
6370
6371         return false;
6372       }
6373
6374     case MVE_VLDRW_GATHER_T5:
6375     case MVE_VLDRD_GATHER_T6:
6376       {
6377         unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6378         unsigned long qm = arm_decode_field_multiple (given, 17, 19, 7, 7);
6379
6380         if (qd == qm)
6381           {
6382             *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6383             return true;
6384           }
6385         else
6386           return false;
6387       }
6388
6389     case MVE_VSTRB_SCATTER_T1:
6390       if (arm_decode_field (given, 16, 19) == 0xf)
6391         {
6392           *unpredictable_code = UNPRED_R15;
6393           return true;
6394         }
6395       else if (arm_decode_field (given, 0, 0) == 1)
6396         {
6397           *unpredictable_code = UNPRED_OS;
6398           return true;
6399         }
6400       else
6401         return false;
6402
6403     case MVE_VSTRH_SCATTER_T2:
6404     case MVE_VSTRW_SCATTER_T3:
6405     case MVE_VSTRD_SCATTER_T4:
6406       if (arm_decode_field (given, 16, 19) == 0xf)
6407         {
6408           *unpredictable_code = UNPRED_R15;
6409           return true;
6410         }
6411       else
6412         return false;
6413
6414     case MVE_VMOV2_VEC_LANE_TO_GP:
6415     case MVE_VMOV2_GP_TO_VEC_LANE:
6416     case MVE_VCVT_BETWEEN_FP_INT:
6417     case MVE_VCVT_FROM_FP_TO_INT:
6418       {
6419         unsigned long rt = arm_decode_field (given, 0, 3);
6420         unsigned long rt2 = arm_decode_field (given, 16, 19);
6421
6422         if ((rt == 0xd) || (rt2 == 0xd))
6423           {
6424             *unpredictable_code = UNPRED_R13;
6425             return true;
6426           }
6427         else if ((rt == 0xf) || (rt2 == 0xf))
6428           {
6429             *unpredictable_code = UNPRED_R15;
6430             return true;
6431           }
6432         else if (rt == rt2 && matched_insn != MVE_VMOV2_GP_TO_VEC_LANE)
6433           {
6434             *unpredictable_code = UNPRED_GP_REGS_EQUAL;
6435             return true;
6436           }
6437
6438         return false;
6439       }
6440
6441     case MVE_VMAXV:
6442     case MVE_VMAXAV:
6443     case MVE_VMAXNMV_FP:
6444     case MVE_VMAXNMAV_FP:
6445     case MVE_VMINNMV_FP:
6446     case MVE_VMINNMAV_FP:
6447     case MVE_VMINV:
6448     case MVE_VMINAV:
6449     case MVE_VABAV:
6450     case MVE_VMOV_HFP_TO_GP:
6451     case MVE_VMOV_GP_TO_VEC_LANE:
6452     case MVE_VMOV_VEC_LANE_TO_GP:
6453       {
6454         unsigned long rda = arm_decode_field (given, 12, 15);
6455         if (rda == 0xd)
6456           {
6457             *unpredictable_code = UNPRED_R13;
6458             return true;
6459           }
6460         else if (rda == 0xf)
6461           {
6462             *unpredictable_code = UNPRED_R15;
6463             return true;
6464           }
6465
6466         return false;
6467       }
6468
6469     case MVE_VMULL_INT:
6470       {
6471         unsigned long Qd;
6472         unsigned long Qm;
6473         unsigned long Qn;
6474
6475         if (arm_decode_field (given, 20, 21) == 2)
6476           {
6477             Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6478             Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6479             Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6480
6481             if ((Qd == Qn) || (Qd == Qm))
6482               {
6483                 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
6484                 return true;
6485               }
6486             else
6487               return false;
6488           }
6489         else
6490           return false;
6491       }
6492
6493     case MVE_VCMUL_FP:
6494     case MVE_VQDMULL_T1:
6495       {
6496         unsigned long Qd;
6497         unsigned long Qm;
6498         unsigned long Qn;
6499
6500         if (arm_decode_field (given, 28, 28) == 1)
6501           {
6502             Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6503             Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6504             Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6505
6506             if ((Qd == Qn) || (Qd == Qm))
6507               {
6508                 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6509                 return true;
6510               }
6511             else
6512               return false;
6513           }
6514         else
6515           return false;
6516       }
6517
6518     case MVE_VQDMULL_T2:
6519       {
6520         unsigned long gpr = arm_decode_field (given, 0, 3);
6521         if (gpr == 0xd)
6522           {
6523             *unpredictable_code = UNPRED_R13;
6524             return true;
6525           }
6526         else if (gpr == 0xf)
6527           {
6528             *unpredictable_code = UNPRED_R15;
6529             return true;
6530           }
6531
6532         if (arm_decode_field (given, 28, 28) == 1)
6533           {
6534             unsigned long Qd
6535               = arm_decode_field_multiple (given, 13, 15, 22, 22);
6536             unsigned long Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6537
6538             if (Qd == Qn)
6539               {
6540                 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6541                 return true;
6542               }
6543             else
6544               return false;
6545           }
6546
6547         return false;
6548       }
6549
6550     case MVE_VMLSLDAV:
6551     case MVE_VRMLSLDAVH:
6552     case MVE_VMLALDAV:
6553     case MVE_VADDLV:
6554       if (arm_decode_field (given, 20, 22) == 6)
6555         {
6556           *unpredictable_code = UNPRED_R13;
6557           return true;
6558         }
6559       else
6560         return false;
6561
6562     case MVE_VDWDUP:
6563     case MVE_VIWDUP:
6564       if (arm_decode_field (given, 1, 3) == 6)
6565         {
6566           *unpredictable_code = UNPRED_R13;
6567           return true;
6568         }
6569       else
6570         return false;
6571
6572     case MVE_VCADD_VEC:
6573     case MVE_VHCADD:
6574       {
6575         unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6576         unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6577         if ((Qd == Qm) && arm_decode_field (given, 20, 21) == 2)
6578           {
6579             *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
6580             return true;
6581           }
6582         else
6583           return false;
6584       }
6585
6586     case MVE_VCADD_FP:
6587       {
6588         unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6589         unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6590         if ((Qd == Qm) && arm_decode_field (given, 20, 20) == 1)
6591           {
6592             *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6593             return true;
6594           }
6595         else
6596           return false;
6597       }
6598
6599     case MVE_VCMLA_FP:
6600       {
6601         unsigned long Qda;
6602         unsigned long Qm;
6603         unsigned long Qn;
6604
6605         if (arm_decode_field (given, 20, 20) == 1)
6606           {
6607             Qda = arm_decode_field_multiple (given, 13, 15, 22, 22);
6608             Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6609             Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6610
6611             if ((Qda == Qn) || (Qda == Qm))
6612               {
6613                 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6614                 return true;
6615               }
6616             else
6617               return false;
6618           }
6619         else
6620           return false;
6621
6622       }
6623
6624     case MVE_VCTP:
6625       if (arm_decode_field (given, 16, 19) == 0xd)
6626         {
6627           *unpredictable_code = UNPRED_R13;
6628           return true;
6629         }
6630       else
6631         return false;
6632
6633     case MVE_VREV64:
6634       {
6635         unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6636         unsigned long qm = arm_decode_field_multiple (given, 1, 3, 6, 6);
6637
6638         if (qd == qm)
6639           {
6640             *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6641             return true;
6642           }
6643         else
6644           return false;
6645       }
6646
6647     case MVE_LSLL:
6648     case MVE_LSLLI:
6649     case MVE_LSRL:
6650     case MVE_ASRL:
6651     case MVE_ASRLI:
6652     case MVE_UQSHLL:
6653     case MVE_UQRSHLL:
6654     case MVE_URSHRL:
6655     case MVE_SRSHRL:
6656     case MVE_SQSHLL:
6657     case MVE_SQRSHRL:
6658       {
6659         unsigned long gpr = arm_decode_field (given, 9, 11);
6660         gpr = ((gpr << 1) | 1);
6661         if (gpr == 0xd)
6662           {
6663             *unpredictable_code = UNPRED_R13;
6664             return true;
6665           }
6666         else if (gpr == 0xf)
6667           {
6668             *unpredictable_code = UNPRED_R15;
6669             return true;
6670           }
6671
6672         return false;
6673       }
6674
6675     default:
6676       return false;
6677     }
6678 }
6679
6680 static void
6681 print_mve_vmov_index (struct disassemble_info *info, unsigned long given)
6682 {
6683   unsigned long op1 = arm_decode_field (given, 21, 22);
6684   unsigned long op2 = arm_decode_field (given, 5, 6);
6685   unsigned long h = arm_decode_field (given, 16, 16);
6686   unsigned long index_operand, esize, targetBeat, idx;
6687   void *stream = info->stream;
6688   fprintf_styled_ftype func = info->fprintf_styled_func;
6689
6690   if ((op1 & 0x2) == 0x2)
6691     {
6692       index_operand = op2;
6693       esize = 8;
6694     }
6695   else if (((op1 & 0x2) == 0x0) && ((op2 & 0x1) == 0x1))
6696     {
6697       index_operand = op2  >> 1;
6698       esize = 16;
6699     }
6700   else if (((op1 & 0x2) == 0) && ((op2 & 0x3) == 0))
6701     {
6702       index_operand = 0;
6703       esize = 32;
6704     }
6705   else
6706     {
6707       func (stream, dis_style_text, "<undefined index>");
6708       return;
6709     }
6710
6711   targetBeat =  (op1 & 0x1) | (h << 1);
6712   idx = index_operand + targetBeat * (32/esize);
6713
6714   func (stream, dis_style_immediate, "%lu", idx);
6715 }
6716
6717 /* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits
6718    in length and integer of floating-point type.  */
6719 static void
6720 print_simd_imm8 (struct disassemble_info *info, unsigned long given,
6721                  unsigned int ibit_loc, const struct mopcode32 *insn)
6722 {
6723   int bits = 0;
6724   int cmode = (given >> 8) & 0xf;
6725   int op = (given >> 5) & 0x1;
6726   unsigned long value = 0, hival = 0;
6727   unsigned shift;
6728   int size = 0;
6729   int isfloat = 0;
6730   void *stream = info->stream;
6731   fprintf_styled_ftype func = info->fprintf_styled_func;
6732
6733   /* On Neon the 'i' bit is at bit 24, on mve it is
6734      at bit 28.  */
6735   bits |= ((given >> ibit_loc) & 1) << 7;
6736   bits |= ((given >> 16) & 7) << 4;
6737   bits |= ((given >> 0) & 15) << 0;
6738
6739   if (cmode < 8)
6740     {
6741       shift = (cmode >> 1) & 3;
6742       value = (unsigned long) bits << (8 * shift);
6743       size = 32;
6744     }
6745   else if (cmode < 12)
6746     {
6747       shift = (cmode >> 1) & 1;
6748       value = (unsigned long) bits << (8 * shift);
6749       size = 16;
6750     }
6751   else if (cmode < 14)
6752     {
6753       shift = (cmode & 1) + 1;
6754       value = (unsigned long) bits << (8 * shift);
6755       value |= (1ul << (8 * shift)) - 1;
6756       size = 32;
6757     }
6758   else if (cmode == 14)
6759     {
6760       if (op)
6761         {
6762           /* Bit replication into bytes.  */
6763           int ix;
6764           unsigned long mask;
6765
6766           value = 0;
6767           hival = 0;
6768           for (ix = 7; ix >= 0; ix--)
6769             {
6770               mask = ((bits >> ix) & 1) ? 0xff : 0;
6771               if (ix <= 3)
6772                 value = (value << 8) | mask;
6773               else
6774                 hival = (hival << 8) | mask;
6775             }
6776           size = 64;
6777         }
6778       else
6779         {
6780           /* Byte replication.  */
6781           value = (unsigned long) bits;
6782           size = 8;
6783         }
6784     }
6785   else if (!op)
6786     {
6787       /* Floating point encoding.  */
6788       int tmp;
6789
6790       value = (unsigned long)  (bits & 0x7f) << 19;
6791       value |= (unsigned long) (bits & 0x80) << 24;
6792       tmp = bits & 0x40 ? 0x3c : 0x40;
6793       value |= (unsigned long) tmp << 24;
6794       size = 32;
6795       isfloat = 1;
6796     }
6797   else
6798     {
6799       func (stream, dis_style_text, "<illegal constant %.8x:%x:%x>",
6800             bits, cmode, op);
6801       size = 32;
6802       return;
6803     }
6804
6805   /* printU determines whether the immediate value should be printed as
6806      unsigned.  */
6807   unsigned printU = 0;
6808   switch (insn->mve_op)
6809     {
6810     default:
6811       break;
6812     /* We want this for instructions that don't have a 'signed' type.  */
6813     case MVE_VBIC_IMM:
6814     case MVE_VORR_IMM:
6815     case MVE_VMVN_IMM:
6816     case MVE_VMOV_IMM_TO_VEC:
6817       printU = 1;
6818       break;
6819     }
6820   switch (size)
6821     {
6822     case 8:
6823       func (stream, dis_style_immediate, "#%ld", value);
6824       func (stream, dis_style_comment_start, "\t@ 0x%.2lx", value);
6825       break;
6826
6827     case 16:
6828       func (stream, dis_style_immediate, printU ? "#%lu" : "#%ld", value);
6829       func (stream, dis_style_comment_start, "\t@ 0x%.4lx", value);
6830       break;
6831
6832     case 32:
6833       if (isfloat)
6834         {
6835           unsigned char valbytes[4];
6836           double fvalue;
6837
6838           /* Do this a byte at a time so we don't have to
6839              worry about the host's endianness.  */
6840           valbytes[0] = value & 0xff;
6841           valbytes[1] = (value >> 8) & 0xff;
6842           valbytes[2] = (value >> 16) & 0xff;
6843           valbytes[3] = (value >> 24) & 0xff;
6844
6845           floatformat_to_double
6846             (& floatformat_ieee_single_little, valbytes,
6847              & fvalue);
6848
6849           func (stream, dis_style_immediate, "#%.7g", fvalue);
6850           func (stream, dis_style_comment_start, "\t@ 0x%.8lx", value);
6851         }
6852       else
6853         {
6854           func (stream, dis_style_immediate,
6855                 printU ? "#%lu" : "#%ld",
6856                 (long) (((value & 0x80000000L) != 0)
6857                         && !printU
6858                         ? value | ~0xffffffffL : value));
6859           func (stream, dis_style_comment_start, "\t@ 0x%.8lx", value);
6860         }
6861       break;
6862
6863     case 64:
6864       func (stream, dis_style_immediate, "#0x%.8lx%.8lx", hival, value);
6865       break;
6866
6867     default:
6868       abort ();
6869     }
6870
6871 }
6872
6873 static void
6874 print_mve_undefined (struct disassemble_info *info,
6875                      enum mve_undefined undefined_code)
6876 {
6877   void *stream = info->stream;
6878   fprintf_styled_ftype func = info->fprintf_styled_func;
6879   /* Initialize REASON to avoid compiler warning about uninitialized
6880      usage, though such usage should be impossible.  */
6881   const char *reason = "??";
6882
6883   switch (undefined_code)
6884     {
6885     case UNDEF_SIZE:
6886       reason = "illegal size";
6887       break;
6888
6889     case UNDEF_SIZE_0:
6890       reason = "size equals zero";
6891       break;
6892
6893     case UNDEF_SIZE_2:
6894       reason = "size equals two";
6895       break;
6896
6897     case UNDEF_SIZE_3:
6898       reason = "size equals three";
6899       break;
6900
6901     case UNDEF_SIZE_LE_1:
6902       reason = "size <= 1";
6903       break;
6904
6905     case UNDEF_SIZE_NOT_0:
6906       reason = "size not equal to 0";
6907       break;
6908
6909     case UNDEF_SIZE_NOT_2:
6910       reason = "size not equal to 2";
6911       break;
6912
6913     case UNDEF_SIZE_NOT_3:
6914       reason = "size not equal to 3";
6915       break;
6916
6917     case UNDEF_NOT_UNS_SIZE_0:
6918       reason = "not unsigned and size = zero";
6919       break;
6920
6921     case UNDEF_NOT_UNS_SIZE_1:
6922       reason = "not unsigned and size = one";
6923       break;
6924
6925     case UNDEF_NOT_UNSIGNED:
6926       reason = "not unsigned";
6927       break;
6928
6929     case UNDEF_VCVT_IMM6:
6930       reason = "invalid imm6";
6931       break;
6932
6933     case UNDEF_VCVT_FSI_IMM6:
6934       reason = "fsi = 0 and invalid imm6";
6935       break;
6936
6937     case UNDEF_BAD_OP1_OP2:
6938       reason = "bad size with op2 = 2 and op1 = 0 or 1";
6939       break;
6940
6941     case UNDEF_BAD_U_OP1_OP2:
6942       reason = "unsigned with op2 = 0 and op1 = 0 or 1";
6943       break;
6944
6945     case UNDEF_OP_0_BAD_CMODE:
6946       reason = "op field equal 0 and bad cmode";
6947       break;
6948
6949     case UNDEF_XCHG_UNS:
6950       reason = "exchange and unsigned together";
6951       break;
6952
6953     case UNDEF_NONE:
6954       reason = "";
6955       break;
6956     }
6957
6958   func (stream, dis_style_text, "\t\tundefined instruction: %s", reason);
6959 }
6960
6961 static void
6962 print_mve_unpredictable (struct disassemble_info *info,
6963                          enum mve_unpredictable unpredict_code)
6964 {
6965   void *stream = info->stream;
6966   fprintf_styled_ftype func = info->fprintf_styled_func;
6967   /* Initialize REASON to avoid compiler warning about uninitialized
6968      usage, though such usage should be impossible.  */
6969   const char *reason = "??";
6970
6971   switch (unpredict_code)
6972     {
6973     case UNPRED_IT_BLOCK:
6974       reason = "mve instruction in it block";
6975       break;
6976
6977     case UNPRED_FCA_0_FCB_1:
6978       reason = "condition bits, fca = 0 and fcb = 1";
6979       break;
6980
6981     case UNPRED_R13:
6982       reason = "use of r13 (sp)";
6983       break;
6984
6985     case UNPRED_R15:
6986       reason = "use of r15 (pc)";
6987       break;
6988
6989     case UNPRED_Q_GT_4:
6990       reason = "start register block > r4";
6991       break;
6992
6993     case UNPRED_Q_GT_6:
6994       reason = "start register block > r6";
6995       break;
6996
6997     case UNPRED_R13_AND_WB:
6998       reason = "use of r13 and write back";
6999       break;
7000
7001     case UNPRED_Q_REGS_EQUAL:
7002       reason = "same vector register used for destination and other operand";
7003       break;
7004
7005     case UNPRED_OS:
7006       reason = "use of offset scaled";
7007       break;
7008
7009     case UNPRED_GP_REGS_EQUAL:
7010       reason = "same general-purpose register used for both operands";
7011       break;
7012
7013     case UNPRED_Q_REGS_EQ_AND_SIZE_1:
7014       reason = "use of identical q registers and size = 1";
7015       break;
7016
7017     case UNPRED_Q_REGS_EQ_AND_SIZE_2:
7018       reason = "use of identical q registers and size = 1";
7019       break;
7020
7021     case UNPRED_NONE:
7022       reason = "";
7023       break;
7024     }
7025
7026   func (stream, dis_style_comment_start, "%s: %s",
7027         UNPREDICTABLE_INSTRUCTION, reason);
7028 }
7029
7030 /* Print register block operand for mve vld2/vld4/vst2/vld4.  */
7031
7032 static void
7033 print_mve_register_blocks (struct disassemble_info *info,
7034                            unsigned long given,
7035                            enum mve_instructions matched_insn)
7036 {
7037   void *stream = info->stream;
7038   fprintf_styled_ftype func = info->fprintf_styled_func;
7039
7040   unsigned long q_reg_start = arm_decode_field_multiple (given,
7041                                                          13, 15,
7042                                                          22, 22);
7043   switch (matched_insn)
7044     {
7045     case MVE_VLD2:
7046     case MVE_VST2:
7047       if (q_reg_start <= 6)
7048         {
7049           func (stream, dis_style_text, "{");
7050           func (stream, dis_style_register, "q%ld", q_reg_start);
7051           func (stream, dis_style_text, ", ");
7052           func (stream, dis_style_register, "q%ld", q_reg_start + 1);
7053           func (stream, dis_style_text, "}");
7054         }
7055       else
7056         func (stream, dis_style_text, "<illegal reg q%ld>", q_reg_start);
7057       break;
7058
7059     case MVE_VLD4:
7060     case MVE_VST4:
7061       if (q_reg_start <= 4)
7062         {
7063           func (stream, dis_style_text, "{");
7064           func (stream, dis_style_register, "q%ld", q_reg_start);
7065           func (stream, dis_style_text, ", ");
7066           func (stream, dis_style_register, "q%ld", q_reg_start + 1);
7067           func (stream, dis_style_text, ", ");
7068           func (stream, dis_style_register, "q%ld", q_reg_start + 2);
7069           func (stream, dis_style_text, ", ");
7070           func (stream, dis_style_register, "q%ld", q_reg_start + 3);
7071           func (stream, dis_style_text, "}");
7072         }
7073       else
7074         func (stream, dis_style_text, "<illegal reg q%ld>", q_reg_start);
7075       break;
7076
7077     default:
7078       break;
7079     }
7080 }
7081
7082 static void
7083 print_mve_rounding_mode (struct disassemble_info *info,
7084                          unsigned long given,
7085                          enum mve_instructions matched_insn)
7086 {
7087   void *stream = info->stream;
7088   fprintf_styled_ftype func = info->fprintf_styled_func;
7089
7090   switch (matched_insn)
7091     {
7092     case MVE_VCVT_FROM_FP_TO_INT:
7093       {
7094         switch (arm_decode_field (given, 8, 9))
7095           {
7096           case 0:
7097             func (stream, dis_style_mnemonic, "a");
7098             break;
7099
7100           case 1:
7101             func (stream, dis_style_mnemonic, "n");
7102             break;
7103
7104           case 2:
7105             func (stream, dis_style_mnemonic, "p");
7106             break;
7107
7108           case 3:
7109             func (stream, dis_style_mnemonic, "m");
7110             break;
7111
7112           default:
7113             break;
7114           }
7115       }
7116       break;
7117
7118     case MVE_VRINT_FP:
7119       {
7120         switch (arm_decode_field (given, 7, 9))
7121           {
7122           case 0:
7123             func (stream, dis_style_mnemonic, "n");
7124             break;
7125
7126           case 1:
7127             func (stream, dis_style_mnemonic, "x");
7128             break;
7129
7130           case 2:
7131             func (stream, dis_style_mnemonic, "a");
7132             break;
7133
7134           case 3:
7135             func (stream, dis_style_mnemonic, "z");
7136             break;
7137
7138           case 5:
7139             func (stream, dis_style_mnemonic, "m");
7140             break;
7141
7142           case 7:
7143             func (stream, dis_style_mnemonic, "p");
7144
7145           case 4:
7146           case 6:
7147           default:
7148             break;
7149           }
7150       }
7151       break;
7152
7153     default:
7154       break;
7155     }
7156 }
7157
7158 static void
7159 print_mve_vcvt_size (struct disassemble_info *info,
7160                      unsigned long given,
7161                      enum mve_instructions matched_insn)
7162 {
7163   unsigned long mode = 0;
7164   void *stream = info->stream;
7165   fprintf_styled_ftype func = info->fprintf_styled_func;
7166
7167   switch (matched_insn)
7168     {
7169     case MVE_VCVT_FP_FIX_VEC:
7170       {
7171         mode = (((given & 0x200) >> 7)
7172                 | ((given & 0x10000000) >> 27)
7173                 | ((given & 0x100) >> 8));
7174
7175         switch (mode)
7176           {
7177           case 0:
7178             func (stream, dis_style_mnemonic, "f16.s16");
7179             break;
7180
7181           case 1:
7182             func (stream, dis_style_mnemonic, "s16.f16");
7183             break;
7184
7185           case 2:
7186             func (stream, dis_style_mnemonic, "f16.u16");
7187             break;
7188
7189           case 3:
7190             func (stream, dis_style_mnemonic, "u16.f16");
7191             break;
7192
7193           case 4:
7194             func (stream, dis_style_mnemonic, "f32.s32");
7195             break;
7196
7197           case 5:
7198             func (stream, dis_style_mnemonic, "s32.f32");
7199             break;
7200
7201           case 6:
7202             func (stream, dis_style_mnemonic, "f32.u32");
7203             break;
7204
7205           case 7:
7206             func (stream, dis_style_mnemonic, "u32.f32");
7207             break;
7208
7209           default:
7210             break;
7211           }
7212         break;
7213       }
7214     case MVE_VCVT_BETWEEN_FP_INT:
7215       {
7216         unsigned long size = arm_decode_field (given, 18, 19);
7217         unsigned long op = arm_decode_field (given, 7, 8);
7218
7219         if (size == 1)
7220           {
7221             switch (op)
7222               {
7223               case 0:
7224                 func (stream, dis_style_mnemonic, "f16.s16");
7225                 break;
7226
7227               case 1:
7228                 func (stream, dis_style_mnemonic, "f16.u16");
7229                 break;
7230
7231               case 2:
7232                 func (stream, dis_style_mnemonic, "s16.f16");
7233                 break;
7234
7235               case 3:
7236                 func (stream, dis_style_mnemonic, "u16.f16");
7237                 break;
7238
7239               default:
7240                 break;
7241               }
7242           }
7243         else if (size == 2)
7244           {
7245             switch (op)
7246               {
7247               case 0:
7248                 func (stream, dis_style_mnemonic, "f32.s32");
7249                 break;
7250
7251               case 1:
7252                 func (stream, dis_style_mnemonic, "f32.u32");
7253                 break;
7254
7255               case 2:
7256                 func (stream, dis_style_mnemonic, "s32.f32");
7257                 break;
7258
7259               case 3:
7260                 func (stream, dis_style_mnemonic, "u32.f32");
7261                 break;
7262               }
7263           }
7264       }
7265       break;
7266
7267     case MVE_VCVT_FP_HALF_FP:
7268       {
7269         unsigned long op = arm_decode_field (given, 28, 28);
7270         if (op == 0)
7271           func (stream, dis_style_mnemonic, "f16.f32");
7272         else if (op == 1)
7273           func (stream, dis_style_mnemonic, "f32.f16");
7274       }
7275       break;
7276
7277     case MVE_VCVT_FROM_FP_TO_INT:
7278       {
7279         unsigned long size = arm_decode_field_multiple (given, 7, 7, 18, 19);
7280
7281         switch (size)
7282           {
7283           case 2:
7284             func (stream, dis_style_mnemonic, "s16.f16");
7285             break;
7286
7287           case 3:
7288             func (stream, dis_style_mnemonic, "u16.f16");
7289             break;
7290
7291           case 4:
7292             func (stream, dis_style_mnemonic, "s32.f32");
7293             break;
7294
7295           case 5:
7296             func (stream, dis_style_mnemonic, "u32.f32");
7297             break;
7298
7299           default:
7300             break;
7301           }
7302       }
7303       break;
7304
7305     default:
7306       break;
7307     }
7308 }
7309
7310 static void
7311 print_mve_rotate (struct disassemble_info *info, unsigned long rot,
7312                   unsigned long rot_width)
7313 {
7314   void *stream = info->stream;
7315   fprintf_styled_ftype func = info->fprintf_styled_func;
7316
7317   if (rot_width == 1)
7318     {
7319       switch (rot)
7320         {
7321         case 0:
7322           func (stream, dis_style_immediate, "90");
7323           break;
7324         case 1:
7325           func (stream, dis_style_immediate, "270");
7326           break;
7327         default:
7328           break;
7329         }
7330     }
7331   else if (rot_width == 2)
7332     {
7333       switch (rot)
7334         {
7335         case 0:
7336           func (stream, dis_style_immediate, "0");
7337           break;
7338         case 1:
7339           func (stream, dis_style_immediate, "90");
7340           break;
7341         case 2:
7342           func (stream, dis_style_immediate, "180");
7343           break;
7344         case 3:
7345           func (stream, dis_style_immediate, "270");
7346           break;
7347         default:
7348           break;
7349         }
7350     }
7351 }
7352
7353 static void
7354 print_instruction_predicate (struct disassemble_info *info)
7355 {
7356   void *stream = info->stream;
7357   fprintf_styled_ftype func = info->fprintf_styled_func;
7358
7359   if (vpt_block_state.next_pred_state == PRED_THEN)
7360     func (stream, dis_style_mnemonic, "t");
7361   else if (vpt_block_state.next_pred_state == PRED_ELSE)
7362     func (stream, dis_style_mnemonic, "e");
7363 }
7364
7365 static void
7366 print_mve_size (struct disassemble_info *info,
7367                 unsigned long size,
7368                 enum mve_instructions matched_insn)
7369 {
7370   void *stream = info->stream;
7371   fprintf_styled_ftype func = info->fprintf_styled_func;
7372
7373   switch (matched_insn)
7374     {
7375     case MVE_VABAV:
7376     case MVE_VABD_VEC:
7377     case MVE_VABS_FP:
7378     case MVE_VABS_VEC:
7379     case MVE_VADD_VEC_T1:
7380     case MVE_VADD_VEC_T2:
7381     case MVE_VADDV:
7382     case MVE_VBRSR:
7383     case MVE_VCADD_VEC:
7384     case MVE_VCLS:
7385     case MVE_VCLZ:
7386     case MVE_VCMP_VEC_T1:
7387     case MVE_VCMP_VEC_T2:
7388     case MVE_VCMP_VEC_T3:
7389     case MVE_VCMP_VEC_T4:
7390     case MVE_VCMP_VEC_T5:
7391     case MVE_VCMP_VEC_T6:
7392     case MVE_VCTP:
7393     case MVE_VDDUP:
7394     case MVE_VDWDUP:
7395     case MVE_VHADD_T1:
7396     case MVE_VHADD_T2:
7397     case MVE_VHCADD:
7398     case MVE_VHSUB_T1:
7399     case MVE_VHSUB_T2:
7400     case MVE_VIDUP:
7401     case MVE_VIWDUP:
7402     case MVE_VLD2:
7403     case MVE_VLD4:
7404     case MVE_VLDRB_GATHER_T1:
7405     case MVE_VLDRH_GATHER_T2:
7406     case MVE_VLDRW_GATHER_T3:
7407     case MVE_VLDRD_GATHER_T4:
7408     case MVE_VLDRB_T1:
7409     case MVE_VLDRH_T2:
7410     case MVE_VMAX:
7411     case MVE_VMAXA:
7412     case MVE_VMAXV:
7413     case MVE_VMAXAV:
7414     case MVE_VMIN:
7415     case MVE_VMINA:
7416     case MVE_VMINV:
7417     case MVE_VMINAV:
7418     case MVE_VMLA:
7419     case MVE_VMLAS:
7420     case MVE_VMUL_VEC_T1:
7421     case MVE_VMUL_VEC_T2:
7422     case MVE_VMULH:
7423     case MVE_VRMULH:
7424     case MVE_VMULL_INT:
7425     case MVE_VNEG_FP:
7426     case MVE_VNEG_VEC:
7427     case MVE_VPT_VEC_T1:
7428     case MVE_VPT_VEC_T2:
7429     case MVE_VPT_VEC_T3:
7430     case MVE_VPT_VEC_T4:
7431     case MVE_VPT_VEC_T5:
7432     case MVE_VPT_VEC_T6:
7433     case MVE_VQABS:
7434     case MVE_VQADD_T1:
7435     case MVE_VQADD_T2:
7436     case MVE_VQDMLADH:
7437     case MVE_VQRDMLADH:
7438     case MVE_VQDMLAH:
7439     case MVE_VQRDMLAH:
7440     case MVE_VQDMLASH:
7441     case MVE_VQRDMLASH:
7442     case MVE_VQDMLSDH:
7443     case MVE_VQRDMLSDH:
7444     case MVE_VQDMULH_T1:
7445     case MVE_VQRDMULH_T2:
7446     case MVE_VQDMULH_T3:
7447     case MVE_VQRDMULH_T4:
7448     case MVE_VQNEG:
7449     case MVE_VQRSHL_T1:
7450     case MVE_VQRSHL_T2:
7451     case MVE_VQSHL_T1:
7452     case MVE_VQSHL_T4:
7453     case MVE_VQSUB_T1:
7454     case MVE_VQSUB_T2:
7455     case MVE_VREV32:
7456     case MVE_VREV64:
7457     case MVE_VRHADD:
7458     case MVE_VRINT_FP:
7459     case MVE_VRSHL_T1:
7460     case MVE_VRSHL_T2:
7461     case MVE_VSHL_T2:
7462     case MVE_VSHL_T3:
7463     case MVE_VSHLL_T2:
7464     case MVE_VST2:
7465     case MVE_VST4:
7466     case MVE_VSTRB_SCATTER_T1:
7467     case MVE_VSTRH_SCATTER_T2:
7468     case MVE_VSTRW_SCATTER_T3:
7469     case MVE_VSTRB_T1:
7470     case MVE_VSTRH_T2:
7471     case MVE_VSUB_VEC_T1:
7472     case MVE_VSUB_VEC_T2:
7473       if (size <= 3)
7474         func (stream, dis_style_mnemonic, "%s", mve_vec_sizename[size]);
7475       else
7476         func (stream, dis_style_text, "<undef size>");
7477       break;
7478
7479     case MVE_VABD_FP:
7480     case MVE_VADD_FP_T1:
7481     case MVE_VADD_FP_T2:
7482     case MVE_VSUB_FP_T1:
7483     case MVE_VSUB_FP_T2:
7484     case MVE_VCMP_FP_T1:
7485     case MVE_VCMP_FP_T2:
7486     case MVE_VFMA_FP_SCALAR:
7487     case MVE_VFMA_FP:
7488     case MVE_VFMS_FP:
7489     case MVE_VFMAS_FP_SCALAR:
7490     case MVE_VMAXNM_FP:
7491     case MVE_VMAXNMA_FP:
7492     case MVE_VMAXNMV_FP:
7493     case MVE_VMAXNMAV_FP:
7494     case MVE_VMINNM_FP:
7495     case MVE_VMINNMA_FP:
7496     case MVE_VMINNMV_FP:
7497     case MVE_VMINNMAV_FP:
7498     case MVE_VMUL_FP_T1:
7499     case MVE_VMUL_FP_T2:
7500     case MVE_VPT_FP_T1:
7501     case MVE_VPT_FP_T2:
7502       if (size == 0)
7503         func (stream, dis_style_mnemonic, "32");
7504       else if (size == 1)
7505         func (stream, dis_style_mnemonic, "16");
7506       break;
7507
7508     case MVE_VCADD_FP:
7509     case MVE_VCMLA_FP:
7510     case MVE_VCMUL_FP:
7511     case MVE_VMLADAV_T1:
7512     case MVE_VMLALDAV:
7513     case MVE_VMLSDAV_T1:
7514     case MVE_VMLSLDAV:
7515     case MVE_VMOVN:
7516     case MVE_VQDMULL_T1:
7517     case MVE_VQDMULL_T2:
7518     case MVE_VQMOVN:
7519     case MVE_VQMOVUN:
7520       if (size == 0)
7521         func (stream, dis_style_mnemonic, "16");
7522       else if (size == 1)
7523         func (stream, dis_style_mnemonic, "32");
7524       break;
7525
7526     case MVE_VMOVL:
7527       if (size == 1)
7528         func (stream, dis_style_mnemonic, "8");
7529       else if (size == 2)
7530         func (stream, dis_style_mnemonic, "16");
7531       break;
7532
7533     case MVE_VDUP:
7534       switch (size)
7535         {
7536         case 0:
7537           func (stream, dis_style_mnemonic, "32");
7538           break;
7539         case 1:
7540           func (stream, dis_style_mnemonic, "16");
7541           break;
7542         case 2:
7543           func (stream, dis_style_mnemonic, "8");
7544           break;
7545         default:
7546           break;
7547         }
7548       break;
7549
7550     case MVE_VMOV_GP_TO_VEC_LANE:
7551     case MVE_VMOV_VEC_LANE_TO_GP:
7552       switch (size)
7553         {
7554         case 0: case 4:
7555           func (stream, dis_style_mnemonic, "32");
7556           break;
7557
7558         case 1: case 3:
7559         case 5: case 7:
7560           func (stream, dis_style_mnemonic, "16");
7561           break;
7562
7563         case 8: case 9: case 10: case 11:
7564         case 12: case 13: case 14: case 15:
7565           func (stream, dis_style_mnemonic, "8");
7566           break;
7567
7568         default:
7569           break;
7570         }
7571       break;
7572
7573     case MVE_VMOV_IMM_TO_VEC:
7574       switch (size)
7575         {
7576         case 0: case 4: case 8:
7577         case 12: case 24: case 26:
7578           func (stream, dis_style_mnemonic, "i32");
7579           break;
7580         case 16: case 20:
7581           func (stream, dis_style_mnemonic, "i16");
7582           break;
7583         case 28:
7584           func (stream, dis_style_mnemonic, "i8");
7585           break;
7586         case 29:
7587           func (stream, dis_style_mnemonic, "i64");
7588           break;
7589         case 30:
7590           func (stream, dis_style_mnemonic, "f32");
7591           break;
7592         default:
7593           break;
7594         }
7595       break;
7596
7597     case MVE_VMULL_POLY:
7598       if (size == 0)
7599         func (stream, dis_style_mnemonic, "p8");
7600       else if (size == 1)
7601         func (stream, dis_style_mnemonic, "p16");
7602       break;
7603
7604     case MVE_VMVN_IMM:
7605       switch (size)
7606         {
7607         case 0: case 2: case 4:
7608         case 6: case 12: case 13:
7609           func (stream, dis_style_mnemonic, "32");
7610           break;
7611
7612         case 8: case 10:
7613           func (stream, dis_style_mnemonic, "16");
7614           break;
7615
7616         default:
7617           break;
7618         }
7619       break;
7620
7621     case MVE_VBIC_IMM:
7622     case MVE_VORR_IMM:
7623       switch (size)
7624         {
7625         case 1: case 3:
7626         case 5: case 7:
7627           func (stream, dis_style_mnemonic, "32");
7628           break;
7629
7630         case 9: case 11:
7631           func (stream, dis_style_mnemonic, "16");
7632           break;
7633
7634         default:
7635           break;
7636         }
7637       break;
7638
7639     case MVE_VQSHRN:
7640     case MVE_VQSHRUN:
7641     case MVE_VQRSHRN:
7642     case MVE_VQRSHRUN:
7643     case MVE_VRSHRN:
7644     case MVE_VSHRN:
7645       {
7646         switch (size)
7647         {
7648         case 1:
7649           func (stream, dis_style_mnemonic, "16");
7650           break;
7651
7652         case 2: case 3:
7653           func (stream, dis_style_mnemonic, "32");
7654           break;
7655
7656         default:
7657           break;
7658         }
7659       }
7660       break;
7661
7662     case MVE_VQSHL_T2:
7663     case MVE_VQSHLU_T3:
7664     case MVE_VRSHR:
7665     case MVE_VSHL_T1:
7666     case MVE_VSHLL_T1:
7667     case MVE_VSHR:
7668     case MVE_VSLI:
7669     case MVE_VSRI:
7670       {
7671         switch (size)
7672         {
7673         case 1:
7674           func (stream, dis_style_mnemonic, "8");
7675           break;
7676
7677         case 2: case 3:
7678           func (stream, dis_style_mnemonic, "16");
7679           break;
7680
7681         case 4: case 5: case 6: case 7:
7682           func (stream, dis_style_mnemonic, "32");
7683           break;
7684
7685         default:
7686           break;
7687         }
7688       }
7689       break;
7690
7691     default:
7692       break;
7693     }
7694 }
7695
7696 /* Return true if INSN is a shift insn with an immediate shift amount
7697    which needs decoding as per print_mve_shift_n.  */
7698
7699 static bool
7700 mve_shift_insn_p (enum mve_instructions insn)
7701 {
7702   switch (insn)
7703     {
7704     case MVE_VQSHL_T2:
7705     case MVE_VQSHLU_T3:
7706     case MVE_VQSHRN:
7707     case MVE_VQSHRUN:
7708     case MVE_VQRSHRN:
7709     case MVE_VQRSHRUN:
7710     case MVE_VRSHR:
7711     case MVE_VRSHRN:
7712     case MVE_VSHL_T1:
7713     case MVE_VSHLL_T1:
7714     case MVE_VSHR:
7715     case MVE_VSHRN:
7716     case MVE_VSLI:
7717     case MVE_VSRI:
7718       return true;
7719     default:
7720       return false;
7721     }
7722 }
7723
7724 static void
7725 print_mve_shift_n (struct disassemble_info *info, long given,
7726                    enum mve_instructions matched_insn)
7727 {
7728   void *stream = info->stream;
7729   fprintf_styled_ftype func = info->fprintf_styled_func;
7730
7731   int startAt0
7732     = matched_insn == MVE_VQSHL_T2
7733       || matched_insn == MVE_VQSHLU_T3
7734       || matched_insn == MVE_VSHL_T1
7735       || matched_insn == MVE_VSHLL_T1
7736       || matched_insn == MVE_VSLI;
7737
7738   unsigned imm6 = (given & 0x3f0000) >> 16;
7739
7740   if (matched_insn == MVE_VSHLL_T1)
7741     imm6 &= 0x1f;
7742
7743   unsigned shiftAmount = 0;
7744   if ((imm6 & 0x20) != 0)
7745     shiftAmount = startAt0 ? imm6 - 32 : 64 - imm6;
7746   else if ((imm6 & 0x10) != 0)
7747     shiftAmount = startAt0 ? imm6 - 16 : 32 - imm6;
7748   else if ((imm6 & 0x08) != 0)
7749     shiftAmount = startAt0 ? imm6 - 8 : 16 - imm6;
7750   else
7751     print_mve_undefined (info, UNDEF_SIZE_0);
7752
7753   func (stream, dis_style_immediate, "%u", shiftAmount);
7754 }
7755
7756 static void
7757 print_vec_condition (struct disassemble_info *info, long given,
7758                      enum mve_instructions matched_insn)
7759 {
7760   void *stream = info->stream;
7761   fprintf_styled_ftype func = info->fprintf_styled_func;
7762   long vec_cond = 0;
7763
7764   switch (matched_insn)
7765     {
7766     case MVE_VPT_FP_T1:
7767     case MVE_VCMP_FP_T1:
7768       vec_cond = (((given & 0x1000) >> 10)
7769                   | ((given & 1) << 1)
7770                   | ((given & 0x0080) >> 7));
7771       func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
7772       break;
7773
7774     case MVE_VPT_FP_T2:
7775     case MVE_VCMP_FP_T2:
7776       vec_cond = (((given & 0x1000) >> 10)
7777                   | ((given & 0x0020) >> 4)
7778                   | ((given & 0x0080) >> 7));
7779       func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
7780       break;
7781
7782     case MVE_VPT_VEC_T1:
7783     case MVE_VCMP_VEC_T1:
7784       vec_cond = (given & 0x0080) >> 7;
7785       func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
7786       break;
7787
7788     case MVE_VPT_VEC_T2:
7789     case MVE_VCMP_VEC_T2:
7790       vec_cond = 2 | ((given & 0x0080) >> 7);
7791       func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
7792       break;
7793
7794     case MVE_VPT_VEC_T3:
7795     case MVE_VCMP_VEC_T3:
7796       vec_cond = 4 | ((given & 1) << 1) | ((given & 0x0080) >> 7);
7797       func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
7798       break;
7799
7800     case MVE_VPT_VEC_T4:
7801     case MVE_VCMP_VEC_T4:
7802       vec_cond = (given & 0x0080) >> 7;
7803       func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
7804       break;
7805
7806     case MVE_VPT_VEC_T5:
7807     case MVE_VCMP_VEC_T5:
7808       vec_cond = 2 | ((given & 0x0080) >> 7);
7809       func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
7810       break;
7811
7812     case MVE_VPT_VEC_T6:
7813     case MVE_VCMP_VEC_T6:
7814       vec_cond = 4 | ((given & 0x0020) >> 4) | ((given & 0x0080) >> 7);
7815       func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
7816       break;
7817
7818     case MVE_NONE:
7819     case MVE_VPST:
7820     default:
7821       break;
7822     }
7823 }
7824
7825 #define W_BIT 21
7826 #define I_BIT 22
7827 #define U_BIT 23
7828 #define P_BIT 24
7829
7830 #define WRITEBACK_BIT_SET (given & (1 << W_BIT))
7831 #define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
7832 #define NEGATIVE_BIT_SET  ((given & (1 << U_BIT)) == 0)
7833 #define PRE_BIT_SET       (given & (1 << P_BIT))
7834
7835 /* The assembler string for an instruction can include %{X:...%} patterns,
7836    where the 'X' is one of the characters understood by this function.
7837
7838    This function takes the X character, and returns a new style.  This new
7839    style will be used by the caller to temporarily change the current base
7840    style.  */
7841
7842 static enum disassembler_style
7843 decode_base_style (const char x)
7844 {
7845   switch (x)
7846     {
7847     case 'A': return dis_style_address;
7848     case 'B': return dis_style_sub_mnemonic;
7849     case 'C': return dis_style_comment_start;
7850     case 'D': return dis_style_assembler_directive;
7851     case 'I': return dis_style_immediate;
7852     case 'M': return dis_style_mnemonic;
7853     case 'O': return dis_style_address_offset;
7854     case 'R': return dis_style_register;
7855     case 'S': return dis_style_symbol;
7856     case 'T': return dis_style_text;
7857     default:
7858       abort ();
7859     }
7860 }
7861
7862 /* Print one coprocessor instruction on INFO->STREAM.
7863    Return TRUE if the instuction matched, FALSE if this is not a
7864    recognised coprocessor instruction.  */
7865
7866 static bool
7867 print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
7868                           bfd_vma pc,
7869                           struct disassemble_info *info,
7870                           long given,
7871                           bool thumb)
7872 {
7873   const struct sopcode32 *insn;
7874   void *stream = info->stream;
7875   fprintf_styled_ftype func = info->fprintf_styled_func;
7876   unsigned long mask;
7877   unsigned long value = 0;
7878   int cond;
7879   int cp_num;
7880   struct arm_private_data *private_data = info->private_data;
7881   arm_feature_set allowed_arches = ARM_ARCH_NONE;
7882   arm_feature_set arm_ext_v8_1m_main =
7883     ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
7884   enum disassembler_style base_style = dis_style_mnemonic;
7885   enum disassembler_style old_base_style = base_style;
7886
7887   allowed_arches = private_data->features;
7888
7889   for (insn = opcodes; insn->assembler; insn++)
7890     {
7891       unsigned long u_reg = 16;
7892       bool is_unpredictable = false;
7893       signed long value_in_comment = 0;
7894       const char *c;
7895
7896       if (ARM_FEATURE_ZERO (insn->arch))
7897         switch (insn->value)
7898           {
7899           case SENTINEL_IWMMXT_START:
7900             if (info->mach != bfd_mach_arm_XScale
7901                 && info->mach != bfd_mach_arm_iWMMXt
7902                 && info->mach != bfd_mach_arm_iWMMXt2)
7903               do
7904                 insn++;
7905               while ((! ARM_FEATURE_ZERO (insn->arch))
7906                      && insn->value != SENTINEL_IWMMXT_END);
7907             continue;
7908
7909           case SENTINEL_IWMMXT_END:
7910             continue;
7911
7912           case SENTINEL_GENERIC_START:
7913             allowed_arches = private_data->features;
7914             continue;
7915
7916           default:
7917             abort ();
7918           }
7919
7920       mask = insn->mask;
7921       value = insn->value;
7922       cp_num = (given >> 8) & 0xf;
7923
7924       if (thumb)
7925         {
7926           /* The high 4 bits are 0xe for Arm conditional instructions, and
7927              0xe for arm unconditional instructions.  The rest of the
7928              encoding is the same.  */
7929           mask |= 0xf0000000;
7930           value |= 0xe0000000;
7931           if (ifthen_state)
7932             cond = IFTHEN_COND;
7933           else
7934             cond = COND_UNCOND;
7935         }
7936       else
7937         {
7938           /* Only match unconditional instuctions against unconditional
7939              patterns.  */
7940           if ((given & 0xf0000000) == 0xf0000000)
7941             {
7942               mask |= 0xf0000000;
7943               cond = COND_UNCOND;
7944             }
7945           else
7946             {
7947               cond = (given >> 28) & 0xf;
7948               if (cond == 0xe)
7949                 cond = COND_UNCOND;
7950             }
7951         }
7952
7953       if ((insn->isa == T32 && !thumb)
7954           || (insn->isa == ARM && thumb))
7955         continue;
7956
7957       if ((given & mask) != value)
7958         continue;
7959
7960       if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
7961         continue;
7962
7963       if (insn->value == 0xfe000010     /* mcr2  */
7964           || insn->value == 0xfe100010  /* mrc2  */
7965           || insn->value == 0xfc100000  /* ldc2  */
7966           || insn->value == 0xfc000000) /* stc2  */
7967         {
7968           if (cp_num == 9 || cp_num == 10 || cp_num == 11)
7969             is_unpredictable = true;
7970
7971           /* Armv8.1-M Mainline FP & MVE instructions.  */
7972           if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
7973               && !ARM_CPU_IS_ANY (allowed_arches)
7974               && (cp_num == 8 || cp_num == 14 || cp_num == 15))
7975             continue;
7976
7977         }
7978       else if (insn->value == 0x0e000000     /* cdp  */
7979                || insn->value == 0xfe000000  /* cdp2  */
7980                || insn->value == 0x0e000010  /* mcr  */
7981                || insn->value == 0x0e100010  /* mrc  */
7982                || insn->value == 0x0c100000  /* ldc  */
7983                || insn->value == 0x0c000000) /* stc  */
7984         {
7985           /* Floating-point instructions.  */
7986           if (cp_num == 9 || cp_num == 10 || cp_num == 11)
7987             continue;
7988
7989           /* Armv8.1-M Mainline FP & MVE instructions.  */
7990           if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
7991               && !ARM_CPU_IS_ANY (allowed_arches)
7992               && (cp_num == 8 || cp_num == 14 || cp_num == 15))
7993             continue;
7994         }
7995       else if ((insn->value == 0xec100f80      /* vldr (system register) */
7996                 || insn->value == 0xec000f80)  /* vstr (system register) */
7997                && arm_decode_field (given, 24, 24) == 0
7998                && arm_decode_field (given, 21, 21) == 0)
7999         /* If the P and W bits are both 0 then these encodings match the MVE
8000            VLDR and VSTR instructions, these are in a different table, so we
8001            don't let it match here.  */
8002         continue;
8003
8004       for (c = insn->assembler; *c; c++)
8005         {
8006           if (*c == '%')
8007             {
8008               const char mod = *++c;
8009
8010               switch (mod)
8011                 {
8012                 case '{':
8013                   ++c;
8014                   if (*c == '\0')
8015                     abort ();
8016                   old_base_style = base_style;
8017                   base_style = decode_base_style (*c);
8018                   ++c;
8019                   if (*c != ':')
8020                     abort ();
8021                   break;
8022
8023                 case '}':
8024                   base_style = old_base_style;
8025                   break;
8026
8027                 case '%':
8028                   func (stream, base_style, "%%");
8029                   break;
8030
8031                 case 'A':
8032                 case 'K':
8033                   {
8034                     int rn = (given >> 16) & 0xf;
8035                     bfd_vma offset = given & 0xff;
8036
8037                     if (mod == 'K')
8038                       offset = given & 0x7f;
8039
8040                     func (stream, dis_style_text, "[");
8041                     func (stream, dis_style_register, "%s",
8042                           arm_regnames [(given >> 16) & 0xf]);
8043
8044                     if (PRE_BIT_SET || WRITEBACK_BIT_SET)
8045                       {
8046                         /* Not unindexed.  The offset is scaled.  */
8047                         if (cp_num == 9)
8048                           /* vldr.16/vstr.16 will shift the address
8049                              left by 1 bit only.  */
8050                           offset = offset * 2;
8051                         else
8052                           offset = offset * 4;
8053
8054                         if (NEGATIVE_BIT_SET)
8055                           offset = - offset;
8056                         if (rn != 15)
8057                           value_in_comment = offset;
8058                       }
8059
8060                     if (PRE_BIT_SET)
8061                       {
8062                         if (offset)
8063                           {
8064                             func (stream, dis_style_text, ", ");
8065                             func (stream, dis_style_immediate, "#%d",
8066                                   (int) offset);
8067                             func (stream, dis_style_text, "]%s",
8068                                   WRITEBACK_BIT_SET ? "!" : "");
8069                           }
8070                         else if (NEGATIVE_BIT_SET)
8071                           {
8072                             func (stream, dis_style_text, ", ");
8073                             func (stream, dis_style_immediate, "#-0");
8074                             func (stream, dis_style_text, "]");
8075                           }
8076                         else
8077                           func (stream, dis_style_text, "]");
8078                       }
8079                     else
8080                       {
8081                         func (stream, dis_style_text, "]");
8082
8083                         if (WRITEBACK_BIT_SET)
8084                           {
8085                             if (offset)
8086                               {
8087                                 func (stream, dis_style_text, ", ");
8088                                 func (stream, dis_style_immediate,
8089                                       "#%d", (int) offset);
8090                               }
8091                             else if (NEGATIVE_BIT_SET)
8092                               {
8093                                 func (stream, dis_style_text, ", ");
8094                                 func (stream, dis_style_immediate, "#-0");
8095                               }
8096                           }
8097                         else
8098                           {
8099                             func (stream, dis_style_text, ", {");
8100                             func (stream, dis_style_immediate, "%s%d",
8101                                   (NEGATIVE_BIT_SET && !offset) ? "-" : "",
8102                                   (int) offset);
8103                             func (stream, dis_style_text, "}");
8104                             value_in_comment = offset;
8105                           }
8106                       }
8107                     if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
8108                       {
8109                         func (stream, dis_style_comment_start, "\t@ ");
8110                         /* For unaligned PCs, apply off-by-alignment
8111                            correction.  */
8112                         info->print_address_func (offset + pc
8113                                                   + info->bytes_per_chunk * 2
8114                                                   - (pc & 3),
8115                                                   info);
8116                       }
8117                   }
8118                   break;
8119
8120                 case 'B':
8121                   {
8122                     int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
8123                     int offset = (given >> 1) & 0x3f;
8124
8125                     func (stream, dis_style_text, "{");
8126                     if (offset == 1)
8127                       func (stream, dis_style_register, "d%d", regno);
8128                     else if (regno + offset > 32)
8129                       {
8130                         func (stream, dis_style_register, "d%d", regno);
8131                         func (stream, dis_style_text, "-<overflow reg d%d>",
8132                               regno + offset - 1);
8133                       }
8134                     else
8135                       {
8136                         func (stream, dis_style_register, "d%d", regno);
8137                         func (stream, dis_style_text, "-");
8138                         func (stream, dis_style_register, "d%d",
8139                               regno + offset - 1);
8140                       }
8141                     func (stream, dis_style_text, "}");
8142                   }
8143                   break;
8144
8145                 case 'C':
8146                   {
8147                     bool single = ((given >> 8) & 1) == 0;
8148                     char reg_prefix = single ? 's' : 'd';
8149                     int Dreg = (given >> 22) & 0x1;
8150                     int Vdreg = (given >> 12) & 0xf;
8151                     int reg = single ? ((Vdreg << 1) | Dreg)
8152                                      : ((Dreg << 4) | Vdreg);
8153                     int num = (given >> (single ? 0 : 1)) & 0x7f;
8154                     int maxreg = single ? 31 : 15;
8155                     int topreg = reg + num - 1;
8156
8157                     func (stream, dis_style_text, "{");
8158                     if (!num)
8159                       {
8160                         /* Nothing.  */
8161                       }
8162                     else if (num == 1)
8163                       {
8164                         func (stream, dis_style_register,
8165                               "%c%d", reg_prefix, reg);
8166                         func (stream, dis_style_text, ", ");
8167                       }
8168                     else if (topreg > maxreg)
8169                       {
8170                         func (stream, dis_style_register, "%c%d",
8171                               reg_prefix, reg);
8172                         func (stream, dis_style_text, "-<overflow reg d%d, ",
8173                               single ? topreg >> 1 : topreg);
8174                       }
8175                     else
8176                       {
8177                         func (stream, dis_style_register,
8178                               "%c%d", reg_prefix, reg);
8179                         func (stream, dis_style_text, "-");
8180                         func (stream, dis_style_register, "%c%d",
8181                               reg_prefix, topreg);
8182                         func (stream, dis_style_text, ", ");
8183                       }
8184                     func (stream, dis_style_register, "VPR");
8185                     func (stream, dis_style_text, "}");
8186                   }
8187                   break;
8188
8189                 case 'u':
8190                   if (cond != COND_UNCOND)
8191                     is_unpredictable = true;
8192
8193                   /* Fall through.  */
8194                 case 'c':
8195                   if (cond != COND_UNCOND && cp_num == 9)
8196                     is_unpredictable = true;
8197
8198                   /* Fall through.  */
8199                 case 'b':
8200                   func (stream, dis_style_mnemonic, "%s",
8201                         arm_conditional[cond]);
8202                   break;
8203
8204                 case 'J':
8205                   {
8206                     unsigned long regno
8207                       = arm_decode_field_multiple (given, 13, 15, 22, 22);
8208
8209                     switch (regno)
8210                       {
8211                       case 0x1:
8212                         func (stream, dis_style_register, "FPSCR");
8213                         break;
8214                       case 0x2:
8215                         func (stream, dis_style_register, "FPSCR_nzcvqc");
8216                         break;
8217                       case 0xc:
8218                         func (stream, dis_style_register, "VPR");
8219                         break;
8220                       case 0xd:
8221                         func (stream, dis_style_register, "P0");
8222                         break;
8223                       case 0xe:
8224                         func (stream, dis_style_register, "FPCXTNS");
8225                         break;
8226                       case 0xf:
8227                         func (stream, dis_style_register, "FPCXTS");
8228                         break;
8229                       default:
8230                         func (stream, dis_style_text, "<invalid reg %lu>",
8231                               regno);
8232                         break;
8233                       }
8234                   }
8235                   break;
8236
8237                 case '0': case '1': case '2': case '3': case '4':
8238                 case '5': case '6': case '7': case '8': case '9':
8239                   {
8240                     int width;
8241
8242                     c = arm_decode_bitfield (c, given, &value, &width);
8243
8244                     switch (*c)
8245                       {
8246                       case 'R':
8247                         if (value == 15)
8248                           is_unpredictable = true;
8249                         /* Fall through.  */
8250                       case 'r':
8251                         if (c[1] == 'u')
8252                           {
8253                             /* Eat the 'u' character.  */
8254                             ++ c;
8255
8256                             if (u_reg == value)
8257                               is_unpredictable = true;
8258                             u_reg = value;
8259                           }
8260                         func (stream, dis_style_register, "%s",
8261                               arm_regnames[value]);
8262                         break;
8263                       case 'V':
8264                         if (given & (1 << 6))
8265                           goto Q;
8266                         /* FALLTHROUGH */
8267                       case 'D':
8268                         func (stream, dis_style_register, "d%ld", value);
8269                         break;
8270                       case 'Q':
8271                       Q:
8272                         if (value & 1)
8273                           func (stream, dis_style_text,
8274                                 "<illegal reg q%ld.5>", value >> 1);
8275                         else
8276                           func (stream, dis_style_register,
8277                                 "q%ld", value >> 1);
8278                         break;
8279                       case 'd':
8280                         func (stream, base_style, "%ld", value);
8281                         value_in_comment = value;
8282                         break;
8283                       case 'E':
8284                         {
8285                           /* Converts immediate 8 bit back to float value.  */
8286                           unsigned floatVal = (value & 0x80) << 24
8287                             | (value & 0x3F) << 19
8288                             | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
8289
8290                           /* Quarter float have a maximum value of 31.0.
8291                              Get floating point value multiplied by 1e7.
8292                              The maximum value stays in limit of a 32-bit int.  */
8293                           unsigned decVal =
8294                             (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
8295                             (16 + (value & 0xF));
8296
8297                           if (!(decVal % 1000000))
8298                             {
8299                               func (stream, dis_style_immediate, "%ld", value);
8300                               func (stream, dis_style_comment_start,
8301                                     "\t@ 0x%08x %c%u.%01u",
8302                                     floatVal, value & 0x80 ? '-' : ' ',
8303                                     decVal / 10000000,
8304                                     decVal % 10000000 / 1000000);
8305                             }
8306                           else if (!(decVal % 10000))
8307                             {
8308                               func (stream, dis_style_immediate, "%ld", value);
8309                               func (stream, dis_style_comment_start,
8310                                     "\t@ 0x%08x %c%u.%03u",
8311                                     floatVal, value & 0x80 ? '-' : ' ',
8312                                     decVal / 10000000,
8313                                     decVal % 10000000 / 10000);
8314                             }
8315                           else
8316                             {
8317                               func (stream, dis_style_immediate, "%ld", value);
8318                               func (stream, dis_style_comment_start,
8319                                     "\t@ 0x%08x %c%u.%07u",
8320                                     floatVal, value & 0x80 ? '-' : ' ',
8321                                     decVal / 10000000, decVal % 10000000);
8322                             }
8323                           break;
8324                         }
8325                       case 'k':
8326                         {
8327                           int from = (given & (1 << 7)) ? 32 : 16;
8328                           func (stream, dis_style_immediate, "%ld",
8329                                 from - value);
8330                         }
8331                         break;
8332
8333                       case 'w':
8334                         if (width == 2)
8335                           func (stream, dis_style_mnemonic, "%s",
8336                                 iwmmxt_wwnames[value]);
8337                         else
8338                           func (stream, dis_style_mnemonic, "%s",
8339                                 iwmmxt_wwssnames[value]);
8340                         break;
8341
8342                       case 'g':
8343                         func (stream, dis_style_register, "%s",
8344                               iwmmxt_regnames[value]);
8345                         break;
8346                       case 'G':
8347                         func (stream, dis_style_register, "%s",
8348                               iwmmxt_cregnames[value]);
8349                         break;
8350
8351                       case 'x':
8352                         func (stream, dis_style_immediate, "0x%lx",
8353                               (value & 0xffffffffUL));
8354                         break;
8355
8356                       case 'c':
8357                         switch (value)
8358                           {
8359                           case 0:
8360                             func (stream, dis_style_mnemonic, "eq");
8361                             break;
8362
8363                           case 1:
8364                             func (stream, dis_style_mnemonic, "vs");
8365                             break;
8366
8367                           case 2:
8368                             func (stream, dis_style_mnemonic, "ge");
8369                             break;
8370
8371                           case 3:
8372                             func (stream, dis_style_mnemonic, "gt");
8373                             break;
8374
8375                           default:
8376                             func (stream, dis_style_text, "??");
8377                             break;
8378                           }
8379                         break;
8380
8381                       case '`':
8382                         c++;
8383                         if (value == 0)
8384                           func (stream, dis_style_mnemonic, "%c", *c);
8385                         break;
8386                       case '\'':
8387                         c++;
8388                         if (value == ((1ul << width) - 1))
8389                           func (stream, base_style, "%c", *c);
8390                         break;
8391                       case '?':
8392                         func (stream, base_style, "%c",
8393                               c[(1 << width) - (int) value]);
8394                         c += 1 << width;
8395                         break;
8396                       default:
8397                         abort ();
8398                       }
8399                   }
8400                   break;
8401
8402                 case 'y':
8403                 case 'z':
8404                   {
8405                     int single = *c++ == 'y';
8406                     int regno;
8407
8408                     switch (*c)
8409                       {
8410                       case '4': /* Sm pair */
8411                       case '0': /* Sm, Dm */
8412                         regno = given & 0x0000000f;
8413                         if (single)
8414                           {
8415                             regno <<= 1;
8416                             regno += (given >> 5) & 1;
8417                           }
8418                         else
8419                           regno += ((given >> 5) & 1) << 4;
8420                         break;
8421
8422                       case '1': /* Sd, Dd */
8423                         regno = (given >> 12) & 0x0000000f;
8424                         if (single)
8425                           {
8426                             regno <<= 1;
8427                             regno += (given >> 22) & 1;
8428                           }
8429                         else
8430                           regno += ((given >> 22) & 1) << 4;
8431                         break;
8432
8433                       case '2': /* Sn, Dn */
8434                         regno = (given >> 16) & 0x0000000f;
8435                         if (single)
8436                           {
8437                             regno <<= 1;
8438                             regno += (given >> 7) & 1;
8439                           }
8440                         else
8441                           regno += ((given >> 7) & 1) << 4;
8442                         break;
8443
8444                       case '3': /* List */
8445                         func (stream, dis_style_text, "{");
8446                         regno = (given >> 12) & 0x0000000f;
8447                         if (single)
8448                           {
8449                             regno <<= 1;
8450                             regno += (given >> 22) & 1;
8451                           }
8452                         else
8453                           regno += ((given >> 22) & 1) << 4;
8454                         break;
8455
8456                       default:
8457                         abort ();
8458                       }
8459
8460                     func (stream, dis_style_register, "%c%d",
8461                           single ? 's' : 'd', regno);
8462
8463                     if (*c == '3')
8464                       {
8465                         int count = given & 0xff;
8466
8467                         if (single == 0)
8468                           count >>= 1;
8469
8470                         if (--count)
8471                           {
8472                             func (stream, dis_style_text, "-");
8473                             func (stream, dis_style_register, "%c%d",
8474                                   single ? 's' : 'd',
8475                                   regno + count);
8476                           }
8477
8478                         func (stream, dis_style_text, "}");
8479                       }
8480                     else if (*c == '4')
8481                       {
8482                         func (stream, dis_style_text, ", ");
8483                         func (stream, dis_style_register, "%c%d",
8484                               single ? 's' : 'd', regno + 1);
8485                       }
8486                   }
8487                   break;
8488
8489                 case 'L':
8490                   switch (given & 0x00400100)
8491                     {
8492                     case 0x00000000:
8493                       func (stream, dis_style_mnemonic, "b");
8494                       break;
8495                     case 0x00400000:
8496                       func (stream, dis_style_mnemonic, "h");
8497                       break;
8498                     case 0x00000100:
8499                       func (stream, dis_style_mnemonic, "w");
8500                       break;
8501                     case 0x00400100:
8502                       func (stream, dis_style_mnemonic, "d");
8503                       break;
8504                     default:
8505                       break;
8506                     }
8507                   break;
8508
8509                 case 'Z':
8510                   {
8511                     /* given (20, 23) | given (0, 3) */
8512                     value = ((given >> 16) & 0xf0) | (given & 0xf);
8513                     func (stream, dis_style_immediate, "%d", (int) value);
8514                   }
8515                   break;
8516
8517                 case 'l':
8518                   /* This is like the 'A' operator, except that if
8519                      the width field "M" is zero, then the offset is
8520                      *not* multiplied by four.  */
8521                   {
8522                     int offset = given & 0xff;
8523                     int multiplier = (given & 0x00000100) ? 4 : 1;
8524
8525                     func (stream, dis_style_text, "[");
8526                     func (stream, dis_style_register, "%s",
8527                           arm_regnames [(given >> 16) & 0xf]);
8528
8529                     if (multiplier > 1)
8530                       {
8531                         value_in_comment = offset * multiplier;
8532                         if (NEGATIVE_BIT_SET)
8533                           value_in_comment = - value_in_comment;
8534                       }
8535
8536                     if (offset)
8537                       {
8538                         if (PRE_BIT_SET)
8539                           {
8540                             func (stream, dis_style_text, ", ");
8541                             func (stream, dis_style_immediate, "#%s%d",
8542                                   NEGATIVE_BIT_SET ? "-" : "",
8543                                   offset * multiplier);
8544                             func (stream, dis_style_text, "]%s",
8545                                   WRITEBACK_BIT_SET ? "!" : "");
8546                           }
8547                         else
8548                           {
8549                             func (stream, dis_style_text, "], ");
8550                             func (stream, dis_style_immediate, "#%s%d",
8551                                   NEGATIVE_BIT_SET ? "-" : "",
8552                                   offset * multiplier);
8553                           }
8554                       }
8555                     else
8556                       func (stream, dis_style_text, "]");
8557                   }
8558                   break;
8559
8560                 case 'r':
8561                   {
8562                     int imm4 = (given >> 4) & 0xf;
8563                     int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
8564                     int ubit = ! NEGATIVE_BIT_SET;
8565                     const char *rm = arm_regnames [given & 0xf];
8566                     const char *rn = arm_regnames [(given >> 16) & 0xf];
8567
8568                     switch (puw_bits)
8569                       {
8570                       case 1:
8571                       case 3:
8572                         func (stream, dis_style_text, "[");
8573                         func (stream, dis_style_register, "%s", rn);
8574                         func (stream, dis_style_text, "], ");
8575                         func (stream, dis_style_text, "%c", ubit ? '+' : '-');
8576                         func (stream, dis_style_register, "%s", rm);
8577                         if (imm4)
8578                           {
8579                             func (stream, dis_style_text, ", ");
8580                             func (stream, dis_style_sub_mnemonic, "lsl ");
8581                             func (stream, dis_style_immediate, "#%d", imm4);
8582                           }
8583                         break;
8584
8585                       case 4:
8586                       case 5:
8587                       case 6:
8588                       case 7:
8589                         func (stream, dis_style_text, "[");
8590                         func (stream, dis_style_register, "%s", rn);
8591                         func (stream, dis_style_text, ", ");
8592                         func (stream, dis_style_text, "%c", ubit ? '+' : '-');
8593                         func (stream, dis_style_register, "%s", rm);
8594                         if (imm4 > 0)
8595                           {
8596                             func (stream, dis_style_text, ", ");
8597                             func (stream, dis_style_sub_mnemonic, "lsl ");
8598                             func (stream, dis_style_immediate, "#%d", imm4);
8599                           }
8600                         func (stream, dis_style_text, "]");
8601                         if (puw_bits == 5 || puw_bits == 7)
8602                           func (stream, dis_style_text, "!");
8603                         break;
8604
8605                       default:
8606                         func (stream, dis_style_text, "INVALID");
8607                       }
8608                   }
8609                   break;
8610
8611                 case 'i':
8612                   {
8613                     long imm5;
8614                     imm5 = ((given & 0x100) >> 4) | (given & 0xf);
8615                     func (stream, dis_style_immediate, "%ld",
8616                           (imm5 == 0) ? 32 : imm5);
8617                   }
8618                   break;
8619
8620                 default:
8621                   abort ();
8622                 }
8623             }
8624           else
8625             {
8626               if (*c == '@')
8627                 base_style = dis_style_comment_start;
8628
8629               if (*c == '\t')
8630                 base_style = dis_style_text;
8631
8632               func (stream, base_style, "%c", *c);
8633             }
8634         }
8635
8636       if (value_in_comment > 32 || value_in_comment < -16)
8637         func (stream, dis_style_comment_start, "\t@ 0x%lx",
8638               (value_in_comment & 0xffffffffUL));
8639
8640       if (is_unpredictable)
8641         func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION);
8642
8643       return true;
8644     }
8645   return false;
8646 }
8647
8648 static bool
8649 print_insn_coprocessor (bfd_vma pc,
8650                         struct disassemble_info *info,
8651                         long given,
8652                         bool thumb)
8653 {
8654   return print_insn_coprocessor_1 (coprocessor_opcodes,
8655                                    pc, info, given, thumb);
8656 }
8657
8658 static bool
8659 print_insn_generic_coprocessor (bfd_vma pc,
8660                                 struct disassemble_info *info,
8661                                 long given,
8662                                 bool thumb)
8663 {
8664   return print_insn_coprocessor_1 (generic_coprocessor_opcodes,
8665                                    pc, info, given, thumb);
8666 }
8667
8668 /* Decodes and prints ARM addressing modes.  Returns the offset
8669    used in the address, if any, if it is worthwhile printing the
8670    offset as a hexadecimal value in a comment at the end of the
8671    line of disassembly.  */
8672
8673 static signed long
8674 print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
8675 {
8676   void *stream = info->stream;
8677   fprintf_styled_ftype func = info->fprintf_styled_func;
8678   bfd_vma offset = 0;
8679
8680   if (((given & 0x000f0000) == 0x000f0000)
8681       && ((given & 0x02000000) == 0))
8682     {
8683       offset = given & 0xfff;
8684
8685       func (stream, dis_style_text, "[");
8686       func (stream, dis_style_register, "pc");
8687
8688       if (PRE_BIT_SET)
8689         {
8690           /* Pre-indexed.  Elide offset of positive zero when
8691              non-writeback.  */
8692           if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
8693             {
8694               func (stream, dis_style_text, ", ");
8695               func (stream, dis_style_immediate, "#%s%d",
8696                     NEGATIVE_BIT_SET ? "-" : "", (int) offset);
8697             }
8698
8699           if (NEGATIVE_BIT_SET)
8700             offset = -offset;
8701
8702           offset += pc + 8;
8703
8704           /* Cope with the possibility of write-back
8705              being used.  Probably a very dangerous thing
8706              for the programmer to do, but who are we to
8707              argue ?  */
8708           func (stream, dis_style_text, "]%s", WRITEBACK_BIT_SET ? "!" : "");
8709         }
8710       else  /* Post indexed.  */
8711         {
8712           func (stream, dis_style_text, "], ");
8713           func (stream, dis_style_immediate, "#%s%d",
8714                 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
8715
8716           /* Ie ignore the offset.  */
8717           offset = pc + 8;
8718         }
8719
8720       func (stream, dis_style_comment_start, "\t@ ");
8721       info->print_address_func (offset, info);
8722       offset = 0;
8723     }
8724   else
8725     {
8726       func (stream, dis_style_text, "[");
8727       func (stream, dis_style_register, "%s",
8728             arm_regnames[(given >> 16) & 0xf]);
8729
8730       if (PRE_BIT_SET)
8731         {
8732           if ((given & 0x02000000) == 0)
8733             {
8734               /* Elide offset of positive zero when non-writeback.  */
8735               offset = given & 0xfff;
8736               if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
8737                 {
8738                   func (stream, dis_style_text, ", ");
8739                   func (stream, dis_style_immediate, "#%s%d",
8740                         NEGATIVE_BIT_SET ? "-" : "", (int) offset);
8741                 }
8742             }
8743           else
8744             {
8745               func (stream, dis_style_text, ", %s",
8746                     NEGATIVE_BIT_SET ? "-" : "");
8747               arm_decode_shift (given, func, stream, true);
8748             }
8749
8750           func (stream, dis_style_text, "]%s",
8751                 WRITEBACK_BIT_SET ? "!" : "");
8752         }
8753       else
8754         {
8755           if ((given & 0x02000000) == 0)
8756             {
8757               /* Always show offset.  */
8758               offset = given & 0xfff;
8759               func (stream, dis_style_text, "], ");
8760               func (stream, dis_style_immediate, "#%s%d",
8761                     NEGATIVE_BIT_SET ? "-" : "", (int) offset);
8762             }
8763           else
8764             {
8765               func (stream, dis_style_text, "], %s",
8766                     NEGATIVE_BIT_SET ? "-" : "");
8767               arm_decode_shift (given, func, stream, true);
8768             }
8769         }
8770       if (NEGATIVE_BIT_SET)
8771         offset = -offset;
8772     }
8773
8774   return (signed long) offset;
8775 }
8776
8777
8778 /* Print one cde instruction on INFO->STREAM.
8779    Return TRUE if the instuction matched, FALSE if this is not a
8780    recognised cde instruction.  */
8781 static bool
8782 print_insn_cde (struct disassemble_info *info, long given, bool thumb)
8783 {
8784   const struct cdeopcode32 *insn;
8785   void *stream = info->stream;
8786   fprintf_styled_ftype func = info->fprintf_styled_func;
8787   enum disassembler_style base_style = dis_style_mnemonic;
8788   enum disassembler_style old_base_style = base_style;
8789
8790   if (thumb)
8791   {
8792     /* Manually extract the coprocessor code from a known point.
8793        This position is the same across all CDE instructions.  */
8794     for (insn = cde_opcodes; insn->assembler; insn++)
8795     {
8796       uint16_t coproc = (given >> insn->coproc_shift) & insn->coproc_mask;
8797       uint16_t coproc_mask = 1 << coproc;
8798       if (! (coproc_mask & cde_coprocs))
8799         continue;
8800
8801       if ((given & insn->mask) == insn->value)
8802       {
8803         bool is_unpredictable = false;
8804         const char *c;
8805
8806         for (c = insn->assembler; *c; c++)
8807         {
8808           if (*c == '%')
8809           {
8810             switch (*++c)
8811             {
8812               case '{':
8813                 ++c;
8814                 if (*c == '\0')
8815                   abort ();
8816                 old_base_style = base_style;
8817                 base_style = decode_base_style (*c);
8818                 ++c;
8819                 if (*c != ':')
8820                   abort ();
8821                 break;
8822
8823               case '}':
8824                 base_style = old_base_style;
8825                 break;
8826
8827               case '%':
8828                 func (stream, base_style, "%%");
8829                 break;
8830
8831               case '0': case '1': case '2': case '3': case '4':
8832               case '5': case '6': case '7': case '8': case '9':
8833               {
8834                 int width;
8835                 unsigned long value;
8836
8837                 c = arm_decode_bitfield (c, given, &value, &width);
8838
8839                 switch (*c)
8840                 {
8841                   case 'S':
8842                     if (value > 10)
8843                       is_unpredictable = true;
8844                     /* Fall through.  */
8845                   case 'R':
8846                     if (value == 13)
8847                       is_unpredictable = true;
8848                     /* Fall through.  */
8849                   case 'r':
8850                     func (stream, dis_style_register, "%s",
8851                           arm_regnames[value]);
8852                     break;
8853
8854                   case 'n':
8855                     if (value == 15)
8856                       func (stream, dis_style_register, "%s", "APSR_nzcv");
8857                     else
8858                       func (stream, dis_style_register, "%s",
8859                             arm_regnames[value]);
8860                     break;
8861
8862                   case 'T':
8863                     func (stream, dis_style_register, "%s",
8864                           arm_regnames[(value + 1) & 15]);
8865                     break;
8866
8867                   case 'd':
8868                     func (stream, dis_style_immediate, "%ld", value);
8869                     break;
8870
8871                   case 'V':
8872                     if (given & (1 << 6))
8873                       func (stream, dis_style_register, "q%ld", value >> 1);
8874                     else if (given & (1 << 24))
8875                       func (stream, dis_style_register, "d%ld", value);
8876                     else
8877                       {
8878                         /* Encoding for S register is different than for D and
8879                            Q registers.  S registers are encoded using the top
8880                            single bit in position 22 as the lowest bit of the
8881                            register number, while for Q and D it represents the
8882                            highest bit of the register number.  */
8883                         uint8_t top_bit = (value >> 4) & 1;
8884                         uint8_t tmp = (value << 1) & 0x1e;
8885                         uint8_t res = tmp | top_bit;
8886                         func (stream, dis_style_register, "s%u", res);
8887                       }
8888                     break;
8889
8890                 default:
8891                   abort ();
8892                 }
8893               }
8894             break;
8895
8896             case 'p':
8897               {
8898                 uint8_t proc_number = (given >> 8) & 0x7;
8899                 func (stream, dis_style_register, "p%u", proc_number);
8900                 break;
8901               }
8902
8903             case 'a':
8904               {
8905                 uint8_t a_offset = 28;
8906                 if (given & (1 << a_offset))
8907                   func (stream, dis_style_mnemonic, "a");
8908                 break;
8909               }
8910           default:
8911             abort ();
8912           }
8913         }
8914         else
8915           {
8916             if (*c == '@')
8917               base_style = dis_style_comment_start;
8918             if (*c == '\t')
8919               base_style = dis_style_text;
8920
8921             func (stream, base_style, "%c", *c);
8922           }
8923       }
8924
8925       if (is_unpredictable)
8926         func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION);
8927
8928       return true;
8929       }
8930     }
8931     return false;
8932   }
8933   else
8934     return false;
8935 }
8936
8937
8938 /* Print one neon instruction on INFO->STREAM.
8939    Return TRUE if the instuction matched, FALSE if this is not a
8940    recognised neon instruction.  */
8941
8942 static bool
8943 print_insn_neon (struct disassemble_info *info, long given, bool thumb)
8944 {
8945   const struct opcode32 *insn;
8946   void *stream = info->stream;
8947   fprintf_styled_ftype func = info->fprintf_styled_func;
8948   enum disassembler_style base_style = dis_style_mnemonic;
8949   enum disassembler_style old_base_style = base_style;
8950
8951   if (thumb)
8952     {
8953       if ((given & 0xef000000) == 0xef000000)
8954         {
8955           /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding.  */
8956           unsigned long bit28 = given & (1 << 28);
8957
8958           given &= 0x00ffffff;
8959           if (bit28)
8960             given |= 0xf3000000;
8961           else
8962             given |= 0xf2000000;
8963         }
8964       else if ((given & 0xff000000) == 0xf9000000)
8965         given ^= 0xf9000000 ^ 0xf4000000;
8966       /* BFloat16 neon instructions without special top byte handling.  */
8967       else if ((given & 0xff000000) == 0xfe000000
8968                || (given & 0xff000000) == 0xfc000000)
8969         ;
8970       /* vdup is also a valid neon instruction.  */
8971       else if ((given & 0xff900f5f) != 0xee800b10)
8972         return false;
8973     }
8974
8975   for (insn = neon_opcodes; insn->assembler; insn++)
8976     {
8977       unsigned long cond_mask = insn->mask;
8978       unsigned long cond_value = insn->value;
8979       int cond;
8980
8981       if (thumb)
8982         {
8983           if ((cond_mask & 0xf0000000) == 0) {
8984               /* For the entries in neon_opcodes, an opcode mask/value with
8985                  the high 4 bits equal to 0 indicates a conditional
8986                  instruction. For thumb however, we need to include those
8987                  bits in the instruction matching.  */
8988               cond_mask |= 0xf0000000;
8989               /* Furthermore, the thumb encoding of a conditional instruction
8990                  will have the high 4 bits equal to 0xe.  */
8991               cond_value |= 0xe0000000;
8992           }
8993           if (ifthen_state)
8994             cond = IFTHEN_COND;
8995           else
8996             cond = COND_UNCOND;
8997         }
8998       else
8999         {
9000           if ((given & 0xf0000000) == 0xf0000000)
9001             {
9002               /* If the instruction is unconditional, update the mask to only
9003                  match against unconditional opcode values.  */
9004               cond_mask |= 0xf0000000;
9005               cond = COND_UNCOND;
9006             }
9007           else
9008             {
9009               cond = (given >> 28) & 0xf;
9010               if (cond == 0xe)
9011                 cond = COND_UNCOND;
9012             }
9013         }
9014
9015       if ((given & cond_mask) == cond_value)
9016         {
9017           signed long value_in_comment = 0;
9018           bool is_unpredictable = false;
9019           const char *c;
9020
9021           for (c = insn->assembler; *c; c++)
9022             {
9023               if (*c == '%')
9024                 {
9025                   switch (*++c)
9026                     {
9027                     case '{':
9028                       ++c;
9029                       if (*c == '\0')
9030                         abort ();
9031                       old_base_style = base_style;
9032                       base_style = decode_base_style (*c);
9033                       ++c;
9034                       if (*c != ':')
9035                         abort ();
9036                       break;
9037
9038                     case '}':
9039                       base_style = old_base_style;
9040                       break;
9041
9042                     case '%':
9043                       func (stream, base_style, "%%");
9044                       break;
9045
9046                     case 'u':
9047                       if (thumb && ifthen_state)
9048                         is_unpredictable = true;
9049
9050                       /* Fall through.  */
9051                     case 'c':
9052                       func (stream, dis_style_mnemonic, "%s",
9053                             arm_conditional[cond]);
9054                       break;
9055
9056                     case 'A':
9057                       {
9058                         static const unsigned char enc[16] =
9059                         {
9060                           0x4, 0x14, /* st4 0,1 */
9061                           0x4, /* st1 2 */
9062                           0x4, /* st2 3 */
9063                           0x3, /* st3 4 */
9064                           0x13, /* st3 5 */
9065                           0x3, /* st1 6 */
9066                           0x1, /* st1 7 */
9067                           0x2, /* st2 8 */
9068                           0x12, /* st2 9 */
9069                           0x2, /* st1 10 */
9070                           0, 0, 0, 0, 0
9071                         };
9072                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
9073                         int rn = ((given >> 16) & 0xf);
9074                         int rm = ((given >> 0) & 0xf);
9075                         int align = ((given >> 4) & 0x3);
9076                         int type = ((given >> 8) & 0xf);
9077                         int n = enc[type] & 0xf;
9078                         int stride = (enc[type] >> 4) + 1;
9079                         int ix;
9080
9081                         func (stream, dis_style_text, "{");
9082                         if (stride > 1)
9083                           for (ix = 0; ix != n; ix++)
9084                             {
9085                               if (ix > 0)
9086                                 func (stream, dis_style_text, ",");
9087                               func (stream, dis_style_register, "d%d",
9088                                     rd + ix * stride);
9089                             }
9090                         else if (n == 1)
9091                           func (stream, dis_style_register, "d%d", rd);
9092                         else
9093                           {
9094                             func (stream, dis_style_register, "d%d", rd);
9095                             func (stream, dis_style_text, "-");
9096                             func (stream, dis_style_register, "d%d",
9097                                   rd + n - 1);
9098                           }
9099                         func (stream, dis_style_text, "}, [");
9100                         func (stream, dis_style_register, "%s",
9101                               arm_regnames[rn]);
9102                         if (align)
9103                           {
9104                             func (stream, dis_style_text, " :");
9105                             func (stream, dis_style_immediate, "%d",
9106                                   32 << align);
9107                           }
9108                         func (stream, dis_style_text, "]");
9109                         if (rm == 0xd)
9110                           func (stream, dis_style_text, "!");
9111                         else if (rm != 0xf)
9112                           {
9113                             func (stream, dis_style_text, ", ");
9114                             func (stream, dis_style_register, "%s",
9115                                   arm_regnames[rm]);
9116                           }
9117                       }
9118                       break;
9119
9120                     case 'B':
9121                       {
9122                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
9123                         int rn = ((given >> 16) & 0xf);
9124                         int rm = ((given >> 0) & 0xf);
9125                         int idx_align = ((given >> 4) & 0xf);
9126                         int align = 0;
9127                         int size = ((given >> 10) & 0x3);
9128                         int idx = idx_align >> (size + 1);
9129                         int length = ((given >> 8) & 3) + 1;
9130                         int stride = 1;
9131                         int i;
9132
9133                         if (length > 1 && size > 0)
9134                           stride = (idx_align & (1 << size)) ? 2 : 1;
9135
9136                         switch (length)
9137                           {
9138                           case 1:
9139                             {
9140                               int amask = (1 << size) - 1;
9141                               if ((idx_align & (1 << size)) != 0)
9142                                 return false;
9143                               if (size > 0)
9144                                 {
9145                                   if ((idx_align & amask) == amask)
9146                                     align = 8 << size;
9147                                   else if ((idx_align & amask) != 0)
9148                                     return false;
9149                                 }
9150                               }
9151                             break;
9152
9153                           case 2:
9154                             if (size == 2 && (idx_align & 2) != 0)
9155                               return false;
9156                             align = (idx_align & 1) ? 16 << size : 0;
9157                             break;
9158
9159                           case 3:
9160                             if ((size == 2 && (idx_align & 3) != 0)
9161                                 || (idx_align & 1) != 0)
9162                               return false;
9163                             break;
9164
9165                           case 4:
9166                             if (size == 2)
9167                               {
9168                                 if ((idx_align & 3) == 3)
9169                                   return false;
9170                                 align = (idx_align & 3) * 64;
9171                               }
9172                             else
9173                               align = (idx_align & 1) ? 32 << size : 0;
9174                             break;
9175
9176                           default:
9177                             abort ();
9178                           }
9179
9180                         func (stream, dis_style_text, "{");
9181                         for (i = 0; i < length; i++)
9182                           {
9183                             if (i > 0)
9184                               func (stream, dis_style_text, ",");
9185                             func (stream, dis_style_register, "d%d[%d]",
9186                                   rd + i * stride, idx);
9187                           }
9188                         func (stream, dis_style_text, "}, [");
9189                         func (stream, dis_style_register, "%s",
9190                               arm_regnames[rn]);
9191                         if (align)
9192                           {
9193                             func (stream, dis_style_text, " :");
9194                             func (stream, dis_style_immediate, "%d", align);
9195                           }
9196                         func (stream, dis_style_text, "]");
9197                         if (rm == 0xd)
9198                           func (stream, dis_style_text, "!");
9199                         else if (rm != 0xf)
9200                           {
9201                             func (stream, dis_style_text, ", ");
9202                             func (stream, dis_style_register, "%s",
9203                                   arm_regnames[rm]);
9204                           }
9205                       }
9206                       break;
9207
9208                     case 'C':
9209                       {
9210                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
9211                         int rn = ((given >> 16) & 0xf);
9212                         int rm = ((given >> 0) & 0xf);
9213                         int align = ((given >> 4) & 0x1);
9214                         int size = ((given >> 6) & 0x3);
9215                         int type = ((given >> 8) & 0x3);
9216                         int n = type + 1;
9217                         int stride = ((given >> 5) & 0x1);
9218                         int ix;
9219
9220                         if (stride && (n == 1))
9221                           n++;
9222                         else
9223                           stride++;
9224
9225                         func (stream, dis_style_text, "{");
9226                         if (stride > 1)
9227                           for (ix = 0; ix != n; ix++)
9228                             {
9229                               if (ix > 0)
9230                                 func (stream, dis_style_text, ",");
9231                               func (stream, dis_style_register, "d%d[]",
9232                                     rd + ix * stride);
9233                             }
9234                         else if (n == 1)
9235                           func (stream, dis_style_register, "d%d[]", rd);
9236                         else
9237                           {
9238                             func (stream, dis_style_register, "d%d[]", rd);
9239                             func (stream, dis_style_text, "-");
9240                             func (stream, dis_style_register, "d%d[]",
9241                                   rd + n - 1);
9242                           }
9243                         func (stream, dis_style_text, "}, [");
9244                         func (stream, dis_style_register, "%s",
9245                               arm_regnames[rn]);
9246                         if (align)
9247                           {
9248                             align = (8 * (type + 1)) << size;
9249                             if (type == 3)
9250                               align = (size > 1) ? align >> 1 : align;
9251                             if (type == 2 || (type == 0 && !size))
9252                               func (stream, dis_style_text,
9253                                     " :<bad align %d>", align);
9254                             else
9255                               {
9256                                 func (stream, dis_style_text, " :");
9257                                 func (stream, dis_style_immediate,
9258                                       "%d", align);
9259                               }
9260                           }
9261                         func (stream, dis_style_text, "]");
9262                         if (rm == 0xd)
9263                           func (stream, dis_style_text, "!");
9264                         else if (rm != 0xf)
9265                           {
9266                             func (stream, dis_style_text, ", ");
9267                             func (stream, dis_style_register, "%s",
9268                                   arm_regnames[rm]);
9269                           }
9270                       }
9271                       break;
9272
9273                     case 'D':
9274                       {
9275                         int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
9276                         int size = (given >> 20) & 3;
9277                         int reg = raw_reg & ((4 << size) - 1);
9278                         int ix = raw_reg >> size >> 2;
9279
9280                         func (stream, dis_style_register, "d%d[%d]", reg, ix);
9281                       }
9282                       break;
9283
9284                     case 'E':
9285                       /* Neon encoded constant for mov, mvn, vorr, vbic.  */
9286                       {
9287                         int bits = 0;
9288                         int cmode = (given >> 8) & 0xf;
9289                         int op = (given >> 5) & 0x1;
9290                         unsigned long value = 0, hival = 0;
9291                         unsigned shift;
9292                         int size = 0;
9293                         int isfloat = 0;
9294
9295                         bits |= ((given >> 24) & 1) << 7;
9296                         bits |= ((given >> 16) & 7) << 4;
9297                         bits |= ((given >> 0) & 15) << 0;
9298
9299                         if (cmode < 8)
9300                           {
9301                             shift = (cmode >> 1) & 3;
9302                             value = (unsigned long) bits << (8 * shift);
9303                             size = 32;
9304                           }
9305                         else if (cmode < 12)
9306                           {
9307                             shift = (cmode >> 1) & 1;
9308                             value = (unsigned long) bits << (8 * shift);
9309                             size = 16;
9310                           }
9311                         else if (cmode < 14)
9312                           {
9313                             shift = (cmode & 1) + 1;
9314                             value = (unsigned long) bits << (8 * shift);
9315                             value |= (1ul << (8 * shift)) - 1;
9316                             size = 32;
9317                           }
9318                         else if (cmode == 14)
9319                           {
9320                             if (op)
9321                               {
9322                                 /* Bit replication into bytes.  */
9323                                 int ix;
9324                                 unsigned long mask;
9325
9326                                 value = 0;
9327                                 hival = 0;
9328                                 for (ix = 7; ix >= 0; ix--)
9329                                   {
9330                                     mask = ((bits >> ix) & 1) ? 0xff : 0;
9331                                     if (ix <= 3)
9332                                       value = (value << 8) | mask;
9333                                     else
9334                                       hival = (hival << 8) | mask;
9335                                   }
9336                                 size = 64;
9337                               }
9338                             else
9339                               {
9340                                 /* Byte replication.  */
9341                                 value = (unsigned long) bits;
9342                                 size = 8;
9343                               }
9344                           }
9345                         else if (!op)
9346                           {
9347                             /* Floating point encoding.  */
9348                             int tmp;
9349
9350                             value = (unsigned long)  (bits & 0x7f) << 19;
9351                             value |= (unsigned long) (bits & 0x80) << 24;
9352                             tmp = bits & 0x40 ? 0x3c : 0x40;
9353                             value |= (unsigned long) tmp << 24;
9354                             size = 32;
9355                             isfloat = 1;
9356                           }
9357                         else
9358                           {
9359                             func (stream, dis_style_text,
9360                                   "<illegal constant %.8x:%x:%x>",
9361                                   bits, cmode, op);
9362                             size = 32;
9363                             break;
9364                           }
9365                         switch (size)
9366                           {
9367                           case 8:
9368                             func (stream, dis_style_immediate, "#%ld", value);
9369                             func (stream, dis_style_comment_start,
9370                                   "\t@ 0x%.2lx", value);
9371                             break;
9372
9373                           case 16:
9374                             func (stream, dis_style_immediate, "#%ld", value);
9375                             func (stream, dis_style_comment_start,
9376                                   "\t@ 0x%.4lx", value);
9377                             break;
9378
9379                           case 32:
9380                             if (isfloat)
9381                               {
9382                                 unsigned char valbytes[4];
9383                                 double fvalue;
9384
9385                                 /* Do this a byte at a time so we don't have to
9386                                    worry about the host's endianness.  */
9387                                 valbytes[0] = value & 0xff;
9388                                 valbytes[1] = (value >> 8) & 0xff;
9389                                 valbytes[2] = (value >> 16) & 0xff;
9390                                 valbytes[3] = (value >> 24) & 0xff;
9391
9392                                 floatformat_to_double
9393                                   (& floatformat_ieee_single_little, valbytes,
9394                                   & fvalue);
9395
9396                                 func (stream, dis_style_immediate,
9397                                       "#%.7g", fvalue);
9398                                 func (stream, dis_style_comment_start,
9399                                       "\t@ 0x%.8lx", value);
9400                               }
9401                             else
9402                               {
9403                                 func (stream, dis_style_immediate, "#%ld",
9404                                       (long) (((value & 0x80000000L) != 0)
9405                                               ? value | ~0xffffffffL : value));
9406                                 func (stream, dis_style_comment_start,
9407                                       "\t@ 0x%.8lx", value);
9408                               }
9409                             break;
9410
9411                           case 64:
9412                             func (stream, dis_style_immediate,
9413                                   "#0x%.8lx%.8lx", hival, value);
9414                             break;
9415
9416                           default:
9417                             abort ();
9418                           }
9419                       }
9420                       break;
9421
9422                     case 'F':
9423                       {
9424                         int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
9425                         int num = (given >> 8) & 0x3;
9426
9427                         func (stream, dis_style_text, "{");
9428                         if (!num)
9429                           func (stream, dis_style_register, "d%d", regno);
9430                         else if (num + regno >= 32)
9431                           {
9432                             func (stream, dis_style_register, "d%d", regno);
9433                             func (stream, dis_style_text, "-<overflow reg d%d",
9434                                   regno + num);
9435                           }
9436                         else
9437                           {
9438                             func (stream, dis_style_register, "d%d", regno);
9439                             func (stream, dis_style_text, "-");
9440                             func (stream, dis_style_register, "d%d",
9441                                   regno + num);
9442                           }
9443                         func (stream, dis_style_text, "}");
9444                       }
9445                       break;
9446
9447
9448                     case '0': case '1': case '2': case '3': case '4':
9449                     case '5': case '6': case '7': case '8': case '9':
9450                       {
9451                         int width;
9452                         unsigned long value;
9453
9454                         c = arm_decode_bitfield (c, given, &value, &width);
9455
9456                         switch (*c)
9457                           {
9458                           case 'r':
9459                             func (stream, dis_style_register, "%s",
9460                                   arm_regnames[value]);
9461                             break;
9462                           case 'd':
9463                             func (stream, base_style, "%ld", value);
9464                             value_in_comment = value;
9465                             break;
9466                           case 'e':
9467                             func (stream, dis_style_immediate, "%ld",
9468                                   (1ul << width) - value);
9469                             break;
9470
9471                           case 'S':
9472                           case 'T':
9473                           case 'U':
9474                             /* Various width encodings.  */
9475                             {
9476                               int base = 8 << (*c - 'S'); /* 8,16 or 32 */
9477                               int limit;
9478                               unsigned low, high;
9479
9480                               c++;
9481                               if (*c >= '0' && *c <= '9')
9482                                 limit = *c - '0';
9483                               else if (*c >= 'a' && *c <= 'f')
9484                                 limit = *c - 'a' + 10;
9485                               else
9486                                 abort ();
9487                               low = limit >> 2;
9488                               high = limit & 3;
9489
9490                               if (value < low || value > high)
9491                                 func (stream, dis_style_text,
9492                                       "<illegal width %d>", base << value);
9493                               else
9494                                 func (stream, base_style, "%d",
9495                                       base << value);
9496                             }
9497                             break;
9498                           case 'R':
9499                             if (given & (1 << 6))
9500                               goto Q;
9501                             /* FALLTHROUGH */
9502                           case 'D':
9503                             func (stream, dis_style_register, "d%ld", value);
9504                             break;
9505                           case 'Q':
9506                           Q:
9507                             if (value & 1)
9508                               func (stream, dis_style_text,
9509                                     "<illegal reg q%ld.5>", value >> 1);
9510                             else
9511                               func (stream, dis_style_register,
9512                                     "q%ld", value >> 1);
9513                             break;
9514
9515                           case '`':
9516                             c++;
9517                             if (value == 0)
9518                               func (stream, dis_style_text, "%c", *c);
9519                             break;
9520                           case '\'':
9521                             c++;
9522                             if (value == ((1ul << width) - 1))
9523                               func (stream, dis_style_text, "%c", *c);
9524                             break;
9525                           case '?':
9526                             func (stream, dis_style_mnemonic, "%c",
9527                                   c[(1 << width) - (int) value]);
9528                             c += 1 << width;
9529                             break;
9530                           default:
9531                             abort ();
9532                           }
9533                       }
9534                       break;
9535
9536                     default:
9537                       abort ();
9538                     }
9539                 }
9540               else
9541                 {
9542                   if (*c == '@')
9543                     base_style = dis_style_comment_start;
9544
9545                   if (*c == '\t')
9546                     base_style = dis_style_text;
9547
9548                   func (stream, base_style, "%c", *c);
9549
9550                 }
9551             }
9552
9553           if (value_in_comment > 32 || value_in_comment < -16)
9554             func (stream, dis_style_comment_start, "\t@ 0x%lx",
9555                   value_in_comment);
9556
9557           if (is_unpredictable)
9558             func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION);
9559
9560           return true;
9561         }
9562     }
9563   return false;
9564 }
9565
9566 /* Print one mve instruction on INFO->STREAM.
9567    Return TRUE if the instuction matched, FALSE if this is not a
9568    recognised mve instruction.  */
9569
9570 static bool
9571 print_insn_mve (struct disassemble_info *info, long given)
9572 {
9573   const struct mopcode32 *insn;
9574   void *stream = info->stream;
9575   fprintf_styled_ftype func = info->fprintf_styled_func;
9576   enum disassembler_style base_style = dis_style_mnemonic;
9577   enum disassembler_style old_base_style = base_style;
9578
9579   for (insn = mve_opcodes; insn->assembler; insn++)
9580     {
9581       if (((given & insn->mask) == insn->value)
9582           && !is_mve_encoding_conflict (given, insn->mve_op))
9583         {
9584           signed long value_in_comment = 0;
9585           bool is_unpredictable = false;
9586           bool is_undefined = false;
9587           const char *c;
9588           enum mve_unpredictable unpredictable_cond = UNPRED_NONE;
9589           enum mve_undefined undefined_cond = UNDEF_NONE;
9590
9591           /* Most vector mve instruction are illegal in a it block.
9592              There are a few exceptions; check for them.  */
9593           if (ifthen_state && !is_mve_okay_in_it (insn->mve_op))
9594             {
9595               is_unpredictable = true;
9596               unpredictable_cond = UNPRED_IT_BLOCK;
9597             }
9598           else if (is_mve_unpredictable (given, insn->mve_op,
9599                                          &unpredictable_cond))
9600             is_unpredictable = true;
9601
9602           if (is_mve_undefined (given, insn->mve_op, &undefined_cond))
9603             is_undefined = true;
9604
9605           /* In "VORR Qd, Qm, Qn", if Qm==Qn, VORR is nothing but VMOV,
9606              i.e "VMOV Qd, Qm".  */
9607           if ((insn->mve_op == MVE_VORR_REG)
9608               && (arm_decode_field (given, 1, 3)
9609                   == arm_decode_field (given, 17, 19)))
9610             continue;
9611
9612           for (c = insn->assembler; *c; c++)
9613             {
9614               if (*c == '%')
9615                 {
9616                   switch (*++c)
9617                     {
9618                     case '{':
9619                       ++c;
9620                       if (*c == '\0')
9621                         abort ();
9622                       old_base_style = base_style;
9623                       base_style = decode_base_style (*c);
9624                       ++c;
9625                       if (*c != ':')
9626                         abort ();
9627                       break;
9628
9629                     case '}':
9630                       base_style = old_base_style;
9631                       break;
9632
9633                     case '%':
9634                       func (stream, base_style, "%%");
9635                       break;
9636
9637                     case 'a':
9638                       /* Don't print anything for '+' as it is implied.  */
9639                       if (arm_decode_field (given, 23, 23) == 0)
9640                         func (stream, dis_style_immediate, "-");
9641                       break;
9642
9643                     case 'c':
9644                       if (ifthen_state)
9645                         func (stream, dis_style_mnemonic, "%s",
9646                               arm_conditional[IFTHEN_COND]);
9647                       break;
9648
9649                     case 'd':
9650                       print_mve_vld_str_addr (info, given, insn->mve_op);
9651                       break;
9652
9653                     case 'i':
9654                       {
9655                         long mve_mask = mve_extract_pred_mask (given);
9656                         func (stream, dis_style_mnemonic, "%s",
9657                               mve_predicatenames[mve_mask]);
9658                       }
9659                       break;
9660
9661                     case 'j':
9662                       {
9663                         unsigned int imm5 = 0;
9664                         imm5 |= arm_decode_field (given, 6, 7);
9665                         imm5 |= (arm_decode_field (given, 12, 14) << 2);
9666                         func (stream, dis_style_immediate, "#%u",
9667                               (imm5 == 0) ? 32 : imm5);
9668                       }
9669                       break;
9670
9671                     case 'k':
9672                       func (stream, dis_style_immediate, "#%u",
9673                             (arm_decode_field (given, 7, 7) == 0) ? 64 : 48);
9674                       break;
9675
9676                     case 'n':
9677                       print_vec_condition (info, given, insn->mve_op);
9678                       break;
9679
9680                     case 'o':
9681                       if (arm_decode_field (given, 0, 0) == 1)
9682                         {
9683                           unsigned long size
9684                             = arm_decode_field (given, 4, 4)
9685                               | (arm_decode_field (given, 6, 6) << 1);
9686
9687                           func (stream, dis_style_text, ", ");
9688                           func (stream, dis_style_sub_mnemonic, "uxtw ");
9689                           func (stream, dis_style_immediate, "#%lu", size);
9690                         }
9691                       break;
9692
9693                     case 'm':
9694                       print_mve_rounding_mode (info, given, insn->mve_op);
9695                       break;
9696
9697                     case 's':
9698                       print_mve_vcvt_size (info, given, insn->mve_op);
9699                       break;
9700
9701                     case 'u':
9702                       {
9703                         unsigned long op1 = arm_decode_field (given, 21, 22);
9704
9705                         if ((insn->mve_op == MVE_VMOV_VEC_LANE_TO_GP))
9706                           {
9707                             /* Check for signed.  */
9708                             if (arm_decode_field (given, 23, 23) == 0)
9709                               {
9710                                 /* We don't print 's' for S32.  */
9711                                 if ((arm_decode_field (given, 5, 6) == 0)
9712                                     && ((op1 == 0) || (op1 == 1)))
9713                                   ;
9714                                 else
9715                                   func (stream, dis_style_mnemonic, "s");
9716                               }
9717                             else
9718                               func (stream, dis_style_mnemonic, "u");
9719                           }
9720                         else
9721                           {
9722                             if (arm_decode_field (given, 28, 28) == 0)
9723                               func (stream, dis_style_mnemonic, "s");
9724                             else
9725                               func (stream, dis_style_mnemonic, "u");
9726                           }
9727                       }
9728                       break;
9729
9730                     case 'v':
9731                       print_instruction_predicate (info);
9732                       break;
9733
9734                     case 'w':
9735                       if (arm_decode_field (given, 21, 21) == 1)
9736                         func (stream, dis_style_text, "!");
9737                       break;
9738
9739                     case 'B':
9740                       print_mve_register_blocks (info, given, insn->mve_op);
9741                       break;
9742
9743                     case 'E':
9744                       /* SIMD encoded constant for mov, mvn, vorr, vbic.  */
9745
9746                       print_simd_imm8 (info, given, 28, insn);
9747                       break;
9748
9749                     case 'N':
9750                       print_mve_vmov_index (info, given);
9751                       break;
9752
9753                     case 'T':
9754                       if (arm_decode_field (given, 12, 12) == 0)
9755                         func (stream, dis_style_mnemonic, "b");
9756                       else
9757                         func (stream, dis_style_mnemonic, "t");
9758                       break;
9759
9760                     case 'X':
9761                       if (arm_decode_field (given, 12, 12) == 1)
9762                         func (stream, dis_style_mnemonic, "x");
9763                       break;
9764
9765                     case '0': case '1': case '2': case '3': case '4':
9766                     case '5': case '6': case '7': case '8': case '9':
9767                       {
9768                         int width;
9769                         unsigned long value;
9770
9771                         c = arm_decode_bitfield (c, given, &value, &width);
9772
9773                         switch (*c)
9774                           {
9775                           case 'Z':
9776                             if (value == 13)
9777                               is_unpredictable = true;
9778                             else if (value == 15)
9779                               func (stream, dis_style_register, "zr");
9780                             else
9781                               func (stream, dis_style_register, "%s",
9782                                     arm_regnames[value]);
9783                             break;
9784
9785                           case 'c':
9786                             func (stream, dis_style_sub_mnemonic, "%s",
9787                                   arm_conditional[value]);
9788                             break;
9789
9790                           case 'C':
9791                             value ^= 1;
9792                             func (stream, dis_style_sub_mnemonic, "%s",
9793                                   arm_conditional[value]);
9794                             break;
9795
9796                           case 'S':
9797                             if (value == 13 || value == 15)
9798                               is_unpredictable = true;
9799                             else
9800                               func (stream, dis_style_register, "%s",
9801                                     arm_regnames[value]);
9802                             break;
9803
9804                           case 's':
9805                             print_mve_size (info,
9806                                             value,
9807                                             insn->mve_op);
9808                             break;
9809                           case 'I':
9810                             if (value == 1)
9811                               func (stream, dis_style_mnemonic, "i");
9812                             break;
9813                           case 'A':
9814                             if (value == 1)
9815                               func (stream, dis_style_mnemonic, "a");
9816                             break;
9817                           case 'h':
9818                             {
9819                               unsigned int odd_reg = (value << 1) | 1;
9820                               func (stream, dis_style_register, "%s",
9821                                     arm_regnames[odd_reg]);
9822                             }
9823                             break;
9824                           case 'i':
9825                             {
9826                               unsigned long imm
9827                                 = arm_decode_field (given, 0, 6);
9828                               unsigned long mod_imm = imm;
9829
9830                               switch (insn->mve_op)
9831                                 {
9832                                 case MVE_VLDRW_GATHER_T5:
9833                                 case MVE_VSTRW_SCATTER_T5:
9834                                   mod_imm = mod_imm << 2;
9835                                   break;
9836                                 case MVE_VSTRD_SCATTER_T6:
9837                                 case MVE_VLDRD_GATHER_T6:
9838                                   mod_imm = mod_imm << 3;
9839                                   break;
9840
9841                                 default:
9842                                   break;
9843                                 }
9844
9845                               func (stream, dis_style_immediate, "%lu",
9846                                     mod_imm);
9847                             }
9848                             break;
9849                           case 'k':
9850                             func (stream, dis_style_immediate, "%lu",
9851                                   64 - value);
9852                             break;
9853                           case 'l':
9854                             {
9855                               unsigned int even_reg = value << 1;
9856                               func (stream, dis_style_register, "%s",
9857                                     arm_regnames[even_reg]);
9858                             }
9859                             break;
9860                           case 'u':
9861                             switch (value)
9862                               {
9863                               case 0:
9864                                 func (stream, dis_style_immediate, "1");
9865                                 break;
9866                               case 1:
9867                                 func (stream, dis_style_immediate, "2");
9868                                 break;
9869                               case 2:
9870                                 func (stream, dis_style_immediate, "4");
9871                                 break;
9872                               case 3:
9873                                 func (stream, dis_style_immediate, "8");
9874                                 break;
9875                               default:
9876                                 break;
9877                               }
9878                             break;
9879                           case 'o':
9880                             print_mve_rotate (info, value, width);
9881                             break;
9882                           case 'r':
9883                             func (stream, dis_style_register, "%s",
9884                                   arm_regnames[value]);
9885                             break;
9886                           case 'd':
9887                             if (mve_shift_insn_p (insn->mve_op))
9888                               print_mve_shift_n (info, given, insn->mve_op);
9889                             else if (insn->mve_op == MVE_VSHLL_T2)
9890                               func (stream, dis_style_immediate, "%s",
9891                                     mve_vec_sizename[value]);
9892                             else
9893                               {
9894                                 if (insn->mve_op == MVE_VSHLC && value == 0)
9895                                   value = 32;
9896                                 func (stream, base_style, "%ld", value);
9897                                 value_in_comment = value;
9898                               }
9899                             break;
9900                           case 'F':
9901                             func (stream, dis_style_register, "s%ld", value);
9902                             break;
9903                           case 'Q':
9904                             if (value & 0x8)
9905                               func (stream, dis_style_text,
9906                                     "<illegal reg q%ld.5>", value);
9907                             else
9908                               func (stream, dis_style_register, "q%ld", value);
9909                             break;
9910                           case 'x':
9911                             func (stream, dis_style_immediate,
9912                                   "0x%08lx", value);
9913                             break;
9914                           default:
9915                             abort ();
9916                           }
9917                         break;
9918                       default:
9919                         abort ();
9920                       }
9921                     }
9922                 }
9923               else
9924                 {
9925                   if (*c == '@')
9926                     base_style = dis_style_comment_start;
9927
9928                   if (*c == '\t')
9929                     base_style = dis_style_text;
9930
9931                   func (stream, base_style, "%c", *c);
9932                 }
9933             }
9934
9935           if (value_in_comment > 32 || value_in_comment < -16)
9936             func (stream, dis_style_comment_start, "\t@ 0x%lx",
9937                   value_in_comment);
9938
9939           if (is_unpredictable)
9940             print_mve_unpredictable (info, unpredictable_cond);
9941
9942           if (is_undefined)
9943             print_mve_undefined (info, undefined_cond);
9944
9945           if (!vpt_block_state.in_vpt_block
9946               && !ifthen_state
9947               && is_vpt_instruction (given))
9948             mark_inside_vpt_block (given);
9949           else if (vpt_block_state.in_vpt_block)
9950             update_vpt_block_state ();
9951
9952           return true;
9953         }
9954     }
9955   return false;
9956 }
9957
9958
9959 /* Return the name of a v7A special register.  */
9960
9961 static const char *
9962 banked_regname (unsigned reg)
9963 {
9964   switch (reg)
9965     {
9966       case 15: return "CPSR";
9967       case 32: return "R8_usr";
9968       case 33: return "R9_usr";
9969       case 34: return "R10_usr";
9970       case 35: return "R11_usr";
9971       case 36: return "R12_usr";
9972       case 37: return "SP_usr";
9973       case 38: return "LR_usr";
9974       case 40: return "R8_fiq";
9975       case 41: return "R9_fiq";
9976       case 42: return "R10_fiq";
9977       case 43: return "R11_fiq";
9978       case 44: return "R12_fiq";
9979       case 45: return "SP_fiq";
9980       case 46: return "LR_fiq";
9981       case 48: return "LR_irq";
9982       case 49: return "SP_irq";
9983       case 50: return "LR_svc";
9984       case 51: return "SP_svc";
9985       case 52: return "LR_abt";
9986       case 53: return "SP_abt";
9987       case 54: return "LR_und";
9988       case 55: return "SP_und";
9989       case 60: return "LR_mon";
9990       case 61: return "SP_mon";
9991       case 62: return "ELR_hyp";
9992       case 63: return "SP_hyp";
9993       case 79: return "SPSR";
9994       case 110: return "SPSR_fiq";
9995       case 112: return "SPSR_irq";
9996       case 114: return "SPSR_svc";
9997       case 116: return "SPSR_abt";
9998       case 118: return "SPSR_und";
9999       case 124: return "SPSR_mon";
10000       case 126: return "SPSR_hyp";
10001       default: return NULL;
10002     }
10003 }
10004
10005 /* Return the name of the DMB/DSB option.  */
10006 static const char *
10007 data_barrier_option (unsigned option)
10008 {
10009   switch (option & 0xf)
10010     {
10011     case 0xf: return "sy";
10012     case 0xe: return "st";
10013     case 0xd: return "ld";
10014     case 0xb: return "ish";
10015     case 0xa: return "ishst";
10016     case 0x9: return "ishld";
10017     case 0x7: return "un";
10018     case 0x6: return "unst";
10019     case 0x5: return "nshld";
10020     case 0x3: return "osh";
10021     case 0x2: return "oshst";
10022     case 0x1: return "oshld";
10023     default:  return NULL;
10024     }
10025 }
10026
10027 /* Print one ARM instruction from PC on INFO->STREAM.  */
10028
10029 static void
10030 print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
10031 {
10032   const struct opcode32 *insn;
10033   void *stream = info->stream;
10034   fprintf_styled_ftype func = info->fprintf_styled_func;
10035   struct arm_private_data *private_data = info->private_data;
10036   enum disassembler_style base_style = dis_style_mnemonic;
10037   enum disassembler_style old_base_style = base_style;
10038
10039   if (print_insn_coprocessor (pc, info, given, false))
10040     return;
10041
10042   if (print_insn_neon (info, given, false))
10043     return;
10044
10045   if (print_insn_generic_coprocessor (pc, info, given, false))
10046     return;
10047
10048   for (insn = arm_opcodes; insn->assembler; insn++)
10049     {
10050       if ((given & insn->mask) != insn->value)
10051         continue;
10052
10053       if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
10054         continue;
10055
10056       /* Special case: an instruction with all bits set in the condition field
10057          (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
10058          or by the catchall at the end of the table.  */
10059       if ((given & 0xF0000000) != 0xF0000000
10060           || (insn->mask & 0xF0000000) == 0xF0000000
10061           || (insn->mask == 0 && insn->value == 0))
10062         {
10063           unsigned long u_reg = 16;
10064           unsigned long U_reg = 16;
10065           bool is_unpredictable = false;
10066           signed long value_in_comment = 0;
10067           const char *c;
10068
10069           for (c = insn->assembler; *c; c++)
10070             {
10071               if (*c == '%')
10072                 {
10073                   bool allow_unpredictable = false;
10074
10075                   switch (*++c)
10076                     {
10077                     case '{':
10078                       ++c;
10079                       if (*c == '\0')
10080                         abort ();
10081                       old_base_style = base_style;
10082                       base_style = decode_base_style (*c);
10083                       ++c;
10084                       if (*c != ':')
10085                         abort ();
10086                       break;
10087
10088                     case '}':
10089                       base_style = old_base_style;
10090                       break;
10091
10092                     case '%':
10093                       func (stream, base_style, "%%");
10094                       break;
10095
10096                     case 'a':
10097                       value_in_comment = print_arm_address (pc, info, given);
10098                       break;
10099
10100                     case 'P':
10101                       /* Set P address bit and use normal address
10102                          printing routine.  */
10103                       value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
10104                       break;
10105
10106                     case 'S':
10107                       allow_unpredictable = true;
10108                       /* Fall through.  */
10109                     case 's':
10110                       if ((given & 0x004f0000) == 0x004f0000)
10111                         {
10112                           /* PC relative with immediate offset.  */
10113                           bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
10114
10115                           if (PRE_BIT_SET)
10116                             {
10117                               /* Elide positive zero offset.  */
10118                               if (offset || NEGATIVE_BIT_SET)
10119                                 {
10120                                   func (stream, dis_style_text, "[");
10121                                   func (stream, dis_style_register, "pc");
10122                                   func (stream, dis_style_text, ", ");
10123                                   func (stream, dis_style_immediate, "#%s%d",
10124                                         (NEGATIVE_BIT_SET ? "-" : ""),
10125                                         (int) offset);
10126                                   func (stream, dis_style_text, "]");
10127                                 }
10128                               else
10129                                 {
10130                                   func (stream, dis_style_text, "[");
10131                                   func (stream, dis_style_register, "pc");
10132                                   func (stream, dis_style_text, "]");
10133                                 }
10134                               if (NEGATIVE_BIT_SET)
10135                                 offset = -offset;
10136                               func (stream, dis_style_comment_start, "\t@ ");
10137                               info->print_address_func (offset + pc + 8, info);
10138                             }
10139                           else
10140                             {
10141                               /* Always show the offset.  */
10142                               func (stream, dis_style_text, "[");
10143                               func (stream, dis_style_register, "pc");
10144                               func (stream, dis_style_text, "], ");
10145                               func (stream, dis_style_immediate, "#%s%d",
10146                                     NEGATIVE_BIT_SET ? "-" : "", (int) offset);
10147                               if (! allow_unpredictable)
10148                                 is_unpredictable = true;
10149                             }
10150                         }
10151                       else
10152                         {
10153                           int offset = ((given & 0xf00) >> 4) | (given & 0xf);
10154
10155                           func (stream, dis_style_text, "[");
10156                           func (stream, dis_style_register, "%s",
10157                                 arm_regnames[(given >> 16) & 0xf]);
10158
10159                           if (PRE_BIT_SET)
10160                             {
10161                               if (IMMEDIATE_BIT_SET)
10162                                 {
10163                                   /* Elide offset for non-writeback
10164                                      positive zero.  */
10165                                   if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
10166                                       || offset)
10167                                     {
10168                                       func (stream, dis_style_text, ", ");
10169                                       func (stream, dis_style_immediate,
10170                                             "#%s%d",
10171                                             (NEGATIVE_BIT_SET ? "-" : ""),
10172                                             offset);
10173                                     }
10174
10175                                   if (NEGATIVE_BIT_SET)
10176                                     offset = -offset;
10177
10178                                   value_in_comment = offset;
10179                                 }
10180                               else
10181                                 {
10182                                   /* Register Offset or Register Pre-Indexed.  */
10183                                   func (stream, dis_style_text, ", %s",
10184                                         NEGATIVE_BIT_SET ? "-" : "");
10185                                   func (stream, dis_style_register, "%s",
10186                                         arm_regnames[given & 0xf]);
10187
10188                                   /* Writing back to the register that is the source/
10189                                      destination of the load/store is unpredictable.  */
10190                                   if (! allow_unpredictable
10191                                       && WRITEBACK_BIT_SET
10192                                       && ((given & 0xf) == ((given >> 12) & 0xf)))
10193                                     is_unpredictable = true;
10194                                 }
10195
10196                               func (stream, dis_style_text, "]%s",
10197                                     WRITEBACK_BIT_SET ? "!" : "");
10198                             }
10199                           else
10200                             {
10201                               if (IMMEDIATE_BIT_SET)
10202                                 {
10203                                   /* Immediate Post-indexed.  */
10204                                   /* PR 10924: Offset must be printed, even if it is zero.  */
10205                                   func (stream, dis_style_text, "], ");
10206                                   func (stream, dis_style_immediate, "#%s%d",
10207                                         NEGATIVE_BIT_SET ? "-" : "", offset);
10208                                   if (NEGATIVE_BIT_SET)
10209                                     offset = -offset;
10210                                   value_in_comment = offset;
10211                                 }
10212                               else
10213                                 {
10214                                   /* Register Post-indexed.  */
10215                                   func (stream, dis_style_text, "], %s",
10216                                         NEGATIVE_BIT_SET ? "-" : "");
10217                                   func (stream, dis_style_register, "%s",
10218                                         arm_regnames[given & 0xf]);
10219
10220                                   /* Writing back to the register that is the source/
10221                                      destination of the load/store is unpredictable.  */
10222                                   if (! allow_unpredictable
10223                                       && (given & 0xf) == ((given >> 12) & 0xf))
10224                                     is_unpredictable = true;
10225                                 }
10226
10227                               if (! allow_unpredictable)
10228                                 {
10229                                   /* Writeback is automatically implied by post- addressing.
10230                                      Setting the W bit is unnecessary and ARM specify it as
10231                                      being unpredictable.  */
10232                                   if (WRITEBACK_BIT_SET
10233                                       /* Specifying the PC register as the post-indexed
10234                                          registers is also unpredictable.  */
10235                                       || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
10236                                     is_unpredictable = true;
10237                                 }
10238                             }
10239                         }
10240                       break;
10241
10242                     case 'b':
10243                       {
10244                         bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
10245                         bfd_vma target = disp * 4 + pc + 8;
10246                         info->print_address_func (target, info);
10247
10248                         /* Fill in instruction information.  */
10249                         info->insn_info_valid = 1;
10250                         info->insn_type = dis_branch;
10251                         info->target = target;
10252                       }
10253                       break;
10254
10255                     case 'c':
10256                       if (((given >> 28) & 0xf) != 0xe)
10257                         func (stream, dis_style_mnemonic, "%s",
10258                               arm_conditional [(given >> 28) & 0xf]);
10259                       break;
10260
10261                     case 'm':
10262                       {
10263                         int started = 0;
10264                         int reg;
10265
10266                         func (stream, dis_style_text, "{");
10267                         for (reg = 0; reg < 16; reg++)
10268                           if ((given & (1 << reg)) != 0)
10269                             {
10270                               if (started)
10271                                 func (stream, dis_style_text, ", ");
10272                               started = 1;
10273                               func (stream, dis_style_register, "%s",
10274                                     arm_regnames[reg]);
10275                             }
10276                         func (stream, dis_style_text, "}");
10277                         if (! started)
10278                           is_unpredictable = true;
10279                       }
10280                       break;
10281
10282                     case 'q':
10283                       arm_decode_shift (given, func, stream, false);
10284                       break;
10285
10286                     case 'o':
10287                       if ((given & 0x02000000) != 0)
10288                         {
10289                           unsigned int rotate = (given & 0xf00) >> 7;
10290                           unsigned int immed = (given & 0xff);
10291                           unsigned int a, i;
10292
10293                           a = (immed << ((32 - rotate) & 31)
10294                                | immed >> rotate) & 0xffffffff;
10295                           /* If there is another encoding with smaller rotate,
10296                              the rotate should be specified directly.  */
10297                           for (i = 0; i < 32; i += 2)
10298                             if ((a << i | a >> ((32 - i) & 31)) <= 0xff)
10299                               break;
10300
10301                           if (i != rotate)
10302                             {
10303                               func (stream, dis_style_immediate, "#%d", immed);
10304                               func (stream, dis_style_text, ", ");
10305                               func (stream, dis_style_immediate, "%d", rotate);
10306                             }
10307                           else
10308                             func (stream, dis_style_immediate, "#%d", a);
10309                           value_in_comment = a;
10310                         }
10311                       else
10312                         arm_decode_shift (given, func, stream, true);
10313                       break;
10314
10315                     case 'p':
10316                       if ((given & 0x0000f000) == 0x0000f000)
10317                         {
10318                           arm_feature_set arm_ext_v6 =
10319                             ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
10320
10321                           /* The p-variants of tst/cmp/cmn/teq are the pre-V6
10322                              mechanism for setting PSR flag bits.  They are
10323                              obsolete in V6 onwards.  */
10324                           if (! ARM_CPU_HAS_FEATURE (private_data->features, \
10325                                                      arm_ext_v6))
10326                             func (stream, dis_style_mnemonic, "p");
10327                           else
10328                             is_unpredictable = true;
10329                         }
10330                       break;
10331
10332                     case 't':
10333                       if ((given & 0x01200000) == 0x00200000)
10334                         func (stream, dis_style_mnemonic, "t");
10335                       break;
10336
10337                     case 'A':
10338                       {
10339                         int offset = given & 0xff;
10340
10341                         value_in_comment = offset * 4;
10342                         if (NEGATIVE_BIT_SET)
10343                           value_in_comment = - value_in_comment;
10344
10345                         func (stream, dis_style_text, "[%s",
10346                               arm_regnames [(given >> 16) & 0xf]);
10347
10348                         if (PRE_BIT_SET)
10349                           {
10350                             if (offset)
10351                               func (stream, dis_style_text, ", #%d]%s",
10352                                     (int) value_in_comment,
10353                                     WRITEBACK_BIT_SET ? "!" : "");
10354                             else
10355                               func (stream, dis_style_text, "]");
10356                           }
10357                         else
10358                           {
10359                             func (stream, dis_style_text, "]");
10360
10361                             if (WRITEBACK_BIT_SET)
10362                               {
10363                                 if (offset)
10364                                   func (stream, dis_style_text,
10365                                         ", #%d", (int) value_in_comment);
10366                               }
10367                             else
10368                               {
10369                                 func (stream, dis_style_text,
10370                                       ", {%d}", (int) offset);
10371                                 value_in_comment = offset;
10372                               }
10373                           }
10374                       }
10375                       break;
10376
10377                     case 'B':
10378                       /* Print ARM V5 BLX(1) address: pc+25 bits.  */
10379                       {
10380                         bfd_vma address;
10381                         bfd_vma offset = 0;
10382
10383                         if (! NEGATIVE_BIT_SET)
10384                           /* Is signed, hi bits should be ones.  */
10385                           offset = (-1) ^ 0x00ffffff;
10386
10387                         /* Offset is (SignExtend(offset field)<<2).  */
10388                         offset += given & 0x00ffffff;
10389                         offset <<= 2;
10390                         address = offset + pc + 8;
10391
10392                         if (given & 0x01000000)
10393                           /* H bit allows addressing to 2-byte boundaries.  */
10394                           address += 2;
10395
10396                         info->print_address_func (address, info);
10397
10398                         /* Fill in instruction information.  */
10399                         info->insn_info_valid = 1;
10400                         info->insn_type = dis_branch;
10401                         info->target = address;
10402                       }
10403                       break;
10404
10405                     case 'C':
10406                       if ((given & 0x02000200) == 0x200)
10407                         {
10408                           const char * name;
10409                           unsigned sysm = (given & 0x004f0000) >> 16;
10410
10411                           sysm |= (given & 0x300) >> 4;
10412                           name = banked_regname (sysm);
10413
10414                           if (name != NULL)
10415                             func (stream, dis_style_register, "%s", name);
10416                           else
10417                             func (stream, dis_style_text,
10418                                   "(UNDEF: %lu)", (unsigned long) sysm);
10419                         }
10420                       else
10421                         {
10422                           func (stream, dis_style_register, "%cPSR_",
10423                                 (given & 0x00400000) ? 'S' : 'C');
10424
10425                           if (given & 0x80000)
10426                             func (stream, dis_style_register, "f");
10427                           if (given & 0x40000)
10428                             func (stream, dis_style_register, "s");
10429                           if (given & 0x20000)
10430                             func (stream, dis_style_register, "x");
10431                           if (given & 0x10000)
10432                             func (stream, dis_style_register, "c");
10433                         }
10434                       break;
10435
10436                     case 'U':
10437                       if ((given & 0xf0) == 0x60)
10438                         {
10439                           switch (given & 0xf)
10440                             {
10441                             case 0xf:
10442                               func (stream, dis_style_sub_mnemonic, "sy");
10443                               break;
10444                             default:
10445                               func (stream, dis_style_immediate, "#%d",
10446                                     (int) given & 0xf);
10447                               break;
10448                             }
10449                         }
10450                       else
10451                         {
10452                           const char * opt = data_barrier_option (given & 0xf);
10453                           if (opt != NULL)
10454                             func (stream, dis_style_sub_mnemonic, "%s", opt);
10455                           else
10456                             func (stream, dis_style_immediate,
10457                                   "#%d", (int) given & 0xf);
10458                         }
10459                       break;
10460
10461                     case '0': case '1': case '2': case '3': case '4':
10462                     case '5': case '6': case '7': case '8': case '9':
10463                       {
10464                         int width;
10465                         unsigned long value;
10466
10467                         c = arm_decode_bitfield (c, given, &value, &width);
10468
10469                         switch (*c)
10470                           {
10471                           case 'R':
10472                             if (value == 15)
10473                               is_unpredictable = true;
10474                             /* Fall through.  */
10475                           case 'r':
10476                           case 'T':
10477                             /* We want register + 1 when decoding T.  */
10478                             if (*c == 'T')
10479                               value = (value + 1) & 0xf;
10480
10481                             if (c[1] == 'u')
10482                               {
10483                                 /* Eat the 'u' character.  */
10484                                 ++ c;
10485
10486                                 if (u_reg == value)
10487                                   is_unpredictable = true;
10488                                 u_reg = value;
10489                               }
10490                             if (c[1] == 'U')
10491                               {
10492                                 /* Eat the 'U' character.  */
10493                                 ++ c;
10494
10495                                 if (U_reg == value)
10496                                   is_unpredictable = true;
10497                                 U_reg = value;
10498                               }
10499                             func (stream, dis_style_register, "%s",
10500                                   arm_regnames[value]);
10501                             break;
10502                           case 'd':
10503                             func (stream, base_style, "%ld", value);
10504                             value_in_comment = value;
10505                             break;
10506                           case 'b':
10507                             func (stream, dis_style_immediate,
10508                                   "%ld", value * 8);
10509                             value_in_comment = value * 8;
10510                             break;
10511                           case 'W':
10512                             func (stream, dis_style_immediate,
10513                                   "%ld", value + 1);
10514                             value_in_comment = value + 1;
10515                             break;
10516                           case 'x':
10517                             func (stream, dis_style_immediate,
10518                                   "0x%08lx", value);
10519
10520                             /* Some SWI instructions have special
10521                                meanings.  */
10522                             if ((given & 0x0fffffff) == 0x0FF00000)
10523                               func (stream, dis_style_comment_start,
10524                                     "\t@ IMB");
10525                             else if ((given & 0x0fffffff) == 0x0FF00001)
10526                               func (stream, dis_style_comment_start,
10527                                     "\t@ IMBRange");
10528                             break;
10529                           case 'X':
10530                             func (stream, dis_style_immediate,
10531                                   "%01lx", value & 0xf);
10532                             value_in_comment = value;
10533                             break;
10534                           case '`':
10535                             c++;
10536                             if (value == 0)
10537                               func (stream, dis_style_text, "%c", *c);
10538                             break;
10539                           case '\'':
10540                             c++;
10541                             if (value == ((1ul << width) - 1))
10542                               func (stream, base_style, "%c", *c);
10543                             break;
10544                           case '?':
10545                             func (stream, base_style, "%c",
10546                                   c[(1 << width) - (int) value]);
10547                             c += 1 << width;
10548                             break;
10549                           default:
10550                             abort ();
10551                           }
10552                       }
10553                       break;
10554
10555                     case 'e':
10556                       {
10557                         int imm;
10558
10559                         imm = (given & 0xf) | ((given & 0xfff00) >> 4);
10560                         func (stream, dis_style_immediate, "%d", imm);
10561                         value_in_comment = imm;
10562                       }
10563                       break;
10564
10565                     case 'E':
10566                       /* LSB and WIDTH fields of BFI or BFC.  The machine-
10567                          language instruction encodes LSB and MSB.  */
10568                       {
10569                         long msb = (given & 0x001f0000) >> 16;
10570                         long lsb = (given & 0x00000f80) >> 7;
10571                         long w = msb - lsb + 1;
10572
10573                         if (w > 0)
10574                           {
10575                             func (stream, dis_style_immediate, "#%lu", lsb);
10576                             func (stream, dis_style_text, ", ");
10577                             func (stream, dis_style_immediate, "#%lu", w);
10578                           }
10579                         else
10580                           func (stream, dis_style_text,
10581                                 "(invalid: %lu:%lu)", lsb, msb);
10582                       }
10583                       break;
10584
10585                     case 'R':
10586                       /* Get the PSR/banked register name.  */
10587                       {
10588                         const char * name;
10589                         unsigned sysm = (given & 0x004f0000) >> 16;
10590
10591                         sysm |= (given & 0x300) >> 4;
10592                         name = banked_regname (sysm);
10593
10594                         if (name != NULL)
10595                           func (stream, dis_style_register, "%s", name);
10596                         else
10597                           func (stream, dis_style_text,
10598                                 "(UNDEF: %lu)", (unsigned long) sysm);
10599                       }
10600                       break;
10601
10602                     case 'V':
10603                       /* 16-bit unsigned immediate from a MOVT or MOVW
10604                          instruction, encoded in bits 0:11 and 15:19.  */
10605                       {
10606                         long hi = (given & 0x000f0000) >> 4;
10607                         long lo = (given & 0x00000fff);
10608                         long imm16 = hi | lo;
10609
10610                         func (stream, dis_style_immediate, "#%lu", imm16);
10611                         value_in_comment = imm16;
10612                       }
10613                       break;
10614
10615                     default:
10616                       abort ();
10617                     }
10618                 }
10619               else
10620                 {
10621
10622                   if (*c == '@')
10623                     base_style = dis_style_comment_start;
10624
10625                   if (*c == '\t')
10626                     base_style = dis_style_text;
10627
10628                   func (stream, base_style, "%c", *c);
10629                 }
10630             }
10631
10632           if (value_in_comment > 32 || value_in_comment < -16)
10633             func (stream, dis_style_comment_start, "\t@ 0x%lx",
10634                   (value_in_comment & 0xffffffffUL));
10635
10636           if (is_unpredictable)
10637             func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION);
10638
10639           return;
10640         }
10641     }
10642   func (stream, dis_style_comment_start, UNKNOWN_INSTRUCTION_32BIT,
10643         (unsigned) given);
10644   return;
10645 }
10646
10647 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM.  */
10648
10649 static void
10650 print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
10651 {
10652   const struct opcode16 *insn;
10653   void *stream = info->stream;
10654   fprintf_styled_ftype func = info->fprintf_styled_func;
10655   enum disassembler_style base_style = dis_style_mnemonic;
10656   enum disassembler_style old_base_style = base_style;
10657
10658   for (insn = thumb_opcodes; insn->assembler; insn++)
10659     if ((given & insn->mask) == insn->value)
10660       {
10661         signed long value_in_comment = 0;
10662         const char *c = insn->assembler;
10663
10664         for (; *c; c++)
10665           {
10666             int domaskpc = 0;
10667             int domasklr = 0;
10668
10669             if (*c != '%')
10670               {
10671                 if (*c == '@')
10672                   base_style = dis_style_comment_start;
10673
10674                 if (*c == '\t')
10675                   base_style = dis_style_text;
10676
10677                 func (stream, base_style, "%c", *c);
10678
10679                 continue;
10680               }
10681
10682             switch (*++c)
10683               {
10684                 case '{':
10685                   ++c;
10686                   if (*c == '\0')
10687                     abort ();
10688                   old_base_style = base_style;
10689                   base_style = decode_base_style (*c);
10690                   ++c;
10691                   if (*c != ':')
10692                     abort ();
10693                   break;
10694
10695                 case '}':
10696                   base_style = old_base_style;
10697                   break;
10698
10699               case '%':
10700                 func (stream, base_style, "%%");
10701                 break;
10702
10703               case 'c':
10704                 if (ifthen_state)
10705                   func (stream, dis_style_mnemonic, "%s",
10706                         arm_conditional[IFTHEN_COND]);
10707                 break;
10708
10709               case 'C':
10710                 if (ifthen_state)
10711                   func (stream, dis_style_mnemonic, "%s",
10712                         arm_conditional[IFTHEN_COND]);
10713                 else
10714                   func (stream, dis_style_mnemonic, "s");
10715                 break;
10716
10717               case 'I':
10718                 {
10719                   unsigned int tmp;
10720
10721                   ifthen_next_state = given & 0xff;
10722                   for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
10723                     func (stream, dis_style_mnemonic,
10724                           ((given ^ tmp) & 0x10) ? "e" : "t");
10725                   func (stream, dis_style_text, "\t");
10726                   func (stream, dis_style_sub_mnemonic, "%s",
10727                         arm_conditional[(given >> 4) & 0xf]);
10728                 }
10729                 break;
10730
10731               case 'x':
10732                 if (ifthen_next_state)
10733                   func (stream, dis_style_comment_start,
10734                         "\t@ unpredictable branch in IT block\n");
10735                 break;
10736
10737               case 'X':
10738                 if (ifthen_state)
10739                   func (stream, dis_style_comment_start,
10740                         "\t@ unpredictable <IT:%s>",
10741                         arm_conditional[IFTHEN_COND]);
10742                 break;
10743
10744               case 'S':
10745                 {
10746                   long reg;
10747
10748                   reg = (given >> 3) & 0x7;
10749                   if (given & (1 << 6))
10750                     reg += 8;
10751
10752                   func (stream, dis_style_register, "%s", arm_regnames[reg]);
10753                 }
10754                 break;
10755
10756               case 'D':
10757                 {
10758                   long reg;
10759
10760                   reg = given & 0x7;
10761                   if (given & (1 << 7))
10762                     reg += 8;
10763
10764                   func (stream, dis_style_register, "%s", arm_regnames[reg]);
10765                 }
10766                 break;
10767
10768               case 'N':
10769                 if (given & (1 << 8))
10770                   domasklr = 1;
10771                 /* Fall through.  */
10772               case 'O':
10773                 if (*c == 'O' && (given & (1 << 8)))
10774                   domaskpc = 1;
10775                 /* Fall through.  */
10776               case 'M':
10777                 {
10778                   int started = 0;
10779                   int reg;
10780
10781                   func (stream, dis_style_text, "{");
10782
10783                   /* It would be nice if we could spot
10784                      ranges, and generate the rS-rE format: */
10785                   for (reg = 0; (reg < 8); reg++)
10786                     if ((given & (1 << reg)) != 0)
10787                       {
10788                         if (started)
10789                           func (stream, dis_style_text, ", ");
10790                         started = 1;
10791                         func (stream, dis_style_register, "%s",
10792                               arm_regnames[reg]);
10793                       }
10794
10795                   if (domasklr)
10796                     {
10797                       if (started)
10798                         func (stream, dis_style_text, ", ");
10799                       started = 1;
10800                       func (stream, dis_style_register, "%s",
10801                             arm_regnames[14] /* "lr" */);
10802                     }
10803
10804                   if (domaskpc)
10805                     {
10806                       if (started)
10807                         func (stream, dis_style_text, ", ");
10808                       func (stream, dis_style_register, "%s",
10809                             arm_regnames[15] /* "pc" */);
10810                     }
10811
10812                   func (stream, dis_style_text, "}");
10813                 }
10814                 break;
10815
10816               case 'W':
10817                 /* Print writeback indicator for a LDMIA.  We are doing a
10818                    writeback if the base register is not in the register
10819                    mask.  */
10820                 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
10821                   func (stream, dis_style_text, "!");
10822                 break;
10823
10824               case 'b':
10825                 /* Print ARM V6T2 CZB address: pc+4+6 bits.  */
10826                 {
10827                   bfd_vma address = (pc + 4
10828                                      + ((given & 0x00f8) >> 2)
10829                                      + ((given & 0x0200) >> 3));
10830                   info->print_address_func (address, info);
10831
10832                   /* Fill in instruction information.  */
10833                   info->insn_info_valid = 1;
10834                   info->insn_type = dis_branch;
10835                   info->target = address;
10836                 }
10837                 break;
10838
10839               case 's':
10840                 /* Right shift immediate -- bits 6..10; 1-31 print
10841                    as themselves, 0 prints as 32.  */
10842                 {
10843                   long imm = (given & 0x07c0) >> 6;
10844                   if (imm == 0)
10845                     imm = 32;
10846                   func (stream, dis_style_immediate, "#%ld", imm);
10847                 }
10848                 break;
10849
10850               case '0': case '1': case '2': case '3': case '4':
10851               case '5': case '6': case '7': case '8': case '9':
10852                 {
10853                   int bitstart = *c++ - '0';
10854                   int bitend = 0;
10855
10856                   while (*c >= '0' && *c <= '9')
10857                     bitstart = (bitstart * 10) + *c++ - '0';
10858
10859                   switch (*c)
10860                     {
10861                     case '-':
10862                       {
10863                         bfd_vma reg;
10864
10865                         c++;
10866                         while (*c >= '0' && *c <= '9')
10867                           bitend = (bitend * 10) + *c++ - '0';
10868                         if (!bitend)
10869                           abort ();
10870                         reg = given >> bitstart;
10871                         reg &= ((bfd_vma) 2 << (bitend - bitstart)) - 1;
10872
10873                         switch (*c)
10874                           {
10875                           case 'r':
10876                             func (stream, dis_style_register, "%s",
10877                                   arm_regnames[reg]);
10878                             break;
10879
10880                           case 'd':
10881                             func (stream, dis_style_immediate, "%ld",
10882                                   (long) reg);
10883                             value_in_comment = reg;
10884                             break;
10885
10886                           case 'H':
10887                             func (stream, dis_style_immediate, "%ld",
10888                                   (long) (reg << 1));
10889                             value_in_comment = reg << 1;
10890                             break;
10891
10892                           case 'W':
10893                             func (stream, dis_style_immediate, "%ld",
10894                                   (long) (reg << 2));
10895                             value_in_comment = reg << 2;
10896                             break;
10897
10898                           case 'a':
10899                             /* PC-relative address -- the bottom two
10900                                bits of the address are dropped
10901                                before the calculation.  */
10902                             info->print_address_func
10903                               (((pc + 4) & ~3) + (reg << 2), info);
10904                             value_in_comment = 0;
10905                             break;
10906
10907                           case 'x':
10908                             func (stream, dis_style_immediate, "0x%04lx",
10909                                   (long) reg);
10910                             break;
10911
10912                           case 'B':
10913                             reg = ((reg ^ (1 << bitend)) - (1 << bitend));
10914                             bfd_vma target = reg * 2 + pc + 4;
10915                             info->print_address_func (target, info);
10916                             value_in_comment = 0;
10917
10918                             /* Fill in instruction information.  */
10919                             info->insn_info_valid = 1;
10920                             info->insn_type = dis_branch;
10921                             info->target = target;
10922                             break;
10923
10924                           case 'c':
10925                             func (stream, dis_style_mnemonic, "%s",
10926                                   arm_conditional [reg]);
10927                             break;
10928
10929                           default:
10930                             abort ();
10931                           }
10932                       }
10933                       break;
10934
10935                     case '\'':
10936                       c++;
10937                       if ((given & (1 << bitstart)) != 0)
10938                         func (stream, base_style, "%c", *c);
10939                       break;
10940
10941                     case '?':
10942                       ++c;
10943                       if ((given & (1 << bitstart)) != 0)
10944                         func (stream, base_style, "%c", *c++);
10945                       else
10946                         func (stream, base_style, "%c", *++c);
10947                       break;
10948
10949                     default:
10950                       abort ();
10951                     }
10952                 }
10953                 break;
10954
10955               default:
10956                 abort ();
10957               }
10958           }
10959
10960         if (value_in_comment > 32 || value_in_comment < -16)
10961           func (stream, dis_style_comment_start,
10962                 "\t@ 0x%lx", value_in_comment);
10963         return;
10964       }
10965
10966   /* No match.  */
10967   func (stream, dis_style_comment_start, UNKNOWN_INSTRUCTION_16BIT,
10968         (unsigned) given);
10969   return;
10970 }
10971
10972 /* Return the name of an V7M special register.  */
10973
10974 static const char *
10975 psr_name (int regno)
10976 {
10977   switch (regno)
10978     {
10979     case 0x0: return "APSR";
10980     case 0x1: return "IAPSR";
10981     case 0x2: return "EAPSR";
10982     case 0x3: return "PSR";
10983     case 0x5: return "IPSR";
10984     case 0x6: return "EPSR";
10985     case 0x7: return "IEPSR";
10986     case 0x8: return "MSP";
10987     case 0x9: return "PSP";
10988     case 0xa: return "MSPLIM";
10989     case 0xb: return "PSPLIM";
10990     case 0x10: return "PRIMASK";
10991     case 0x11: return "BASEPRI";
10992     case 0x12: return "BASEPRI_MAX";
10993     case 0x13: return "FAULTMASK";
10994     case 0x14: return "CONTROL";
10995     case 0x88: return "MSP_NS";
10996     case 0x89: return "PSP_NS";
10997     case 0x8a: return "MSPLIM_NS";
10998     case 0x8b: return "PSPLIM_NS";
10999     case 0x90: return "PRIMASK_NS";
11000     case 0x91: return "BASEPRI_NS";
11001     case 0x93: return "FAULTMASK_NS";
11002     case 0x94: return "CONTROL_NS";
11003     case 0x98: return "SP_NS";
11004     default: return "<unknown>";
11005     }
11006 }
11007
11008 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM.  */
11009
11010 static void
11011 print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
11012 {
11013   const struct opcode32 *insn;
11014   void *stream = info->stream;
11015   fprintf_styled_ftype func = info->fprintf_styled_func;
11016   bool is_mve = is_mve_architecture (info);
11017   enum disassembler_style base_style = dis_style_mnemonic;
11018   enum disassembler_style old_base_style = base_style;
11019
11020   if (print_insn_coprocessor (pc, info, given, true))
11021     return;
11022
11023   if (!is_mve && print_insn_neon (info, given, true))
11024     return;
11025
11026   if (is_mve && print_insn_mve (info, given))
11027     return;
11028
11029   if (print_insn_cde (info, given, true))
11030     return;
11031
11032   if (print_insn_generic_coprocessor (pc, info, given, true))
11033     return;
11034
11035   for (insn = thumb32_opcodes; insn->assembler; insn++)
11036     if ((given & insn->mask) == insn->value)
11037       {
11038         bool is_clrm = false;
11039         bool is_unpredictable = false;
11040         signed long value_in_comment = 0;
11041         const char *c = insn->assembler;
11042
11043         for (; *c; c++)
11044           {
11045             if (*c != '%')
11046               {
11047                 if (*c == '@')
11048                   base_style = dis_style_comment_start;
11049                 if (*c == '\t')
11050                   base_style = dis_style_text;
11051                 func (stream, base_style, "%c", *c);
11052                 continue;
11053               }
11054
11055             switch (*++c)
11056               {
11057               case '{':
11058                 ++c;
11059                 if (*c == '\0')
11060                   abort ();
11061                 old_base_style = base_style;
11062                 base_style = decode_base_style (*c);
11063                 ++c;
11064                 if (*c != ':')
11065                   abort ();
11066                 break;
11067
11068               case '}':
11069                 base_style = old_base_style;
11070                 break;
11071
11072               case '%':
11073                 func (stream, base_style, "%%");
11074                 break;
11075
11076               case 'c':
11077                 if (ifthen_state)
11078                   func (stream, dis_style_mnemonic, "%s",
11079                         arm_conditional[IFTHEN_COND]);
11080                 break;
11081
11082               case 'x':
11083                 if (ifthen_next_state)
11084                   func (stream, dis_style_comment_start,
11085                         "\t@ unpredictable branch in IT block\n");
11086                 break;
11087
11088               case 'X':
11089                 if (ifthen_state)
11090                   func (stream, dis_style_comment_start,
11091                         "\t@ unpredictable <IT:%s>",
11092                         arm_conditional[IFTHEN_COND]);
11093                 break;
11094
11095               case 'I':
11096                 {
11097                   unsigned int imm12 = 0;
11098
11099                   imm12 |= (given & 0x000000ffu);
11100                   imm12 |= (given & 0x00007000u) >> 4;
11101                   imm12 |= (given & 0x04000000u) >> 15;
11102                   func (stream, dis_style_immediate, "#%u", imm12);
11103                   value_in_comment = imm12;
11104                 }
11105                 break;
11106
11107               case 'M':
11108                 {
11109                   unsigned int bits = 0, imm, imm8, mod;
11110
11111                   bits |= (given & 0x000000ffu);
11112                   bits |= (given & 0x00007000u) >> 4;
11113                   bits |= (given & 0x04000000u) >> 15;
11114                   imm8 = (bits & 0x0ff);
11115                   mod = (bits & 0xf00) >> 8;
11116                   switch (mod)
11117                     {
11118                     case 0: imm = imm8; break;
11119                     case 1: imm = ((imm8 << 16) | imm8); break;
11120                     case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
11121                     case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
11122                     default:
11123                       mod  = (bits & 0xf80) >> 7;
11124                       imm8 = (bits & 0x07f) | 0x80;
11125                       imm  = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
11126                     }
11127                   func (stream, dis_style_immediate, "#%u", imm);
11128                   value_in_comment = imm;
11129                 }
11130                 break;
11131
11132               case 'J':
11133                 {
11134                   unsigned int imm = 0;
11135
11136                   imm |= (given & 0x000000ffu);
11137                   imm |= (given & 0x00007000u) >> 4;
11138                   imm |= (given & 0x04000000u) >> 15;
11139                   imm |= (given & 0x000f0000u) >> 4;
11140                   func (stream, dis_style_immediate, "#%u", imm);
11141                   value_in_comment = imm;
11142                 }
11143                 break;
11144
11145               case 'K':
11146                 {
11147                   unsigned int imm = 0;
11148
11149                   imm |= (given & 0x000f0000u) >> 16;
11150                   imm |= (given & 0x00000ff0u) >> 0;
11151                   imm |= (given & 0x0000000fu) << 12;
11152                   func (stream, dis_style_immediate, "#%u", imm);
11153                   value_in_comment = imm;
11154                 }
11155                 break;
11156
11157               case 'H':
11158                 {
11159                   unsigned int imm = 0;
11160
11161                   imm |= (given & 0x000f0000u) >> 4;
11162                   imm |= (given & 0x00000fffu) >> 0;
11163                   func (stream, dis_style_immediate, "#%u", imm);
11164                   value_in_comment = imm;
11165                 }
11166                 break;
11167
11168               case 'V':
11169                 {
11170                   unsigned int imm = 0;
11171
11172                   imm |= (given & 0x00000fffu);
11173                   imm |= (given & 0x000f0000u) >> 4;
11174                   func (stream, dis_style_immediate, "#%u", imm);
11175                   value_in_comment = imm;
11176                 }
11177                 break;
11178
11179               case 'S':
11180                 {
11181                   unsigned int reg = (given & 0x0000000fu);
11182                   unsigned int stp = (given & 0x00000030u) >> 4;
11183                   unsigned int imm = 0;
11184                   imm |= (given & 0x000000c0u) >> 6;
11185                   imm |= (given & 0x00007000u) >> 10;
11186
11187                   func (stream, dis_style_register, "%s", arm_regnames[reg]);
11188                   switch (stp)
11189                     {
11190                     case 0:
11191                       if (imm > 0)
11192                         {
11193                           func (stream, dis_style_text, ", ");
11194                           func (stream, dis_style_sub_mnemonic, "lsl ");
11195                           func (stream, dis_style_immediate, "#%u", imm);
11196                         }
11197                       break;
11198
11199                     case 1:
11200                       if (imm == 0)
11201                         imm = 32;
11202                       func (stream, dis_style_text, ", ");
11203                       func (stream, dis_style_sub_mnemonic, "lsr ");
11204                       func (stream, dis_style_immediate, "#%u", imm);
11205                       break;
11206
11207                     case 2:
11208                       if (imm == 0)
11209                         imm = 32;
11210                       func (stream, dis_style_text, ", ");
11211                       func (stream, dis_style_sub_mnemonic, "asr ");
11212                       func (stream, dis_style_immediate, "#%u", imm);
11213                       break;
11214
11215                     case 3:
11216                       if (imm == 0)
11217                         {
11218                           func (stream, dis_style_text, ", ");
11219                           func (stream, dis_style_sub_mnemonic, "rrx");
11220                         }
11221                       else
11222                         {
11223                           func (stream, dis_style_text, ", ");
11224                           func (stream, dis_style_sub_mnemonic, "ror ");
11225                           func (stream, dis_style_immediate, "#%u", imm);
11226                         }
11227                     }
11228                 }
11229                 break;
11230
11231               case 'a':
11232                 {
11233                   unsigned int Rn  = (given & 0x000f0000) >> 16;
11234                   unsigned int U   = ! NEGATIVE_BIT_SET;
11235                   unsigned int op  = (given & 0x00000f00) >> 8;
11236                   unsigned int i12 = (given & 0x00000fff);
11237                   unsigned int i8  = (given & 0x000000ff);
11238                   bool writeback = false, postind = false;
11239                   bfd_vma offset = 0;
11240
11241                   func (stream, dis_style_text, "[");
11242                   func (stream, dis_style_register, "%s", arm_regnames[Rn]);
11243                   if (U) /* 12-bit positive immediate offset.  */
11244                     {
11245                       offset = i12;
11246                       if (Rn != 15)
11247                         value_in_comment = offset;
11248                     }
11249                   else if (Rn == 15) /* 12-bit negative immediate offset.  */
11250                     offset = - (int) i12;
11251                   else if (op == 0x0) /* Shifted register offset.  */
11252                     {
11253                       unsigned int Rm = (i8 & 0x0f);
11254                       unsigned int sh = (i8 & 0x30) >> 4;
11255
11256                       func (stream, dis_style_text, ", ");
11257                       func (stream, dis_style_register, "%s",
11258                             arm_regnames[Rm]);
11259                       if (sh)
11260                         {
11261                           func (stream, dis_style_text, ", ");
11262                           func (stream, dis_style_sub_mnemonic, "lsl ");
11263                           func (stream, dis_style_immediate, "#%u", sh);
11264                         }
11265                       func (stream, dis_style_text, "]");
11266                       break;
11267                     }
11268                   else switch (op)
11269                     {
11270                     case 0xE:  /* 8-bit positive immediate offset.  */
11271                       offset = i8;
11272                       break;
11273
11274                     case 0xC:  /* 8-bit negative immediate offset.  */
11275                       offset = -i8;
11276                       break;
11277
11278                     case 0xF:  /* 8-bit + preindex with wb.  */
11279                       offset = i8;
11280                       writeback = true;
11281                       break;
11282
11283                     case 0xD:  /* 8-bit - preindex with wb.  */
11284                       offset = -i8;
11285                       writeback = true;
11286                       break;
11287
11288                     case 0xB:  /* 8-bit + postindex.  */
11289                       offset = i8;
11290                       postind = true;
11291                       break;
11292
11293                     case 0x9:  /* 8-bit - postindex.  */
11294                       offset = -i8;
11295                       postind = true;
11296                       break;
11297
11298                     default:
11299                       func (stream, dis_style_text, ", <undefined>]");
11300                       goto skip;
11301                     }
11302
11303                   if (postind)
11304                     {
11305                       func (stream, dis_style_text, "], ");
11306                       func (stream, dis_style_immediate, "#%d", (int) offset);
11307                     }
11308                   else
11309                     {
11310                       if (offset)
11311                         {
11312                           func (stream, dis_style_text, ", ");
11313                           func (stream, dis_style_immediate, "#%d",
11314                                 (int) offset);
11315                         }
11316                       func (stream, dis_style_text, writeback ? "]!" : "]");
11317                     }
11318
11319                   if (Rn == 15)
11320                     {
11321                       func (stream, dis_style_comment_start, "\t@ ");
11322                       info->print_address_func (((pc + 4) & ~3) + offset, info);
11323                     }
11324                 }
11325               skip:
11326                 break;
11327
11328               case 'A':
11329                 {
11330                   unsigned int U   = ! NEGATIVE_BIT_SET;
11331                   unsigned int W   = WRITEBACK_BIT_SET;
11332                   unsigned int Rn  = (given & 0x000f0000) >> 16;
11333                   unsigned int off = (given & 0x000000ff);
11334
11335                   func (stream, dis_style_text, "[");
11336                   func (stream, dis_style_register, "%s", arm_regnames[Rn]);
11337
11338                   if (PRE_BIT_SET)
11339                     {
11340                       if (off || !U)
11341                         {
11342                           func (stream, dis_style_text, ", ");
11343                           func (stream, dis_style_immediate, "#%c%u",
11344                                 U ? '+' : '-', off * 4);
11345                           value_in_comment = off * 4 * (U ? 1 : -1);
11346                         }
11347                       func (stream, dis_style_text, "]");
11348                       if (W)
11349                         func (stream, dis_style_text, "!");
11350                     }
11351                   else
11352                     {
11353                       func (stream, dis_style_text, "], ");
11354                       if (W)
11355                         {
11356                           func (stream, dis_style_immediate, "#%c%u",
11357                                 U ? '+' : '-', off * 4);
11358                           value_in_comment = off * 4 * (U ? 1 : -1);
11359                         }
11360                       else
11361                         {
11362                           func (stream, dis_style_text, "{");
11363                           func (stream, dis_style_immediate, "%u", off);
11364                           func (stream, dis_style_text, "}");
11365                           value_in_comment = off;
11366                         }
11367                     }
11368                 }
11369                 break;
11370
11371               case 'w':
11372                 {
11373                   unsigned int Sbit = (given & 0x01000000) >> 24;
11374                   unsigned int type = (given & 0x00600000) >> 21;
11375
11376                   switch (type)
11377                     {
11378                     case 0:
11379                       func (stream, dis_style_mnemonic, Sbit ? "sb" : "b");
11380                       break;
11381                     case 1:
11382                       func (stream, dis_style_mnemonic, Sbit ? "sh" : "h");
11383                       break;
11384                     case 2:
11385                       if (Sbit)
11386                         func (stream, dis_style_text, "??");
11387                       break;
11388                     case 3:
11389                       func (stream, dis_style_text, "??");
11390                       break;
11391                     }
11392                 }
11393                 break;
11394
11395               case 'n':
11396                 is_clrm = true;
11397                 /* Fall through.  */
11398               case 'm':
11399                 {
11400                   int started = 0;
11401                   int reg;
11402
11403                   func (stream, dis_style_text, "{");
11404                   for (reg = 0; reg < 16; reg++)
11405                     if ((given & (1 << reg)) != 0)
11406                       {
11407                         if (started)
11408                           func (stream, dis_style_text, ", ");
11409                         started = 1;
11410                         if (is_clrm && reg == 13)
11411                           func (stream, dis_style_text, "(invalid: %s)",
11412                                 arm_regnames[reg]);
11413                         else if (is_clrm && reg == 15)
11414                           func (stream, dis_style_register, "%s", "APSR");
11415                         else
11416                           func (stream, dis_style_register, "%s",
11417                                 arm_regnames[reg]);
11418                       }
11419                   func (stream, dis_style_text, "}");
11420                 }
11421                 break;
11422
11423               case 'E':
11424                 {
11425                   unsigned int msb = (given & 0x0000001f);
11426                   unsigned int lsb = 0;
11427
11428                   lsb |= (given & 0x000000c0u) >> 6;
11429                   lsb |= (given & 0x00007000u) >> 10;
11430                   func (stream, dis_style_immediate, "#%u", lsb);
11431                   func (stream, dis_style_text, ", ");
11432                   func (stream, dis_style_immediate, "#%u", msb - lsb + 1);
11433                 }
11434                 break;
11435
11436               case 'F':
11437                 {
11438                   unsigned int width = (given & 0x0000001f) + 1;
11439                   unsigned int lsb = 0;
11440
11441                   lsb |= (given & 0x000000c0u) >> 6;
11442                   lsb |= (given & 0x00007000u) >> 10;
11443                   func (stream, dis_style_immediate, "#%u", lsb);
11444                   func (stream, dis_style_text, ", ");
11445                   func (stream, dis_style_immediate, "#%u", width);
11446                 }
11447                 break;
11448
11449               case 'G':
11450                 {
11451                   unsigned int boff = (((given & 0x07800000) >> 23) << 1);
11452                   func (stream, dis_style_immediate, "%x", boff);
11453                 }
11454                 break;
11455
11456               case 'W':
11457                 {
11458                   unsigned int immA = (given & 0x001f0000u) >> 16;
11459                   unsigned int immB = (given & 0x000007feu) >> 1;
11460                   unsigned int immC = (given & 0x00000800u) >> 11;
11461                   bfd_vma offset = 0;
11462
11463                   offset |= immA << 12;
11464                   offset |= immB << 2;
11465                   offset |= immC << 1;
11466                   /* Sign extend.  */
11467                   offset = (offset & 0x10000) ? offset - (1 << 17) : offset;
11468
11469                   info->print_address_func (pc + 4 + offset, info);
11470                 }
11471                 break;
11472
11473               case 'Y':
11474                 {
11475                   unsigned int immA = (given & 0x007f0000u) >> 16;
11476                   unsigned int immB = (given & 0x000007feu) >> 1;
11477                   unsigned int immC = (given & 0x00000800u) >> 11;
11478                   bfd_vma offset = 0;
11479
11480                   offset |= immA << 12;
11481                   offset |= immB << 2;
11482                   offset |= immC << 1;
11483                   /* Sign extend.  */
11484                   offset = (offset & 0x40000) ? offset - (1 << 19) : offset;
11485
11486                   info->print_address_func (pc + 4 + offset, info);
11487                 }
11488                 break;
11489
11490               case 'Z':
11491                 {
11492                   unsigned int immA = (given & 0x00010000u) >> 16;
11493                   unsigned int immB = (given & 0x000007feu) >> 1;
11494                   unsigned int immC = (given & 0x00000800u) >> 11;
11495                   bfd_vma offset = 0;
11496
11497                   offset |= immA << 12;
11498                   offset |= immB << 2;
11499                   offset |= immC << 1;
11500                   /* Sign extend.  */
11501                   offset = (offset & 0x1000) ? offset - (1 << 13) : offset;
11502
11503                   info->print_address_func (pc + 4 + offset, info);
11504
11505                   unsigned int T    = (given & 0x00020000u) >> 17;
11506                   unsigned int endoffset = (((given & 0x07800000) >> 23) << 1);
11507                   unsigned int boffset   = (T == 1) ? 4 : 2;
11508                   func (stream, dis_style_text, ", ");
11509                   func (stream, dis_style_immediate, "%x",
11510                         endoffset + boffset);
11511                 }
11512                 break;
11513
11514               case 'Q':
11515                 {
11516                   unsigned int immh = (given & 0x000007feu) >> 1;
11517                   unsigned int imml = (given & 0x00000800u) >> 11;
11518                   bfd_vma imm32 = 0;
11519
11520                   imm32 |= immh << 2;
11521                   imm32 |= imml << 1;
11522
11523                   info->print_address_func (pc + 4 + imm32, info);
11524                 }
11525                 break;
11526
11527               case 'P':
11528                 {
11529                   unsigned int immh = (given & 0x000007feu) >> 1;
11530                   unsigned int imml = (given & 0x00000800u) >> 11;
11531                   bfd_vma imm32 = 0;
11532
11533                   imm32 |= immh << 2;
11534                   imm32 |= imml << 1;
11535
11536                   info->print_address_func (pc + 4 - imm32, info);
11537                 }
11538                 break;
11539
11540               case 'b':
11541                 {
11542                   unsigned int S = (given & 0x04000000u) >> 26;
11543                   unsigned int J1 = (given & 0x00002000u) >> 13;
11544                   unsigned int J2 = (given & 0x00000800u) >> 11;
11545                   bfd_vma offset = 0;
11546
11547                   offset |= !S << 20;
11548                   offset |= J2 << 19;
11549                   offset |= J1 << 18;
11550                   offset |= (given & 0x003f0000) >> 4;
11551                   offset |= (given & 0x000007ff) << 1;
11552                   offset -= (1 << 20);
11553
11554                   bfd_vma target = pc + 4 + offset;
11555                   info->print_address_func (target, info);
11556
11557                   /* Fill in instruction information.  */
11558                   info->insn_info_valid = 1;
11559                   info->insn_type = dis_branch;
11560                   info->target = target;
11561                 }
11562                 break;
11563
11564               case 'B':
11565                 {
11566                   unsigned int S = (given & 0x04000000u) >> 26;
11567                   unsigned int I1 = (given & 0x00002000u) >> 13;
11568                   unsigned int I2 = (given & 0x00000800u) >> 11;
11569                   bfd_vma offset = 0;
11570
11571                   offset |= !S << 24;
11572                   offset |= !(I1 ^ S) << 23;
11573                   offset |= !(I2 ^ S) << 22;
11574                   offset |= (given & 0x03ff0000u) >> 4;
11575                   offset |= (given & 0x000007ffu) << 1;
11576                   offset -= (1 << 24);
11577                   offset += pc + 4;
11578
11579                   /* BLX target addresses are always word aligned.  */
11580                   if ((given & 0x00001000u) == 0)
11581                       offset &= ~2u;
11582
11583                   info->print_address_func (offset, info);
11584
11585                   /* Fill in instruction information.  */
11586                   info->insn_info_valid = 1;
11587                   info->insn_type = dis_branch;
11588                   info->target = offset;
11589                 }
11590                 break;
11591
11592               case 's':
11593                 {
11594                   unsigned int shift = 0;
11595
11596                   shift |= (given & 0x000000c0u) >> 6;
11597                   shift |= (given & 0x00007000u) >> 10;
11598                   if (WRITEBACK_BIT_SET)
11599                     {
11600                       func (stream, dis_style_text, ", ");
11601                       func (stream, dis_style_sub_mnemonic, "asr ");
11602                       func (stream, dis_style_immediate, "#%u", shift);
11603                     }
11604                   else if (shift)
11605                     {
11606                       func (stream, dis_style_text, ", ");
11607                       func (stream, dis_style_sub_mnemonic, "lsl ");
11608                       func (stream, dis_style_immediate, "#%u", shift);
11609                     }
11610                   /* else print nothing - lsl #0 */
11611                 }
11612                 break;
11613
11614               case 'R':
11615                 {
11616                   unsigned int rot = (given & 0x00000030) >> 4;
11617
11618                   if (rot)
11619                     {
11620                       func (stream, dis_style_text, ", ");
11621                       func (stream, dis_style_sub_mnemonic, "ror ");
11622                       func (stream, dis_style_immediate, "#%u", rot * 8);
11623                     }
11624                 }
11625                 break;
11626
11627               case 'U':
11628                 if ((given & 0xf0) == 0x60)
11629                   {
11630                     switch (given & 0xf)
11631                       {
11632                       case 0xf:
11633                         func (stream, dis_style_sub_mnemonic, "sy");
11634                         break;
11635                       default:
11636                         func (stream, dis_style_immediate, "#%d",
11637                               (int) given & 0xf);
11638                         break;
11639                       }
11640                   }
11641                 else
11642                   {
11643                     const char * opt = data_barrier_option (given & 0xf);
11644                     if (opt != NULL)
11645                       func (stream, dis_style_sub_mnemonic, "%s", opt);
11646                     else
11647                       func (stream, dis_style_immediate, "#%d",
11648                             (int) given & 0xf);
11649                    }
11650                 break;
11651
11652               case 'C':
11653                 if ((given & 0xff) == 0)
11654                   {
11655                     func (stream, dis_style_register, "%cPSR_",
11656                           (given & 0x100000) ? 'S' : 'C');
11657
11658                     if (given & 0x800)
11659                       func (stream, dis_style_register, "f");
11660                     if (given & 0x400)
11661                       func (stream, dis_style_register, "s");
11662                     if (given & 0x200)
11663                       func (stream, dis_style_register, "x");
11664                     if (given & 0x100)
11665                       func (stream, dis_style_register, "c");
11666                   }
11667                 else if ((given & 0x20) == 0x20)
11668                   {
11669                     char const* name;
11670                     unsigned sysm = (given & 0xf00) >> 8;
11671
11672                     sysm |= (given & 0x30);
11673                     sysm |= (given & 0x00100000) >> 14;
11674                     name = banked_regname (sysm);
11675
11676                     if (name != NULL)
11677                       func (stream, dis_style_register, "%s", name);
11678                     else
11679                       func (stream, dis_style_text,
11680                             "(UNDEF: %lu)", (unsigned long) sysm);
11681                   }
11682                 else
11683                   {
11684                     func (stream, dis_style_register, "%s",
11685                           psr_name (given & 0xff));
11686                   }
11687                 break;
11688
11689               case 'D':
11690                 if (((given & 0xff) == 0)
11691                     || ((given & 0x20) == 0x20))
11692                   {
11693                     char const* name;
11694                     unsigned sm = (given & 0xf0000) >> 16;
11695
11696                     sm |= (given & 0x30);
11697                     sm |= (given & 0x00100000) >> 14;
11698                     name = banked_regname (sm);
11699
11700                     if (name != NULL)
11701                       func (stream, dis_style_register, "%s", name);
11702                     else
11703                       func (stream, dis_style_text,
11704                             "(UNDEF: %lu)", (unsigned long) sm);
11705                   }
11706                 else
11707                   func (stream, dis_style_register, "%s",
11708                         psr_name (given & 0xff));
11709                 break;
11710
11711               case '0': case '1': case '2': case '3': case '4':
11712               case '5': case '6': case '7': case '8': case '9':
11713                 {
11714                   int width;
11715                   unsigned long val;
11716
11717                   c = arm_decode_bitfield (c, given, &val, &width);
11718
11719                   switch (*c)
11720                     {
11721                     case 's':
11722                       if (val <= 3)
11723                         func (stream, dis_style_mnemonic, "%s",
11724                               mve_vec_sizename[val]);
11725                       else
11726                         func (stream, dis_style_text, "<undef size>");
11727                       break;
11728
11729                     case 'd':
11730                       func (stream, base_style, "%lu", val);
11731                       value_in_comment = val;
11732                       break;
11733
11734                     case 'D':
11735                       func (stream, dis_style_immediate, "%lu", val + 1);
11736                       value_in_comment = val + 1;
11737                       break;
11738
11739                     case 'W':
11740                       func (stream, dis_style_immediate, "%lu", val * 4);
11741                       value_in_comment = val * 4;
11742                       break;
11743
11744                     case 'S':
11745                       if (val == 13)
11746                         is_unpredictable = true;
11747                       /* Fall through.  */
11748                     case 'R':
11749                       if (val == 15)
11750                         is_unpredictable = true;
11751                       /* Fall through.  */
11752                     case 'r':
11753                       func (stream, dis_style_register, "%s",
11754                             arm_regnames[val]);
11755                       break;
11756
11757                     case 'c':
11758                       func (stream, base_style, "%s", arm_conditional[val]);
11759                       break;
11760
11761                     case '\'':
11762                       c++;
11763                       if (val == ((1ul << width) - 1))
11764                         func (stream, base_style, "%c", *c);
11765                       break;
11766
11767                     case '`':
11768                       c++;
11769                       if (val == 0)
11770                         func (stream, dis_style_immediate, "%c", *c);
11771                       break;
11772
11773                     case '?':
11774                       func (stream, dis_style_mnemonic, "%c",
11775                             c[(1 << width) - (int) val]);
11776                       c += 1 << width;
11777                       break;
11778
11779                     case 'x':
11780                       func (stream, dis_style_immediate, "0x%lx",
11781                             val & 0xffffffffUL);
11782                       break;
11783
11784                     default:
11785                       abort ();
11786                     }
11787                 }
11788                 break;
11789
11790               case 'L':
11791                 /* PR binutils/12534
11792                    If we have a PC relative offset in an LDRD or STRD
11793                    instructions then display the decoded address.  */
11794                 if (((given >> 16) & 0xf) == 0xf)
11795                   {
11796                     bfd_vma offset = (given & 0xff) * 4;
11797
11798                     if ((given & (1 << 23)) == 0)
11799                       offset = - offset;
11800                     func (stream, dis_style_comment_start, "\t@ ");
11801                     info->print_address_func ((pc & ~3) + 4 + offset, info);
11802                   }
11803                 break;
11804
11805               default:
11806                 abort ();
11807               }
11808           }
11809
11810         if (value_in_comment > 32 || value_in_comment < -16)
11811           func (stream, dis_style_comment_start, "\t@ 0x%lx",
11812                 value_in_comment);
11813
11814         if (is_unpredictable)
11815           func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION);
11816
11817         return;
11818       }
11819
11820   /* No match.  */
11821   func (stream, dis_style_comment_start, UNKNOWN_INSTRUCTION_32BIT,
11822         (unsigned) given);
11823   return;
11824 }
11825
11826 /* Print data bytes on INFO->STREAM.  */
11827
11828 static void
11829 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
11830                  struct disassemble_info *info,
11831                  long given)
11832 {
11833   fprintf_styled_ftype func = info->fprintf_styled_func;
11834
11835   switch (info->bytes_per_chunk)
11836     {
11837     case 1:
11838       func (info->stream, dis_style_assembler_directive, ".byte");
11839       func (info->stream, dis_style_text, "\t");
11840       func (info->stream, dis_style_immediate, "0x%02lx", given);
11841       break;
11842     case 2:
11843       func (info->stream, dis_style_assembler_directive, ".short");
11844       func (info->stream, dis_style_text, "\t");
11845       func (info->stream, dis_style_immediate, "0x%04lx", given);
11846       break;
11847     case 4:
11848       func (info->stream, dis_style_assembler_directive, ".word");
11849       func (info->stream, dis_style_text, "\t");
11850       func (info->stream, dis_style_immediate, "0x%08lx", given);
11851       break;
11852     default:
11853       abort ();
11854     }
11855 }
11856
11857 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
11858    being displayed in symbol relative addresses.
11859
11860    Also disallow private symbol, with __tagsym$$ prefix,
11861    from ARM RVCT toolchain being displayed.  */
11862
11863 bool
11864 arm_symbol_is_valid (asymbol * sym,
11865                      struct disassemble_info * info ATTRIBUTE_UNUSED)
11866 {
11867   const char * name;
11868
11869   if (sym == NULL)
11870     return false;
11871
11872   name = bfd_asymbol_name (sym);
11873
11874   return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
11875 }
11876
11877 /* Parse the string of disassembler options.  */
11878
11879 static void
11880 parse_arm_disassembler_options (const char *options)
11881 {
11882   const char *opt;
11883
11884   force_thumb = false;
11885   FOR_EACH_DISASSEMBLER_OPTION (opt, options)
11886     {
11887       if (startswith (opt, "reg-names-"))
11888         {
11889           unsigned int i;
11890           for (i = 0; i < NUM_ARM_OPTIONS; i++)
11891             if (disassembler_options_cmp (opt, regnames[i].name) == 0)
11892               {
11893                 regname_selected = i;
11894                 break;
11895               }
11896
11897           if (i >= NUM_ARM_OPTIONS)
11898             /* xgettext: c-format */
11899             opcodes_error_handler (_("unrecognised register name set: %s"),
11900                                    opt);
11901         }
11902       else if (startswith (opt, "force-thumb"))
11903         force_thumb = 1;
11904       else if (startswith (opt, "no-force-thumb"))
11905         force_thumb = 0;
11906       else if (startswith (opt, "coproc"))
11907         {
11908           const char *procptr = opt + sizeof ("coproc") - 1;
11909           char *endptr;
11910           uint8_t coproc_number = strtol (procptr, &endptr, 10);
11911           if (endptr != procptr + 1 || coproc_number > 7)
11912             {
11913               opcodes_error_handler (_("cde coprocessor not between 0-7: %s"),
11914                                      opt);
11915               continue;
11916             }
11917           if (*endptr != '=')
11918             {
11919               opcodes_error_handler (_("coproc must have an argument: %s"),
11920                                      opt);
11921               continue;
11922             }
11923           endptr += 1;
11924           if (startswith (endptr, "generic"))
11925             cde_coprocs &= ~(1 << coproc_number);
11926           else if (startswith (endptr, "cde")
11927                    || startswith (endptr, "CDE"))
11928             cde_coprocs |= (1 << coproc_number);
11929           else
11930             {
11931               opcodes_error_handler (
11932                   _("coprocN argument takes options \"generic\","
11933                     " \"cde\", or \"CDE\": %s"), opt);
11934             }
11935         }
11936       else
11937         /* xgettext: c-format */
11938         opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
11939     }
11940
11941   return;
11942 }
11943
11944 static bool
11945 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
11946                          enum map_type *map_symbol);
11947
11948 /* Search back through the insn stream to determine if this instruction is
11949    conditionally executed.  */
11950
11951 static void
11952 find_ifthen_state (bfd_vma pc,
11953                    struct disassemble_info *info,
11954                    bool little)
11955 {
11956   unsigned char b[2];
11957   unsigned int insn;
11958   int status;
11959   /* COUNT is twice the number of instructions seen.  It will be odd if we
11960      just crossed an instruction boundary.  */
11961   int count;
11962   int it_count;
11963   unsigned int seen_it;
11964   bfd_vma addr;
11965
11966   ifthen_address = pc;
11967   ifthen_state = 0;
11968
11969   addr = pc;
11970   count = 1;
11971   it_count = 0;
11972   seen_it = 0;
11973   /* Scan backwards looking for IT instructions, keeping track of where
11974      instruction boundaries are.  We don't know if something is actually an
11975      IT instruction until we find a definite instruction boundary.  */
11976   for (;;)
11977     {
11978       if (addr == 0 || info->symbol_at_address_func (addr, info))
11979         {
11980           /* A symbol must be on an instruction boundary, and will not
11981              be within an IT block.  */
11982           if (seen_it && (count & 1))
11983             break;
11984
11985           return;
11986         }
11987       addr -= 2;
11988       status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
11989       if (status)
11990         return;
11991
11992       if (little)
11993         insn = (b[0]) | (b[1] << 8);
11994       else
11995         insn = (b[1]) | (b[0] << 8);
11996       if (seen_it)
11997         {
11998           if ((insn & 0xf800) < 0xe800)
11999             {
12000               /* Addr + 2 is an instruction boundary.  See if this matches
12001                  the expected boundary based on the position of the last
12002                  IT candidate.  */
12003               if (count & 1)
12004                 break;
12005               seen_it = 0;
12006             }
12007         }
12008       if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
12009         {
12010           enum map_type type = MAP_ARM;
12011           bool found = mapping_symbol_for_insn (addr, info, &type);
12012
12013           if (!found || (found && type == MAP_THUMB))
12014             {
12015               /* This could be an IT instruction.  */
12016               seen_it = insn;
12017               it_count = count >> 1;
12018             }
12019         }
12020       if ((insn & 0xf800) >= 0xe800)
12021         count++;
12022       else
12023         count = (count + 2) | 1;
12024       /* IT blocks contain at most 4 instructions.  */
12025       if (count >= 8 && !seen_it)
12026         return;
12027     }
12028   /* We found an IT instruction.  */
12029   ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
12030   if ((ifthen_state & 0xf) == 0)
12031     ifthen_state = 0;
12032 }
12033
12034 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
12035    mapping symbol.  */
12036
12037 static int
12038 is_mapping_symbol (struct disassemble_info *info,
12039                    int n,
12040                    enum map_type *map_type)
12041 {
12042   const char *name = bfd_asymbol_name (info->symtab[n]);
12043
12044   if (name[0] == '$'
12045       && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
12046       && (name[2] == 0 || name[2] == '.'))
12047     {
12048       *map_type = ((name[1] == 'a') ? MAP_ARM
12049                    : (name[1] == 't') ? MAP_THUMB
12050                    : MAP_DATA);
12051       return true;
12052     }
12053
12054   return false;
12055 }
12056
12057 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
12058    Returns nonzero if *MAP_TYPE was set.  */
12059
12060 static int
12061 get_map_sym_type (struct disassemble_info *info,
12062                   int n,
12063                   enum map_type *map_type)
12064 {
12065   /* If the symbol is in a different section, ignore it.  */
12066   if (info->section != NULL && info->section != info->symtab[n]->section)
12067     return false;
12068
12069   return is_mapping_symbol (info, n, map_type);
12070 }
12071
12072 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
12073    Returns nonzero if *MAP_TYPE was set.  */
12074
12075 static int
12076 get_sym_code_type (struct disassemble_info *info,
12077                    int n,
12078                    enum map_type *map_type)
12079 {
12080   elf_symbol_type *es;
12081   unsigned int type;
12082   asymbol * sym;
12083
12084   /* If the symbol is in a different section, ignore it.  */
12085   if (info->section != NULL && info->section != info->symtab[n]->section)
12086     return false;
12087
12088   /* PR 30230: Reject non-ELF symbols, eg synthetic ones.  */
12089   sym = info->symtab[n];
12090   if (bfd_asymbol_flavour (sym) != bfd_target_elf_flavour)
12091     return false;
12092
12093   es = (elf_symbol_type *) sym;
12094   type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
12095
12096   /* If the symbol has function type then use that.  */
12097   if (type == STT_FUNC || type == STT_GNU_IFUNC)
12098     {
12099       if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
12100           == ST_BRANCH_TO_THUMB)
12101         *map_type = MAP_THUMB;
12102       else
12103         *map_type = MAP_ARM;
12104       return true;
12105     }
12106
12107   return false;
12108 }
12109
12110 /* Search the mapping symbol state for instruction at pc.  This is only
12111    applicable for elf target.
12112
12113    There is an assumption Here, info->private_data contains the correct AND
12114    up-to-date information about current scan process.  The information will be
12115    used to speed this search process.
12116
12117    Return TRUE if the mapping state can be determined, and map_symbol
12118    will be updated accordingly.  Otherwise, return FALSE.  */
12119
12120 static bool
12121 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
12122                          enum map_type *map_symbol)
12123 {
12124   bfd_vma addr, section_vma = 0;
12125   int n, last_sym = -1;
12126   bool found = false;
12127   bool can_use_search_opt_p = false;
12128
12129   /* Sanity check.  */
12130   if (info == NULL)
12131     return false;
12132
12133   /* Default to DATA.  A text section is required by the ABI to contain an
12134      INSN mapping symbol at the start.  A data section has no such
12135      requirement, hence if no mapping symbol is found the section must
12136      contain only data.  This however isn't very useful if the user has
12137      fully stripped the binaries.  If this is the case use the section
12138      attributes to determine the default.  If we have no section default to
12139      INSN as well, as we may be disassembling some raw bytes on a baremetal
12140      HEX file or similar.  */
12141   enum map_type type = MAP_DATA;
12142   if ((info->section && info->section->flags & SEC_CODE) || !info->section)
12143     type = MAP_ARM;
12144   struct arm_private_data *private_data;
12145
12146   if (info->private_data == NULL || info->symtab == NULL
12147       || info->symtab_size == 0
12148       || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
12149     return false;
12150
12151   private_data = info->private_data;
12152
12153   /* First, look for mapping symbols.  */
12154   if (pc <= private_data->last_mapping_addr)
12155     private_data->last_mapping_sym = -1;
12156
12157   /* Start scanning at the start of the function, or wherever
12158      we finished last time.  */
12159   n = info->symtab_pos + 1;
12160
12161   /* If the last stop offset is different from the current one it means we
12162      are disassembling a different glob of bytes.  As such the optimization
12163      would not be safe and we should start over.  */
12164   can_use_search_opt_p
12165     = (private_data->last_mapping_sym >= 0
12166        && info->stop_offset == private_data->last_stop_offset);
12167
12168   if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
12169     n = private_data->last_mapping_sym;
12170
12171   /* Look down while we haven't passed the location being disassembled.
12172      The reason for this is that there's no defined order between a symbol
12173      and an mapping symbol that may be at the same address.  We may have to
12174      look at least one position ahead.  */
12175   for (; n < info->symtab_size; n++)
12176     {
12177       addr = bfd_asymbol_value (info->symtab[n]);
12178       if (addr > pc)
12179         break;
12180       if (get_map_sym_type (info, n, &type))
12181         {
12182           last_sym = n;
12183           found = true;
12184         }
12185     }
12186
12187   if (!found)
12188     {
12189       n = info->symtab_pos;
12190       if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
12191         n = private_data->last_mapping_sym;
12192
12193       /* No mapping symbol found at this address.  Look backwards
12194          for a preceeding one, but don't go pass the section start
12195          otherwise a data section with no mapping symbol can pick up
12196          a text mapping symbol of a preceeding section.  The documentation
12197          says section can be NULL, in which case we will seek up all the
12198          way to the top.  */
12199       if (info->section)
12200         section_vma = info->section->vma;
12201
12202       for (; n >= 0; n--)
12203         {
12204           addr = bfd_asymbol_value (info->symtab[n]);
12205           if (addr < section_vma)
12206             break;
12207
12208           if (get_map_sym_type (info, n, &type))
12209             {
12210               last_sym = n;
12211               found = true;
12212               break;
12213             }
12214         }
12215     }
12216
12217   /* If no mapping symbol was found, try looking up without a mapping
12218      symbol.  This is done by walking up from the current PC to the nearest
12219      symbol.  We don't actually have to loop here since symtab_pos will
12220      contain the nearest symbol already.  */
12221   if (!found)
12222     {
12223       n = info->symtab_pos;
12224       if (n >= 0 && get_sym_code_type (info, n, &type))
12225         {
12226           last_sym = n;
12227           found = true;
12228         }
12229     }
12230
12231   private_data->last_mapping_sym = last_sym;
12232   private_data->last_type = type;
12233   private_data->last_stop_offset = info->stop_offset;
12234
12235   *map_symbol = type;
12236   return found;
12237 }
12238
12239 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
12240    of the supplied arm_feature_set structure with bitmasks indicating
12241    the supported base architectures and coprocessor extensions.
12242
12243    FIXME: This could more efficiently implemented as a constant array,
12244    although it would also be less robust.  */
12245
12246 static void
12247 select_arm_features (unsigned long mach,
12248                      arm_feature_set * features)
12249 {
12250   arm_feature_set arch_fset;
12251   const arm_feature_set fpu_any = FPU_ANY;
12252
12253 #undef ARM_SET_FEATURES
12254 #define ARM_SET_FEATURES(FSET) \
12255   {                                                     \
12256     const arm_feature_set fset = FSET;                  \
12257     arch_fset = fset;                                   \
12258   }
12259
12260   /* When several architecture versions share the same bfd_mach_arm_XXX value
12261      the most featureful is chosen.  */
12262   switch (mach)
12263     {
12264     case bfd_mach_arm_2:         ARM_SET_FEATURES (ARM_ARCH_V2); break;
12265     case bfd_mach_arm_2a:        ARM_SET_FEATURES (ARM_ARCH_V2S); break;
12266     case bfd_mach_arm_3:         ARM_SET_FEATURES (ARM_ARCH_V3); break;
12267     case bfd_mach_arm_3M:        ARM_SET_FEATURES (ARM_ARCH_V3M); break;
12268     case bfd_mach_arm_4:         ARM_SET_FEATURES (ARM_ARCH_V4); break;
12269     case bfd_mach_arm_ep9312:
12270     case bfd_mach_arm_4T:        ARM_SET_FEATURES (ARM_ARCH_V4T); break;
12271     case bfd_mach_arm_5:         ARM_SET_FEATURES (ARM_ARCH_V5); break;
12272     case bfd_mach_arm_5T:        ARM_SET_FEATURES (ARM_ARCH_V5T); break;
12273     case bfd_mach_arm_5TE:       ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
12274     case bfd_mach_arm_XScale:    ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
12275     case bfd_mach_arm_iWMMXt:    ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
12276     case bfd_mach_arm_iWMMXt2:   ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
12277     case bfd_mach_arm_5TEJ:      ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
12278     case bfd_mach_arm_6:         ARM_SET_FEATURES (ARM_ARCH_V6); break;
12279     case bfd_mach_arm_6KZ:       ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
12280     case bfd_mach_arm_6T2:       ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
12281     case bfd_mach_arm_6K:        ARM_SET_FEATURES (ARM_ARCH_V6K); break;
12282     case bfd_mach_arm_7:         ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
12283     case bfd_mach_arm_6M:        ARM_SET_FEATURES (ARM_ARCH_V6M); break;
12284     case bfd_mach_arm_6SM:       ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
12285     case bfd_mach_arm_7EM:       ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
12286     case bfd_mach_arm_8:
12287         {
12288           /* Add bits for extensions that Armv8.6-A recognizes.  */
12289           arm_feature_set armv8_6_ext_fset
12290             = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
12291           ARM_SET_FEATURES (ARM_ARCH_V8_6A);
12292           ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_6_ext_fset);
12293           break;
12294         }
12295     case bfd_mach_arm_8R:        ARM_SET_FEATURES (ARM_ARCH_V8R); break;
12296     case bfd_mach_arm_8M_BASE:   ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
12297     case bfd_mach_arm_8M_MAIN:   ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
12298     case bfd_mach_arm_8_1M_MAIN:
12299       ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN);
12300       arm_feature_set mve_all
12301         = ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP);
12302       ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, mve_all);
12303       force_thumb = 1;
12304       break;
12305     case bfd_mach_arm_9:         ARM_SET_FEATURES (ARM_ARCH_V9A); break;
12306       /* If the machine type is unknown allow all architecture types and all
12307          extensions, with the exception of MVE as that clashes with NEON.  */
12308     case bfd_mach_arm_unknown:
12309       ARM_SET_FEATURES (ARM_ARCH_UNKNOWN);
12310       break;
12311     default:
12312       abort ();
12313     }
12314 #undef ARM_SET_FEATURES
12315
12316   /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
12317      and thus on bfd_mach_arm_XXX value.  Therefore for a given
12318      bfd_mach_arm_XXX value all coprocessor feature bits should be allowed.  */
12319   ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
12320 }
12321
12322
12323 /* NOTE: There are no checks in these routines that
12324    the relevant number of data bytes exist.  */
12325
12326 static int
12327 print_insn (bfd_vma pc, struct disassemble_info *info, bool little)
12328 {
12329   unsigned char b[4];
12330   unsigned long given;
12331   int status;
12332   int is_thumb = false;
12333   int is_data = false;
12334   int little_code;
12335   unsigned int  size = 4;
12336   void (*printer) (bfd_vma, struct disassemble_info *, long);
12337   bool found = false;
12338   struct arm_private_data *private_data;
12339
12340   /* Clear instruction information field.  */
12341   info->insn_info_valid = 0;
12342   info->branch_delay_insns = 0;
12343   info->data_size = 0;
12344   info->insn_type = dis_noninsn;
12345   info->target = 0;
12346   info->target2 = 0;
12347
12348   if (info->disassembler_options)
12349     {
12350       parse_arm_disassembler_options (info->disassembler_options);
12351
12352       /* To avoid repeated parsing of these options, we remove them here.  */
12353       info->disassembler_options = NULL;
12354     }
12355
12356   /* PR 10288: Control which instructions will be disassembled.  */
12357   if (info->private_data == NULL)
12358     {
12359       static struct arm_private_data private;
12360
12361       if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
12362         /* If the user did not use the -m command line switch then default to
12363            disassembling all types of ARM instruction.
12364
12365            The info->mach value has to be ignored as this will be based on
12366            the default archictecture for the target and/or hints in the notes
12367            section, but it will never be greater than the current largest arm
12368            machine value (iWMMXt2), which is only equivalent to the V5TE
12369            architecture.  ARM architectures have advanced beyond the machine
12370            value encoding, and these newer architectures would be ignored if
12371            the machine value was used.
12372
12373            Ie the -m switch is used to restrict which instructions will be
12374            disassembled.  If it is necessary to use the -m switch to tell
12375            objdump that an ARM binary is being disassembled, eg because the
12376            input is a raw binary file, but it is also desired to disassemble
12377            all ARM instructions then use "-marm".  This will select the
12378            "unknown" arm architecture which is compatible with any ARM
12379            instruction.  */
12380           info->mach = bfd_mach_arm_unknown;
12381
12382       /* Compute the architecture bitmask from the machine number.
12383          Note: This assumes that the machine number will not change
12384          during disassembly....  */
12385       select_arm_features (info->mach, & private.features);
12386
12387       private.last_mapping_sym = -1;
12388       private.last_mapping_addr = 0;
12389       private.last_stop_offset = 0;
12390
12391       info->private_data = & private;
12392     }
12393
12394   private_data = info->private_data;
12395
12396   /* Decide if our code is going to be little-endian, despite what the
12397      function argument might say.  */
12398   little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
12399
12400   /* For ELF, consult the symbol table to determine what kind of code
12401      or data we have.  */
12402   if (info->symtab_size != 0
12403       && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
12404     {
12405       bfd_vma addr;
12406       int n;
12407       int last_sym = -1;
12408       enum map_type type = MAP_ARM;
12409
12410       found = mapping_symbol_for_insn (pc, info, &type);
12411       last_sym = private_data->last_mapping_sym;
12412
12413       is_thumb = (private_data->last_type == MAP_THUMB);
12414       is_data = (private_data->last_type == MAP_DATA);
12415
12416       /* Look a little bit ahead to see if we should print out
12417          two or four bytes of data.  If there's a symbol,
12418          mapping or otherwise, after two bytes then don't
12419          print more.  */
12420       if (is_data)
12421         {
12422           size = 4 - (pc & 3);
12423           for (n = last_sym + 1; n < info->symtab_size; n++)
12424             {
12425               addr = bfd_asymbol_value (info->symtab[n]);
12426               if (addr > pc
12427                   && (info->section == NULL
12428                       || info->section == info->symtab[n]->section))
12429                 {
12430                   if (addr - pc < size)
12431                     size = addr - pc;
12432                   break;
12433                 }
12434             }
12435           /* If the next symbol is after three bytes, we need to
12436              print only part of the data, so that we can use either
12437              .byte or .short.  */
12438           if (size == 3)
12439             size = (pc & 1) ? 1 : 2;
12440         }
12441     }
12442
12443   if (info->symbols != NULL)
12444     {
12445       if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
12446         {
12447           coff_symbol_type * cs;
12448
12449           cs = coffsymbol (*info->symbols);
12450           is_thumb = (   cs->native->u.syment.n_sclass == C_THUMBEXT
12451                       || cs->native->u.syment.n_sclass == C_THUMBSTAT
12452                       || cs->native->u.syment.n_sclass == C_THUMBLABEL
12453                       || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
12454                       || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
12455         }
12456       else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
12457                && !found)
12458         {
12459           /* If no mapping symbol has been found then fall back to the type
12460              of the function symbol.  */
12461           elf_symbol_type *  es;
12462           unsigned int       type;
12463
12464           es = *(elf_symbol_type **)(info->symbols);
12465           type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
12466
12467           is_thumb =
12468             ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
12469               == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
12470         }
12471       else if (bfd_asymbol_flavour (*info->symbols)
12472                == bfd_target_mach_o_flavour)
12473         {
12474           bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
12475
12476           is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
12477         }
12478     }
12479
12480   if (force_thumb)
12481     is_thumb = true;
12482
12483   if (is_data)
12484     info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
12485   else
12486     info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
12487
12488   info->bytes_per_line = 4;
12489
12490   /* PR 10263: Disassemble data if requested to do so by the user.  */
12491   if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
12492     {
12493       int i;
12494
12495       /* Size was already set above.  */
12496       info->bytes_per_chunk = size;
12497       printer = print_insn_data;
12498
12499       status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
12500       given = 0;
12501       if (little)
12502         for (i = size - 1; i >= 0; i--)
12503           given = b[i] | (given << 8);
12504       else
12505         for (i = 0; i < (int) size; i++)
12506           given = b[i] | (given << 8);
12507     }
12508   else if (!is_thumb)
12509     {
12510       /* In ARM mode endianness is a straightforward issue: the instruction
12511          is four bytes long and is either ordered 0123 or 3210.  */
12512       printer = print_insn_arm;
12513       info->bytes_per_chunk = 4;
12514       size = 4;
12515
12516       status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
12517       if (little_code)
12518         given = (b[0]) | (b[1] << 8) | (b[2] << 16) | ((unsigned) b[3] << 24);
12519       else
12520         given = (b[3]) | (b[2] << 8) | (b[1] << 16) | ((unsigned) b[0] << 24);
12521     }
12522   else
12523     {
12524       /* In Thumb mode we have the additional wrinkle of two
12525          instruction lengths.  Fortunately, the bits that determine
12526          the length of the current instruction are always to be found
12527          in the first two bytes.  */
12528       printer = print_insn_thumb16;
12529       info->bytes_per_chunk = 2;
12530       size = 2;
12531
12532       status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
12533       if (little_code)
12534         given = (b[0]) | (b[1] << 8);
12535       else
12536         given = (b[1]) | (b[0] << 8);
12537
12538       if (!status)
12539         {
12540           /* These bit patterns signal a four-byte Thumb
12541              instruction.  */
12542           if ((given & 0xF800) == 0xF800
12543               || (given & 0xF800) == 0xF000
12544               || (given & 0xF800) == 0xE800)
12545             {
12546               status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
12547               if (little_code)
12548                 given = (b[0]) | (b[1] << 8) | (given << 16);
12549               else
12550                 given = (b[1]) | (b[0] << 8) | (given << 16);
12551
12552               printer = print_insn_thumb32;
12553               size = 4;
12554             }
12555         }
12556
12557       if (ifthen_address != pc)
12558         find_ifthen_state (pc, info, little_code);
12559
12560       if (ifthen_state)
12561         {
12562           if ((ifthen_state & 0xf) == 0x8)
12563             ifthen_next_state = 0;
12564           else
12565             ifthen_next_state = (ifthen_state & 0xe0)
12566                                 | ((ifthen_state & 0xf) << 1);
12567         }
12568     }
12569
12570   if (status)
12571     {
12572       info->memory_error_func (status, pc, info);
12573       return -1;
12574     }
12575   if (info->flags & INSN_HAS_RELOC)
12576     /* If the instruction has a reloc associated with it, then
12577        the offset field in the instruction will actually be the
12578        addend for the reloc.  (We are using REL type relocs).
12579        In such cases, we can ignore the pc when computing
12580        addresses, since the addend is not currently pc-relative.  */
12581     pc = 0;
12582
12583   printer (pc, info, given);
12584
12585   if (is_thumb)
12586     {
12587       ifthen_state = ifthen_next_state;
12588       ifthen_address += size;
12589     }
12590   return size;
12591 }
12592
12593 int
12594 print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
12595 {
12596   /* Detect BE8-ness and record it in the disassembler info.  */
12597   if (info->flavour == bfd_target_elf_flavour
12598       && info->section != NULL
12599       && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
12600     info->endian_code = BFD_ENDIAN_LITTLE;
12601
12602   return print_insn (pc, info, false);
12603 }
12604
12605 int
12606 print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
12607 {
12608   return print_insn (pc, info, true);
12609 }
12610
12611 const disasm_options_and_args_t *
12612 disassembler_options_arm (void)
12613 {
12614   static disasm_options_and_args_t *opts_and_args;
12615
12616   if (opts_and_args == NULL)
12617     {
12618       disasm_options_t *opts;
12619       unsigned int i;
12620
12621       opts_and_args = XNEW (disasm_options_and_args_t);
12622       opts_and_args->args = NULL;
12623
12624       opts = &opts_and_args->options;
12625       opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
12626       opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
12627       opts->arg = NULL;
12628       for (i = 0; i < NUM_ARM_OPTIONS; i++)
12629         {
12630           opts->name[i] = regnames[i].name;
12631           if (regnames[i].description != NULL)
12632             opts->description[i] = _(regnames[i].description);
12633           else
12634             opts->description[i] = NULL;
12635         }
12636       /* The array we return must be NULL terminated.  */
12637       opts->name[i] = NULL;
12638       opts->description[i] = NULL;
12639     }
12640
12641   return opts_and_args;
12642 }
12643
12644 void
12645 print_arm_disassembler_options (FILE *stream)
12646 {
12647   unsigned int i, max_len = 0;
12648   fprintf (stream, _("\n\
12649 The following ARM specific disassembler options are supported for use with\n\
12650 the -M switch:\n"));
12651
12652   for (i = 0; i < NUM_ARM_OPTIONS; i++)
12653     {
12654       unsigned int len = strlen (regnames[i].name);
12655       if (max_len < len)
12656         max_len = len;
12657     }
12658
12659   for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
12660     fprintf (stream, "  %s%*c %s\n",
12661              regnames[i].name,
12662              (int)(max_len - strlen (regnames[i].name)), ' ',
12663              _(regnames[i].description));
12664 }