| blob | 1dde0b478c3d1bc9b88a63dd703225c9a2bb3703 |
1 /* simulator.c -- Interface for the AArch64 simulator.
3 Copyright (C) 2015-2024 Free Software Foundation, Inc.
5 Contributed by Red Hat.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 /* This must come before any other includes. */
25 #include <stdlib.h>
26 #include <stdio.h>
27 #include <string.h>
28 #include <sys/types.h>
29 #include <math.h>
30 #include <time.h>
31 #include <limits.h>
40 #define NO_SP 0
41 #define SP_OK 1
43 #define TST(_flag) (aarch64_test_CPSR_bit (cpu, _flag))
44 #define IS_SET(_X) (TST (( _X )) ? 1 : 0)
45 #define IS_CLEAR(_X) (TST (( _X )) ? 0 : 1)
47 /* Space saver macro. */
48 #define INSTR(HIGH, LOW) uimm (aarch64_get_instr (cpu), (HIGH), (LOW))
50 #define HALT_UNALLOC \
51 do \
52 { \
53 TRACE_DISASM (cpu, aarch64_get_PC (cpu)); \
54 TRACE_INSN (cpu, \
57 __LINE__, aarch64_get_PC (cpu)); \
58 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, aarch64_get_PC (cpu),\
59 sim_stopped, SIM_SIGILL); \
60 } \
61 while (0)
63 #define HALT_NYI \
64 do \
65 { \
66 TRACE_DISASM (cpu, aarch64_get_PC (cpu)); \
67 TRACE_INSN (cpu, \
70 __LINE__, aarch64_get_PC (cpu)); \
71 if (! TRACE_ANY_P (cpu)) \
73 aarch64_get_instr (cpu)); \
74 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, aarch64_get_PC (cpu),\
75 sim_stopped, SIM_SIGABRT); \
76 } \
77 while (0)
79 #define NYI_assert(HI, LO, EXPECTED) \
80 do \
81 { \
82 if (INSTR ((HI), (LO)) != (EXPECTED)) \
83 HALT_NYI; \
84 } \
85 while (0)
87 static uint64_t
89 {
94 /* The immediate value is S+1 bits to 1, left rotated by SIMDsize - R
95 (in other words, right rotated by R), then replicated. */
97 {
100 }
101 else
102 {
104 {
111 }
113 /* Top bits are IGNORED. */
115 }
117 /* NOTE: if S = simd_size - 1 we get 0xf..f which is rejected. */
121 /* S+1 consecutive bits to 1. */
122 /* NOTE: S can't be 63 due to detection above. */
125 /* Rotate to the left by simd_size - R. */
129 /* Replicate the value according to SIMD size. */
131 {
139 }
142 }
144 /* Instr[22,10] encodes N immr and imms. we want a lookup table
145 for each possible combination i.e. 13 bits worth of int entries. */
146 #define LI_TABLE_SIZE (1 << 13)
149 void
151 {
155 {
161 }
162 }
164 static void
166 {
167 /* instr[14,0] == type : 0 ==> method entry, 1 ==> method reentry
168 2 ==> exit Java, 3 ==> start next bytecode. */
174 {
176 /* aarch64_notifyMethodEntry (aarch64_get_reg_u64 (cpu, R23, 0),
177 aarch64_get_reg_u64 (cpu, R22, 0)); */
180 /* aarch64_notifyMethodReentry (aarch64_get_reg_u64 (cpu, R23, 0),
181 aarch64_get_reg_u64 (cpu, R22, 0)); */
184 /* aarch64_notifyMethodExit (); */
187 /* aarch64_notifyBCStart (aarch64_get_reg_u64 (cpu, R23, 0),
188 aarch64_get_reg_u64 (cpu, R22, 0)); */
190 }
191 }
193 /* secondary decode within top level groups */
195 static void
197 {
198 /* assert instr[28,27] = 00
200 We provide 2 pseudo instructions:
202 HALT stops execution of the simulator causing an immediate
203 return to the x86 code which entered it.
205 CALLOUT initiates recursive entry into x86 code. A register
206 argument holds the address of the x86 routine. Immediate
207 values in the instruction identify the number of general
208 purpose and floating point register arguments to be passed
209 and the type of any value to be returned. */
218 {
222 }
226 /* We do not handle callouts at the moment. */
228 {
232 }
237 else
238 HALT_UNALLOC;
239 }
241 /* Load-store single register (unscaled offset)
242 These instructions employ a base register plus an unscaled signed
243 9 bit offset.
245 N.B. the base register (source) can be Xn or SP. all other
246 registers may not be SP. */
248 /* 32 bit load 32 bit unscaled signed 9 bit. */
249 static void
251 {
259 }
261 /* 64 bit load 64 bit unscaled signed 9 bit. */
262 static void
264 {
272 }
274 /* 32 bit load zero-extended byte unscaled signed 9 bit. */
275 static void
277 {
285 }
287 /* 32 bit load sign-extended byte unscaled signed 9 bit. */
288 static void
290 {
298 }
300 /* 64 bit load sign-extended byte unscaled signed 9 bit. */
301 static void
303 {
311 }
313 /* 32 bit load zero-extended short unscaled signed 9 bit */
314 static void
316 {
324 }
326 /* 32 bit load sign-extended short unscaled signed 9 bit */
327 static void
329 {
337 }
339 /* 64 bit load sign-extended short unscaled signed 9 bit */
340 static void
342 {
350 }
352 /* 64 bit load sign-extended word unscaled signed 9 bit */
353 static void
355 {
363 }
365 /* N.B. with stores the value in source is written to the address
366 identified by source2 modified by offset. */
368 /* 32 bit store 32 bit unscaled signed 9 bit. */
369 static void
371 {
379 }
381 /* 64 bit store 64 bit unscaled signed 9 bit */
382 static void
384 {
392 }
394 /* 32 bit store byte unscaled signed 9 bit */
395 static void
397 {
405 }
407 /* 32 bit store short unscaled signed 9 bit */
408 static void
410 {
418 }
420 /* Load single register pc-relative label
421 Offset is a signed 19 bit immediate count in words
422 rt may not be SP. */
424 /* 32 bit pc-relative load */
425 static void
427 {
432 aarch64_get_mem_u32
434 }
436 /* 64 bit pc-relative load */
437 static void
439 {
444 aarch64_get_mem_u64
446 }
448 /* sign extended 32 bit pc-relative load */
449 static void
451 {
456 aarch64_get_mem_s32
458 }
460 /* float pc-relative load */
461 static void
463 {
468 aarch64_get_mem_u32
470 }
472 /* double pc-relative load */
473 static void
475 {
480 aarch64_get_mem_u64
482 }
484 /* long double pc-relative load. */
485 static void
487 {
490 FRegister a;
495 }
497 /* This can be used to scale an offset by applying
498 the requisite shift. the second argument is either
499 16, 32 or 64. */
501 #define SCALE(_offset, _elementSize) \
502 ((_offset) << ScaleShift ## _elementSize)
504 /* This can be used to optionally scale a register derived offset
505 by applying the requisite shift as indicated by the Scaling
506 argument. The second argument is either Byte, Short, Word
507 or Long. The third argument is either Scaled or Unscaled.
508 N.B. when _Scaling is Scaled the shift gets ANDed with
509 all 1s while when it is Unscaled it gets ANDed with 0. */
511 #define OPT_SCALE(_offset, _elementType, _Scaling) \
512 ((_offset) << (_Scaling ? ScaleShift ## _elementType : 0))
514 /* This can be used to zero or sign extend a 32 bit register derived
515 value to a 64 bit value. the first argument must be the value as
516 a uint32_t and the second must be either UXTW or SXTW. The result
517 is returned as an int64_t. */
521 {
522 union
523 {
528 /* A branchless variant of this ought to be possible. */
534 }
536 /* Scalar Floating Point
538 FP load/store single register (4 addressing modes)
540 N.B. the base register (source) can be the stack pointer.
541 The secondary source register (source2) can only be an Xn register. */
543 /* Load 32 bit unscaled signed 9 bit with pre- or post-writeback. */
544 static void
546 {
561 }
563 /* Load 8 bit with unsigned 12 bit offset. */
564 static void
566 {
573 }
575 /* Load 16 bit scaled unsigned 12 bit. */
576 static void
578 {
585 }
587 /* Load 32 bit scaled unsigned 12 bit. */
588 static void
590 {
597 }
599 /* Load 64 bit scaled unsigned 12 bit. */
600 static void
602 {
609 }
611 /* Load 128 bit scaled unsigned 12 bit. */
612 static void
614 {
622 }
624 /* Load 32 bit scaled or unscaled zero- or sign-extended
625 32-bit register offset. */
626 static void
628 {
639 }
641 /* Load 64 bit unscaled signed 9 bit with pre- or post-writeback. */
642 static void
644 {
660 }
662 /* Load 64 bit scaled or unscaled zero- or sign-extended 32-bit register offset. */
663 static void
665 {
671 }
673 /* Load 128 bit unscaled signed 9 bit with pre- or post-writeback. */
674 static void
676 {
677 FRegister a;
694 }
696 /* Load 128 bit scaled or unscaled zero- or sign-extended 32-bit register offset */
697 static void
699 {
705 }
707 /* Memory Access
709 load-store single register
710 There are four addressing modes available here which all employ a
711 64 bit source (base) register.
713 N.B. the base register (source) can be the stack pointer.
714 The secondary source register (source2)can only be an Xn register.
716 Scaled, 12-bit, unsigned immediate offset, without pre- and
717 post-index options.
718 Unscaled, 9-bit, signed immediate offset with pre- or post-index
719 writeback.
720 scaled or unscaled 64-bit register offset.
721 scaled or unscaled 32-bit extended register offset.
723 All offsets are assumed to be raw from the decode i.e. the
724 simulator is expected to adjust scaled offsets based on the
725 accessed data size with register or extended register offset
726 versions the same applies except that in the latter case the
727 operation may also require a sign extend.
729 A separate method is provided for each possible addressing mode. */
731 /* 32 bit load 32 bit scaled unsigned 12 bit */
732 static void
734 {
739 /* The target register may not be SP but the source may be. */
743 }
745 /* 32 bit load 32 bit unscaled signed 9 bit with pre- or post-writeback. */
746 static void
748 {
754 HALT_UNALLOC;
769 }
771 /* 32 bit load 32 bit scaled or unscaled
772 zero- or sign-extended 32-bit register offset */
773 static void
775 {
779 /* rn may reference SP, rm and rt must reference ZR */
788 }
790 /* 64 bit load 64 bit scaled unsigned 12 bit */
791 static void
793 {
798 /* The target register may not be SP but the source may be. */
802 }
804 /* 64 bit load 64 bit unscaled signed 9 bit with pre- or post-writeback. */
805 static void
807 {
813 HALT_UNALLOC;
828 }
830 /* 64 bit load 64 bit scaled or unscaled zero-
831 or sign-extended 32-bit register offset. */
832 static void
834 {
838 /* rn may reference SP, rm and rt must reference ZR */
847 }
849 /* 32 bit load zero-extended byte scaled unsigned 12 bit. */
850 static void
852 {
857 /* The target register may not be SP but the source may be
858 there is no scaling required for a byte load. */
860 aarch64_get_mem_u8
862 }
864 /* 32 bit load zero-extended byte unscaled signed 9 bit with pre- or post-writeback. */
865 static void
867 {
873 HALT_UNALLOC;
888 }
890 /* 32 bit load zero-extended byte scaled or unscaled zero-
891 or sign-extended 32-bit register offset. */
892 static void
894 {
898 /* rn may reference SP, rm and rt must reference ZR */
902 extension);
905 /* There is no scaling required for a byte load. */
908 }
910 /* 64 bit load sign-extended byte unscaled signed 9 bit
911 with pre- or post-writeback. */
912 static void
914 {
921 HALT_UNALLOC;
937 }
939 /* 64 bit load sign-extended byte scaled unsigned 12 bit. */
940 static void
942 {
944 }
946 /* 64 bit load sign-extended byte scaled or unscaled zero-
947 or sign-extended 32-bit register offset. */
948 static void
950 {
954 /* rn may reference SP, rm and rt must reference ZR */
958 extension);
960 /* There is no scaling required for a byte load. */
963 }
965 /* 32 bit load zero-extended short scaled unsigned 12 bit. */
966 static void
968 {
974 /* The target register may not be SP but the source may be. */
978 }
980 /* 32 bit load zero-extended short unscaled signed 9 bit
981 with pre- or post-writeback. */
982 static void
984 {
990 HALT_UNALLOC;
1005 }
1007 /* 32 bit load zero-extended short scaled or unscaled zero-
1008 or sign-extended 32-bit register offset. */
1009 static void
1011 {
1015 /* rn may reference SP, rm and rt must reference ZR */
1024 }
1026 /* 32 bit load sign-extended short scaled unsigned 12 bit. */
1027 static void
1029 {
1035 /* The target register may not be SP but the source may be. */
1039 }
1041 /* 32 bit load sign-extended short unscaled signed 9 bit
1042 with pre- or post-writeback. */
1043 static void
1045 {
1051 HALT_UNALLOC;
1067 }
1069 /* 32 bit load sign-extended short scaled or unscaled zero-
1070 or sign-extended 32-bit register offset. */
1071 static void
1073 {
1077 /* rn may reference SP, rm and rt must reference ZR */
1087 }
1089 /* 64 bit load sign-extended short scaled unsigned 12 bit. */
1090 static void
1092 {
1098 /* The target register may not be SP but the source may be. */
1102 }
1104 /* 64 bit load sign-extended short unscaled signed 9 bit
1105 with pre- or post-writeback. */
1106 static void
1108 {
1115 HALT_UNALLOC;
1131 }
1133 /* 64 bit load sign-extended short scaled or unscaled zero-
1134 or sign-extended 32-bit register offset. */
1135 static void
1137 {
1142 /* rn may reference SP, rm and rt must reference ZR */
1152 }
1154 /* 64 bit load sign-extended 32 bit scaled unsigned 12 bit. */
1155 static void
1157 {
1165 /* The target register may not be SP but the source may be. */
1167 }
1169 /* 64 bit load sign-extended 32 bit unscaled signed 9 bit
1170 with pre- or post-writeback. */
1171 static void
1173 {
1179 HALT_UNALLOC;
1194 }
1196 /* 64 bit load sign-extended 32 bit scaled or unscaled zero-
1197 or sign-extended 32-bit register offset. */
1198 static void
1200 {
1204 /* rn may reference SP, rm and rt must reference ZR */
1213 }
1215 /* N.B. with stores the value in source is written to the
1216 address identified by source2 modified by source3/offset. */
1218 /* 32 bit store scaled unsigned 12 bit. */
1219 static void
1221 {
1226 /* The target register may not be SP but the source may be. */
1230 }
1232 /* 32 bit store unscaled signed 9 bit with pre- or post-writeback. */
1233 static void
1235 {
1241 HALT_UNALLOC;
1255 }
1257 /* 32 bit store scaled or unscaled zero- or
1258 sign-extended 32-bit register offset. */
1259 static void
1261 {
1273 }
1275 /* 64 bit store scaled unsigned 12 bit. */
1276 static void
1278 {
1287 }
1289 /* 64 bit store unscaled signed 9 bit with pre- or post-writeback. */
1290 static void
1292 {
1298 HALT_UNALLOC;
1313 }
1315 /* 64 bit store scaled or unscaled zero-
1316 or sign-extended 32-bit register offset. */
1317 static void
1319 {
1323 /* rn may reference SP, rm and rt must reference ZR */
1327 extension);
1333 }
1335 /* 32 bit store byte scaled unsigned 12 bit. */
1336 static void
1338 {
1343 /* The target register may not be SP but the source may be.
1344 There is no scaling required for a byte load. */
1348 }
1350 /* 32 bit store byte unscaled signed 9 bit with pre- or post-writeback. */
1351 static void
1353 {
1359 HALT_UNALLOC;
1374 }
1376 /* 32 bit store byte scaled or unscaled zero-
1377 or sign-extended 32-bit register offset. */
1378 static void
1380 {
1384 /* rn may reference SP, rm and rt must reference ZR */
1388 extension);
1391 /* There is no scaling required for a byte load. */
1394 }
1396 /* 32 bit store short scaled unsigned 12 bit. */
1397 static void
1399 {
1404 /* The target register may not be SP but the source may be. */
1408 }
1410 /* 32 bit store short unscaled signed 9 bit with pre- or post-writeback. */
1411 static void
1413 {
1419 HALT_UNALLOC;
1434 }
1436 /* 32 bit store short scaled or unscaled zero-
1437 or sign-extended 32-bit register offset. */
1438 static void
1440 {
1444 /* rn may reference SP, rm and rt must reference ZR */
1453 }
1455 /* Prefetch unsigned 12 bit. */
1456 static void
1458 {
1459 /* instr[4,0] = prfop : 00000 ==> PLDL1KEEP, 00001 ==> PLDL1STRM,
1460 00010 ==> PLDL2KEEP, 00001 ==> PLDL2STRM,
1461 00100 ==> PLDL3KEEP, 00101 ==> PLDL3STRM,
1462 10000 ==> PSTL1KEEP, 10001 ==> PSTL1STRM,
1463 10010 ==> PSTL2KEEP, 10001 ==> PSTL2STRM,
1464 10100 ==> PSTL3KEEP, 10101 ==> PSTL3STRM,
1465 ow ==> UNALLOC
1466 PrfOp prfop = prfop (instr, 4, 0);
1467 uint64_t address = aarch64_get_reg_u64 (cpu, rn, SP_OK)
1468 + SCALE (offset, 64). */
1470 /* TODO : implement prefetch of address. */
1471 }
1473 /* Prefetch scaled or unscaled zero- or sign-extended 32-bit register offset. */
1474 static void
1476 {
1477 /* instr[4,0] = prfop : 00000 ==> PLDL1KEEP, 00001 ==> PLDL1STRM,
1478 00010 ==> PLDL2KEEP, 00001 ==> PLDL2STRM,
1479 00100 ==> PLDL3KEEP, 00101 ==> PLDL3STRM,
1480 10000 ==> PSTL1KEEP, 10001 ==> PSTL1STRM,
1481 10010 ==> PSTL2KEEP, 10001 ==> PSTL2STRM,
1482 10100 ==> PSTL3KEEP, 10101 ==> PSTL3STRM,
1483 ow ==> UNALLOC
1484 rn may reference SP, rm may only reference ZR
1485 PrfOp prfop = prfop (instr, 4, 0);
1486 uint64_t base = aarch64_get_reg_u64 (cpu, rn, SP_OK);
1487 int64_t extended = extend (aarch64_get_reg_u32 (cpu, rm, NO_SP),
1488 extension);
1489 uint64_t displacement = OPT_SCALE (extended, 64, scaling);
1490 uint64_t address = base + displacement. */
1492 /* TODO : implement prefetch of address */
1493 }
1495 /* 64 bit pc-relative prefetch. */
1496 static void
1498 {
1499 /* instr[4,0] = prfop : 00000 ==> PLDL1KEEP, 00001 ==> PLDL1STRM,
1500 00010 ==> PLDL2KEEP, 00001 ==> PLDL2STRM,
1501 00100 ==> PLDL3KEEP, 00101 ==> PLDL3STRM,
1502 10000 ==> PSTL1KEEP, 10001 ==> PSTL1STRM,
1503 10010 ==> PSTL2KEEP, 10001 ==> PSTL2STRM,
1504 10100 ==> PSTL3KEEP, 10101 ==> PSTL3STRM,
1505 ow ==> UNALLOC
1506 PrfOp prfop = prfop (instr, 4, 0);
1507 uint64_t address = aarch64_get_PC (cpu) + offset. */
1509 /* TODO : implement this */
1510 }
1512 /* Load-store exclusive. */
1514 static void
1516 {
1521 /* int ordered = INSTR (15, 15); */
1522 /* int exclusive = ! INSTR (23, 23); */
1526 {
1539 }
1540 }
1542 static void
1544 {
1553 {
1558 }
1562 }
1564 static void
1566 {
1567 /* instr[29,27] == 011
1568 instr[25,24] == 00
1569 instr[31,30:26] = opc: 000 ==> LDRW, 001 ==> FLDRS
1570 010 ==> LDRX, 011 ==> FLDRD
1571 100 ==> LDRSW, 101 ==> FLDRQ
1572 110 ==> PRFM, 111 ==> UNALLOC
1573 instr[26] ==> V : 0 ==> GReg, 1 ==> FReg
1574 instr[23, 5] == simm19 */
1576 /* unsigned rt = INSTR (4, 0); */
1581 {
1591 HALT_UNALLOC;
1592 }
1593 }
1595 /* Immediate arithmetic
1596 The aimm argument is a 12 bit unsigned value or a 12 bit unsigned
1597 value left shifted by 12 bits (done at decode).
1599 N.B. the register args (dest, source) can normally be Xn or SP.
1600 the exception occurs for flag setting instructions which may
1601 only use Xn for the output (dest). */
1603 /* 32 bit add immediate. */
1604 static void
1606 {
1613 }
1615 /* 64 bit add immediate. */
1616 static void
1618 {
1625 }
1627 static void
1629 {
1649 }
1651 #define NEG(a) (((a) & signbit) == signbit)
1652 #define POS(a) (((a) & signbit) == 0)
1654 static void
1656 {
1677 }
1679 static void
1681 {
1702 }
1704 static void
1706 {
1727 }
1729 static void
1731 {
1736 else
1741 else
1745 }
1747 static void
1749 {
1754 else
1759 else
1763 }
1765 /* 32 bit add immediate set flags. */
1766 static void
1768 {
1771 /* TODO : do we need to worry about signs here? */
1777 }
1779 /* 64 bit add immediate set flags. */
1780 static void
1782 {
1791 }
1793 /* 32 bit sub immediate. */
1794 static void
1796 {
1803 }
1805 /* 64 bit sub immediate. */
1806 static void
1808 {
1815 }
1817 /* 32 bit sub immediate set flags. */
1818 static void
1820 {
1829 }
1831 /* 64 bit sub immediate set flags. */
1832 static void
1834 {
1843 }
1845 /* Data Processing Register. */
1847 /* First two helpers to perform the shift operations. */
1851 {
1853 {
1860 {
1863 }
1865 {
1869 }
1870 }
1871 }
1875 {
1877 {
1884 {
1887 }
1889 {
1893 }
1894 }
1895 }
1897 /* Arithmetic shifted register.
1898 These allow an optional LSL, ASR or LSR to the second source
1899 register with a count up to the register bit count.
1901 N.B register args may not be SP. */
1903 /* 32 bit ADD shifted register. */
1904 static void
1906 {
1916 }
1918 /* 64 bit ADD shifted register. */
1919 static void
1921 {
1931 }
1933 /* 32 bit ADD shifted register setting flags. */
1934 static void
1936 {
1948 }
1950 /* 64 bit ADD shifted register setting flags. */
1951 static void
1953 {
1965 }
1967 /* 32 bit SUB shifted register. */
1968 static void
1970 {
1980 }
1982 /* 64 bit SUB shifted register. */
1983 static void
1985 {
1995 }
1997 /* 32 bit SUB shifted register setting flags. */
1998 static void
2000 {
2012 }
2014 /* 64 bit SUB shifted register setting flags. */
2015 static void
2017 {
2029 }
2031 /* First a couple more helpers to fetch the
2032 relevant source register element either
2033 sign or zero extended as required by the
2034 extension value. */
2036 static uint32_t
2038 {
2040 {
2050 }
2051 }
2053 static uint64_t
2055 {
2057 {
2067 }
2068 }
2070 /* Arithmetic extending register
2071 These allow an optional sign extension of some portion of the
2072 second source register followed by an optional left shift of
2073 between 1 and 4 bits (i.e. a shift of 0-4 bits???)
2075 N.B output (dest) and first input arg (source) may normally be Xn
2076 or SP. However, for flag setting operations dest can only be
2077 Xn. Second input registers are always Xn. */
2079 /* 32 bit ADD extending register. */
2080 static void
2082 {
2091 }
2093 /* 64 bit ADD extending register.
2094 N.B. This subsumes the case with 64 bit source2 and UXTX #n or LSL #0. */
2095 static void
2097 {
2106 }
2108 /* 32 bit ADD extending register setting flags. */
2109 static void
2111 {
2122 }
2124 /* 64 bit ADD extending register setting flags */
2125 /* N.B. this subsumes the case with 64 bit source2 and UXTX #n or LSL #0 */
2126 static void
2128 {
2139 }
2141 /* 32 bit SUB extending register. */
2142 static void
2144 {
2153 }
2155 /* 64 bit SUB extending register. */
2156 /* N.B. this subsumes the case with 64 bit source2 and UXTX #n or LSL #0. */
2157 static void
2159 {
2168 }
2170 /* 32 bit SUB extending register setting flags. */
2171 static void
2173 {
2184 }
2186 /* 64 bit SUB extending register setting flags */
2187 /* N.B. this subsumes the case with 64 bit source2 and UXTX #n or LSL #0 */
2188 static void
2190 {
2201 }
2203 static void
2205 {
2206 /* instr[31] = size : 0 ==> 32 bit, 1 ==> 64 bit
2207 instr[30] = op : 0 ==> ADD, 1 ==> SUB
2208 instr[29] = set : 0 ==> no flags, 1 ==> set flags
2209 instr[28,24] = 10001
2210 instr[23,22] = shift : 00 == LSL#0, 01 = LSL#12 1x = UNALLOC
2211 instr[21,10] = uimm12
2212 instr[9,5] = Rn
2213 instr[4,0] = Rd */
2215 /* N.B. the shift is applied at decode before calling the add/sub routine. */
2223 HALT_UNALLOC;
2229 {
2238 }
2239 }
2241 static void
2243 {
2244 /* instr[31] = size : 0 ==> 32 bit, 1 ==> 64 bit
2245 instr[30,29] = op : 00 ==> ADD, 01 ==> ADDS, 10 ==> SUB, 11 ==> SUBS
2246 instr[28,24] = 01011
2247 instr[23,22] = shift : 0 ==> LSL, 1 ==> LSR, 2 ==> ASR, 3 ==> UNALLOC
2248 instr[21] = 0
2249 instr[20,16] = Rm
2250 instr[15,10] = count : must be 0xxxxx for 32 bit
2251 instr[9,5] = Rn
2252 instr[4,0] = Rd */
2261 /* Shift encoded as ROR is unallocated. */
2263 HALT_UNALLOC;
2265 /* 32 bit operations must have count[5] = 0
2266 or else we have an UNALLOC. */
2268 HALT_UNALLOC;
2270 /* Dispatch on size:op i.e instr [31,29]. */
2272 {
2281 }
2282 }
2284 static void
2286 {
2287 /* instr[31] = size : 0 ==> 32 bit, 1 ==> 64 bit
2288 instr[30] = op : 0 ==> ADD, 1 ==> SUB
2289 instr[29] = set? : 0 ==> no flags, 1 ==> set flags
2290 instr[28,24] = 01011
2291 instr[23,22] = opt : 0 ==> ok, 1,2,3 ==> UNALLOC
2292 instr[21] = 1
2293 instr[20,16] = Rm
2294 instr[15,13] = option : 000 ==> UXTB, 001 ==> UXTH,
2295 000 ==> LSL|UXTW, 001 ==> UXTZ,
2296 000 ==> SXTB, 001 ==> SXTH,
2297 000 ==> SXTW, 001 ==> SXTX,
2298 instr[12,10] = shift : 0,1,2,3,4 ==> ok, 5,6,7 ==> UNALLOC
2299 instr[9,5] = Rn
2300 instr[4,0] = Rd */
2308 /* Shift may not exceed 4. */
2310 HALT_UNALLOC;
2312 /* Dispatch on size:op:set?. */
2314 {
2323 }
2324 }
2326 /* Conditional data processing
2327 Condition register is implicit 3rd source. */
2329 /* 32 bit add with carry. */
2330 /* N.B register args may not be SP. */
2332 static void
2334 {
2344 }
2346 /* 64 bit add with carry */
2347 static void
2349 {
2359 }
2361 /* 32 bit add with carry setting flags. */
2362 static void
2364 {
2376 }
2378 /* 64 bit add with carry setting flags. */
2379 static void
2381 {
2393 }
2395 /* 32 bit sub with carry. */
2396 static void
2398 {
2408 }
2410 /* 64 bit sub with carry */
2411 static void
2413 {
2423 }
2425 /* 32 bit sub with carry setting flags */
2426 static void
2428 {
2441 }
2443 /* 64 bit sub with carry setting flags */
2444 static void
2446 {
2459 }
2461 static void
2463 {
2464 /* instr[31] = size : 0 ==> 32 bit, 1 ==> 64 bit
2465 instr[30] = op : 0 ==> ADC, 1 ==> SBC
2466 instr[29] = set? : 0 ==> no flags, 1 ==> set flags
2467 instr[28,21] = 1 1010 000
2468 instr[20,16] = Rm
2469 instr[15,10] = op2 : 00000 ==> ok, ow ==> UNALLOC
2470 instr[9,5] = Rn
2471 instr[4,0] = Rd */
2478 HALT_UNALLOC;
2480 /* Dispatch on size:op:set?. */
2482 {
2491 }
2492 }
2494 static uint32_t
2496 {
2497 /* This should be reduceable to branchless logic
2498 by some careful testing of bits in CC followed
2499 by the requisite masking and combining of bits
2500 from the flag register.
2502 For now we do it with a switch. */
2506 {
2526 }
2528 }
2530 static void
2532 {
2533 /* instr[31] = size : 0 ==> 32 bit, 1 ==> 64 bit
2534 instr[30] = compare with positive (1) or negative value (0)
2535 instr[29,21] = 1 1101 0010
2536 instr[20,16] = Rm or const
2537 instr[15,12] = cond
2538 instr[11] = compare reg (0) or const (1)
2539 instr[10] = 0
2540 instr[9,5] = Rn
2541 instr[4] = 0
2542 instr[3,0] = value for CPSR bits if the comparison does not take place. */
2553 {
2556 }
2563 {
2567 else
2570 }
2571 else
2572 {
2576 else
2579 }
2580 }
2582 static void
2584 {
2585 /* MOV Vd.T, Vs.T (alias for ORR Vd.T, Vn.T, Vm.T where Vn == Vm)
2587 instr[31] = 0
2588 instr[30] = half(0)/full(1)
2589 instr[29,21] = 001110101
2590 instr[20,16] = Vs
2591 instr[15,10] = 000111
2592 instr[9,5] = Vs
2593 instr[4,0] = Vd */
2602 HALT_NYI;
2609 }
2611 static void
2613 {
2614 /* instr[31] = 0
2615 instr[30] = word(0)/long(1)
2616 instr[29,21] = 00 1110 000
2617 instr[20,16] = element size and index
2618 instr[15,10] = 00 0010 11
2619 instr[9,5] = V source
2620 instr[4,0] = R dest */
2634 {
2637 }
2639 {
2642 }
2644 {
2647 }
2648 else
2649 HALT_UNALLOC;
2652 {
2657 else
2666 else
2677 HALT_UNALLOC;
2678 }
2679 }
2681 static void
2683 {
2684 /* instr[31] = 0
2685 instr[30] = word(0)/long(1)
2686 instr[29,21] = 00 1110 000
2687 instr[20,16] = element size and index
2688 instr[15,10] = 00 0011 11
2689 instr[9,5] = V source
2690 instr[4,0] = R dest */
2704 {
2706 {
2709 }
2711 {
2714 }
2716 {
2719 }
2720 else
2721 HALT_UNALLOC;
2722 }
2724 {
2727 }
2728 else
2729 HALT_UNALLOC;
2732 {
2754 HALT_UNALLOC;
2755 }
2756 }
2758 static void
2760 {
2761 /* instr[31,21] = 01001110000
2762 instr[20,16] = element size and index
2763 instr[15,10] = 000111
2764 instr[9,5] = W source
2765 instr[4,0] = V dest */
2776 {
2780 }
2782 {
2786 }
2788 {
2792 }
2794 {
2798 }
2799 else
2800 HALT_NYI;
2801 }
2803 static void
2805 {
2806 /* instr[31] = 0
2807 instr[30] = half(0)/full(1)
2808 instr[29,21] = 00 1110 000
2809 instr[20,16] = element size and index
2810 instr[15,10] = 0000 01
2811 instr[9,5] = V source
2812 instr[4,0] = V dest. */
2824 {
2829 }
2831 {
2836 }
2838 {
2843 }
2844 else
2845 {
2847 HALT_UNALLOC;
2850 HALT_UNALLOC;
2856 }
2857 }
2859 static void
2861 {
2862 /* instr[31] = 0
2863 instr[30] = half(0)/full(1)
2864 instr[29,21] = 00 1110 000
2865 instr[20,16] = Vm
2866 instr[15] = 0
2867 instr[14,13] = vec length
2868 instr[12,10] = 000
2869 instr[9,5] = V start
2870 instr[4,0] = V dest */
2884 {
2896 else
2900 }
2901 }
2903 static void
2905 {
2906 /* instr[31] = 0
2907 instr[30] = half(0)/full(1)
2908 instr[29,24] = 00 1110
2909 instr[23,22] = size
2910 instr[21] = 0
2911 instr[20,16] = Vm
2912 instr[15] = 0
2913 instr[14] = TRN1 (0) / TRN2 (1)
2914 instr[13,10] = 1010
2915 instr[9,5] = V source
2916 instr[4,0] = V dest. */
2930 {
2933 {
2934 aarch64_set_vec_u8
2937 aarch64_set_vec_u8
2940 }
2945 {
2946 aarch64_set_vec_u16
2949 aarch64_set_vec_u16
2952 }
2956 aarch64_set_vec_u32
2958 aarch64_set_vec_u32
2960 aarch64_set_vec_u32
2962 aarch64_set_vec_u32
2968 HALT_UNALLOC;
2975 }
2976 }
2978 static void
2980 {
2981 /* instr[31] = 0
2982 instr[30] = 0=> zero top 64-bits, 1=> duplicate into top 64-bits
2983 [must be 1 for 64-bit xfer]
2984 instr[29,20] = 00 1110 0000
2985 instr[19,16] = element size: 0001=> 8-bits, 0010=> 16-bits,
2986 0100=> 32-bits. 1000=>64-bits
2987 instr[15,10] = 0000 11
2988 instr[9,5] = W source
2989 instr[4,0] = V dest. */
3001 {
3019 HALT_NYI;
3025 HALT_NYI;
3026 }
3027 }
3029 static void
3031 {
3032 /* instr[31] = 0
3033 instr[30] = half(0)/full(1)
3034 instr[29,24] = 00 1110
3035 instr[23,22] = size: byte(00), half(01), word (10), long (11)
3036 instr[21] = 0
3037 instr[20,16] = Vm
3038 instr[15] = 0
3039 instr[14] = lower (0) / upper (1)
3040 instr[13,10] = 0110
3041 instr[9,5] = Vn
3042 instr[4,0] = Vd. */
3068 {
3081 {
3091 }
3102 {
3108 }
3116 {
3119 }
3124 HALT_UNALLOC;
3129 }
3134 }
3136 static void
3138 {
3139 /* instr[31] = 0
3140 instr[30] = half(0)/full(1)
3141 instr[29,24] = 00 1110
3142 instr[23,22] = size: byte(00), hald(01), word (10), long (11)
3143 instr[21] = 0
3144 instr[20,16] = Vm
3145 instr[15] = 0
3146 instr[14] = lower (0) / upper (1)
3147 instr[13,10] = 1110
3148 instr[9,5] = Vn
3149 instr[4,0] = Vd. */
3176 {
3178 val1 =
3188 val2 =
3200 val1 =
3206 val2 =
3222 }
3227 }
3229 /* Floating point immediates are encoded in 8 bits.
3230 fpimm[7] = sign bit.
3231 fpimm[6:4] = signed exponent.
3232 fpimm[3:0] = fraction (assuming leading 1).
3233 i.e. F = s * 1.f * 2^(e - b). */
3235 static float
3237 {
3245 /* The fp value is s * n/16 * 2r where n is 16+e. */
3248 /* N.B. exponent is signed. */
3250 {
3255 }
3256 else
3257 {
3262 }
3268 }
3270 static double
3272 {
3280 /* The fp value is s * n/16 * 2r where n is 16+e. */
3283 /* N.B. exponent is signed. */
3285 {
3290 }
3291 else
3292 {
3297 }
3303 }
3305 static void
3307 {
3308 /* instr[31] = 0
3309 instr[30] = full/half selector
3310 instr[29,19] = 00111100000
3311 instr[18,16] = high 3 bits of uimm8
3312 instr[15,12] = size & shift:
3313 0000 => 32-bit
3314 0010 => 32-bit + LSL#8
3315 0100 => 32-bit + LSL#16
3316 0110 => 32-bit + LSL#24
3317 1010 => 16-bit + LSL#8
3318 1000 => 16-bit
3319 1101 => 32-bit + MSL#16
3320 1100 => 32-bit + MSL#8
3321 1110 => 8-bit
3322 1111 => double
3323 instr[11,10] = 01
3324 instr[9,5] = low 5-bits of uimm8
3325 instr[4,0] = Vd. */
3337 {
3349 ATTRIBUTE_FALLTHROUGH;
3358 ATTRIBUTE_FALLTHROUGH;
3372 {
3377 }
3380 HALT_NYI;
3381 }
3382 }
3384 static void
3386 {
3387 /* instr[31] = 0
3388 instr[30] = full/half selector
3389 instr[29,19] = 10111100000
3390 instr[18,16] = high 3 bits of uimm8
3391 instr[15,12] = selector
3392 instr[11,10] = 01
3393 instr[9,5] = low 5-bits of uimm8
3394 instr[4,0] = Vd. */
3406 {
3419 ATTRIBUTE_FALLTHROUGH;
3429 ATTRIBUTE_FALLTHROUGH;
3439 {
3448 }
3451 {
3455 HALT_UNALLOC;
3460 }
3463 HALT_NYI;
3464 }
3465 }
3467 #define ABS(A) ((A) < 0 ? - (A) : (A))
3469 static void
3471 {
3472 /* instr[31] = 0
3473 instr[30] = half(0)/full(1)
3474 instr[29,24] = 00 1110
3475 instr[23,22] = size: 00=> 8-bit, 01=> 16-bit, 10=> 32-bit, 11=> 64-bit
3476 instr[21,10] = 10 0000 1011 10
3477 instr[9,5] = Vn
3478 instr[4.0] = Vd. */
3490 {
3511 HALT_NYI;
3516 }
3517 }
3519 static void
3521 {
3522 /* instr[31] = 0
3523 instr[30] = full/half selector
3524 instr[29,24] = 00 1110
3525 instr[23,22] = size: 00=> 8-bit, 01=> 16-bit, 10=> 32-bit, 11=> 64-bit
3526 instr[21,10] = 11 0001 1011 10
3527 instr[9,5] = Vm
3528 instr[4.0] = Rd. */
3540 {
3542 {
3548 }
3551 {
3557 }
3560 {
3563 HALT_UNALLOC;
3568 }
3571 HALT_UNALLOC;
3572 }
3573 }
3575 static void
3577 {
3578 /* instr[31,21] = 01001110000
3579 instr[20,18] = size & element selector
3580 instr[17,14] = 0000
3581 instr[13] = direction: to vec(0), from vec (1)
3582 instr[12,10] = 111
3583 instr[9,5] = Vm
3584 instr[4,0] = Vd. */
3596 {
3598 {
3599 /* 32-bit moves. */
3603 }
3604 else
3605 {
3606 /* 64-bit moves. */
3608 HALT_NYI;
3613 }
3614 }
3615 else
3616 {
3618 {
3619 /* 32-bit moves. */
3623 }
3624 else
3625 {
3626 /* 64-bit moves. */
3628 HALT_NYI;
3633 }
3634 }
3635 }
3637 #define DO_VEC_WIDENING_MUL(N, DST_TYPE, READ_TYPE, WRITE_TYPE) \
3638 do \
3639 { \
3640 DST_TYPE a[N], b[N]; \
3641 \
3642 for (i = 0; i < (N); i++) \
3643 { \
3644 a[i] = aarch64_get_vec_##READ_TYPE (cpu, vn, i + bias); \
3645 b[i] = aarch64_get_vec_##READ_TYPE (cpu, vm, i + bias); \
3646 } \
3647 for (i = 0; i < (N); i++) \
3648 aarch64_set_vec_##WRITE_TYPE (cpu, vd, i, a[i] * b[i]); \
3649 } \
3650 while (0)
3652 static void
3654 {
3655 /* instr[31] = 0
3656 instr[30] = lower(0)/upper(1) selector
3657 instr[29] = signed(0)/unsigned(1)
3658 instr[28,24] = 0 1110
3659 instr[23,22] = size: 8-bit (00), 16-bit (01), 32-bit (10)
3660 instr[21] = 1
3661 instr[20,16] = Vm
3662 instr[15,10] = 11 0000
3663 instr[9,5] = Vn
3664 instr[4.0] = Vd. */
3677 /* NB: Read source values before writing results, in case
3678 the source and destination vectors are the same. */
3680 {
3686 else
3695 else
3704 else
3709 HALT_NYI;
3710 }
3711 }
3713 static void
3715 {
3716 /* instr[31] = 0
3717 instr[30] = half(0)/full(1)
3718 instr[29,24] = 001110
3719 instr[23] = FADD(0)/FSUB(1)
3720 instr[22] = float (0)/double(1)
3721 instr[21] = 1
3722 instr[20,16] = Vm
3723 instr[15,10] = 110101
3724 instr[9,5] = Vn
3725 instr[4.0] = Vd. */
3739 {
3741 {
3743 HALT_NYI;
3749 }
3750 else
3751 {
3756 }
3757 }
3758 else
3759 {
3761 {
3763 HALT_NYI;
3769 }
3770 else
3771 {
3776 }
3777 }
3778 }
3780 static void
3782 {
3783 /* instr[31] = 0
3784 instr[30] = full/half selector
3785 instr[29,24] = 001110
3786 instr[23,22] = size: 00=> 8-bit, 01=> 16-bit, 10=> 32-bit, 11=> 64-bit
3787 instr[21] = 1
3788 instr[20,16] = Vn
3789 instr[15,10] = 100001
3790 instr[9,5] = Vm
3791 instr[4.0] = Vd. */
3805 {
3826 HALT_UNALLOC;
3833 }
3834 }
3836 static void
3838 {
3839 /* instr[31] = 0
3840 instr[30] = full/half selector
3841 instr[29,24] = 00 1110
3842 instr[23,22] = size: 00=> 8-bit, 01=> 16-bit, 10=> 32-bit
3843 instr[21] = 1
3844 instr[20,16] = Vn
3845 instr[15,10] = 10 0111
3846 instr[9,5] = Vm
3847 instr[4.0] = Vd. */
3862 {
3876 HALT_UNALLOC;
3877 }
3878 }
3880 static void
3882 {
3883 /* instr[31] = 0
3884 instr[30] = full/half selector
3885 instr[29,24] = 00 1110
3886 instr[23,22] = size: 00=> 8-bit, 01=> 16-bit, 10=> 32-bit
3887 instr[21] = 1
3888 instr[20,16] = Vn
3889 instr[15,10] = 1001 01
3890 instr[9,5] = Vm
3891 instr[4.0] = Vd. */
3905 {
3931 HALT_UNALLOC;
3932 }
3933 }
3935 static float
3937 {
3939 {
3943 }
3947 }
3949 static float
3951 {
3953 {
3957 }
3961 }
3963 static double
3965 {
3967 {
3971 }
3975 }
3977 static double
3979 {
3981 {
3985 }
3989 }
3991 static void
3993 {
3994 /* instr [31] = 0
3995 instr [30] = half (0)/full (1)
3996 instr [29,24] = 10 1110
3997 instr [23] = max(0)/min(1)
3998 instr [22] = float (0)/double (1)
3999 instr [21] = 1
4000 instr [20,16] = Vn
4001 instr [15,10] = 1100 01
4002 instr [9,5] = Vm
4003 instr [4.0] = Vd. */
4016 {
4021 HALT_NYI;
4028 }
4029 else
4030 {
4049 }
4050 }
4052 static void
4054 {
4055 /* instr[31] = 0
4056 instr[30] = half (0)/full (1)
4057 instr[29,21] = 001110001
4058 instr[20,16] = Vm
4059 instr[15,10] = 000111
4060 instr[9,5] = Vn
4061 instr[4.0] = Vd. */
4077 }
4079 static void
4081 {
4082 /* instr[31] = 0
4083 instr[30] = half (0)/full (1)
4084 instr[29,21] = 101110011
4085 instr[20,16] = Vm
4086 instr[15,10] = 000111
4087 instr[9,5] = Vn
4088 instr[4.0] = Vd. */
4106 }
4108 static void
4110 {
4111 /* instr[31] = 0
4112 instr[30] = half (0)/full (1)
4113 instr[29,21] = 10 1110 001
4114 instr[20,16] = Vm
4115 instr[15,10] = 000111
4116 instr[9,5] = Vn
4117 instr[4.0] = Vd. */
4133 }
4135 static void
4137 {
4138 /* instr[31] = 0
4139 instr[30] = half (0)/full (1)
4140 instr[29,23] = 10 1110 1
4141 instr[22] = BIT (0) / BIF (1)
4142 instr[21] = 1
4143 instr[20,16] = Vm
4144 instr[15,10] = 0001 11
4145 instr[9,5] = Vn
4146 instr[4.0] = Vd. */
4161 {
4168 else
4171 }
4172 }
4174 static void
4176 {
4177 /* instr[31] = 0
4178 instr[30] = half (0)/full (1)
4179 instr[29,21] = 00 1110 111
4180 instr[20,16] = Vm
4181 instr[15,10] = 00 0111
4182 instr[9,5] = Vn
4183 instr[4.0] = Vd. */
4199 }
4201 static void
4203 {
4204 /* instr[31] = 0
4205 instr[30] = half (0)/full (1)
4206 instr[29,21] = 00 1110 101
4207 instr[20,16] = Vm
4208 instr[15,10] = 0001 11
4209 instr[9,5] = Vn
4210 instr[4.0] = Vd. */
4226 }
4228 static void
4230 {
4231 /* instr[31] = 0
4232 instr[30] = half (0)/full (1)
4233 instr[29,21] = 00 1110 011
4234 instr[20,16] = Vm
4235 instr[15,10] = 00 0111
4236 instr[9,5] = Vn
4237 instr[4.0] = Vd. */
4253 }
4255 static void
4257 {
4258 /* instr[31] = 0
4259 instr[30] = first part (0)/ second part (1)
4260 instr[29,24] = 00 1110
4261 instr[23,22] = size: byte(00), half(01), word (10)
4262 instr[21,10] = 1000 0100 1010
4263 instr[9,5] = Vs
4264 instr[4,0] = Vd. */
4276 {
4294 }
4295 }
4297 /* Return the number of bits set in the input value. */
4298 #if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 4)
4299 # define popcount __builtin_popcount
4300 #else
4301 static int
4303 {
4305 {
4310 };
4312 /* Only counts the low 8 bits of the input as that is all we need. */
4314 }
4315 #endif
4317 static void
4319 {
4320 /* instr[31] = 0
4321 instr[30] = half (0)/ full (1)
4322 instr[29,24] = 00 1110
4323 instr[23,22] = size: byte(00)
4324 instr[21,10] = 1000 0001 0110
4325 instr[9,5] = Vs
4326 instr[4,0] = Vd. */
4338 HALT_UNALLOC;
4345 }
4347 static void
4349 {
4350 /* instr[31] = 0
4351 instr[30] = half(0)/full(1)
4352 instr[29] = signed (0)/unsigned(1)
4353 instr[28,24] = 0 1110
4354 instr[23,22] = size: byte(00), half(01), word (10)
4355 instr[21] = 1
4356 instr[20,17] = 1 000
4357 instr[16] = max(0)/min(1)
4358 instr[15,10] = 1010 10
4359 instr[9,5] = V source
4360 instr[4.0] = R dest. */
4374 {
4376 {
4379 {
4396 HALT_UNALLOC;
4397 }
4400 }
4403 {
4406 {
4424 HALT_UNALLOC;
4425 }
4428 }
4431 {
4434 {
4452 HALT_UNALLOC;
4453 }
4456 }
4459 {
4462 {
4480 HALT_UNALLOC;
4481 }
4484 }
4485 }
4486 }
4488 static void
4490 {
4491 /* instr[31,24] = 0110 1110
4492 instr[23] = max(0)/min(1)
4493 instr[22,14] = 011 0000 11
4494 instr[13,12] = nm(00)/normal(11)
4495 instr[11,10] = 10
4496 instr[9,5] = V source
4497 instr[4.0] = R dest. */
4510 {
4512 {
4524 HALT_NYI;
4525 }
4526 }
4527 else
4528 {
4530 {
4542 HALT_NYI;
4543 }
4544 }
4547 }
4549 static void
4551 {
4552 /* instr[31] = 0
4553 instr[30] = half(0)/full(1)
4554 instr[29,24] = 00 1110
4555 instr[23] = max(0)/min(1)
4556 instr[22] = float(0)/double(1)
4557 instr[21] = 1
4558 instr[20,16] = Vm
4559 instr[15,14] = 11
4560 instr[13,12] = nm(00)/normal(11)
4561 instr[11,10] = 01
4562 instr[9,5] = Vn
4563 instr[4,0] = Vd. */
4579 {
4583 HALT_NYI;
4589 else
4590 HALT_NYI;
4596 }
4597 else
4598 {
4605 else
4606 HALT_NYI;
4612 }
4613 }
4615 static void
4617 {
4618 /* instr[31] = 0
4619 instr[30] = Q
4620 instr[29,23] = 00 1110 0
4621 instr[22] = float(0)/double(1)
4622 instr[21,10] = 10 0001 1101 10
4623 instr[9,5] = Vn
4624 instr[4,0] = Vd. */
4637 {
4639 HALT_UNALLOC;
4642 {
4645 }
4646 }
4647 else
4648 {
4650 {
4653 }
4654 }
4655 }
4657 #define VEC_CMP(SOURCE, CMP) \
4658 do \
4659 { \
4660 switch (size) \
4661 { \
4662 case 0: \
4663 for (i = 0; i < (full ? 16 : 8); i++) \
4664 aarch64_set_vec_u8 (cpu, vd, i, \
4665 aarch64_get_vec_##SOURCE##8 (cpu, vn, i) \
4666 CMP \
4667 aarch64_get_vec_##SOURCE##8 (cpu, vm, i) \
4668 ? -1 : 0); \
4669 return; \
4670 case 1: \
4671 for (i = 0; i < (full ? 8 : 4); i++) \
4672 aarch64_set_vec_u16 (cpu, vd, i, \
4673 aarch64_get_vec_##SOURCE##16 (cpu, vn, i) \
4674 CMP \
4675 aarch64_get_vec_##SOURCE##16 (cpu, vm, i) \
4676 ? -1 : 0); \
4677 return; \
4678 case 2: \
4679 for (i = 0; i < (full ? 4 : 2); i++) \
4680 aarch64_set_vec_u32 (cpu, vd, i, \
4681 aarch64_get_vec_##SOURCE##32 (cpu, vn, i) \
4682 CMP \
4683 aarch64_get_vec_##SOURCE##32 (cpu, vm, i) \
4684 ? -1 : 0); \
4685 return; \
4686 case 3: \
4687 if (! full) \
4688 HALT_UNALLOC; \
4689 for (i = 0; i < 2; i++) \
4690 aarch64_set_vec_u64 (cpu, vd, i, \
4691 aarch64_get_vec_##SOURCE##64 (cpu, vn, i) \
4692 CMP \
4693 aarch64_get_vec_##SOURCE##64 (cpu, vm, i) \
4694 ? -1ULL : 0); \
4695 return; \
4696 default: \
4697 HALT_UNALLOC; \
4698 } \
4699 } \
4700 while (0)
4702 #define VEC_CMP0(SOURCE, CMP) \
4703 do \
4704 { \
4705 switch (size) \
4706 { \
4707 case 0: \
4708 for (i = 0; i < (full ? 16 : 8); i++) \
4709 aarch64_set_vec_u8 (cpu, vd, i, \
4710 aarch64_get_vec_##SOURCE##8 (cpu, vn, i) \
4711 CMP 0 ? -1 : 0); \
4712 return; \
4713 case 1: \
4714 for (i = 0; i < (full ? 8 : 4); i++) \
4715 aarch64_set_vec_u16 (cpu, vd, i, \
4716 aarch64_get_vec_##SOURCE##16 (cpu, vn, i) \
4717 CMP 0 ? -1 : 0); \
4718 return; \
4719 case 2: \
4720 for (i = 0; i < (full ? 4 : 2); i++) \
4721 aarch64_set_vec_u32 (cpu, vd, i, \
4722 aarch64_get_vec_##SOURCE##32 (cpu, vn, i) \
4723 CMP 0 ? -1 : 0); \
4724 return; \
4725 case 3: \
4726 if (! full) \
4727 HALT_UNALLOC; \
4728 for (i = 0; i < 2; i++) \
4729 aarch64_set_vec_u64 (cpu, vd, i, \
4730 aarch64_get_vec_##SOURCE##64 (cpu, vn, i) \
4731 CMP 0 ? -1ULL : 0); \
4732 return; \
4733 default: \
4734 HALT_UNALLOC; \
4735 } \
4736 } \
4737 while (0)
4739 #define VEC_FCMP0(CMP) \
4740 do \
4741 { \
4742 if (vm != 0) \
4743 HALT_NYI; \
4744 if (INSTR (22, 22)) \
4745 { \
4746 if (! full) \
4747 HALT_NYI; \
4748 for (i = 0; i < 2; i++) \
4749 aarch64_set_vec_u64 (cpu, vd, i, \
4750 aarch64_get_vec_double (cpu, vn, i) \
4751 CMP 0.0 ? -1 : 0); \
4752 } \
4753 else \
4754 { \
4755 for (i = 0; i < (full ? 4 : 2); i++) \
4756 aarch64_set_vec_u32 (cpu, vd, i, \
4757 aarch64_get_vec_float (cpu, vn, i) \
4758 CMP 0.0 ? -1 : 0); \
4759 } \
4760 return; \
4761 } \
4762 while (0)
4764 #define VEC_FCMP(CMP) \
4765 do \
4766 { \
4767 if (INSTR (22, 22)) \
4768 { \
4769 if (! full) \
4770 HALT_NYI; \
4771 for (i = 0; i < 2; i++) \
4772 aarch64_set_vec_u64 (cpu, vd, i, \
4773 aarch64_get_vec_double (cpu, vn, i) \
4774 CMP \
4775 aarch64_get_vec_double (cpu, vm, i) \
4776 ? -1 : 0); \
4777 } \
4778 else \
4779 { \
4780 for (i = 0; i < (full ? 4 : 2); i++) \
4781 aarch64_set_vec_u32 (cpu, vd, i, \
4782 aarch64_get_vec_float (cpu, vn, i) \
4783 CMP \
4784 aarch64_get_vec_float (cpu, vm, i) \
4785 ? -1 : 0); \
4786 } \
4787 return; \
4788 } \
4789 while (0)
4791 static void
4793 {
4794 /* instr[31] = 0
4795 instr[30] = half(0)/full(1)
4796 instr[29] = part-of-comparison-type
4797 instr[28,24] = 0 1110
4798 instr[23,22] = size of integer compares: byte(00), half(01), word (10), long (11)
4799 type of float compares: single (-0) / double (-1)
4800 instr[21] = 1
4801 instr[20,16] = Vm or 00000 (compare vs 0)
4802 instr[15,10] = part-of-comparison-type
4803 instr[9,5] = Vn
4804 instr[4.0] = Vd. */
4821 {
4822 /* A compare vs 0. */
4824 {
4833 else
4834 HALT_NYI;
4836 }
4837 }
4840 {
4841 /* A floating point compare. */
4848 {
4859 HALT_NYI;
4860 }
4861 }
4862 else
4863 {
4867 {
4881 HALT_NYI;
4883 }
4884 }
4885 }
4887 static void
4889 {
4890 /* instr[31] = 0
4891 instr[30] = first part (0)/ second part (1)
4892 instr[29,24] = 00 1110
4893 instr[23,22] = size: byte(00), half(01), word (10), long (11)
4894 instr[21] = 1
4895 instr[20,16] = Vm
4896 instr[15,10] = 0100 01
4897 instr[9,5] = Vn
4898 instr[4,0] = Vd. */
4911 /* FIXME: What is a signed shift left in this context ?. */
4915 {
4918 {
4923 else
4926 }
4931 {
4936 else
4939 }
4944 {
4949 else
4952 }
4957 HALT_UNALLOC;
4959 {
4964 else
4967 }
4969 }
4970 }
4972 static void
4974 {
4975 /* instr[31] = 0
4976 instr[30] = first part (0)/ second part (1)
4977 instr[29,24] = 10 1110
4978 instr[23,22] = size: byte(00), half(01), word (10), long (11)
4979 instr[21] = 1
4980 instr[20,16] = Vm
4981 instr[15,10] = 0100 01
4982 instr[9,5] = Vn
4983 instr[4,0] = Vd */
4997 {
5000 {
5005 else
5008 }
5013 {
5018 else
5021 }
5026 {
5031 else
5034 }
5039 HALT_UNALLOC;
5041 {
5046 else
5049 }
5051 }
5052 }
5054 static void
5056 {
5057 /* instr[31] = 0
5058 instr[30] = full/half selector
5059 instr[29,23] = 0011100
5060 instr[22] = size: 0=>float, 1=>double
5061 instr[21] = 1
5062 instr[20,16] = Vn
5063 instr[15,10] = 1100 11
5064 instr[9,5] = Vm
5065 instr[4.0] = Vd. */
5079 {
5081 HALT_UNALLOC;
5087 }
5088 else
5089 {
5095 }
5096 }
5098 static void
5100 {
5101 /* instr[31] = 0
5102 instr[30] = full/half selector
5103 instr[29] = SMAX (0) / UMAX (1)
5104 instr[28,24] = 0 1110
5105 instr[23,22] = size: 00=> 8-bit, 01=> 16-bit, 10=> 32-bit
5106 instr[21] = 1
5107 instr[20,16] = Vn
5108 instr[15,10] = 0110 01
5109 instr[9,5] = Vm
5110 instr[4.0] = Vd. */
5124 {
5126 {
5155 HALT_UNALLOC;
5156 }
5157 }
5158 else
5159 {
5161 {
5190 HALT_UNALLOC;
5191 }
5192 }
5193 }
5195 static void
5197 {
5198 /* instr[31] = 0
5199 instr[30] = full/half selector
5200 instr[29] = SMIN (0) / UMIN (1)
5201 instr[28,24] = 0 1110
5202 instr[23,22] = size: 00=> 8-bit, 01=> 16-bit, 10=> 32-bit
5203 instr[21] = 1
5204 instr[20,16] = Vn
5205 instr[15,10] = 0110 11
5206 instr[9,5] = Vm
5207 instr[4.0] = Vd. */
5221 {
5223 {
5252 HALT_UNALLOC;
5253 }
5254 }
5255 else
5256 {
5258 {
5287 HALT_UNALLOC;
5288 }
5289 }
5290 }
5292 static void
5294 {
5295 /* instr[31] = 0
5296 instr[30] = lower (0) / upper (1)
5297 instr[29] = signed (0) / unsigned (1)
5298 instr[28,24] = 0 1110
5299 instr[23,22] = size: bytes (00), half (01), word (10)
5300 instr[21] = 1
5301 insrt[20,16] = Vm
5302 instr[15,10] = 0010 00
5303 instr[9,5] = Vn
5304 instr[4,0] = V dest. */
5318 HALT_UNALLOC;
5322 {
5325 ATTRIBUTE_FALLTHROUGH;
5328 {
5353 HALT_UNALLOC;
5354 }
5359 ATTRIBUTE_FALLTHROUGH;
5362 {
5387 HALT_UNALLOC;
5388 }
5390 }
5391 }
5393 static void
5395 {
5396 /* instr[31] = 0
5397 instr[30] = half(0)/full(1)
5398 instr[29,24] = 00 1110
5399 instr[23,22] = size: bytes (00), half (01), word (10), long (11)
5400 instr[21] = 1
5401 insrt[20,16] = Vm
5402 instr[15,10] = 1011 11
5403 instr[9,5] = Vn
5404 instr[4,0] = V dest. */
5407 FRegister copy_vn;
5408 FRegister copy_vm;
5420 /* Make copies of the source registers in case vd == vn/vm. */
5426 {
5430 {
5435 }
5441 {
5446 }
5452 {
5457 }
5462 HALT_UNALLOC;
5466 }
5467 }
5469 /* Float point vector convert to longer (precision). */
5470 static void
5472 {
5473 /* instr[31] = 0
5474 instr[30] = half (0) / all (1)
5475 instr[29,23] = 00 1110 0
5476 instr[22] = single (0) / double (1)
5477 instr[21,10] = 10 0001 0111 10
5478 instr[9,5] = Rn
5479 instr[4,0] = Rd. */
5492 {
5496 }
5497 else
5498 {
5499 HALT_NYI;
5501 #if 0
5502 /* TODO: Implement missing half-float support. */
5506 #endif
5507 }
5508 }
5510 static void
5512 {
5513 /* instr[31] = 0
5514 instr[30] = half(0)/full(1)
5515 instr[29,23] = 00 1110 1
5516 instr[22] = float(0)/double(1)
5517 instr[21,16] = 10 0000
5518 instr[15,10] = 1111 10
5519 instr[9,5] = Vn
5520 instr[4,0] = Vd. */
5532 {
5534 HALT_NYI;
5539 }
5540 else
5541 {
5545 }
5546 }
5548 static void
5550 {
5551 /* instr[31] = 0
5552 instr[30] = half (0) / all (1)
5553 instr[29,23] = 00 1110 1
5554 instr[22] = single (0) / double (1)
5555 instr[21,10] = 10 0001 1011 10
5556 instr[9,5] = Rn
5557 instr[4,0] = Rd. */
5570 {
5572 HALT_UNALLOC;
5577 }
5578 else
5582 }
5584 static void
5586 {
5587 /* instr[31] = 0
5588 instr[30] = full/half
5589 instr[29,24] = 00 1110
5590 instr[23,22] = size
5591 instr[21,10] = 10 0000 0000 10
5592 instr[9,5] = Rn
5593 instr[4,0] = Rd. */
5600 FRegister val;
5607 {
5624 HALT_UNALLOC;
5625 }
5630 }
5632 static void
5634 {
5635 /* instr[31] = 0
5636 instr[30] = full/half
5637 instr[29,24] = 00 1110
5638 instr[23,22] = size
5639 instr[21,10] = 10 0000 0001 10
5640 instr[9,5] = Rn
5641 instr[4,0] = Rd. */
5648 FRegister val;
5655 {
5662 HALT_UNALLOC;
5663 }
5668 }
5670 static void
5672 {
5673 /* instr[31] = 0
5674 instr[30] = half/full
5675 instr[29,24] = 00 1110
5676 instr[23,21] = ???
5677 instr[20,16] = Vm
5678 instr[15,10] = sub-opcode
5679 instr[9,5] = Vn
5680 instr[4,0] = Vd */
5684 {
5686 {
5693 {
5717 HALT_NYI;
5718 }
5719 }
5722 {
5727 }
5728 }
5731 {
5737 {
5743 }
5761 {
5764 }
5768 {
5773 }
5795 HALT_NYI;
5796 }
5797 }
5799 static void
5801 {
5802 /* instr[31] = 0
5803 instr[30,29] = SXTL (00), UXTL (01), SXTL2 (10), UXTL2 (11)
5804 instr[28,22] = 0 1111 00
5805 instr[21,16] = size & shift (USHLL, SSHLL, USHLL2, SSHLL2)
5806 instr[15,10] = 1010 01
5807 instr[9,5] = V source
5808 instr[4,0] = V dest. */
5819 {
5822 ATTRIBUTE_FALLTHROUGH;
5825 {
5829 /* Get the source values before setting the destination values
5830 in case the source and destination are the same. */
5835 }
5837 {
5846 }
5847 else
5848 {
5858 }
5863 ATTRIBUTE_FALLTHROUGH;
5866 {
5873 }
5875 {
5883 }
5884 else
5885 {
5895 }
5897 }
5898 }
5900 static void
5902 {
5903 /* instr [31] = 0
5904 instr [30] = half(0)/full(1)
5905 instr [29,23] = 001 1110
5906 instr [22,16] = size and shift amount
5907 instr [15,10] = 01 0101
5908 instr [9, 5] = Vs
5909 instr [4, 0] = Vd. */
5922 {
5926 HALT_UNALLOC;
5929 {
5932 }
5935 }
5938 {
5942 {
5945 }
5948 }
5951 {
5955 {
5958 }
5961 }
5964 HALT_UNALLOC;
5969 {
5972 }
5973 }
5975 static void
5977 {
5978 /* instr [31] = 0
5979 instr [30] = half(0)/full(1)
5980 instr [29] = signed(0)/unsigned(1)
5981 instr [28,23] = 0 1111 0
5982 instr [22,16] = size and shift amount
5983 instr [15,10] = 0000 01
5984 instr [9, 5] = Vs
5985 instr [4, 0] = Vd. */
5999 {
6003 HALT_UNALLOC;
6007 {
6010 }
6011 else
6013 {
6016 }
6019 }
6022 {
6027 {
6030 }
6031 else
6033 {
6036 }
6039 }
6042 {
6047 {
6050 }
6051 else
6053 {
6056 }
6059 }
6062 HALT_UNALLOC;
6068 {
6071 }
6072 else
6074 {
6077 }
6078 }
6080 static void
6082 {
6083 /* instr[31] = 0
6084 instr[30] = half/full
6085 instr[29,24] = 00 1111
6086 instr[23,22] = size
6087 instr[21] = L
6088 instr[20] = M
6089 instr[19,16] = m
6090 instr[15,12] = 1000
6091 instr[11] = H
6092 instr[10] = 0
6093 instr[9,5] = Vn
6094 instr[4,0] = Vd */
6112 {
6114 {
6115 /* 16 bit products. */
6125 {
6129 }
6130 }
6134 {
6135 /* 32 bit products. */
6145 {
6149 }
6150 }
6154 HALT_UNALLOC;
6155 }
6156 }
6158 static void
6160 {
6161 /* instr[31] = 0
6162 instr[30] = half/full
6163 instr[29,23] = 00 1111 1
6164 instr[22] = size
6165 instr[21] = L
6166 instr[20,16] = m
6167 instr[15,12] = 0001
6168 instr[11] = H
6169 instr[10] = 0
6170 instr[9,5] = Vn
6171 instr[4,0] = Vd */
6188 {
6192 HALT_UNALLOC;
6197 {
6202 }
6203 }
6204 else
6205 {
6210 {
6215 }
6216 }
6217 }
6219 static void
6221 {
6222 /* instr[31] = 0
6223 instr[30] = half/full
6224 instr[29,24] = 00 1111
6225 instr[23] = ?
6226 instr[22,16] = element size & index
6227 instr[15,10] = sub-opcode
6228 instr[9,5] = Vm
6229 instr[4,0] = Vd */
6234 {
6236 {
6248 HALT_NYI;
6249 }
6250 }
6251 else
6252 {
6254 {
6261 }
6262 }
6263 }
6265 static void
6267 {
6268 /* instr[31] = 0
6269 instr[30] = full(1)/half(0)
6270 instr[29,24] = 10 1110
6271 instr[23,22] = size: byte(00), half (01), word (10), long (11)
6272 instr[21,10] = 1000 0010 1110
6273 instr[9,5] = Vs
6274 instr[4,0] = Vd */
6286 {
6304 HALT_NYI;
6308 }
6309 }
6311 static void
6313 {
6314 /* instr[31] = 0
6315 instr[30] = full(1)/half(0)
6316 instr[29,23] = 101 1101
6317 instr[22] = single(0)/double(1)
6318 instr[21,10] = 1000 0111 1110
6319 instr[9,5] = Vs
6320 instr[4,0] = Vd. */
6335 else
6339 }
6341 static void
6343 {
6344 /* instr[31] = 0
6345 instr[30] = half(0)/full(1)
6346 instr[29,24] = 10 1111
6347 instr[23,22] = 16-bit(01)/32-bit(10)
6348 instr[21,20+11] = index (if 16-bit)
6349 instr[21+11] = index (if 32-bit)
6350 instr[20,16] = Vm
6351 instr[15,12] = 0100
6352 instr[11] = part of index
6353 instr[10] = 0
6354 instr[9,5] = Vs
6355 instr[4,0] = Vd. */
6368 {
6370 {
6375 HALT_NYI;
6385 }
6388 {
6397 }
6402 HALT_NYI;
6403 }
6404 }
6406 static void
6408 {
6409 /* instr [31] = 0
6410 instr [30] = half(0)/full(1)
6411 instr [29,24] = 10 1110
6412 instr [23,22] = size: byte(00, half(01), word (10), long (11)
6413 instr [21] = 1
6414 instr [20,16] = Vm
6415 instr [15,10] = 10 0001
6416 instr [9, 5] = Vn
6417 instr [4, 0] = Vd. */
6431 {
6455 HALT_UNALLOC;
6462 }
6463 }
6465 static void
6467 {
6468 /* instr [31] = 0
6469 instr [30] = half(0)/full(1)
6470 instr [29,24] = 10 1110
6471 instr [23,22] = size: byte(00, half(01), word (10)
6472 instr [21] = 1
6473 instr [20,16] = Vm
6474 instr [15,10] = 10 0101
6475 instr [9, 5] = Vn
6476 instr [4, 0] = Vd. */
6490 {
6516 HALT_UNALLOC;
6517 }
6518 }
6520 static void
6522 {
6523 /* instr [31] = 0
6524 instr [30] = half(0)/full(1)
6525 instr [29,23] = 10 1110 0
6526 instr [22] = float()/double(1)
6527 instr [21] = 1
6528 instr [20,16] = Vm
6529 instr [15,10] = 1111 11
6530 instr [9, 5] = Vn
6531 instr [4, 0] = Vd. */
6545 {
6547 HALT_UNALLOC;
6553 }
6554 else
6559 }
6561 static void
6563 {
6564 /* instr [31] = 0
6565 instr [30] = half(0)/full(1)
6566 instr [29,23] = 10 1110 0
6567 instr [22] = float(0)/double(1)
6568 instr [21] = 1
6569 instr [20,16] = Vm
6570 instr [15,10] = 1101 11
6571 instr [9, 5] = Vn
6572 instr [4, 0] = Vd. */
6586 {
6588 HALT_UNALLOC;
6594 }
6595 else
6600 }
6602 static void
6604 {
6605 /* instr [31] = 0
6606 instr [30] = half(0)/full(1)
6607 instr [29,23] = 10 1110 0
6608 instr [22] = float(0)/double(1)
6609 instr [21] = 1
6610 instr [20,16] = Vm
6611 instr [15,10] = 1101 01
6612 instr [9, 5] = Vn
6613 instr [4, 0] = Vd. */
6626 {
6627 /* Extract values before adding them incase vd == vn/vm. */
6634 HALT_UNALLOC;
6638 }
6639 else
6640 {
6641 /* Extract values before adding them incase vd == vn/vm. */
6648 {
6658 }
6659 else
6660 {
6663 }
6664 }
6665 }
6667 static void
6669 {
6670 /* instr[31] = 0
6671 instr[30] = half(0)/full(1)
6672 instr[29,23] = 10 1110 1
6673 instr[22] = single(0)/double(1)
6674 instr[21,10] = 10 0001 1111 10
6675 instr[9,5] = Vsrc
6676 instr[4,0] = Vdest. */
6688 {
6690 HALT_UNALLOC;
6695 }
6696 else
6697 {
6701 }
6702 }
6704 static void
6706 {
6707 /* instr[31] = 0
6708 instr[30] = half (0)/full (1)
6709 instr[29,23] = 10 1110 1
6710 instr[22] = single (0)/double (1)
6711 instr[21,10] = 10 0000 1111 10
6712 instr[9,5] = Vsrc
6713 instr[4,0] = Vdest. */
6725 {
6727 HALT_UNALLOC;
6732 }
6733 else
6734 {
6738 }
6739 }
6741 static void
6743 {
6744 /* instr[31] = 0
6745 instr[30] = half (0)/full (1)
6746 instr[29,10] = 10 1110 0010 0000 0101 10
6747 instr[9,5] = Vn
6748 instr[4.0] = Vd. */
6760 }
6762 static unsigned int
6764 {
6770 do
6771 {
6775 count ++;
6776 }
6780 }
6782 static void
6784 {
6785 /* instr[31] = 0
6786 instr[30] = half (0)/full (1)
6787 instr[29,24] = 10 1110
6788 instr[23,22] = size
6789 instr[21,10] = 10 0000 0100 10
6790 instr[9,5] = Vn
6791 instr[4.0] = Vd. */
6803 {
6818 HALT_UNALLOC;
6822 }
6823 }
6825 static void
6827 {
6828 /* instr[31,21] = 0110 1110 000
6829 instr[20,16] = size & dest index
6830 instr[15] = 0
6831 instr[14,11] = source index
6832 instr[10] = 1
6833 instr[9,5] = Vs
6834 instr[4.0] = Vd. */
6847 {
6848 /* Move a byte. */
6853 }
6855 {
6856 /* Move 16-bits. */
6862 }
6864 {
6865 /* Move 32-bits. */
6871 }
6872 else
6873 {
6880 }
6881 }
6883 static void
6885 {
6886 /* instr[31] = 0
6887 instr[30] = full/half
6888 instr[29,24] = 10 1110
6889 instr[23,22] = size
6890 instr[21,10] = 10 0000 0000 10
6891 instr[9,5] = Rn
6892 instr[4,0] = Rd. */
6899 FRegister val;
6906 {
6918 HALT_UNALLOC;
6919 }
6924 }
6926 static void
6928 {
6929 /* instr[31] = 0
6930 instr[30] = full/half
6931 instr[29,21] = 10 1110 000
6932 instr[20,16] = Vm
6933 instr[15] = 0
6934 instr[14,11] = source index
6935 instr[10] = 0
6936 instr[9,5] = Vn
6937 instr[4.0] = Vd. */
6946 FRegister val;
6953 HALT_UNALLOC;
6966 }
6968 static void
6970 {
6971 /* instr [28,25] = 0 111. */
6975 {
6978 {
6981 }
6982 }
6985 {
6988 }
6991 {
6994 }
6998 {
7000 {
7003 }
7004 }
7007 {
7013 {
7015 {
7022 {
7027 }
7045 {
7049 }
7065 }
7066 }
7069 {
7072 else
7075 }
7078 {
7083 {
7086 }
7088 }
7093 {
7099 HALT_NYI;
7100 }
7104 }
7106 HALT_NYI;
7107 }
7109 /* 3 sources. */
7111 /* Float multiply add. */
7112 static void
7114 {
7124 }
7126 /* Double multiply add. */
7127 static void
7129 {
7139 }
7141 /* Float multiply subtract. */
7142 static void
7144 {
7154 }
7156 /* Double multiply subtract. */
7157 static void
7159 {
7169 }
7171 /* Float negative multiply add. */
7172 static void
7174 {
7184 }
7186 /* Double negative multiply add. */
7187 static void
7189 {
7199 }
7201 /* Float negative multiply subtract. */
7202 static void
7204 {
7214 }
7216 /* Double negative multiply subtract. */
7217 static void
7219 {
7229 }
7231 static void
7233 {
7234 /* instr[31] ==> M : 0 ==> OK, 1 ==> UNALLOC
7235 instr[30] = 0
7236 instr[29] ==> S : 0 ==> OK, 1 ==> UNALLOC
7237 instr[28,25] = 1111
7238 instr[24] = 1
7239 instr[23,22] ==> type : 0 ==> single, 01 ==> double, 1x ==> UNALLOC
7240 instr[21] ==> o1 : 0 ==> unnegated, 1 ==> negated
7241 instr[15] ==> o2 : 0 ==> ADD, 1 ==> SUB */
7244 /* dispatch on combined type:o1:o2. */
7248 HALT_UNALLOC;
7251 {
7261 /* type > 1 is currently unallocated. */
7262 HALT_UNALLOC;
7263 }
7264 }
7266 static void
7268 {
7269 HALT_NYI;
7270 }
7272 static void
7274 {
7275 /* instr [31,23] = 0001 1110 0
7276 instr [22] = type
7277 instr [21] = 1
7278 instr [20,16] = Rm
7279 instr [15,12] = condition
7280 instr [11,10] = 01
7281 instr [9,5] = Rn
7282 instr [4] = 0
7283 instr [3,0] = nzcv */
7294 {
7297 }
7300 {
7301 /* Double precision. */
7305 /* FIXME: Check for NaNs. */
7312 }
7313 else
7314 {
7315 /* Single precision. */
7319 /* FIXME: Check for NaNs. */
7326 }
7327 }
7329 /* 2 sources. */
7331 /* Float add. */
7332 static void
7334 {
7342 }
7344 /* Double add. */
7345 static void
7347 {
7355 }
7357 /* Float divide. */
7358 static void
7360 {
7368 }
7370 /* Double divide. */
7371 static void
7373 {
7381 }
7383 /* Float multiply. */
7384 static void
7386 {
7394 }
7396 /* Double multiply. */
7397 static void
7399 {
7407 }
7409 /* Float negate and multiply. */
7410 static void
7412 {
7420 }
7422 /* Double negate and multiply. */
7423 static void
7425 {
7433 }
7435 /* Float subtract. */
7436 static void
7438 {
7446 }
7448 /* Double subtract. */
7449 static void
7451 {
7459 }
7461 static void
7463 {
7464 /* instr[31,23] = 0 0011 1100
7465 instr[22] = float(0)/double(1)
7466 instr[21] = 1
7467 instr[20,16] = Sm
7468 instr[15,10] = 01 1110
7469 instr[9,5] = Sn
7470 instr[4,0] = Cpu */
7484 else
7488 }
7490 static void
7492 {
7493 /* instr[31,23] = 0 0011 1100
7494 instr[22] = float(0)/double(1)
7495 instr[21] = 1
7496 instr[20,16] = Sm
7497 instr[15,10] = 01 1010
7498 instr[9,5] = Sn
7499 instr[4,0] = Cpu */
7513 else
7517 }
7519 static void
7521 {
7522 /* instr[31] ==> M : 0 ==> OK, 1 ==> UNALLOC
7523 instr[30] = 0
7524 instr[29] ==> S : 0 ==> OK, 1 ==> UNALLOC
7525 instr[28,25] = 1111
7526 instr[24] = 0
7527 instr[23,22] ==> type : 0 ==> single, 01 ==> double, 1x ==> UNALLOC
7528 instr[21] = 1
7529 instr[20,16] = Vm
7530 instr[15,12] ==> opcode : 0000 ==> FMUL, 0001 ==> FDIV
7531 0010 ==> FADD, 0011 ==> FSUB,
7532 0100 ==> FMAX, 0101 ==> FMIN
7533 0110 ==> FMAXNM, 0111 ==> FMINNM
7534 1000 ==> FNMUL, ow ==> UNALLOC
7535 instr[11,10] = 10
7536 instr[9,5] = Vn
7537 instr[4,0] = Vd */
7541 /* Dispatch on opcode. */
7545 HALT_UNALLOC;
7548 HALT_UNALLOC;
7552 {
7561 /* Have not yet implemented fmax and fmin. */
7564 HALT_NYI;
7567 HALT_UNALLOC;
7568 }
7571 {
7582 HALT_NYI;
7585 HALT_UNALLOC;
7586 }
7587 }
7589 static void
7591 {
7592 /* FCSEL
7593 instr[31,23] = 0 0011 1100
7594 instr[22] = 0=>single 1=>double
7595 instr[21] = 1
7596 instr[20,16] = Sm
7597 instr[15,12] = cond
7598 instr[11,10] = 11
7599 instr[9,5] = Sn
7600 instr[4,0] = Cpu */
7613 else
7616 }
7618 /* Store 32 bit unscaled signed 9 bit. */
7619 static void
7621 {
7628 }
7630 /* Store 64 bit unscaled signed 9 bit. */
7631 static void
7633 {
7640 }
7642 /* Store 128 bit unscaled signed 9 bit. */
7643 static void
7645 {
7648 FRegister a;
7655 }
7657 /* TODO FP move register. */
7659 /* 32 bit fp to fp move register. */
7660 static void
7662 {
7668 }
7670 /* 64 bit fp to fp move register. */
7671 static void
7673 {
7679 }
7681 /* 32 bit GReg to Vec move register. */
7682 static void
7684 {
7690 }
7692 /* 64 bit g to fp move register. */
7693 static void
7695 {
7701 }
7703 /* 32 bit fp to g move register. */
7704 static void
7706 {
7712 }
7714 /* 64 bit fp to g move register. */
7715 static void
7717 {
7723 }
7725 /* FP move immediate
7727 These install an immediate 8 bit value in the target register
7728 where the 8 bits comprise 1 sign bit, 4 bits of fraction and a 3
7729 bit exponent. */
7731 static void
7733 {
7740 }
7742 static void
7744 {
7751 }
7753 static void
7755 {
7756 /* instr[31,23] == 00111100
7757 instr[22] == type : single(0)/double(1)
7758 instr[21] == 1
7759 instr[20,13] == imm8
7760 instr[12,10] == 100
7761 instr[9,5] == imm5 : 00000 ==> PK, ow ==> UNALLOC
7762 instr[4,0] == Rd */
7768 HALT_UNALLOC;
7772 else
7774 }
7776 /* TODO specific decode and execute for group Load Store. */
7778 /* TODO FP load/store single register (unscaled offset). */
7780 /* TODO load 8 bit unscaled signed 9 bit. */
7781 /* TODO load 16 bit unscaled signed 9 bit. */
7783 /* Load 32 bit unscaled signed 9 bit. */
7784 static void
7786 {
7793 }
7795 /* Load 64 bit unscaled signed 9 bit. */
7796 static void
7798 {
7805 }
7807 /* Load 128 bit unscaled signed 9 bit. */
7808 static void
7810 {
7813 FRegister a;
7819 }
7821 /* TODO store 8 bit unscaled signed 9 bit. */
7822 /* TODO store 16 bit unscaled signed 9 bit. */
7825 /* 1 source. */
7827 /* Float absolute value. */
7828 static void
7830 {
7837 }
7839 /* Double absolute value. */
7840 static void
7842 {
7849 }
7851 /* Float negative value. */
7852 static void
7854 {
7860 }
7862 /* Double negative value. */
7863 static void
7865 {
7871 }
7873 /* Float square root. */
7874 static void
7876 {
7882 }
7884 /* Double square root. */
7885 static void
7887 {
7894 }
7896 /* Convert double to float. */
7897 static void
7899 {
7905 }
7907 /* Convert float to double. */
7908 static void
7910 {
7916 }
7918 static void
7920 {
7921 /* instr[31,23] = 0001 1110 0
7922 instr[22] = single(0)/double(1)
7923 instr[21,18] = 1001
7924 instr[17,15] = rounding mode
7925 instr[14,10] = 10000
7926 instr[9,5] = source
7927 instr[4,0] = dest */
7939 /* FIXME: Add support for rmode == 6 exactness check. */
7944 {
7948 {
7950 {
7954 {
7957 }
7961 }
7966 else
7973 else
7987 HALT_NYI;
7990 HALT_UNALLOC;
7991 }
7992 }
7997 {
7999 {
8003 {
8006 }
8010 }
8015 else
8022 else
8036 HALT_NYI;
8039 HALT_UNALLOC;
8040 }
8041 }
8043 /* Convert half to float. */
8044 static void
8046 {
8054 }
8056 /* Convert half to double. */
8057 static void
8059 {
8067 }
8069 static void
8071 {
8079 }
8081 /* Convert double to half. */
8082 static void
8084 {
8092 }
8094 static void
8096 {
8097 /* instr[31] ==> M : 0 ==> OK, 1 ==> UNALLOC
8098 instr[30] = 0
8099 instr[29] ==> S : 0 ==> OK, 1 ==> UNALLOC
8100 instr[28,25] = 1111
8101 instr[24] = 0
8102 instr[23,22] ==> type : 00 ==> source is single,
8103 01 ==> source is double
8104 10 ==> UNALLOC
8105 11 ==> UNALLOC or source is half
8106 instr[21] = 1
8107 instr[20,15] ==> opcode : with type 00 or 01
8108 000000 ==> FMOV, 000001 ==> FABS,
8109 000010 ==> FNEG, 000011 ==> FSQRT,
8110 000100 ==> UNALLOC, 000101 ==> FCVT,(to single/double)
8111 000110 ==> UNALLOC, 000111 ==> FCVT (to half)
8112 001000 ==> FRINTN, 001001 ==> FRINTP,
8113 001010 ==> FRINTM, 001011 ==> FRINTZ,
8114 001100 ==> FRINTA, 001101 ==> UNALLOC
8115 001110 ==> FRINTX, 001111 ==> FRINTI
8116 with type 11
8117 000100 ==> FCVT (half-to-single)
8118 000101 ==> FCVT (half-to-double)
8119 instr[14,10] = 10000. */
8126 HALT_UNALLOC;
8129 {
8134 else
8135 HALT_UNALLOC;
8137 }
8140 HALT_UNALLOC;
8143 {
8147 else
8154 else
8161 else
8168 else
8175 else
8176 HALT_UNALLOC;
8181 HALT_UNALLOC;
8198 else
8203 HALT_NYI;
8206 HALT_UNALLOC;
8207 }
8208 }
8210 /* 32 bit signed int to float. */
8211 static void
8213 {
8218 aarch64_set_FP_float
8220 }
8222 /* signed int to float. */
8223 static void
8225 {
8230 aarch64_set_FP_float
8232 }
8234 /* 32 bit signed int to double. */
8235 static void
8237 {
8242 aarch64_set_FP_double
8244 }
8246 /* signed int to double. */
8247 static void
8249 {
8254 aarch64_set_FP_double
8256 }
8267 #define UINT_MIN 0
8268 #define ULONG_MIN 0
8278 /* Check for FP exception conditions:
8279 NaN raises IO
8280 Infinity raises IO
8281 Out of Range raises IO and IX and saturates value
8282 Denormal raises ID and IX and sets to zero. */
8283 #define RAISE_EXCEPTIONS(F, VALUE, FTYPE, ITYPE) \
8284 do \
8285 { \
8286 switch (fpclassify (F)) \
8287 { \
8288 case FP_INFINITE: \
8289 case FP_NAN: \
8290 aarch64_set_FPSR (cpu, IO); \
8291 if (signbit (F)) \
8292 VALUE = ITYPE##_MAX; \
8293 else \
8294 VALUE = ITYPE##_MIN; \
8295 break; \
8296 \
8297 case FP_NORMAL: \
8298 if (F >= FTYPE##_##ITYPE##_MAX) \
8299 { \
8300 aarch64_set_FPSR_bits (cpu, IO | IX, IO | IX); \
8301 VALUE = ITYPE##_MAX; \
8302 } \
8303 else if (F <= FTYPE##_##ITYPE##_MIN) \
8304 { \
8305 aarch64_set_FPSR_bits (cpu, IO | IX, IO | IX); \
8306 VALUE = ITYPE##_MIN; \
8307 } \
8308 break; \
8309 \
8310 case FP_SUBNORMAL: \
8311 aarch64_set_FPSR_bits (cpu, IO | IX | ID, IX | ID); \
8312 VALUE = 0; \
8313 break; \
8314 \
8315 default: \
8316 case FP_ZERO: \
8317 VALUE = 0; \
8318 break; \
8319 } \
8320 } \
8321 while (0)
8323 /* 32 bit convert float to signed int truncate towards zero. */
8324 static void
8326 {
8329 /* TODO : check that this rounds toward zero. */
8336 /* Avoid sign extension to 64 bit. */
8338 }
8340 /* 64 bit convert float to signed int truncate towards zero. */
8341 static void
8343 {
8353 }
8355 /* 32 bit convert double to signed int truncate towards zero. */
8356 static void
8358 {
8361 /* TODO : check that this rounds toward zero. */
8368 /* Avoid sign extension to 64 bit. */
8370 }
8372 /* 64 bit convert double to signed int truncate towards zero. */
8373 static void
8375 {
8378 /* TODO : check that this rounds toward zero. */
8388 }
8390 static void
8392 {
8393 /* instr[31] = size: 32-bit (0), 64-bit (1)
8394 instr[30,23] = 00111100
8395 instr[22] = type: single (0)/ double (1)
8396 instr[21] = enable (0)/disable(1) precision
8397 instr[20,16] = 11001
8398 instr[15,10] = precision
8399 instr[9,5] = Rs
8400 instr[4,0] = Rd. */
8409 /* Convert to fixed point. */
8410 HALT_NYI;
8414 {
8415 /* Convert to unsigned 64-bit integer. */
8417 {
8421 /* Do not raise an exception if we have reached ULONG_MAX. */
8426 }
8427 else
8428 {
8432 /* Do not raise an exception if we have reached ULONG_MAX. */
8437 }
8438 }
8439 else
8440 {
8443 /* Convert to unsigned 32-bit integer. */
8445 {
8449 /* Do not raise an exception if we have reached UINT_MAX. */
8452 }
8453 else
8454 {
8458 /* Do not raise an exception if we have reached UINT_MAX. */
8461 }
8464 }
8465 }
8467 static void
8469 {
8470 /* instr[31] = size: 32-bit (0), 64-bit (1)
8471 instr[30,23] = 001 1110 0
8472 instr[22] = type: single (0)/ double (1)
8473 instr[21] = enable (0)/disable(1) precision
8474 instr[20,16] = 0 0011
8475 instr[15,10] = precision
8476 instr[9,5] = Rs
8477 instr[4,0] = Rd. */
8486 HALT_NYI;
8488 /* FIXME: Add exception raising. */
8491 {
8496 else
8498 }
8499 else
8500 {
8505 else
8507 }
8508 }
8510 static void
8512 {
8513 /* instr[31,17] == 100 1111 0101 0111
8514 instr[16] ==> direction 0=> to GR, 1=> from GR
8515 instr[15,10] => ???
8516 instr[9,5] ==> source
8517 instr[4,0] ==> dest. */
8525 HALT_UNALLOC;
8530 else
8532 }
8534 static void
8536 {
8537 /* instr[31] = size : 0 ==> 32 bit, 1 ==> 64 bit
8538 instr[30 = 0
8539 instr[29] = S : 0 ==> OK, 1 ==> UNALLOC
8540 instr[28,25] = 1111
8541 instr[24] = 0
8542 instr[23,22] = type : 00 ==> single, 01 ==> double, 1x ==> UNALLOC
8543 instr[21] = 1
8544 instr[20,19] = rmode
8545 instr[18,16] = opcode
8546 instr[15,10] = 10 0000 */
8555 {
8558 }
8563 HALT_UNALLOC;
8567 HALT_UNALLOC;
8573 {
8576 {
8582 }
8586 {
8590 }
8594 {
8598 }
8602 {
8608 }
8622 HALT_NYI;
8623 }
8624 }
8626 static void
8628 {
8631 /* FIXME: Add exception raising. */
8635 {
8636 /* Subtracting two infinities may give a NaN. We only need to compare
8637 the signs, which we can get from isinf. */
8646 }
8647 else
8648 {
8657 }
8660 }
8662 static void
8664 {
8673 }
8675 /* Float compare to zero -- Invalid Operation exception
8676 only on signaling NaNs. */
8677 static void
8679 {
8685 }
8687 /* Float compare -- Invalid Operation exception on all NaNs. */
8688 static void
8690 {
8699 }
8701 /* Float compare to zero -- Invalid Operation exception on all NaNs. */
8702 static void
8704 {
8710 }
8712 static void
8714 {
8717 /* FIXME: Add exception raising. */
8721 {
8722 /* Subtracting two infinities may give a NaN. We only need to compare
8723 the signs, which we can get from isinf. */
8732 }
8733 else
8734 {
8743 }
8746 }
8748 /* Double compare -- Invalid Operation exception only on signaling NaNs. */
8749 static void
8751 {
8760 }
8762 /* Double compare to zero -- Invalid Operation exception
8763 only on signaling NaNs. */
8764 static void
8766 {
8772 }
8774 /* Double compare -- Invalid Operation exception on all NaNs. */
8775 static void
8777 {
8786 }
8788 /* Double compare to zero -- Invalid Operation exception on all NaNs. */
8789 static void
8791 {
8797 }
8799 static void
8801 {
8802 /* assert instr[28,25] == 1111
8803 instr[30:24:21:13,10] = 0011000
8804 instr[31] = M : 0 ==> OK, 1 ==> UNALLOC
8805 instr[29] ==> S : 0 ==> OK, 1 ==> UNALLOC
8806 instr[23,22] ==> type : 0 ==> single, 01 ==> double, 1x ==> UNALLOC
8807 instr[15,14] ==> op : 00 ==> OK, ow ==> UNALLOC
8808 instr[4,0] ==> opcode2 : 00000 ==> FCMP, 10000 ==> FCMPE,
8809 01000 ==> FCMPZ, 11000 ==> FCMPEZ,
8810 ow ==> UNALLOC */
8818 HALT_UNALLOC;
8821 HALT_UNALLOC;
8824 HALT_UNALLOC;
8827 HALT_UNALLOC;
8829 /* dispatch on type and top 2 bits of opcode. */
8833 {
8842 }
8843 }
8845 static void
8847 {
8848 /* instr [31,23] = 0111 1110 0
8849 instr [22] = single(0)/double(1)
8850 instr [21,10] = 11 0000 1101 10
8851 instr [9,5] = Fn
8852 instr [4,0] = Fd. */
8862 {
8867 }
8868 else
8869 {
8874 }
8875 }
8877 /* Floating point absolute difference. */
8879 static void
8881 {
8882 /* instr [31,23] = 0111 1110 1
8883 instr [22] = float(0)/double(1)
8884 instr [21] = 1
8885 instr [20,16] = Rm
8886 instr [15,10] = 1101 01
8887 instr [9, 5] = Rn
8888 instr [4, 0] = Rd. */
8903 else
8907 }
8909 static void
8911 {
8912 /* instr [31,21] = 0101 1110 111
8913 instr [20,16] = Rm
8914 instr [15,10] = 00 1101
8915 instr [9, 5] = Rn
8916 instr [4, 0] = Rd. */
8929 }
8931 static void
8933 {
8934 /* instr [31,23] = 0111 1111 0
8935 instr [22,16] = shift amount
8936 instr [15,10] = 0000 01
8937 instr [9, 5] = Rn
8938 instr [4, 0] = Rd. */
8950 }
8952 static void
8954 {
8955 /* instr [31,21] = 0101 1110 111
8956 instr [20,16] = Rm
8957 instr [15,10] = 0100 01
8958 instr [9, 5] = Rn
8959 instr [4, 0] = Rd. */
8973 else
8976 }
8978 /* Floating point scalar compare greater than or equal to 0. */
8979 static void
8981 {
8982 /* instr [31,23] = 0111 1110 1
8983 instr [22,22] = size
8984 instr [21,16] = 1000 00
8985 instr [15,10] = 1100 10
8986 instr [9, 5] = Rn
8987 instr [4, 0] = Rd. */
9001 else
9004 }
9006 /* Floating point scalar compare less than or equal to 0. */
9007 static void
9009 {
9010 /* instr [31,23] = 0111 1110 1
9011 instr [22,22] = size
9012 instr [21,16] = 1000 00
9013 instr [15,10] = 1101 10
9014 instr [9, 5] = Rn
9015 instr [4, 0] = Rd. */
9029 else
9032 }
9034 /* Floating point scalar compare greater than 0. */
9035 static void
9037 {
9038 /* instr [31,23] = 0101 1110 1
9039 instr [22,22] = size
9040 instr [21,16] = 1000 00
9041 instr [15,10] = 1100 10
9042 instr [9, 5] = Rn
9043 instr [4, 0] = Rd. */
9057 else
9060 }
9062 /* Floating point scalar compare equal to 0. */
9063 static void
9065 {
9066 /* instr [31,23] = 0101 1110 1
9067 instr [22,22] = size
9068 instr [21,16] = 1000 00
9069 instr [15,10] = 1101 10
9070 instr [9, 5] = Rn
9071 instr [4, 0] = Rd. */
9085 else
9088 }
9090 /* Floating point scalar compare less than 0. */
9091 static void
9093 {
9094 /* instr [31,23] = 0101 1110 1
9095 instr [22,22] = size
9096 instr [21,16] = 1000 00
9097 instr [15,10] = 1110 10
9098 instr [9, 5] = Rn
9099 instr [4, 0] = Rd. */
9113 else
9116 }
9118 static void
9120 {
9121 /* instr [31,23] = 0101 1111 0
9122 instr [22,16] = shift amount
9123 instr [15,10] = 0101 01 [SHL]
9124 instr [15,10] = 0000 01 [SSHR]
9125 instr [9, 5] = Rn
9126 instr [4, 0] = Rd. */
9135 HALT_UNALLOC;
9139 {
9151 HALT_NYI;
9152 }
9153 }
9155 /* FCMEQ FCMGT FCMGE. */
9156 static void
9158 {
9159 /* instr [31,30] = 01
9160 instr [29] = U
9161 instr [28,24] = 1 1110
9162 instr [23] = E
9163 instr [22] = size
9164 instr [21] = 1
9165 instr [20,16] = Rm
9166 instr [15,12] = 1110
9167 instr [11] = AC
9168 instr [10] = 1
9169 instr [9, 5] = Rn
9170 instr [4, 0] = Rd. */
9188 {
9193 {
9201 ATTRIBUTE_FALLTHROUGH;
9209 ATTRIBUTE_FALLTHROUGH;
9215 HALT_UNALLOC;
9216 }
9220 }
9226 {
9234 ATTRIBUTE_FALLTHROUGH;
9242 ATTRIBUTE_FALLTHROUGH;
9248 HALT_UNALLOC;
9249 }
9252 }
9254 /* An alias of DUP. */
9255 static void
9257 {
9258 /* instr [31,21] = 0101 1110 000
9259 instr [20,16] = imm5
9260 instr [15,10] = 0000 01
9261 instr [9, 5] = Rn
9262 instr [4, 0] = Rd. */
9273 {
9274 /* 8-bit. */
9276 aarch64_set_vec_u8
9278 }
9280 {
9281 /* 16-bit. */
9283 aarch64_set_vec_u16
9285 }
9287 {
9288 /* 32-bit. */
9290 aarch64_set_vec_u32
9292 }
9294 {
9295 /* 64-bit. */
9297 aarch64_set_vec_u64
9299 }
9300 else
9301 HALT_UNALLOC;
9302 }
9304 static void
9306 {
9307 /* instr [31,10] = 0111 1110 1110 0000 1011 10
9308 instr [9, 5] = Rn
9309 instr [4, 0] = Rd. */
9318 }
9320 static void
9322 {
9323 /* instr [31,21] = 0111 1110 111
9324 instr [20,16] = Rm
9325 instr [15,10] = 0100 01
9326 instr [9, 5] = Rn
9327 instr [4, 0] = Rd. */
9340 else
9342 }
9344 static void
9346 {
9347 /* instr [31,21] = 0101 1110 111
9348 instr [20,16] = Fn
9349 instr [15,10] = 1000 01
9350 instr [9,5] = Fm
9351 instr [4,0] = Fd. */
9370 }
9372 static void
9374 {
9375 /* instr [31,23] = 0111 1110 0
9376 instr [22] = single(0)/double(1)
9377 instr [21,10] = 10 0001 1101 10
9378 instr [9,5] = rn
9379 instr [4,0] = rd. */
9389 {
9393 }
9394 else
9395 {
9399 }
9400 }
9402 static void
9404 {
9405 /* instr [30] = 1. */
9406 /* instr [28,25] = 1111. */
9408 {
9411 {
9415 }
9422 {
9425 {
9428 }
9429 HALT_NYI;
9432 }
9437 {
9447 HALT_NYI;
9448 }
9454 {
9461 HALT_NYI;
9462 }
9465 HALT_NYI;
9466 }
9467 }
9469 static void
9471 {
9472 /* instr [28,25] = 1 111. */
9474 /* We are currently only interested in the basic
9475 scalar fp routines which all have bit 30 = 0. */
9479 /* instr[24] is set for FP data processing 3-source and clear for
9480 all other basic scalar fp instruction groups. */
9484 /* instr[21] is clear for floating <-> fixed conversions and set for
9485 all other basic scalar fp instruction groups. */
9489 /* instr[11,10] : 01 ==> cond compare, 10 ==> Data Proc 2 Source
9490 11 ==> cond select, 00 ==> other. */
9491 else
9493 {
9499 /* Now an ordered cascade of tests.
9500 FP immediate has instr [12] == 1.
9501 FP compare has instr [13] == 1.
9502 FP Data Proc 1 Source has instr [14] == 1.
9503 FP floating <--> integer conversions has instr [15] == 0. */
9516 else
9517 /* If we get here then instr[15] == 1 which means UNALLOC. */
9518 HALT_UNALLOC;
9519 }
9520 }
9522 /* PC relative addressing. */
9524 static void
9526 {
9527 /* instr[31] = op : 0 ==> ADR, 1 ==> ADRP
9528 instr[30,29] = immlo
9529 instr[23,5] = immhi. */
9543 {
9546 }
9550 }
9552 /* Specific decode and execute for group Data Processing Immediate. */
9554 static void
9556 {
9557 /* assert instr[28,24] = 10000. */
9559 }
9561 /* Immediate logical.
9562 The bimm32/64 argument is constructed by replicating a 2, 4, 8,
9563 16, 32 or 64 bit sequence pulled out at decode and possibly
9564 inverting it..
9566 N.B. the output register (dest) can normally be Xn or SP
9567 the exception occurs for flag setting instructions which may
9568 only use Xn for the output (dest). The input register can
9569 never be SP. */
9571 /* 32 bit and immediate. */
9572 static void
9574 {
9581 }
9583 /* 64 bit and immediate. */
9584 static void
9586 {
9593 }
9595 /* 32 bit and immediate set flags. */
9596 static void
9598 {
9608 }
9610 /* 64 bit and immediate set flags. */
9611 static void
9613 {
9623 }
9625 /* 32 bit exclusive or immediate. */
9626 static void
9628 {
9635 }
9637 /* 64 bit exclusive or immediate. */
9638 static void
9640 {
9647 }
9649 /* 32 bit or immediate. */
9650 static void
9652 {
9659 }
9661 /* 64 bit or immediate. */
9662 static void
9664 {
9671 }
9673 /* Logical shifted register.
9674 These allow an optional LSL, ASR, LSR or ROR to the second source
9675 register with a count up to the register bit count.
9676 N.B register args may not be SP. */
9678 /* 32 bit AND shifted register. */
9679 static void
9681 {
9687 aarch64_set_reg_u64
9690 }
9692 /* 64 bit AND shifted register. */
9693 static void
9695 {
9701 aarch64_set_reg_u64
9704 }
9706 /* 32 bit AND shifted register setting flags. */
9707 static void
9709 {
9721 }
9723 /* 64 bit AND shifted register setting flags. */
9724 static void
9726 {
9738 }
9740 /* 32 bit BIC shifted register. */
9741 static void
9743 {
9749 aarch64_set_reg_u64
9752 }
9754 /* 64 bit BIC shifted register. */
9755 static void
9757 {
9763 aarch64_set_reg_u64
9766 }
9768 /* 32 bit BIC shifted register setting flags. */
9769 static void
9771 {
9783 }
9785 /* 64 bit BIC shifted register setting flags. */
9786 static void
9788 {
9800 }
9802 /* 32 bit EON shifted register. */
9803 static void
9805 {
9811 aarch64_set_reg_u64
9814 }
9816 /* 64 bit EON shifted register. */
9817 static void
9819 {
9825 aarch64_set_reg_u64
9828 }
9830 /* 32 bit EOR shifted register. */
9831 static void
9833 {
9839 aarch64_set_reg_u64
9842 }
9844 /* 64 bit EOR shifted register. */
9845 static void
9847 {
9853 aarch64_set_reg_u64
9856 }
9858 /* 32 bit ORR shifted register. */
9859 static void
9861 {
9867 aarch64_set_reg_u64
9870 }
9872 /* 64 bit ORR shifted register. */
9873 static void
9875 {
9881 aarch64_set_reg_u64
9884 }
9886 /* 32 bit ORN shifted register. */
9887 static void
9889 {
9895 aarch64_set_reg_u64
9898 }
9900 /* 64 bit ORN shifted register. */
9901 static void
9903 {
9909 aarch64_set_reg_u64
9912 }
9914 static void
9916 {
9917 /* assert instr[28,23] = 1001000
9918 instr[31] = size : 0 ==> 32 bit, 1 ==> 64 bit
9919 instr[30,29] = op : 0 ==> AND, 1 ==> ORR, 2 ==> EOR, 3 ==> ANDS
9920 instr[22] = N : used to construct immediate mask
9921 instr[21,16] = immr
9922 instr[15,10] = imms
9923 instr[9,5] = Rn
9924 instr[4,0] = Rd */
9926 /* 32 bit operations must have N = 0 or else we have an UNALLOC. */
9929 /* uint32_t immr = INSTR (21, 16);. */
9930 /* uint32_t imms = INSTR (15, 10);. */
9936 HALT_UNALLOC;
9939 HALT_UNALLOC;
9942 {
9946 {
9951 }
9952 }
9953 else
9954 {
9956 {
9961 }
9962 }
9963 HALT_UNALLOC;
9964 }
9966 /* Immediate move.
9967 The uimm argument is a 16 bit value to be inserted into the
9968 target register the pos argument locates the 16 bit word in the
9969 dest register i.e. it is in {0, 1} for 32 bit and {0, 1, 2,
9970 3} for 64 bit.
9971 N.B register arg may not be SP so it should be.
9972 accessed using the setGZRegisterXXX accessors. */
9974 /* 32 bit move 16 bit immediate zero remaining shorts. */
9975 static void
9977 {
9982 }
9984 /* 64 bit move 16 bit immediate zero remaining shorts. */
9985 static void
9987 {
9992 }
9994 /* 32 bit move 16 bit immediate negated. */
9995 static void
9997 {
10002 }
10004 /* 64 bit move 16 bit immediate negated. */
10005 static void
10007 {
10011 aarch64_set_reg_u64
10014 }
10016 /* 32 bit move 16 bit immediate keep remaining shorts. */
10017 static void
10019 {
10027 }
10029 /* 64 bit move 16 it immediate keep remaining shorts. */
10030 static void
10032 {
10040 }
10042 static void
10044 {
10045 /* assert instr[28:23] = 100101
10046 instr[31] = size : 0 ==> 32 bit, 1 ==> 64 bit
10047 instr[30,29] = op : 0 ==> MOVN, 1 ==> UNALLOC, 2 ==> MOVZ, 3 ==> MOVK
10048 instr[22,21] = shift : 00 == LSL#0, 01 = LSL#16, 10 = LSL#32, 11 = LSL#48
10049 instr[20,5] = uimm16
10050 instr[4,0] = Rd */
10052 /* N.B. the (multiple of 16) shift is applied by the called routine,
10053 we just pass the multiplier. */
10060 /* 32 bit can only shift 0 or 1 lot of 16.
10061 anything else is an unallocated instruction. */
10063 HALT_UNALLOC;
10066 HALT_UNALLOC;
10071 {
10076 else
10078 }
10079 else
10080 {
10085 else
10087 }
10088 }
10090 /* Bitfield operations.
10091 These take a pair of bit positions r and s which are in {0..31}
10092 or {0..63} depending on the instruction word size.
10093 N.B register args may not be SP. */
10095 /* OK, we start with ubfm which just needs to pick
10096 some bits out of source zero the rest and write
10097 the result to dest. Just need two logical shifts. */
10099 /* 32 bit bitfield move, left and right of affected zeroed
10100 if r <= s Wd<s-r:0> = Wn<s:r> else Wd<32+s-r,32-r> = Wn<s:0>. */
10101 static void
10103 {
10108 /* Pick either s+1-r or s+1 consecutive bits out of the original word. */
10110 {
10111 /* 31:...:s:xxx:r:...:0 ==> 31:...:s-r:xxx:0.
10112 We want only bits s:xxx:r at the bottom of the word
10113 so we LSL bit s up to bit 31 i.e. by 31 - s
10114 and then we LSR to bring bit 31 down to bit s - r
10115 i.e. by 31 + r - s. */
10118 }
10119 else
10120 {
10121 /* 31:...:s:xxx:0 ==> 31:...:31-(r-1)+s:xxx:31-(r-1):...:0
10122 We want only bits s:xxx:0 starting at it 31-(r-1)
10123 so we LSL bit s up to bit 31 i.e. by 31 - s
10124 and then we LSL to bring bit 31 down to 31-(r-1)+s
10125 i.e. by r - (s + 1). */
10128 }
10133 }
10135 /* 64 bit bitfield move, left and right of affected zeroed
10136 if r <= s Wd<s-r:0> = Wn<s:r> else Wd<64+s-r,64-r> = Wn<s:0>. */
10137 static void
10139 {
10145 {
10146 /* 63:...:s:xxx:r:...:0 ==> 63:...:s-r:xxx:0.
10147 We want only bits s:xxx:r at the bottom of the word.
10148 So we LSL bit s up to bit 63 i.e. by 63 - s
10149 and then we LSR to bring bit 63 down to bit s - r
10150 i.e. by 63 + r - s. */
10153 }
10154 else
10155 {
10156 /* 63:...:s:xxx:0 ==> 63:...:63-(r-1)+s:xxx:63-(r-1):...:0.
10157 We want only bits s:xxx:0 starting at it 63-(r-1).
10158 So we LSL bit s up to bit 63 i.e. by 63 - s
10159 and then we LSL to bring bit 63 down to 63-(r-1)+s
10160 i.e. by r - (s + 1). */
10163 }
10168 }
10170 /* The signed versions need to insert sign bits
10171 on the left of the inserted bit field. so we do
10172 much the same as the unsigned version except we
10173 use an arithmetic shift right -- this just means
10174 we need to operate on signed values. */
10176 /* 32 bit bitfield move, left of affected sign-extended, right zeroed. */
10177 /* If r <= s Wd<s-r:0> = Wn<s:r> else Wd<32+s-r,32-r> = Wn<s:0>. */
10178 static void
10180 {
10183 /* as per ubfm32 but use an ASR instead of an LSR. */
10187 {
10190 }
10191 else
10192 {
10195 }
10200 }
10202 /* 64 bit bitfield move, left of affected sign-extended, right zeroed. */
10203 /* If r <= s Wd<s-r:0> = Wn<s:r> else Wd<64+s-r,64-r> = Wn<s:0>. */
10204 static void
10206 {
10209 /* acpu per ubfm but use an ASR instead of an LSR. */
10213 {
10216 }
10217 else
10218 {
10221 }
10226 }
10228 /* Finally, these versions leave non-affected bits
10229 as is. so we need to generate the bits as per
10230 ubfm and also generate a mask to pick the
10231 bits from the original and computed values. */
10233 /* 32 bit bitfield move, non-affected bits left as is.
10234 If r <= s Wd<s-r:0> = Wn<s:r> else Wd<32+s-r,32-r> = Wn<s:0>. */
10235 static void
10237 {
10244 /* Pick either s+1-r or s+1 consecutive bits out of the original word. */
10246 {
10247 /* 31:...:s:xxx:r:...:0 ==> 31:...:s-r:xxx:0.
10248 We want only bits s:xxx:r at the bottom of the word
10249 so we LSL bit s up to bit 31 i.e. by 31 - s
10250 and then we LSR to bring bit 31 down to bit s - r
10251 i.e. by 31 + r - s. */
10254 /* the mask must include the same bits. */
10257 }
10258 else
10259 {
10260 /* 31:...:s:xxx:0 ==> 31:...:31-(r-1)+s:xxx:31-(r-1):...:0.
10261 We want only bits s:xxx:0 starting at it 31-(r-1)
10262 so we LSL bit s up to bit 31 i.e. by 31 - s
10263 and then we LSL to bring bit 31 down to 31-(r-1)+s
10264 i.e. by r - (s + 1). */
10267 /* The mask must include the same bits. */
10270 }
10280 }
10282 /* 64 bit bitfield move, non-affected bits left as is.
10283 If r <= s Wd<s-r:0> = Wn<s:r> else Wd<64+s-r,64-r> = Wn<s:0>. */
10284 static void
10286 {
10293 {
10294 /* 63:...:s:xxx:r:...:0 ==> 63:...:s-r:xxx:0.
10295 We want only bits s:xxx:r at the bottom of the word
10296 so we LSL bit s up to bit 63 i.e. by 63 - s
10297 and then we LSR to bring bit 63 down to bit s - r
10298 i.e. by 63 + r - s. */
10301 /* The mask must include the same bits. */
10304 }
10305 else
10306 {
10307 /* 63:...:s:xxx:0 ==> 63:...:63-(r-1)+s:xxx:63-(r-1):...:0
10308 We want only bits s:xxx:0 starting at it 63-(r-1)
10309 so we LSL bit s up to bit 63 i.e. by 63 - s
10310 and then we LSL to bring bit 63 down to 63-(r-1)+s
10311 i.e. by r - (s + 1). */
10314 /* The mask must include the same bits. */
10317 }
10321 aarch64_set_reg_u64
10323 }
10325 static void
10327 {
10328 /* assert instr[28:23] = 100110
10329 instr[31] = size : 0 ==> 32 bit, 1 ==> 64 bit
10330 instr[30,29] = op : 0 ==> SBFM, 1 ==> BFM, 2 ==> UBFM, 3 ==> UNALLOC
10331 instr[22] = N : must be 0 for 32 bit, 1 for 64 bit ow UNALLOC
10332 instr[21,16] = immr : 0xxxxx for 32 bit, xxxxxx for 64 bit
10333 instr[15,10] = imms : 0xxxxx for 32 bit, xxxxxx for 64 bit
10334 instr[9,5] = Rn
10335 instr[4,0] = Rd */
10337 /* 32 bit operations must have N = 0 or else we have an UNALLOC. */
10342 /* 32 bit operations must have immr[5] = 0 and imms[5] = 0. */
10343 /* or else we have an UNALLOC. */
10347 HALT_UNALLOC;
10350 HALT_UNALLOC;
10354 HALT_UNALLOC;
10356 /* Switch on combined size and op. */
10359 {
10367 }
10368 }
10370 static void
10372 {
10373 /* instr[31:21] = 00010011100
10374 instr[20,16] = Rm
10375 instr[15,10] = imms : 0xxxxx for 32 bit
10376 instr[9,5] = Rn
10377 instr[4,0] = Rd */
10392 }
10394 static void
10396 {
10397 /* instr[31:21] = 10010011100
10398 instr[20,16] = Rm
10399 instr[15,10] = imms
10400 instr[9,5] = Rn
10401 instr[4,0] = Rd */
10413 }
10415 static void
10417 {
10418 /* assert instr[28:23] = 100111
10419 instr[31] = size : 0 ==> 32 bit, 1 ==> 64 bit
10420 instr[30,29] = op21 : 0 ==> EXTR, 1,2,3 ==> UNALLOC
10421 instr[22] = N : must be 0 for 32 bit, 1 for 64 bit or UNALLOC
10422 instr[21] = op0 : must be 0 or UNALLOC
10423 instr[20,16] = Rm
10424 instr[15,10] = imms : 0xxxxx for 32 bit, xxxxxx for 64 bit
10425 instr[9,5] = Rn
10426 instr[4,0] = Rd */
10428 /* 32 bit operations must have N = 0 or else we have an UNALLOC. */
10429 /* 64 bit operations must have N = 1 or else we have an UNALLOC. */
10433 /* 32 bit operations must have imms[5] = 0
10434 or else we have an UNALLOC. */
10438 HALT_UNALLOC;
10441 HALT_UNALLOC;
10443 /* Switch on combined size and op. */
10453 HALT_NYI;
10454 else
10455 HALT_UNALLOC;
10456 }
10458 static void
10460 {
10461 /* uint32_t group = dispatchGroup (aarch64_get_instr (cpu));
10462 assert group == GROUP_DPIMM_1000 || grpoup == GROUP_DPIMM_1001
10463 bits [25,23] of a DPImm are the secondary dispatch vector. */
10467 {
10495 /* Should never reach here. */
10496 HALT_NYI;
10497 }
10498 }
10500 static void
10502 {
10503 /* instr[29,24] == 111_00
10504 instr[21] == 0
10505 instr[11,10] == 00
10506 instr[31,30] = size
10507 instr[26] = V
10508 instr[23,22] = opc
10509 instr[20,12] = simm9
10510 instr[9,5] = rn may be SP. */
10511 /* unsigned rt = INSTR (4, 0); */
10517 {
10518 /* GReg operations. */
10520 {
10536 /* PRFUM NYI. */
10537 HALT_NYI;
10542 HALT_UNALLOC;
10543 }
10544 }
10546 /* FReg operations. */
10548 {
10560 HALT_NYI;
10569 HALT_UNALLOC;
10570 }
10571 }
10573 /* N.B. A preliminary note regarding all the ldrs<x>32
10574 instructions
10576 The signed value loaded by these instructions is cast to unsigned
10577 before being assigned to aarch64_get_reg_u64 (cpu, N) i.e. to the
10578 64 bit element of the GReg union. this performs a 32 bit sign extension
10579 (as required) but avoids 64 bit sign extension, thus ensuring that the
10580 top half of the register word is zero. this is what the spec demands
10581 when a 32 bit load occurs. */
10583 /* 32 bit load sign-extended byte scaled unsigned 12 bit. */
10584 static void
10586 {
10590 /* The target register may not be SP but the source may be
10591 there is no scaling required for a byte load. */
10595 }
10597 /* 32 bit load sign-extended byte scaled or unscaled zero-
10598 or sign-extended 32-bit register offset. */
10599 static void
10601 {
10606 /* rn may reference SP, rm and rt must reference ZR. */
10610 extension);
10612 /* There is no scaling required for a byte load. */
10613 aarch64_set_reg_u64
10616 }
10618 /* 32 bit load sign-extended byte unscaled signed 9 bit with
10619 pre- or post-writeback. */
10620 static void
10622 {
10628 HALT_UNALLOC;
10643 }
10645 /* 8 bit store scaled. */
10646 static void
10648 {
10655 }
10657 /* 8 bit store scaled or unscaled zero- or
10658 sign-extended 8-bit register offset. */
10659 static void
10661 {
10668 extension);
10671 aarch64_set_mem_u8
10673 }
10675 /* 16 bit store scaled. */
10676 static void
10678 {
10682 aarch64_set_mem_u16
10686 }
10688 /* 16 bit store scaled or unscaled zero-
10689 or sign-extended 16-bit register offset. */
10690 static void
10692 {
10699 extension);
10702 aarch64_set_mem_u16
10704 }
10706 /* 32 bit store scaled unsigned 12 bit. */
10707 static void
10709 {
10713 aarch64_set_mem_u32
10717 }
10719 /* 32 bit store unscaled signed 9 bit with pre- or post-writeback. */
10720 static void
10722 {
10738 }
10740 /* 32 bit store scaled or unscaled zero-
10741 or sign-extended 32-bit register offset. */
10742 static void
10744 {
10751 extension);
10754 aarch64_set_mem_u32
10756 }
10758 /* 64 bit store scaled unsigned 12 bit. */
10759 static void
10761 {
10765 aarch64_set_mem_u64
10769 }
10771 /* 64 bit store unscaled signed 9 bit with pre- or post-writeback. */
10772 static void
10774 {
10790 }
10792 /* 64 bit store scaled or unscaled zero-
10793 or sign-extended 32-bit register offset. */
10794 static void
10796 {
10803 extension);
10806 aarch64_set_mem_u64
10808 }
10810 /* 128 bit store scaled unsigned 12 bit. */
10811 static void
10813 {
10814 FRegister a;
10823 }
10825 /* 128 bit store unscaled signed 9 bit with pre- or post-writeback. */
10826 static void
10828 {
10829 FRegister a;
10845 }
10847 /* 128 bit store scaled or unscaled zero-
10848 or sign-extended 32-bit register offset. */
10849 static void
10851 {
10858 extension);
10861 FRegister a;
10865 }
10867 static void
10869 {
10870 /* instr[31,30] = size
10871 instr[29,27] = 111
10872 instr[26] = V
10873 instr[25,24] = 00
10874 instr[23,22] = opc
10875 instr[21] = 0
10876 instr[20,12] = simm9
10877 instr[11] = wb : 0 ==> Post, 1 ==> Pre
10878 instr[10] = 0
10879 instr[9,5] = Rn may be SP.
10880 instr[4,0] = Rt */
10888 {
10889 /* GReg operations. */
10891 {
10910 HALT_UNALLOC;
10911 }
10912 }
10914 /* FReg operations. */
10916 {
10928 HALT_NYI;
10937 HALT_UNALLOC;
10938 }
10939 }
10941 static void
10943 {
10944 /* instr[31,30] = size
10945 instr[29,27] = 111
10946 instr[26] = V
10947 instr[25,24] = 00
10948 instr[23,22] = opc
10949 instr[21] = 1
10950 instr[20,16] = rm
10951 instr[15,13] = option : 010 ==> UXTW, 011 ==> UXTX/LSL,
10952 110 ==> SXTW, 111 ==> SXTX,
10953 ow ==> RESERVED
10954 instr[12] = scaled
10955 instr[11,10] = 10
10956 instr[9,5] = rn
10957 instr[4,0] = rt. */
10964 /* Check for illegal extension types. */
10966 HALT_UNALLOC;
10972 {
10973 /* GReg operations. */
10975 {
10994 HALT_UNALLOC;
10995 }
10996 }
10998 /* FReg operations. */
11000 {
11002 HALT_NYI;
11005 HALT_NYI;
11022 HALT_UNALLOC;
11023 }
11024 }
11026 static void
11028 {
11029 /* instr[29,24] == 111_01
11030 instr[31,30] = size
11031 instr[26] = V
11032 instr[23,22] = opc
11033 instr[21,10] = uimm12 : unsigned immediate offset
11034 instr[9,5] = rn may be SP.
11035 instr[4,0] = rt. */
11042 {
11043 /* GReg operations. */
11045 {
11064 HALT_UNALLOC;
11065 }
11066 }
11068 /* FReg operations. */
11070 {
11090 HALT_UNALLOC;
11091 }
11092 }
11094 static void
11096 {
11097 /* assert instr[29:24] = 001000;
11098 instr[31,30] = size
11099 instr[23] = 0 if exclusive
11100 instr[22] = L : 1 if load, 0 if store
11101 instr[21] = 1 if pair
11102 instr[20,16] = Rs
11103 instr[15] = o0 : 1 if ordered
11104 instr[14,10] = Rt2
11105 instr[9,5] = Rn
11106 instr[4.0] = Rt. */
11109 {
11113 }
11114 }
11116 static void
11118 {
11121 /* instr[29,25] = 111_0
11122 instr[24] == 0 ==> dispatch, 1 ==> ldst reg unsigned immediate
11123 instr[21:11,10] is the secondary dispatch. */
11125 {
11128 }
11132 {
11143 HALT_NYI;
11144 }
11145 }
11147 static void
11149 {
11173 }
11175 static void
11177 {
11201 }
11203 static void
11205 {
11211 /* Treat this as unalloc to make sure we don't do it. */
11213 HALT_UNALLOC;
11228 }
11230 static void
11232 {
11238 /* Treat this as unalloc to make sure we don't do it. */
11240 HALT_UNALLOC;
11255 }
11257 static void
11259 {
11265 /* Treat this as unalloc to make sure we don't do it. */
11267 HALT_UNALLOC;
11282 }
11284 static void
11286 {
11287 /* instr[31,30] = size (10=> 64-bit, 01=> signed 32-bit, 00=> 32-bit)
11288 instr[29,25] = instruction encoding: 101_0
11289 instr[26] = V : 1 if fp 0 if gp
11290 instr[24,23] = addressing mode (10=> offset, 01=> post, 11=> pre)
11291 instr[22] = load/store (1=> load)
11292 instr[21,15] = signed, scaled, offset
11293 instr[14,10] = Rn
11294 instr[ 9, 5] = Rd
11295 instr[ 4, 0] = Rm. */
11301 {
11321 HALT_UNALLOC;
11322 }
11323 }
11325 static void
11327 {
11346 }
11348 static void
11350 {
11369 }
11371 static void
11373 {
11374 FRegister a;
11395 }
11397 static void
11399 {
11406 HALT_UNALLOC;
11421 }
11423 static void
11425 {
11432 HALT_UNALLOC;
11447 }
11449 static void
11451 {
11452 FRegister a;
11459 HALT_UNALLOC;
11476 }
11478 static void
11480 {
11481 /* instr[31,30] = size (10=> 128-bit, 01=> 64-bit, 00=> 32-bit)
11482 instr[29,25] = instruction encoding
11483 instr[24,23] = addressing mode (10=> offset, 01=> post, 11=> pre)
11484 instr[22] = load/store (1=> load)
11485 instr[21,15] = signed, scaled, offset
11486 instr[14,10] = Rn
11487 instr[ 9, 5] = Rd
11488 instr[ 4, 0] = Rm */
11494 {
11517 HALT_UNALLOC;
11518 }
11519 }
11523 {
11525 }
11527 /* Load multiple N-element structures to M consecutive registers. */
11528 static void
11530 {
11539 {
11544 {
11548 }
11555 {
11559 }
11566 {
11570 }
11577 {
11581 }
11583 }
11584 }
11586 /* Load multiple 4-element structures into four consecutive registers. */
11587 static void
11589 {
11591 }
11593 /* Load multiple 3-element structures into three consecutive registers. */
11594 static void
11596 {
11598 }
11600 /* Load multiple 2-element structures into two consecutive registers. */
11601 static void
11603 {
11605 }
11607 /* Load multiple 1-element structures into one register. */
11608 static void
11610 {
11612 }
11614 /* Load multiple 1-element structures into two registers. */
11615 static void
11617 {
11619 }
11621 /* Load multiple 1-element structures into three registers. */
11622 static void
11624 {
11626 }
11628 /* Load multiple 1-element structures into four registers. */
11629 static void
11631 {
11633 }
11635 /* Store multiple N-element structures from M consecutive registers. */
11636 static void
11638 {
11647 {
11652 {
11653 aarch64_set_mem_u8
11657 }
11664 {
11665 aarch64_set_mem_u16
11669 }
11676 {
11677 aarch64_set_mem_u32
11681 }
11688 {
11689 aarch64_set_mem_u64
11693 }
11695 }
11696 }
11698 /* Store multiple 4-element structure from four consecutive registers. */
11699 static void
11701 {
11703 }
11705 /* Store multiple 3-element structures from three consecutive registers. */
11706 static void
11708 {
11710 }
11712 /* Store multiple 2-element structures from two consecutive registers. */
11713 static void
11715 {
11717 }
11719 /* Store multiple 1-element structures from one register. */
11720 static void
11722 {
11724 }
11726 /* Store multiple 1-element structures from two registers. */
11727 static void
11729 {
11731 }
11733 /* Store multiple 1-element structures from three registers. */
11734 static void
11736 {
11738 }
11740 /* Store multiple 1-element structures from four registers. */
11741 static void
11743 {
11745 }
11747 #define LDn_STn_SINGLE_LANE_AND_SIZE() \
11748 do \
11749 { \
11750 switch (INSTR (15, 14)) \
11751 { \
11752 case 0: \
11753 lane = (full << 3) | (s << 2) | size; \
11754 size = 0; \
11755 break; \
11756 \
11757 case 1: \
11758 if ((size & 1) == 1) \
11759 HALT_UNALLOC; \
11760 lane = (full << 2) | (s << 1) | (size >> 1); \
11761 size = 1; \
11762 break; \
11763 \
11764 case 2: \
11765 if ((size & 2) == 2) \
11766 HALT_UNALLOC; \
11767 \
11768 if ((size & 1) == 0) \
11769 { \
11770 lane = (full << 1) | s; \
11771 size = 2; \
11772 } \
11773 else \
11774 { \
11775 if (s) \
11776 HALT_UNALLOC; \
11777 lane = full; \
11778 size = 3; \
11779 } \
11780 break; \
11781 \
11782 default: \
11783 HALT_UNALLOC; \
11784 } \
11785 } \
11786 while (0)
11788 /* Load single structure into one lane of N registers. */
11789 static void
11791 {
11792 /* instr[31] = 0
11793 instr[30] = element selector 0=>half, 1=>all elements
11794 instr[29,24] = 00 1101
11795 instr[23] = 0=>simple, 1=>post
11796 instr[22] = 1
11797 instr[21] = width: LD1-or-LD3 (0) / LD2-or-LD4 (1)
11798 instr[20,16] = 0 0000 (simple), Vinc (reg-post-inc, no SP),
11799 11111 (immediate post inc)
11800 instr[15,13] = opcode
11801 instr[12] = S, used for lane number
11802 instr[11,10] = size, also used for lane number
11803 instr[9,5] = address
11804 instr[4,0] = Vd */
11817 /* Compute the lane number first (using size), and then compute size. */
11822 {
11824 {
11828 }
11831 {
11835 }
11838 {
11842 }
11845 {
11849 }
11850 }
11851 }
11853 /* Store single structure from one lane from N registers. */
11854 static void
11856 {
11857 /* instr[31] = 0
11858 instr[30] = element selector 0=>half, 1=>all elements
11859 instr[29,24] = 00 1101
11860 instr[23] = 0=>simple, 1=>post
11861 instr[22] = 0
11862 instr[21] = width: LD1-or-LD3 (0) / LD2-or-LD4 (1)
11863 instr[20,16] = 0 0000 (simple), Vinc (reg-post-inc, no SP),
11864 11111 (immediate post inc)
11865 instr[15,13] = opcode
11866 instr[12] = S, used for lane number
11867 instr[11,10] = size, also used for lane number
11868 instr[9,5] = address
11869 instr[4,0] = Vd */
11882 /* Compute the lane number first (using size), and then compute size. */
11887 {
11889 {
11893 }
11896 {
11900 }
11903 {
11907 }
11910 {
11914 }
11915 }
11916 }
11918 /* Load single structure into all lanes of N registers. */
11919 static void
11921 {
11922 /* instr[31] = 0
11923 instr[30] = element selector 0=>half, 1=>all elements
11924 instr[29,24] = 00 1101
11925 instr[23] = 0=>simple, 1=>post
11926 instr[22] = 1
11927 instr[21] = width: LD1R-or-LD3R (0) / LD2R-or-LD4R (1)
11928 instr[20,16] = 0 0000 (simple), Vinc (reg-post-inc, no SP),
11929 11111 (immediate post inc)
11930 instr[15,14] = 11
11931 instr[13] = width: LD1R-or-LD2R (0) / LD3R-or-LD4R (1)
11932 instr[12] = 0
11933 instr[11,10] = element size 00=> byte(b), 01=> half(h),
11934 10=> word(s), 11=> double(d)
11935 instr[9,5] = address
11936 instr[4,0] = Vd */
11951 {
11953 {
11958 }
11961 {
11966 }
11969 {
11974 }
11977 {
11982 }
11985 HALT_UNALLOC;
11986 }
11987 }
11989 static void
11991 {
11992 /* {LD|ST}<N> {Vd..Vd+N}, vaddr
11994 instr[31] = 0
11995 instr[30] = element selector 0=>half, 1=>all elements
11996 instr[29,25] = 00110
11997 instr[24] = 0=>multiple struct, 1=>single struct
11998 instr[23] = 0=>simple, 1=>post
11999 instr[22] = 0=>store, 1=>load
12000 instr[21] = 0 (LDn) / small(0)-large(1) selector (LDnR)
12001 instr[20,16] = 00000 (simple), Vinc (reg-post-inc, no SP),
12002 11111 (immediate post inc)
12003 instr[15,12] = elements and destinations. eg for load:
12004 0000=>LD4 => load multiple 4-element to
12005 four consecutive registers
12006 0100=>LD3 => load multiple 3-element to
12007 three consecutive registers
12008 1000=>LD2 => load multiple 2-element to
12009 two consecutive registers
12010 0010=>LD1 => load multiple 1-element to
12011 four consecutive registers
12012 0110=>LD1 => load multiple 1-element to
12013 three consecutive registers
12014 1010=>LD1 => load multiple 1-element to
12015 two consecutive registers
12016 0111=>LD1 => load multiple 1-element to
12017 one register
12018 1100=>LDR1,LDR2
12019 1110=>LDR3,LDR4
12020 instr[11,10] = element size 00=> byte(b), 01=> half(h),
12021 10=> word(s), 11=> double(d)
12022 instr[9,5] = Vn, can be SP
12023 instr[4,0] = Vd */
12033 HALT_NYI;
12043 HALT_UNALLOC;
12046 {
12050 {
12054 {
12056 {
12059 {
12069 else
12073 HALT_UNALLOC;
12074 }
12075 }
12077 {
12080 }
12082 {
12085 }
12086 else
12087 HALT_UNALLOC;
12088 }
12089 else
12090 {
12092 {
12098 /* One register, immediate offset variant. */
12103 /* Two registers, immediate offset variant. */
12108 /* Three registers, immediate offset variant. */
12113 /* Four registers, immediate offset variant. */
12118 HALT_UNALLOC;
12119 }
12123 }
12126 }
12127 else
12130 }
12131 else
12132 {
12134 }
12137 {
12139 {
12144 else
12145 HALT_UNALLOC;
12147 }
12149 /* Stores. */
12151 {
12154 }
12156 HALT_UNALLOC;
12157 }
12160 {
12162 {
12172 HALT_UNALLOC;
12173 }
12174 }
12176 /* Stores. */
12178 {
12187 HALT_UNALLOC;
12188 }
12189 }
12191 static void
12193 {
12194 /* uint32_t group = dispatchGroup (aarch64_get_instr (cpu));
12195 assert group == GROUP_LDST_0100 || group == GROUP_LDST_0110 ||
12196 group == GROUP_LDST_1100 || group == GROUP_LDST_1110
12197 bits [29,28:26] of a LS are the secondary dispatch vector. */
12201 {
12223 /* Should never reach here. */
12224 HALT_NYI;
12225 }
12226 }
12228 /* Specific decode and execute for group Data Processing Register. */
12230 static void
12232 {
12233 /* instr[31] = size : 0 ==> 32 bit, 1 ==> 64 bit
12234 instr[30,29] = op
12235 instr[28:24] = 01010
12236 instr[23,22] = shift : 0 ==> LSL, 1 ==> LSR, 2 ==> ASR, 3 ==> ROR
12237 instr[21] = N
12238 instr[20,16] = Rm
12239 instr[15,10] = count : must be 0xxxxx for 32 bit
12240 instr[9,5] = Rn
12241 instr[4,0] = Rd */
12247 /* 32 bit operations must have count[5] = 0.
12248 or else we have an UNALLOC. */
12250 HALT_UNALLOC;
12252 /* Dispatch on size:op:N. */
12254 {
12271 }
12272 }
12274 /* 32 bit conditional select. */
12275 static void
12277 {
12286 }
12288 /* 64 bit conditional select. */
12289 static void
12291 {
12300 }
12302 /* 32 bit conditional increment. */
12303 static void
12305 {
12314 }
12316 /* 64 bit conditional increment. */
12317 static void
12319 {
12328 }
12330 /* 32 bit conditional invert. */
12331 static void
12333 {
12342 }
12344 /* 64 bit conditional invert. */
12345 static void
12347 {
12356 }
12358 /* 32 bit conditional negate. */
12359 static void
12361 {
12370 }
12372 /* 64 bit conditional negate. */
12373 static void
12375 {
12384 }
12386 static void
12388 {
12389 /* instr[28,21] = 11011011
12390 instr[31] = size : 0 ==> 32 bit, 1 ==> 64 bit
12391 instr[30:11,10] = op : 000 ==> CSEL, 001 ==> CSINC,
12392 100 ==> CSINV, 101 ==> CSNEG,
12393 _1_ ==> UNALLOC
12394 instr[29] = S : 0 ==> ok, 1 ==> UNALLOC
12395 instr[15,12] = cond
12396 instr[29] = S : 0 ==> ok, 1 ==> UNALLOC */
12403 HALT_UNALLOC;
12406 HALT_UNALLOC;
12409 {
12418 }
12419 }
12421 /* Some helpers for counting leading 1 or 0 bits. */
12423 /* Counts the number of leading bits which are the same
12424 in a 32 bit value in the range 1 to 32. */
12425 static uint32_t
12427 {
12434 {
12438 {
12442 }
12443 else
12444 {
12448 }
12449 }
12452 {
12460 else
12462 }
12465 }
12467 /* Counts the number of leading bits which are the same
12468 in a 64 bit value in the range 1 to 64. */
12469 static uint64_t
12471 {
12478 {
12482 {
12486 }
12487 else
12488 {
12492 }
12493 }
12496 {
12504 else
12506 }
12509 }
12511 /* Bit operations. */
12512 /* N.B register args may not be SP. */
12514 /* 32 bit count leading sign bits. */
12515 static void
12517 {
12521 /* N.B. the result needs to exclude the leading bit. */
12522 aarch64_set_reg_u64
12524 }
12526 /* 64 bit count leading sign bits. */
12527 static void
12529 {
12533 /* N.B. the result needs to exclude the leading bit. */
12534 aarch64_set_reg_u64
12536 }
12538 /* 32 bit count leading zero bits. */
12539 static void
12541 {
12546 /* if the sign (top) bit is set then the count is 0. */
12549 else
12551 }
12553 /* 64 bit count leading zero bits. */
12554 static void
12556 {
12561 /* if the sign (top) bit is set then the count is 0. */
12564 else
12566 }
12568 /* 32 bit reverse bits. */
12569 static void
12571 {
12579 {
12583 }
12585 }
12587 /* 64 bit reverse bits. */
12588 static void
12590 {
12598 {
12602 }
12604 }
12606 /* 32 bit reverse bytes. */
12607 static void
12609 {
12617 {
12621 }
12623 }
12625 /* 64 bit reverse bytes. */
12626 static void
12628 {
12636 {
12640 }
12642 }
12644 /* 32 bit reverse shorts. */
12645 /* N.B.this reverses the order of the bytes in each half word. */
12646 static void
12648 {
12656 {
12660 }
12662 }
12664 /* 64 bit reverse shorts. */
12665 /* N.B.this reverses the order of the bytes in each half word. */
12666 static void
12668 {
12676 {
12680 }
12682 }
12684 static void
12686 {
12687 /* instr[30] = 1
12688 instr[28,21] = 111010110
12689 instr[31] = size : 0 ==> 32 bit, 1 ==> 64 bit
12690 instr[29] = S : 0 ==> ok, 1 ==> UNALLOC
12691 instr[20,16] = opcode2 : 00000 ==> ok, ow ==> UNALLOC
12692 instr[15,10] = opcode : 000000 ==> RBIT, 000001 ==> REV16,
12693 000010 ==> REV, 000011 ==> UNALLOC
12694 000100 ==> CLZ, 000101 ==> CLS
12695 ow ==> UNALLOC
12696 instr[9,5] = rn : may not be SP
12697 instr[4,0] = rd : may not be SP. */
12705 HALT_UNALLOC;
12708 HALT_UNALLOC;
12711 HALT_UNALLOC;
12714 {
12727 }
12728 }
12730 /* Variable shift.
12731 Shifts by count supplied in register.
12732 N.B register args may not be SP.
12733 These all use the shifted auxiliary function for
12734 simplicity and clarity. Writing the actual shift
12735 inline would avoid a branch and so be faster but
12736 would also necessitate getting signs right. */
12738 /* 32 bit arithmetic shift right. */
12739 static void
12741 {
12746 aarch64_set_reg_u64
12750 }
12752 /* 64 bit arithmetic shift right. */
12753 static void
12755 {
12760 aarch64_set_reg_u64
12764 }
12766 /* 32 bit logical shift left. */
12767 static void
12769 {
12774 aarch64_set_reg_u64
12778 }
12780 /* 64 bit arithmetic shift left. */
12781 static void
12783 {
12788 aarch64_set_reg_u64
12792 }
12794 /* 32 bit logical shift right. */
12795 static void
12797 {
12802 aarch64_set_reg_u64
12806 }
12808 /* 64 bit logical shift right. */
12809 static void
12811 {
12816 aarch64_set_reg_u64
12820 }
12822 /* 32 bit rotate right. */
12823 static void
12825 {
12830 aarch64_set_reg_u64
12834 }
12836 /* 64 bit rotate right. */
12837 static void
12839 {
12844 aarch64_set_reg_u64
12848 }
12851 /* divide. */
12853 /* 32 bit signed divide. */
12854 static void
12856 {
12860 /* N.B. the pseudo-code does the divide using 64 bit data. */
12861 /* TODO : check that this rounds towards zero as required. */
12867 }
12869 /* 64 bit signed divide. */
12870 static void
12872 {
12877 /* TODO : check that this rounds towards zero as required. */
12880 aarch64_set_reg_s64
12883 }
12885 /* 32 bit unsigned divide. */
12886 static void
12888 {
12893 /* N.B. the pseudo-code does the divide using 64 bit data. */
12899 }
12901 /* 64 bit unsigned divide. */
12902 static void
12904 {
12909 /* TODO : check that this rounds towards zero as required. */
12912 aarch64_set_reg_u64
12915 }
12917 static void
12919 {
12920 /* assert instr[30] == 0
12921 instr[28,21] == 11010110
12922 instr[31] = size : 0 ==> 32 bit, 1 ==> 64 bit
12923 instr[29] = S : 0 ==> ok, 1 ==> UNALLOC
12924 instr[15,10] = opcode : 000010 ==> UDIV, 000011 ==> CPUIV,
12925 001000 ==> LSLV, 001001 ==> LSRV
12926 001010 ==> ASRV, 001011 ==> RORV
12927 ow ==> UNALLOC. */
12934 HALT_UNALLOC;
12937 HALT_UNALLOC;
12943 {
12957 }
12958 }
12961 /* Multiply. */
12963 /* 32 bit multiply and add. */
12964 static void
12966 {
12977 }
12979 /* 64 bit multiply and add. */
12980 static void
12982 {
12993 }
12995 /* 32 bit multiply and sub. */
12996 static void
12998 {
13009 }
13011 /* 64 bit multiply and sub. */
13012 static void
13014 {
13025 }
13027 /* Signed multiply add long -- source, source2 : 32 bit, source3 : 64 bit. */
13028 static void
13030 {
13036 /* N.B. we need to multiply the signed 32 bit values in rn, rm to
13037 obtain a 64 bit product. */
13038 aarch64_set_reg_s64
13043 }
13045 /* Signed multiply sub long -- source, source2 : 32 bit, source3 : 64 bit. */
13046 static void
13048 {
13054 /* N.B. we need to multiply the signed 32 bit values in rn, rm to
13055 obtain a 64 bit product. */
13056 aarch64_set_reg_s64
13061 }
13063 /* Integer Multiply/Divide. */
13065 /* First some macros and a helper function. */
13066 /* Macros to test or access elements of 64 bit words. */
13068 /* Mask used to access lo 32 bits of 64 bit unsigned int. */
13069 #define LOW_WORD_MASK ((1ULL << 32) - 1)
13070 /* Return the lo 32 bit word of a 64 bit unsigned int as a 64 bit unsigned int. */
13071 #define lowWordToU64(_value_u64) ((_value_u64) & LOW_WORD_MASK)
13072 /* Return the hi 32 bit word of a 64 bit unsigned int as a 64 bit unsigned int. */
13073 #define highWordToU64(_value_u64) ((_value_u64) >> 32)
13075 /* Offset of sign bit in 64 bit signed integger. */
13076 #define SIGN_SHIFT_U64 63
13077 /* The sign bit itself -- also identifies the minimum negative int value. */
13078 #define SIGN_BIT_U64 (1UL << SIGN_SHIFT_U64)
13079 /* Return true if a 64 bit signed int presented as an unsigned int is the
13080 most negative value. */
13081 #define isMinimumU64(_value_u64) ((_value_u64) == SIGN_BIT_U64)
13082 /* Return true (non-zero) if a 64 bit signed int presented as an unsigned
13083 int has its sign bit set to false. */
13084 #define isSignSetU64(_value_u64) ((_value_u64) & SIGN_BIT_U64)
13085 /* Return 1L or -1L according to whether a 64 bit signed int presented as
13086 an unsigned int has its sign bit set or not. */
13087 #define signOfU64(_value_u64) (1L + (((value_u64) >> SIGN_SHIFT_U64) * -2L)
13088 /* Clear the sign bit of a 64 bit signed int presented as an unsigned int. */
13089 #define clearSignU64(_value_u64) ((_value_u64) &= ~SIGN_BIT_U64)
13091 /* Multiply two 64 bit ints and return.
13092 the hi 64 bits of the 128 bit product. */
13094 static uint64_t
13096 {
13104 /* Cross-multiply and collect results. */
13110 /* Start accumulating 64 bit results. */
13111 /* Drop bottom half of lowest cross-product. */
13113 /* Add in middle products. */
13116 /* Check for overflow. */
13118 /* Carry over 1 into top cross-product. */
13119 carry++;
13123 /* Check for overflow. */
13125 /* Carry over 1 into top cross-product. */
13126 carry++;
13128 /* Drop lowest 32 bits of middle cross-product. */
13130 /* Move carry bit to just above middle cross-product highest bit. */
13133 /* Add top cross-product plus and any carry. */
13137 }
13139 /* Signed multiply high, source, source2 :
13140 64 bit, dest <-- high 64-bit of result. */
13141 static void
13143 {
13157 HALT_UNALLOC;
13159 /* Convert to unsigned and use the unsigned mul64hi routine
13160 the fix the sign up afterwards. */
13162 {
13165 }
13166 else
13167 {
13169 }
13172 {
13175 }
13176 else
13177 {
13179 }
13187 {
13188 /* Multiply 128-bit result by -1, which means highpart gets inverted,
13189 and has carry in added only if low part is 0. */
13193 }
13196 }
13198 /* Unsigned multiply add long -- source, source2 :
13199 32 bit, source3 : 64 bit. */
13200 static void
13202 {
13209 /* N.B. we need to multiply the signed 32 bit values in rn, rm to
13210 obtain a 64 bit product. */
13211 aarch64_set_reg_u64
13216 }
13218 /* Unsigned multiply sub long -- source, source2 : 32 bit, source3 : 64 bit. */
13219 static void
13221 {
13228 /* N.B. we need to multiply the signed 32 bit values in rn, rm to
13229 obtain a 64 bit product. */
13230 aarch64_set_reg_u64
13235 }
13237 /* Unsigned multiply high, source, source2 :
13238 64 bit, dest <-- high 64-bit of result. */
13239 static void
13241 {
13248 HALT_UNALLOC;
13254 }
13256 static void
13258 {
13259 /* assert instr[28,24] == 11011. */
13260 /* instr[31] = size : 0 ==> 32 bit, 1 ==> 64 bit (for rd at least)
13261 instr[30,29] = op54 : 00 ==> ok, ow ==> UNALLOC
13262 instr[23,21] = op31 : 111 ==> UNALLOC, o2 ==> ok
13263 instr[15] = o0 : 0/1 ==> ok
13264 instr[23,21:15] ==> op : 0000 ==> MADD, 0001 ==> MSUB, (32/64 bit)
13265 0010 ==> SMADDL, 0011 ==> SMSUBL, (64 bit only)
13266 0100 ==> SMULH, (64 bit only)
13267 1010 ==> UMADDL, 1011 ==> UNSUBL, (64 bit only)
13268 1100 ==> UMULH (64 bit only)
13269 ow ==> UNALLOC. */
13278 HALT_UNALLOC;
13281 {
13283 HALT_UNALLOC;
13287 else
13290 }
13295 {
13305 }
13306 }
13308 static void
13310 {
13311 /* uint32_t group = dispatchGroup (aarch64_get_instr (cpu));
13312 assert group == GROUP_DPREG_0101 || group == GROUP_DPREG_1101
13313 bits [28:24:21] of a DPReg are the secondary dispatch vector. */
13317 {
13329 {
13330 /* This set bundles a variety of different operations. */
13331 /* Check for. */
13332 /* 1) add/sub w carry. */
13335 /* 2) cond compare register/immediate. */
13338 /* 3) cond select. */
13341 /* 4) data proc 1/2 source. */
13355 {
13356 /* Bit 30 is clear for data proc 2 source
13357 and set for data proc 1 source. */
13360 else
13362 }
13364 else
13365 /* Should not reach here. */
13366 HALT_NYI;
13369 }
13375 HALT_UNALLOC;
13381 /* Should never reach here. */
13382 HALT_NYI;
13383 }
13384 }
13386 /* Unconditional Branch immediate.
13387 Offset is a PC-relative byte offset in the range +/- 128MiB.
13388 The offset is assumed to be raw from the decode i.e. the
13389 simulator is expected to scale them from word offsets to byte. */
13391 /* Unconditional branch. */
13392 static void
13394 {
13396 }
13400 /* Unconditional branch and link -- writes return PC to LR. */
13401 static void
13403 {
13409 {
13420 );
13421 }
13422 }
13424 /* Unconditional Branch register.
13425 Branch/return address is in source register. */
13427 /* Unconditional branch. */
13428 static void
13430 {
13434 }
13436 /* Unconditional branch and link -- writes return PC to LR. */
13437 static void
13439 {
13440 /* Ensure we read the destination before we write LR. */
13448 {
13459 );
13460 }
13461 }
13463 /* Return -- assembler will default source to LR this is functionally
13464 equivalent to br but, presumably, unlike br it side effects the
13465 branch predictor. */
13466 static void
13468 {
13474 {
13479 }
13480 }
13482 /* NOP -- we implement this and call it from the decode in case we
13483 want to intercept it later. */
13485 static void
13487 {
13489 }
13491 /* Data synchronization barrier. */
13493 static void
13495 {
13497 }
13499 /* Data memory barrier. */
13501 static void
13503 {
13505 }
13507 /* Instruction synchronization barrier. */
13509 static void
13511 {
13513 }
13515 static void
13517 {
13518 /* assert instr[30,26] == 00101
13519 instr[31] ==> 0 == B, 1 == BL
13520 instr[25,0] == imm26 branch offset counted in words. */
13523 /* We have a 26 byte signed word offset which we need to pass to the
13524 execute routine as a signed byte offset. */
13529 else
13531 }
13533 /* Control Flow. */
13535 /* Conditional branch
13537 Offset is a PC-relative byte offset in the range +/- 1MiB pos is
13538 a bit position in the range 0 .. 63
13540 cc is a CondCode enum value as pulled out of the decode
13542 N.B. any offset register (source) can only be Xn or Wn. */
13544 static void
13546 {
13547 /* The test returns TRUE if CC is met. */
13551 }
13553 /* 32 bit branch on register non-zero. */
13554 static void
13556 {
13562 }
13564 /* 64 bit branch on register zero. */
13565 static void
13567 {
13573 }
13575 /* 32 bit branch on register non-zero. */
13576 static void
13578 {
13584 }
13586 /* 64 bit branch on register zero. */
13587 static void
13589 {
13595 }
13597 /* Branch on register bit test non-zero -- one size fits all. */
13598 static void
13600 {
13606 }
13608 /* Branch on register bit test zero -- one size fits all. */
13609 static void
13611 {
13617 }
13619 static void
13621 {
13622 /* instr[30,25] = 01 1010
13623 instr[31] = size : 0 ==> 32, 1 ==> 64
13624 instr[24] = op : 0 ==> CBZ, 1 ==> CBNZ
13625 instr[23,5] = simm19 branch offset counted in words
13626 instr[4,0] = rt */
13633 {
13636 else
13638 }
13639 else
13640 {
13643 else
13645 }
13646 }
13648 static void
13650 {
13651 /* instr[31] = b5 : bit 5 of test bit idx
13652 instr[30,25] = 01 1011
13653 instr[24] = op : 0 ==> TBZ, 1 == TBNZ
13654 instr[23,19] = b40 : bits 4 to 0 of test bit idx
13655 instr[18,5] = simm14 : signed offset counted in words
13656 instr[4,0] = uimm5 */
13665 else
13667 }
13669 static void
13671 {
13672 /* instr[31,25] = 010 1010
13673 instr[24] = op1; op => 00 ==> B.cond
13674 instr[23,5] = simm19 : signed offset counted in words
13675 instr[4] = op0
13676 instr[3,0] = cond */
13684 HALT_UNALLOC;
13689 }
13691 static void
13693 {
13694 /* instr[31,25] = 110 1011
13695 instr[24,21] = op : 0 ==> BR, 1 => BLR, 2 => RET, 3 => ERET, 4 => DRPS
13696 instr[20,16] = op2 : must be 11111
13697 instr[15,10] = op3 : must be 000000
13698 instr[4,0] = op2 : must be 11111. */
13708 HALT_UNALLOC;
13719 else
13720 {
13721 /* ERET and DRPS accept 0b11111 for rn = instr [4,0]. */
13722 /* anything else is unallocated. */
13726 HALT_UNALLOC;
13729 HALT_NYI;
13731 HALT_UNALLOC;
13732 }
13733 }
13735 /* FIXME: We should get the Angel SWI values from ../../libgloss/aarch64/svc.h
13736 but this may not be available. So instead we define the values we need
13737 here. */
13738 #define AngelSVC_Reason_Open 0x01
13739 #define AngelSVC_Reason_Close 0x02
13740 #define AngelSVC_Reason_Write 0x05
13741 #define AngelSVC_Reason_Read 0x06
13742 #define AngelSVC_Reason_IsTTY 0x09
13743 #define AngelSVC_Reason_Seek 0x0A
13744 #define AngelSVC_Reason_FLen 0x0C
13745 #define AngelSVC_Reason_Remove 0x0E
13746 #define AngelSVC_Reason_Rename 0x0F
13747 #define AngelSVC_Reason_Clock 0x10
13748 #define AngelSVC_Reason_Time 0x11
13749 #define AngelSVC_Reason_System 0x12
13750 #define AngelSVC_Reason_Errno 0x13
13751 #define AngelSVC_Reason_GetCmdLine 0x15
13752 #define AngelSVC_Reason_HeapInfo 0x16
13753 #define AngelSVC_Reason_ReportException 0x18
13754 #define AngelSVC_Reason_Elapsed 0x30
13757 static void
13759 {
13764 {
13768 }
13770 /* We have encountered an Angel SVC call. See if we can process it. */
13772 {
13774 {
13775 /* Get the values. */
13779 /* Get the pointer */
13783 /* Fill in the memory block. */
13784 /* Start addr of heap. */
13786 /* End addr of heap. */
13788 /* Lowest stack addr. */
13790 /* Initial stack addr. */
13794 }
13798 {
13799 /* Get the pointer */
13800 /* uint64_t ptr = aarch64_get_reg_u64 (cpu, 1, SP_OK);. */
13801 /* FIXME: For now we just assume that we will only be asked
13802 to open the standard file descriptors. */
13807 }
13811 {
13815 }
13824 result =
13825 #ifdef CLOCKS_PER_SEC
13829 #else
13830 /* Presume unix... clock() returns microseconds. */
13832 #endif
13833 ;
13838 {
13839 /* Get the pointer */
13843 /* FIXME: No command line for now. */
13846 }
13855 {
13856 /* Get the pointer */
13858 /* Get the write control block. */
13868 {
13874 }
13876 {
13878 }
13880 {
13885 }
13886 else
13887 {
13893 }
13894 }
13898 {
13899 /* Get the pointer */
13901 /*ptr = aarch64_get_mem_u64 (cpu, ptr);. */
13912 else
13915 }
13931 }
13934 }
13936 static void
13938 {
13939 /* instr[31:24] = 11010100
13940 instr[23,21] = opc : 000 ==> GEN EXCPN, 001 ==> BRK
13941 010 ==> HLT, 101 ==> DBG GEN EXCPN
13942 instr[20,5] = imm16
13943 instr[4,2] = opc2 000 ==> OK, ow ==> UNALLOC
13944 instr[1,0] = LL : discriminates opc */
13954 HALT_UNALLOC;
13958 /* We only implement HLT and BRK for now. */
13960 {
13964 }
13970 HALT_NYI;
13972 else
13973 HALT_UNALLOC;
13974 }
13976 /* Stub for accessing system registers. */
13978 static uint64_t
13981 {
13983 /* DCZID_EL0 - the Data Cache Zero ID register.
13984 We do not support DC ZVA at the moment, so
13985 we return a value with the disable bit set.
13986 We implement support for the DCZID register since
13987 it is used by the C library's memset function. */
13991 /* Cache Type Register. */
13995 /* TPIDR_EL0 - thread pointer id. */
14007 HALT_NYI;
14008 }
14010 static void
14013 {
14023 else
14024 HALT_NYI;
14025 }
14027 static void
14029 {
14030 /* instr[31:20] = 1101 0101 0001 1
14031 instr[19] = op0
14032 instr[18,16] = op1
14033 instr[15,12] = CRn
14034 instr[11,8] = CRm
14035 instr[7,5] = op2
14036 instr[4,0] = Rt */
14047 }
14049 static void
14051 {
14052 /* instr[31:19] = 1101 0101 0000 0
14053 instr[18,16] = op1
14054 instr[15,12] = 0100
14055 instr[11,8] = CRm
14056 instr[7,5] = op2
14057 instr[4,0] = 1 1111 */
14060 /*unsigned crm = INSTR (11, 8);*/
14068 {
14071 else
14072 HALT_UNALLOC;
14073 }
14075 {
14080 else
14081 HALT_UNALLOC;
14082 }
14083 else
14084 HALT_UNALLOC;
14085 }
14087 static void
14089 {
14090 /* instr[31:20] = 1101 0101 0001
14091 instr[19] = op0
14092 instr[18,16] = op1
14093 instr[15,12] = CRn
14094 instr[11,8] = CRm
14095 instr[7,5] = op2
14096 instr[4,0] = Rt */
14110 }
14112 static void
14114 {
14115 /* instr[31,19] = 1101 0101 0000 1
14116 instr[18,16] = op1
14117 instr[15,12] = CRn
14118 instr[11,8] = CRm
14119 instr[7,5] = op2
14120 instr[4,0] = Rt */
14123 /* FIXME: For now we just silently accept system ops. */
14124 }
14126 static void
14128 {
14129 /* instr[31:22] = 1101 01010 0
14130 instr[21] = L
14131 instr[20,19] = op0
14132 instr[18,16] = op1
14133 instr[15,12] = CRn
14134 instr[11,8] = CRm
14135 instr[7,5] = op2
14136 instr[4,0] = uimm5 */
14138 /* We are interested in HINT, DSB, DMB and ISB
14140 Hint #0 encodes NOOP (this is the only hint we care about)
14141 L == 0, op0 == 0, op1 = 011, CRn = 0010, Rt = 11111,
14142 CRm op2 != 0000 000 OR CRm op2 == 0000 000 || CRm op > 0000 101
14144 DSB, DMB, ISB are data store barrier, data memory barrier and
14145 instruction store barrier, respectively, where
14147 L == 0, op0 == 0, op1 = 011, CRn = 0011, Rt = 11111,
14148 op2 : DSB ==> 100, DMB ==> 101, ISB ==> 110
14149 CRm<3:2> ==> domain, CRm<1:0> ==> types,
14150 domain : 00 ==> OuterShareable, 01 ==> Nonshareable,
14151 10 ==> InerShareable, 11 ==> FullSystem
14152 types : 01 ==> Reads, 10 ==> Writes,
14153 11 ==> All, 00 ==> All (domain == FullSystem). */
14160 {
14163 {
14164 /* NOP has CRm != 0000 OR. */
14165 /* (CRm == 0000 AND (op2 == 000 OR op2 > 101)). */
14170 {
14171 /* Actually call nop method so we can reimplement it later. */
14174 }
14175 }
14176 HALT_NYI;
14179 {
14183 {
14189 }
14190 }
14207 else
14208 HALT_NYI;
14210 }
14211 }
14213 static void
14215 {
14216 /* uint32_t group = dispatchGroup (aarch64_get_instr (cpu));
14217 assert group == GROUP_BREXSYS_1010 || group == GROUP_BREXSYS_1011
14218 bits [31,29] of a BrExSys are the secondary dispatch vector. */
14222 {
14227 /* Compare has bit 25 clear while test has it set. */
14230 else
14235 /* This is a conditional branch if bit 25 is clear otherwise
14236 unallocated. */
14239 else
14240 HALT_UNALLOC;
14244 HALT_UNALLOC;
14251 /* Compare has bit 25 clear while test has it set. */
14254 else
14259 /* Unconditional branch reg has bit 25 set. */
14263 /* This includes both Excpn Gen, System and unalloc operations.
14264 We need to decode the Excpn Gen operation BRK so we can plant
14265 debugger entry points.
14266 Excpn Gen operations have instr [24] = 0.
14267 we need to decode at least one of the System operations NOP
14268 which is an alias for HINT #0.
14269 System operations have instr [24,22] = 100. */
14276 else
14277 HALT_UNALLOC;
14282 HALT_UNALLOC;
14285 /* Should never reach here. */
14286 HALT_NYI;
14287 }
14288 }
14290 static void
14292 {
14293 /* We need to check if gdb wants an in here. */
14294 /* checkBreak (cpu);. */
14299 {
14317 HALT_UNALLOC;
14320 /* Should never reach here. */
14321 HALT_NYI;
14322 }
14323 }
14325 static bfd_boolean
14327 {
14335 /* Code is always little-endian. */
14347 }
14349 void
14351 {
14355 {
14360 }
14364 }
14366 void
14368 {
14371 /* Install SP, FP and PC and set LR to -20
14372 so we can detect a top-level return. */
14379 }