sim/testsuite/bfin/c_alu2op_conv_xb.s

   1 //Original:/testcases/core/c_alu2op_conv_xb/c_alu2op_conv_xb.dsp
   2 // Spec Reference: alu2op convert xb
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8
   9
  10 imm32 r0, 0x00789abc;
  11 imm32 r1, 0x12345678;
  12 imm32 r2, 0x23456789;
  13 imm32 r3, 0x3456789a;
  14 imm32 r4, 0x856789ab;
  15 imm32 r5, 0x96789abc;
  16 imm32 r6, 0xa789abcd;
  17 imm32 r7, 0xb89abcde;
  18 R0 = R0.B (X);
  19 R1 = R0.B (X);
  20 R2 = R0.B (X);
  21 R3 = R0.B (X);
  22 R4 = R0.B (X);
  23 R5 = R0.B (X);
  24 R6 = R0.B (X);
  25 R7 = R0.B (X);
  26 CHECKREG r0, 0xFFFFFFBC;
  27 CHECKREG r1, 0xFFFFFFBC;
  28 CHECKREG r2, 0xFFFFFFBC;
  29 CHECKREG r3, 0xFFFFFFBC;
  30 CHECKREG r4, 0xFFFFFFBC;
  31 CHECKREG r5, 0xFFFFFFBC;
  32 CHECKREG r6, 0xFFFFFFBC;
  33 CHECKREG r7, 0xFFFFFFBC;
  34
  35 imm32 r0, 0x01230002;
  36 imm32 r1, 0x00374659;
  37 imm32 r2, 0x93456789;
  38 imm32 r3, 0xa456789a;
  39 imm32 r4, 0xb56789ab;
  40 imm32 r5, 0xc6789abc;
  41 imm32 r6, 0xd789abcd;
  42 imm32 r7, 0xe89abcde;
  43 R0 = R1.B (X);
  44 R2 = R1.B (X);
  45 R3 = R1.B (X);
  46 R4 = R1.B (X);
  47 R5 = R1.B (X);
  48 R6 = R1.B (X);
  49 R7 = R1.B (X);
  50 R1 = R1.B (X);
  51 CHECKREG r0, 0x00000059;
  52 CHECKREG r1, 0x00000059;
  53 CHECKREG r2, 0x00000059;
  54 CHECKREG r3, 0x00000059;
  55 CHECKREG r4, 0x00000059;
  56 CHECKREG r5, 0x00000059;
  57 CHECKREG r6, 0x00000059;
  58 CHECKREG r7, 0x00000059;
  59
  60 imm32 r0, 0x10789abc;
  61 imm32 r1, 0x11345678;
  62 imm32 r2, 0x93156789;
  63 imm32 r3, 0xd451789a;
  64 imm32 r4, 0x856719ab;
  65 imm32 r5, 0x267891bc;
  66 imm32 r6, 0xa789ab1d;
  67 imm32 r7, 0x989ab1de;
  68 R0 = R2.B (X);
  69 R1 = R2.B (X);
  70 R3 = R2.B (X);
  71 R4 = R2.B (X);
  72 R5 = R2.B (X);
  73 R6 = R2.B (X);
  74 R7 = R2.B (X);
  75 R2 = R2.B (X);
  76 CHECKREG r0, 0xFFFFFF89;
  77 CHECKREG r1, 0xFFFFFF89;
  78 CHECKREG r2, 0xFFFFFF89;
  79 CHECKREG r3, 0xFFFFFF89;
  80 CHECKREG r4, 0xFFFFFF89;
  81 CHECKREG r5, 0xFFFFFF89;
  82 CHECKREG r6, 0xFFFFFF89;
  83 CHECKREG r7, 0xFFFFFF89;
  84
  85 imm32 r0, 0x21230002;
  86 imm32 r1, 0x02374659;
  87 imm32 r2, 0x93256789;
  88 imm32 r3, 0xa952789a;
  89 imm32 r4, 0xb59729ab;
  90 imm32 r5, 0xc67992bc;
  91 imm32 r6, 0xd7899b2d;
  92 imm32 r7, 0xe89ab9d2;
  93 R0 = R3.B (X);
  94 R1 = R3.B (X);
  95 R2 = R3.B (X);
  96 R4 = R3.B (X);
  97 R5 = R3.B (X);
  98 R6 = R3.B (X);
  99 R7 = R3.B (X);
 100 R3 = R3.B (X);
 101 CHECKREG r0, 0xFFFFFF9A;
 102 CHECKREG r1, 0xFFFFFF9A;
 103 CHECKREG r2, 0xFFFFFF9A;
 104 CHECKREG r3, 0xFFFFFF9A;
 105 CHECKREG r4, 0xFFFFFF9A;
 106 CHECKREG r5, 0xFFFFFF9A;
 107 CHECKREG r6, 0xFFFFFF9A;
 108 CHECKREG r7, 0xFFFFFF9A;
 109
 110 imm32 r0, 0xa0789abc;
 111 imm32 r1, 0x1a345678;
 112 imm32 r2, 0x23a56789;
 113 imm32 r3, 0x645a789a;
 114 imm32 r4, 0x8667a9ab;
 115 imm32 r5, 0x96689abc;
 116 imm32 r6, 0xa787abad;
 117 imm32 r7, 0xb89a7cda;
 118 R0 = R4.B (X);
 119 R1 = R4.B (X);
 120 R2 = R4.B (X);
 121 R3 = R4.B (X);
 122 R4 = R4.B (X);
 123 R5 = R4.B (X);
 124 R6 = R4.B (X);
 125 R7 = R4.B (X);
 126 CHECKREG r0, 0xFFFFFFAB;
 127 CHECKREG r1, 0xFFFFFFAB;
 128 CHECKREG r2, 0xFFFFFFAB;
 129 CHECKREG r3, 0xFFFFFFAB;
 130 CHECKREG r4, 0xFFFFFFAB;
 131 CHECKREG r5, 0xFFFFFFAB;
 132 CHECKREG r6, 0xFFFFFFAB;
 133 CHECKREG r7, 0xFFFFFFAB;
 134
 135 imm32 r0, 0xf1230002;
 136 imm32 r1, 0x0f374659;
 137 imm32 r2, 0x93f56789;
 138 imm32 r3, 0xa45f789a;
 139 imm32 r4, 0xb567f9ab;
 140 imm32 r5, 0xc6789fbc;
 141 imm32 r6, 0xd789abfd;
 142 imm32 r7, 0xe89abcdf;
 143 R0 = R5.B (X);
 144 R1 = R5.B (X);
 145 R2 = R5.B (X);
 146 R3 = R5.B (X);
 147 R4 = R5.B (X);
 148 R6 = R5.B (X);
 149 R7 = R5.B (X);
 150 R5 = R5.B (X);
 151 CHECKREG r0, 0xFFFFFFBC;
 152 CHECKREG r1, 0xFFFFFFBC;
 153 CHECKREG r2, 0xFFFFFFBC;
 154 CHECKREG r3, 0xFFFFFFBC;
 155 CHECKREG r4, 0xFFFFFFBC;
 156 CHECKREG r5, 0xFFFFFFBC;
 157 CHECKREG r6, 0xFFFFFFBC;
 158 CHECKREG r7, 0xFFFFFFBC;
 159
 160 imm32 r0, 0xe0789abc;
 161 imm32 r1, 0xe2345678;
 162 imm32 r2, 0x2e456789;
 163 imm32 r3, 0x34e6789a;
 164 imm32 r4, 0x856e89ab;
 165 imm32 r5, 0x9678eabc;
 166 imm32 r6, 0xa789aecd;
 167 imm32 r7, 0xb89abcee;
 168 R0 = R6.B (X);
 169 R1 = R6.B (X);
 170 R2 = R6.B (X);
 171 R3 = R6.B (X);
 172 R4 = R6.B (X);
 173 R5 = R6.B (X);
 174 R7 = R6.B (X);
 175 R6 = R6.B (X);
 176 CHECKREG r0, 0xFFFFFFCD;
 177 CHECKREG r1, 0xFFFFFFCD;
 178 CHECKREG r2, 0xFFFFFFCD;
 179 CHECKREG r3, 0xFFFFFFCD;
 180 CHECKREG r4, 0xFFFFFFCD;
 181 CHECKREG r5, 0xFFFFFFCD;
 182 CHECKREG r6, 0xFFFFFFCD;
 183 CHECKREG r7, 0xFFFFFFCD;
 184
 185 imm32 r0, 0x012300f5;
 186 imm32 r1, 0x80374659;
 187 imm32 r2, 0x98456589;
 188 imm32 r3, 0xa486589a;
 189 imm32 r4, 0xb56589ab;
 190 imm32 r5, 0xc6588abc;
 191 imm32 r6, 0xd589a8cd;
 192 imm32 r7, 0x589abc88;
 193 R0 = R7.B (X);
 194 R1 = R7.B (X);
 195 R2 = R7.B (X);
 196 R3 = R7.B (X);
 197 R4 = R7.B (X);
 198 R5 = R7.B (X);
 199 R6 = R7.B (X);
 200 R7 = R7.B (X);
 201 CHECKREG r0, 0xFFFFFF88;
 202 CHECKREG r1, 0xFFFFFF88;
 203 CHECKREG r2, 0xFFFFFF88;
 204 CHECKREG r3, 0xFFFFFF88;
 205 CHECKREG r4, 0xFFFFFF88;
 206 CHECKREG r5, 0xFFFFFF88;
 207 CHECKREG r6, 0xFFFFFF88;
 208 CHECKREG r7, 0xFFFFFF88;
 209
 210
 211 pass