sim/testsuite/bfin/c_alu2op_conv_xh.s

   1 //Original:/testcases/core/c_alu2op_conv_xh/c_alu2op_conv_xh.dsp
   2 // Spec Reference: alu2op convert xh
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8
   9
  10
  11 imm32 r0, 0x00789abc;
  12 imm32 r1, 0x12345678;
  13 imm32 r2, 0x23456789;
  14 imm32 r3, 0x3456789a;
  15 imm32 r4, 0x856789ab;
  16 imm32 r5, 0x96789abc;
  17 imm32 r6, 0xa789abcd;
  18 imm32 r7, 0xb89abcde;
  19 R0 = R0.L (X);
  20 R1 = R0.L (X);
  21 R2 = R0.L (X);
  22 R3 = R0.L (X);
  23 R4 = R0.L (X);
  24 R5 = R0.L (X);
  25 R6 = R0.L (X);
  26 R7 = R0.L (X);
  27 CHECKREG r0, 0xFFFF9ABC;
  28 CHECKREG r1, 0xFFFF9ABC;
  29 CHECKREG r2, 0xFFFF9ABC;
  30 CHECKREG r3, 0xFFFF9ABC;
  31 CHECKREG r4, 0xFFFF9ABC;
  32 CHECKREG r5, 0xFFFF9ABC;
  33 CHECKREG r6, 0xFFFF9ABC;
  34 CHECKREG r7, 0xFFFF9ABC;
  35
  36 imm32 r0, 0x01230002;
  37 imm32 r1, 0x00374659;
  38 imm32 r2, 0x93456789;
  39 imm32 r3, 0xa456789a;
  40 imm32 r4, 0xb56789ab;
  41 imm32 r5, 0xc6789abc;
  42 imm32 r6, 0xd789abcd;
  43 imm32 r7, 0xe89abcde;
  44 R0 = R1.L (X);
  45 R2 = R1.L (X);
  46 R3 = R1.L (X);
  47 R4 = R1.L (X);
  48 R5 = R1.L (X);
  49 R6 = R1.L (X);
  50 R7 = R1.L (X);
  51 R1 = R1.L (X);
  52 CHECKREG r0, 0x00004659;
  53 CHECKREG r1, 0x00004659;
  54 CHECKREG r2, 0x00004659;
  55 CHECKREG r3, 0x00004659;
  56 CHECKREG r4, 0x00004659;
  57 CHECKREG r5, 0x00004659;
  58 CHECKREG r6, 0x00004659;
  59 CHECKREG r7, 0x00004659;
  60
  61 imm32 r0, 0x10789abc;
  62 imm32 r1, 0x11345678;
  63 imm32 r2, 0x93156789;
  64 imm32 r3, 0xd451789a;
  65 imm32 r4, 0x856719ab;
  66 imm32 r5, 0x267891bc;
  67 imm32 r6, 0xa789ab1d;
  68 imm32 r7, 0x989ab1de;
  69 R0 = R2.L (X);
  70 R1 = R2.L (X);
  71 R3 = R2.L (X);
  72 R4 = R2.L (X);
  73 R5 = R2.L (X);
  74 R6 = R2.L (X);
  75 R7 = R2.L (X);
  76 R2 = R2.L (X);
  77 CHECKREG r0, 0x00006789;
  78 CHECKREG r1, 0x00006789;
  79 CHECKREG r2, 0x00006789;
  80 CHECKREG r3, 0x00006789;
  81 CHECKREG r4, 0x00006789;
  82 CHECKREG r5, 0x00006789;
  83 CHECKREG r6, 0x00006789;
  84 CHECKREG r7, 0x00006789;
  85
  86 imm32 r0, 0x21230002;
  87 imm32 r1, 0x02374659;
  88 imm32 r2, 0x93256789;
  89 imm32 r3, 0xa952789a;
  90 imm32 r4, 0xb59729ab;
  91 imm32 r5, 0xc67992bc;
  92 imm32 r6, 0xd7899b2d;
  93 imm32 r7, 0xe89ab9d2;
  94 R0 = R3.L (X);
  95 R1 = R3.L (X);
  96 R2 = R3.L (X);
  97 R4 = R3.L (X);
  98 R5 = R3.L (X);
  99 R6 = R3.L (X);
 100 R7 = R3.L (X);
 101 R3 = R3.L (X);
 102 CHECKREG r0, 0x0000789A;
 103 CHECKREG r1, 0x0000789A;
 104 CHECKREG r2, 0x0000789A;
 105 CHECKREG r3, 0x0000789A;
 106 CHECKREG r4, 0x0000789A;
 107 CHECKREG r5, 0x0000789A;
 108 CHECKREG r6, 0x0000789A;
 109 CHECKREG r7, 0x0000789A;
 110
 111 imm32 r0, 0xa0789abc;
 112 imm32 r1, 0x1a345678;
 113 imm32 r2, 0x23a56789;
 114 imm32 r3, 0x645a789a;
 115 imm32 r4, 0x8667a9ab;
 116 imm32 r5, 0x96689abc;
 117 imm32 r6, 0xa787abad;
 118 imm32 r7, 0xb89a7cda;
 119 R0 = R4.L (X);
 120 R1 = R4.L (X);
 121 R2 = R4.L (X);
 122 R3 = R4.L (X);
 123 R4 = R4.L (X);
 124 R5 = R4.L (X);
 125 R6 = R4.L (X);
 126 R7 = R4.L (X);
 127 CHECKREG r0, 0xFFFFA9AB;
 128 CHECKREG r1, 0xFFFFA9AB;
 129 CHECKREG r2, 0xFFFFA9AB;
 130 CHECKREG r3, 0xFFFFA9AB;
 131 CHECKREG r4, 0xFFFFA9AB;
 132 CHECKREG r5, 0xFFFFA9AB;
 133 CHECKREG r6, 0xFFFFA9AB;
 134 CHECKREG r7, 0xFFFFA9AB;
 135
 136 imm32 r0, 0xf1230002;
 137 imm32 r1, 0x0f374659;
 138 imm32 r2, 0x93f56789;
 139 imm32 r3, 0xa45f789a;
 140 imm32 r4, 0xb567f9ab;
 141 imm32 r5, 0xc6789fbc;
 142 imm32 r6, 0xd789abfd;
 143 imm32 r7, 0xe89abcdf;
 144 R0 = R5.L (X);
 145 R1 = R5.L (X);
 146 R2 = R5.L (X);
 147 R3 = R5.L (X);
 148 R4 = R5.L (X);
 149 R6 = R5.L (X);
 150 R7 = R5.L (X);
 151 R5 = R5.L (X);
 152 CHECKREG r0, 0xFFFF9FBC;
 153 CHECKREG r1, 0xFFFF9FBC;
 154 CHECKREG r2, 0xFFFF9FBC;
 155 CHECKREG r3, 0xFFFF9FBC;
 156 CHECKREG r4, 0xFFFF9FBC;
 157 CHECKREG r5, 0xFFFF9FBC;
 158 CHECKREG r6, 0xFFFF9FBC;
 159 CHECKREG r7, 0xFFFF9FBC;
 160
 161 imm32 r0, 0xe0789abc;
 162 imm32 r1, 0xe2345678;
 163 imm32 r2, 0x2e456789;
 164 imm32 r3, 0x34e6789a;
 165 imm32 r4, 0x856e89ab;
 166 imm32 r5, 0x9678eabc;
 167 imm32 r6, 0xa789aecd;
 168 imm32 r7, 0xb89abcee;
 169 R0 = R6.L (X);
 170 R1 = R6.L (X);
 171 R2 = R6.L (X);
 172 R3 = R6.L (X);
 173 R4 = R6.L (X);
 174 R5 = R6.L (X);
 175 R7 = R6.L (X);
 176 R6 = R6.L (X);
 177 CHECKREG r0, 0xFFFFAECD;
 178 CHECKREG r1, 0xFFFFAECD;
 179 CHECKREG r2, 0xFFFFAECD;
 180 CHECKREG r3, 0xFFFFAECD;
 181 CHECKREG r4, 0xFFFFAECD;
 182 CHECKREG r5, 0xFFFFAECD;
 183 CHECKREG r6, 0xFFFFAECD;
 184 CHECKREG r7, 0xFFFFAECD;
 185
 186 imm32 r0, 0x012300f5;
 187 imm32 r1, 0x80374659;
 188 imm32 r2, 0x98456589;
 189 imm32 r3, 0xa486589a;
 190 imm32 r4, 0xb56589ab;
 191 imm32 r5, 0xc6588abc;
 192 imm32 r6, 0xd589a8cd;
 193 imm32 r7, 0x589abc88;
 194 R0 = R7.L (X);
 195 R1 = R7.L (X);
 196 R2 = R7.L (X);
 197 R3 = R7.L (X);
 198 R4 = R7.L (X);
 199 R5 = R7.L (X);
 200 R6 = R7.L (X);
 201 R7 = R7.L (X);
 202 CHECKREG r0, 0xFFFFBC88;
 203 CHECKREG r1, 0xFFFFBC88;
 204 CHECKREG r2, 0xFFFFBC88;
 205 CHECKREG r3, 0xFFFFBC88;
 206 CHECKREG r4, 0xFFFFBC88;
 207 CHECKREG r5, 0xFFFFBC88;
 208 CHECKREG r6, 0xFFFFBC88;
 209 CHECKREG r7, 0xFFFFBC88;
 210
 211
 212 pass